From 96c0ae58f09b438f404468c061196580dbdf99e7 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Thu, 26 Feb 2015 10:44:47 -0600 Subject: [PATCH 001/143] Added sleep and deepsleep for LPC11U68. Needs testing on board --- .../hal/TARGET_NXP/TARGET_LPC11U6X/device.h | 2 +- .../TARGET_NXP/TARGET_LPC11U6X/sleep_api.c | 65 +++++++++++++++++++ 2 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h index 0c8b33203b..4894a9640d 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h @@ -44,7 +44,7 @@ #define DEVICE_SEMIHOST 0 #define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_SLEEP 0 +#define DEVICE_SLEEP 1 #define DEVICE_DEBUG_AWARENESS 0 diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c new file mode 100644 index 0000000000..4109ffe4b7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "mbed_interface.h" + +void sleep(void) { + +#if (DEVICE_SEMIHOST == 1) + // ensure debug is disconnected + mbed_interface_disconnect(); +#endif + + // PCON[PM] (bits 2:0) set to 0 + LPC_PMU->PCON &= ~0x03; + + // SRC[SLEEPDEEP] set to 0 = sleep + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + // wait for interrupt + __WFI(); +} + + +void deepsleep(void) { + +#if (DEVICE_SEMIHOST == 1) + // ensure debug is disconnected + mbed_interface_disconnect(); +#endif + + // PCON[PM] (bits 2:0) set to 1 + LPC_PMU->PCON &= ~0x03; + LPC_PMU->PCON |= 0x01; + + //According to user manual it is kinda picky about reserved bits, so we follow that nicely + //Keep WDOSC and BOD in same state as they are now during deepsleep + LPC_SYSCON->PDSLEEPCFG = 0x00000037 | (LPC_SYSCON->PDRUNCFG & (0x00000048)); + + // Power up same as before powerdown + LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; + + // All interrupts can wake + LPC_SYSCON->STARTERP0 = 0xFF; + LPC_SYSCON->STARTERP1 = 0xFFFFFFFF; + + // SRC[SLEEPDEEP] set to 1 = deep sleep + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // wait for interrupt + __WFI(); +} From db6792f7ccfbab9d33009b2f1709019e17dbd7d4 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Thu, 26 Feb 2015 11:08:52 -0600 Subject: [PATCH 002/143] Renamed sleep implementation file and added DEVICE_SLEEP #defines --- .../hal/TARGET_NXP/TARGET_LPC11U6X/{sleep_api.c => sleep.c} | 4 ++++ 1 file changed, 4 insertions(+) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/{sleep_api.c => sleep.c} (98%) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c index 4109ffe4b7..ede20f99dc 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c @@ -17,6 +17,8 @@ #include "cmsis.h" #include "mbed_interface.h" +#if DEVICE_SLEEP + void sleep(void) { #if (DEVICE_SEMIHOST == 1) @@ -63,3 +65,5 @@ void deepsleep(void) { // wait for interrupt __WFI(); } + +#endif From 1bbb0ee1099cb8ec66f8af42511b57b3418860e8 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Tue, 17 Mar 2015 13:41:40 -0500 Subject: [PATCH 003/143] Added macros to alias the endpoint callback functions to support configurability. --- libraries/USBDevice/USBAudio/USBAudio.cpp | 4 ++-- libraries/USBDevice/USBAudio/USBAudio.h | 4 ++-- libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h | 6 ++++++ libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h | 6 ++++++ libraries/USBDevice/USBHID/USBKeyboard.cpp | 2 +- libraries/USBDevice/USBHID/USBKeyboard.h | 2 +- libraries/USBDevice/USBHID/USBMouseKeyboard.cpp | 2 +- libraries/USBDevice/USBHID/USBMouseKeyboard.h | 2 +- libraries/USBDevice/USBMIDI/USBMIDI.cpp | 2 +- libraries/USBDevice/USBMIDI/USBMIDI.h | 2 +- libraries/USBDevice/USBMSD/USBMSD.cpp | 4 ++-- libraries/USBDevice/USBMSD/USBMSD.h | 4 ++-- libraries/USBDevice/USBSerial/USBSerial.cpp | 2 +- libraries/USBDevice/USBSerial/USBSerial.h | 2 +- 17 files changed, 46 insertions(+), 16 deletions(-) diff --git a/libraries/USBDevice/USBAudio/USBAudio.cpp b/libraries/USBDevice/USBAudio/USBAudio.cpp index fc383b6c13..aab9e774e3 100644 --- a/libraries/USBDevice/USBAudio/USBAudio.cpp +++ b/libraries/USBDevice/USBAudio/USBAudio.cpp @@ -119,7 +119,7 @@ float USBAudio::getVolume() { } -bool USBAudio::EP3_OUT_callback() { +bool USBAudio::EPISO_OUT_callback() { uint32_t size = 0; interruptOUT = true; if (buf_stream_in != NULL) { @@ -132,7 +132,7 @@ bool USBAudio::EP3_OUT_callback() { } -bool USBAudio::EP3_IN_callback() { +bool USBAudio::EPISO_IN_callback() { interruptIN = true; writeIN = true; return true; diff --git a/libraries/USBDevice/USBAudio/USBAudio.h b/libraries/USBDevice/USBAudio/USBAudio.h index 6b6b4bcc45..5038f053c8 100644 --- a/libraries/USBDevice/USBAudio/USBAudio.h +++ b/libraries/USBDevice/USBAudio/USBAudio.h @@ -216,12 +216,12 @@ protected: /* * Callback called when a packet is received */ - virtual bool EP3_OUT_callback(); + virtual bool EPISO_OUT_callback(); /* * Callback called when a packet has been sent */ - virtual bool EP3_IN_callback(); + virtual bool EPISO_IN_callback(); private: diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h b/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h index 5cb3f7b395..87721a21c5 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h @@ -81,12 +81,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h b/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h index 5f642df15a..b4ddaa5142 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h @@ -53,12 +53,18 @@ /* Bulk endpoint */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoint */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoint */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h b/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h index 3f7aa6ba4d..383b7e36fc 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h @@ -81,12 +81,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h b/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h index e939c7673e..f25a3d8623 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h @@ -65,12 +65,18 @@ /* Bulk endpoints */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoints */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoints */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h b/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h index 1c95f2c807..1d520d11c9 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h @@ -49,12 +49,18 @@ /* Bulk endpoint */ #define EPBULK_OUT (EP2OUT) #define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback /* Interrupt endpoint */ #define EPINT_OUT (EP1OUT) #define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback /* Isochronous endpoint */ #define EPISO_OUT (EP3OUT) #define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback #define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) #define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) diff --git a/libraries/USBDevice/USBHID/USBKeyboard.cpp b/libraries/USBDevice/USBHID/USBKeyboard.cpp index 81857095bc..df4ca4798b 100644 --- a/libraries/USBDevice/USBHID/USBKeyboard.cpp +++ b/libraries/USBDevice/USBHID/USBKeyboard.cpp @@ -420,7 +420,7 @@ uint8_t * USBKeyboard::reportDesc() { } -bool USBKeyboard::EP1_OUT_callback() { +bool USBKeyboard::EPINT_OUT_callback() { uint32_t bytesRead = 0; uint8_t led[65]; USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE); diff --git a/libraries/USBDevice/USBHID/USBKeyboard.h b/libraries/USBDevice/USBHID/USBKeyboard.h index c9e08b16bc..c58ae56f0e 100644 --- a/libraries/USBDevice/USBHID/USBKeyboard.h +++ b/libraries/USBDevice/USBHID/USBKeyboard.h @@ -150,7 +150,7 @@ public: * * @returns if handle by subclass, return true */ - virtual bool EP1_OUT_callback(); + virtual bool EPINT_OUT_callback(); /** * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important: diff --git a/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp b/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp index 848d81a686..cd68091202 100644 --- a/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp +++ b/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp @@ -548,7 +548,7 @@ uint8_t * USBMouseKeyboard::reportDesc() { return NULL; } -bool USBMouseKeyboard::EP1_OUT_callback() { +bool USBMouseKeyboard::EPINT_OUT_callback() { uint32_t bytesRead = 0; uint8_t led[65]; USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE); diff --git a/libraries/USBDevice/USBHID/USBMouseKeyboard.h b/libraries/USBDevice/USBHID/USBMouseKeyboard.h index 7eaa355e37..1b19b10db2 100644 --- a/libraries/USBDevice/USBHID/USBMouseKeyboard.h +++ b/libraries/USBDevice/USBHID/USBMouseKeyboard.h @@ -202,7 +202,7 @@ class USBMouseKeyboard: public USBHID, public Stream * * @returns if handle by subclass, return true */ - virtual bool EP1_OUT_callback(); + virtual bool EPINT_OUT_callback(); private: diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/libraries/USBDevice/USBMIDI/USBMIDI.cpp index 09594805fb..048ab728bc 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.cpp +++ b/libraries/USBDevice/USBMIDI/USBMIDI.cpp @@ -35,7 +35,7 @@ void USBMIDI::attach(void (*fptr)(MIDIMessage)) { } -bool USBMIDI::EP2_OUT_callback() { +bool USBMIDI::EPBULK_OUT_callback() { uint8_t buf[64]; uint32_t len; readEP(EPBULK_OUT, buf, &len, 64); diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.h b/libraries/USBDevice/USBMIDI/USBMIDI.h index fdf5d6d6bb..6b673b63c8 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.h +++ b/libraries/USBDevice/USBMIDI/USBMIDI.h @@ -78,7 +78,7 @@ public: protected: - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); virtual bool USBCallback_setConfiguration(uint8_t configuration); /* * Get string product descriptor diff --git a/libraries/USBDevice/USBMSD/USBMSD.cpp b/libraries/USBDevice/USBMSD/USBMSD.cpp index c5ce390846..f2b6e3d791 100644 --- a/libraries/USBDevice/USBMSD/USBMSD.cpp +++ b/libraries/USBDevice/USBMSD/USBMSD.cpp @@ -147,7 +147,7 @@ void USBMSD::reset() { // Called in ISR context called when a data is received -bool USBMSD::EP2_OUT_callback() { +bool USBMSD::EPBULK_OUT_callback() { uint32_t size = 0; uint8_t buf[MAX_PACKET_SIZE_EPBULK]; readEP(EPBULK_OUT, buf, &size, MAX_PACKET_SIZE_EPBULK); @@ -184,7 +184,7 @@ bool USBMSD::EP2_OUT_callback() { } // Called in ISR context when a data has been transferred -bool USBMSD::EP2_IN_callback() { +bool USBMSD::EPBULK_IN_callback() { switch (stage) { // the device has to send data to the host diff --git a/libraries/USBDevice/USBMSD/USBMSD.h b/libraries/USBDevice/USBMSD/USBMSD.h index 9bf48ed373..ff750026c1 100644 --- a/libraries/USBDevice/USBMSD/USBMSD.h +++ b/libraries/USBDevice/USBMSD/USBMSD.h @@ -158,12 +158,12 @@ protected: /* * Callback called when a packet is received */ - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); /* * Callback called when a packet has been sent */ - virtual bool EP2_IN_callback(); + virtual bool EPBULK_IN_callback(); /* * Set configuration of device. Add endpoints diff --git a/libraries/USBDevice/USBSerial/USBSerial.cpp b/libraries/USBDevice/USBSerial/USBSerial.cpp index 3a1acfd829..4dc28b9e3c 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.cpp +++ b/libraries/USBDevice/USBSerial/USBSerial.cpp @@ -46,7 +46,7 @@ bool USBSerial::writeBlock(uint8_t * buf, uint16_t size) { -bool USBSerial::EP2_OUT_callback() { +bool USBSerial::EPBULK_OUT_callback() { uint8_t c[65]; uint32_t size = 0; diff --git a/libraries/USBDevice/USBSerial/USBSerial.h b/libraries/USBDevice/USBSerial/USBSerial.h index d5e2ec71d1..e83aea6b18 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.h +++ b/libraries/USBDevice/USBSerial/USBSerial.h @@ -145,7 +145,7 @@ public: } protected: - virtual bool EP2_OUT_callback(); + virtual bool EPBULK_OUT_callback(); virtual void lineCodingChanged(int baud, int bits, int parity, int stop){ if (settingsChangedCallback) { settingsChangedCallback(baud, bits, parity, stop); From bbe2e0caed57112344d1b8099364d9c804024c1d Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Tue, 17 Mar 2015 14:18:56 -0500 Subject: [PATCH 004/143] Using "Data Terminal Ready" signal to determine when the host is connected. --- libraries/USBDevice/USBSerial/USBCDC.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/libraries/USBDevice/USBSerial/USBCDC.cpp b/libraries/USBDevice/USBSerial/USBCDC.cpp index 12f84751fb..aa55541f37 100644 --- a/libraries/USBDevice/USBSerial/USBCDC.cpp +++ b/libraries/USBDevice/USBSerial/USBCDC.cpp @@ -27,6 +27,10 @@ static uint8_t cdc_line_coding[7]= {0x80, 0x25, 0x00, 0x00, 0x00, 0x00, 0x08}; #define CDC_GET_LINE_CODING 0x21 #define CDC_SET_CONTROL_LINE_STATE 0x22 +// Control Line State bits +#define CLS_DTR (1 << 0) +#define CLS_RTS (1 << 1) + #define MAX_CDC_REPORT_SIZE MAX_PACKET_SIZE_EPBULK USBCDC::USBCDC(uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect_blocking): USBDevice(vendor_id, product_id, product_release) { @@ -54,10 +58,13 @@ bool USBCDC::USBCallback_request(void) { transfer->remaining = 7; transfer->notify = true; success = true; - terminal_connected = true; break; case CDC_SET_CONTROL_LINE_STATE: - terminal_connected = false; + if (transfer->setup.wValue & CLS_DTR) { + terminal_connected = true; + } else { + terminal_connected = false; + } success = true; break; default: From a8de31c4bed20d8c238c8c28e1add607bcc8aebe Mon Sep 17 00:00:00 2001 From: Przemek Wirkus Date: Fri, 20 Mar 2015 14:11:20 +0000 Subject: [PATCH 005/143] Added timeouts (delays) on serial port and mounting point accesses in host_test and copy plugins to prevent serial/disk io errors when device remounts USB iface of interface chip --- workspace_tools/host_tests/host_test.py | 34 +++++++++++++++---- .../host_tests_plugins/host_test_plugins.py | 31 +++++++++++++++++ .../host_tests_plugins/module_copy_mbed.py | 2 ++ .../host_tests_plugins/module_copy_shell.py | 2 ++ 4 files changed, 63 insertions(+), 6 deletions(-) diff --git a/workspace_tools/host_tests/host_test.py b/workspace_tools/host_tests/host_test.py index c00c8ba2fe..4dd16505a2 100644 --- a/workspace_tools/host_tests/host_test.py +++ b/workspace_tools/host_tests/host_test.py @@ -126,21 +126,43 @@ class Mbed: serial_baud = serial_baud if serial_baud is not None else self.serial_baud serial_timeout = serial_timeout if serial_timeout is not None else self.serial_timeout + # Clear serial port if self.serial: self.serial.close() self.serial = None - result = True - try: - self.serial = Serial(self.port, baudrate=serial_baud, timeout=serial_timeout) - except Exception as e: - print "MBED: %s"% str(e) - result = False + # We will pool for serial to be re-mounted if it was unmounted after device reset + result = self.pool_for_serial_init(serial_baud, serial_timeout) # Blocking + # Port can be opened if result: self.flush() return result + def pool_for_serial_init(self, serial_baud, serial_timeout, pooling_loops=40, init_delay=0.5, loop_delay=0.25): + """ Functions pools for serial port readiness + """ + result = True + last_error = None + # This loop is used to check for serial port availability due to + # some delays and remounting when devices are being flashed with new software. + for i in range(pooling_loops): + sleep(loop_delay if i else init_delay) + try: + self.serial = Serial(self.port, baudrate=serial_baud, timeout=serial_timeout) + except Exception as e: + result = False + last_error = "MBED: %s"% str(e) + stdout.write('.') + stdout.flush() + else: + print "...port ready!" + result = True + break + if not result and last_error: + print last_error + return result + def set_serial_timeout(self, timeout): """ Wraps self.mbed.serial object timeout property """ diff --git a/workspace_tools/host_tests/host_tests_plugins/host_test_plugins.py b/workspace_tools/host_tests/host_tests_plugins/host_test_plugins.py index a2fd7fbcd3..e57d44b8f5 100644 --- a/workspace_tools/host_tests/host_tests_plugins/host_test_plugins.py +++ b/workspace_tools/host_tests/host_tests_plugins/host_test_plugins.py @@ -15,6 +15,9 @@ See the License for the specific language governing permissions and limitations under the License. """ +from os import access, F_OK +from sys import stdout +from time import sleep from subprocess import call @@ -58,6 +61,34 @@ class HostTestPluginBase: print "Plugin error: %s::%s: %s"% (self.name, self.type, text) return False + def print_plugin_info(self, text, NL=True): + """ Function prints notification in console and exits always with True + """ + if NL: + print "Plugin info: %s::%s: %s"% (self.name, self.type, text) + else: + print "Plugin info: %s::%s: %s"% (self.name, self.type, text), + return True + + def print_plugin_char(self, char): + """ Function prints char on stdout + """ + stdout.write(char) + stdout.flush() + return True + + def check_mount_point_ready(self, destination_disk, init_delay=0.2, loop_delay=0.25): + """ Checks if destination_disk is ready and can be accessed by e.g. copy commands + @init_delay - Initial delay time before first access check + @loop_delay - pooling delay for access check + """ + if not access(destination_disk, F_OK): + self.print_plugin_info("Waiting for mount point '%s' to be ready..."% destination_disk, NL=False) + sleep(init_delay) + while not access(destination_disk, F_OK): + sleep(loop_delay) + self.print_plugin_char('.') + def check_parameters(self, capabilitity, *args, **kwargs): """ This function should be ran each time we call execute() to check if none of the required parameters is missing. diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py index dc5d8fd9dd..18fe0c42ae 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py @@ -59,6 +59,8 @@ class HostTestPluginCopyMethod_Mbed(HostTestPluginBase): if capabilitity == 'default': image_path = kwargs['image_path'] destination_disk = kwargs['destination_disk'] + # Wait for mount point to be ready + self.check_mount_point_ready(destination_disk) # Blocking result = self.generic_mbed_copy(image_path, destination_disk) return result diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py index 9d57a56d30..b1561f86d5 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py @@ -42,6 +42,8 @@ class HostTestPluginCopyMethod_Shell(HostTestPluginBase): if self.check_parameters(capabilitity, *args, **kwargs) is True: image_path = kwargs['image_path'] destination_disk = kwargs['destination_disk'] + # Wait for mount point to be ready + self.check_mount_point_ready(destination_disk) # Blocking # Prepare correct command line parameter values image_base_name = basename(image_path) destination_path = join(destination_disk, image_base_name) From 79a05aa39cc7c3f61ddcd6d148590b8aae5cafb9 Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Thu, 8 Jan 2015 11:57:54 +0000 Subject: [PATCH 006/143] fixes #984: updating to v7.1 of the Nordic SDK. Re-organized file layout to match that from the SDK. --- .../TARGET_MCU_NORDIC_32K/startup_nRF51822.s | 25 +- .../TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h | 4 +- .../TARGET_MCU_NRF51822/cmsis_nvic.h | 2 +- .../compiler_abstraction.h | 124 +- .../TARGET_MCU_NRF51822/nordic_global.h | 17 - .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h | 48 + .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h | 316 +++-- .../TARGET_MCU_NRF51822/nrf51822.h | 27 - .../TARGET_MCU_NRF51822/nrf51_bitfields.h | 1240 +++++++++++++---- .../TARGET_MCU_NRF51822}/nrf_delay.h | 2 +- .../{system_nrf51822.c => system_nrf51.c} | 62 +- .../TARGET_MCU_NRF51822/system_nrf51.h | 68 + .../TARGET_MCU_NRF51822/system_nrf51822.h | 58 - .../components/libraries/crc16}/crc16.h | 0 .../libraries/scheduler}/app_scheduler.h | 26 +- .../components/libraries/util}/app_error.h | 56 +- .../components/libraries/util}/app_util.h | 6 +- .../Lib/nrf-sdk/app_common/app_button.h | 187 --- .../Lib/nrf-sdk/app_common/app_fifo.h | 83 -- .../Lib/nrf-sdk/app_common/app_gpiote.h | 226 --- .../Lib/nrf-sdk/app_common/app_timer.h | 313 ----- .../Lib/nrf-sdk/app_common/app_trace.h | 55 - .../Lib/nrf-sdk/app_common/app_uart.h | 286 ---- .../Lib/nrf-sdk/app_common/hal_transport.h | 227 --- .../Lib/nrf-sdk/app_common/hci_mem_pool.h | 132 -- .../app_common/hci_mem_pool_internal.h | 32 - .../Lib/nrf-sdk/app_common/hci_slip.h | 129 -- .../Lib/nrf-sdk/app_common/hci_transport.h | 220 --- .../Lib/nrf-sdk/app_common/pstorage.h | 381 ----- .../Lib/nrf-sdk/sd_common/app_util_platform.h | 110 -- .../TARGET_MCU_NRF51822/serial_api.c | 12 +- workspace_tools/targets.py | 22 +- 32 files changed, 1512 insertions(+), 2984 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h rename libraries/mbed/targets/{hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk => cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822}/nrf_delay.h (99%) rename libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/{system_nrf51822.c => system_nrf51.c} (54%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/crc16}/crc16.h (100%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/scheduler}/app_scheduler.h (85%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/util}/app_error.h (67%) mode change 100755 => 100644 rename libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/{nrf-sdk/app_common => nordic_sdk/components/libraries/util}/app_util.h (97%) mode change 100755 => 100644 delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s index 90f77553ba..ea211543df 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s @@ -62,7 +62,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD WDT_IRQHandler ;WDT DCD RTC1_IRQHandler ;RTC1 DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD LPCOMP_IRQHandler ;LPCOMP DCD SWI0_IRQHandler ;SWI0 DCD SWI1_IRQHandler ;SWI1 DCD SWI2_IRQHandler ;SWI2 @@ -85,19 +85,28 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Reset Handler -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address +NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask Reset_Handler PROC EXPORT Reset_Handler [WEAK] - IMPORT SystemInit + IMPORT SystemInit IMPORT __main + + MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk ORRS R2, R2, R1 STR R2, [R0] - LDR R0, =SystemInit + + LDR R0, =NRF_POWER_RAMONB_ADDRESS + LDR R2, [R0] + ORRS R2, R2, R1 + STR R2, [R0] + + LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 @@ -147,7 +156,7 @@ Default_Handler PROC EXPORT WDT_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] EXPORT QDEC_IRQHandler [WEAK] - EXPORT LPCOMP_COMP_IRQHandler [WEAK] + EXPORT LPCOMP_IRQHandler [WEAK] EXPORT SWI0_IRQHandler [WEAK] EXPORT SWI1_IRQHandler [WEAK] EXPORT SWI2_IRQHandler [WEAK] @@ -172,7 +181,7 @@ CCM_AAR_IRQHandler WDT_IRQHandler RTC1_IRQHandler QDEC_IRQHandler -LPCOMP_COMP_IRQHandler +LPCOMP_IRQHandler SWI0_IRQHandler SWI1_IRQHandler SWI2_IRQHandler diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h index 137286f6a7..b73fdadde8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h @@ -1,13 +1,13 @@ /* mbed Microcontroller Library - CMSIS * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * + * * A generic CMSIS include header, pulling in LPC407x_8x specifics */ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "nrf51822.h" +#include "nrf.h" #include "cmsis_nvic.h" #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h index f80068b65d..ab365b2a79 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h @@ -35,7 +35,7 @@ #define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 -#include "nrf51822.h" +#include "nrf51.h" #include "cmsis.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h index 9c64181ea7..18d70eb207 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h @@ -1,47 +1,107 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * The information contained herein is confidential property of Nordic - * Semiconductor ASA.Terms and conditions of usage are described in detail - * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - #ifndef _COMPILER_ABSTRACTION_H #define _COMPILER_ABSTRACTION_H /*lint ++flb "Enter library region" */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - #define __current_sp() __get_SP() + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!< weak keyword for ARM Compiler */ + #endif + + #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */ -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -static __INLINE unsigned int __current_sp(void) - { - register unsigned sp asm("sp"); - return sp; - } - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!> define weak function for IAR Compiler */ + #endif + + #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */ + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */ + #endif + + #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */ + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp asm("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */ + #endif + + #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */ + #endif /*lint --flb "Leave library region" */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h deleted file mode 100644 index 46235d4f5c..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _NORDIC_GLOBAL_H_ -#define _NORDIC_GLOBAL_H_ - -/* There are no global defines in mbed, so we need to define */ -/* mandatory conditional compilation flags here */ -//#define NRF51 -#ifndef DEBUG_NRF_USER -#define DEBUG_NRF_USER -#endif -#ifndef BLE_STACK_SUPPORT_REQD -#define BLE_STACK_SUPPORT_REQD -#endif -#ifndef BOARD_PCA10001 -#define BOARD_PCA10001 -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h new file mode 100644 index 0000000000..e77307f3f6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h @@ -0,0 +1,48 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_H +#define NRF_H + +#ifndef _WIN32 + +/* Family selection for main includes. NRF51 must be selected. */ +#ifdef NRF51 + #include "nrf51.h" + #include "nrf51_bitfields.h" +#else + #error "Device family must be defined. See nrf.h." +#endif /* NRF51 */ + +#include "compiler_abstraction.h" + +#endif /* _WIN32 */ + +#endif /* NRF_H */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h index 1027f03ef7..266d8f0ed1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h @@ -1,14 +1,46 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + +/****************************************************************************************************//** + * @file nRF51.h * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * nRF51 from Nordic Semiconductor. * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * @version V522 + * @date 31. October 2014 * - */ + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nRF51.xml' Version 522, + * + * @par Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -58,7 +90,7 @@ typedef enum { WDT_IRQn = 16, /*!< 16 WDT */ RTC1_IRQn = 17, /*!< 17 RTC1 */ QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ SWI0_IRQn = 20, /*!< 20 SWI0 */ SWI1_IRQn = 21, /*!< 21 SWI1 */ SWI2_IRQn = 22, /*!< 22 SWI2 */ @@ -77,16 +109,15 @@ typedef enum { /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ -/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */ +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< Cortex-M0 processor and core peripherals */ -#include "system_nrf51822.h" /*!< nRF51 System */ - +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nRF51 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -124,6 +155,24 @@ typedef struct { __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ } AMLI_RAMPRI_Type; +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK. */ + __IO uint32_t MOSI; /*!< Pin select for MOSI. */ + __IO uint32_t MISO; /*!< Pin select for MISO. */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ + __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ + __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ +} SPIM_TXD_Type; + typedef struct { __O uint32_t EN; /*!< Enable channel group. */ __O uint32_t DIS; /*!< Disable channel group. */ @@ -134,6 +183,15 @@ typedef struct { __IO uint32_t TEP; /*!< Channel task end-point. */ } PPI_CH_Type; +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part variant */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __I uint32_t RESERVED[3]; /*!< Reserved */ +} FICR_INFO_Type; + /* ================================================================================ */ /* ================ POWER ================ */ @@ -155,20 +213,26 @@ typedef struct { /*!< POWER Structure __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED3[61]; __IO uint32_t RESETREAS; /*!< Reset reason. */ - __I uint32_t RESERVED4[63]; + __I uint32_t RESERVED4[9]; + __I uint32_t RAMSTATUS; /*!< Ram status register. */ + __I uint32_t RESERVED5[53]; __O uint32_t SYSTEMOFF; /*!< System off register. */ - __I uint32_t RESERVED5[3]; + __I uint32_t RESERVED6[3]; __IO uint32_t POFCON; /*!< Power failure configuration. */ - __I uint32_t RESERVED6[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained register. */ - __I uint32_t RESERVED7; + __I uint32_t RESERVED8; __IO uint32_t RAMON; /*!< Ram on/off. */ - __I uint32_t RESERVED8[7]; + __I uint32_t RESERVED9[7]; __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register is a retained register. */ - __I uint32_t RESERVED9[12]; + __I uint32_t RESERVED10[3]; + __IO uint32_t RAMONB; /*!< Ram on/off. */ + __I uint32_t RESERVED11[8]; __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ + __I uint32_t RESERVED12[291]; + __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ } NRF_POWER_Type; @@ -193,16 +257,20 @@ typedef struct { /*!< CLOCK Structure __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */ - __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */ + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ __I uint32_t RESERVED2[124]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[64]; + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ - __I uint32_t RESERVED4[2]; + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ - __I uint32_t RESERVED5[63]; + __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is + triggered. */ + __I uint32_t RESERVED5[62]; __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ __I uint32_t RESERVED6[7]; __IO uint32_t CTIV; /*!< Calibration timer interval. */ @@ -225,9 +293,10 @@ typedef struct { /*!< MPU Structure __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ __I uint32_t RESERVED1[52]; - __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */ - __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */ + __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ + __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ } NRF_MPU_Type; @@ -299,17 +368,17 @@ typedef struct { /*!< RADIO Structure __I uint32_t RESERVED1[2]; __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */ __I uint32_t RESERVED2[53]; - __IO uint32_t SHORTS; /*!< Shortcut for the radio. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ __I uint32_t RESERVED3[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED4[61]; __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ - __I uint32_t RESERVED5; + __I uint32_t CD; /*!< Carrier detect. */ __I uint32_t RXMATCH; /*!< Received address. */ __I uint32_t RXCRC; /*!< Received CRC. */ - __IO uint32_t DAI; /*!< Device address match index. */ - __I uint32_t RESERVED6[60]; + __I uint32_t DAI; /*!< Device address match index. */ + __I uint32_t RESERVED5[60]; __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ __IO uint32_t FREQUENCY; /*!< Frequency. */ __IO uint32_t TXPOWER; /*!< Output power. */ @@ -327,23 +396,23 @@ typedef struct { /*!< RADIO Structure __IO uint32_t CRCINIT; /*!< CRC initial value. */ __IO uint32_t TEST; /*!< Test features enable register. */ __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ - __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */ - __I uint32_t RESERVED7; + __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ + __I uint32_t RESERVED6; __I uint32_t STATE; /*!< Current radio state. */ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ - __I uint32_t RESERVED8[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t BCC; /*!< Bit counter compare. */ - __I uint32_t RESERVED9[39]; + __I uint32_t RESERVED8[39]; __IO uint32_t DAB[8]; /*!< Device address base segment. */ __IO uint32_t DAP[8]; /*!< Device address prefix. */ __IO uint32_t DACNF; /*!< Device address match configuration. */ - __I uint32_t RESERVED10[56]; + __I uint32_t RESERVED9[56]; __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ - __I uint32_t RESERVED11[561]; + __I uint32_t RESERVED10[561]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_RADIO_Type; @@ -375,9 +444,8 @@ typedef struct { /*!< UART Structure __I uint32_t RESERVED4[7]; __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED6[63]; - __IO uint32_t INTEN; /*!< Interrupt enable register. */ + __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ + __I uint32_t RESERVED6[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED7[93]; @@ -390,7 +458,7 @@ typedef struct { /*!< UART Structure __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consummed. If read when no character + Once read the character is consumed. If read when no character available, the UART will stop working. */ __O uint32_t TXD; /*!< TXD register. */ __I uint32_t RESERVED10; @@ -424,7 +492,7 @@ typedef struct { /*!< SPI Structure __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ __I uint32_t RESERVED4; - __IO uint32_t RXD; /*!< RX data. */ + __I uint32_t RXD; /*!< RX data. */ __IO uint32_t TXD; /*!< TX data. */ __I uint32_t RESERVED5; __IO uint32_t FREQUENCY; /*!< SPI frequency */ @@ -462,26 +530,28 @@ typedef struct { /*!< TWI Structure __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ __I uint32_t RESERVED6[4]; __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ - __I uint32_t RESERVED7[49]; + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ + __I uint32_t RESERVED8[45]; __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED8[64]; + __I uint32_t RESERVED9[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED9[110]; + __I uint32_t RESERVED10[110]; __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED10[14]; + __I uint32_t RESERVED11[14]; __IO uint32_t ENABLE; /*!< Enable two-wire master. */ - __I uint32_t RESERVED11; + __I uint32_t RESERVED12; __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ - __I uint32_t RESERVED12[2]; - __IO uint32_t RXD; /*!< RX data register. */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RX data register. */ __IO uint32_t TXD; /*!< TX data register. */ - __I uint32_t RESERVED13; + __I uint32_t RESERVED14; __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ - __I uint32_t RESERVED14[24]; + __I uint32_t RESERVED15[24]; __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ - __I uint32_t RESERVED15[668]; + __I uint32_t RESERVED16[668]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_TWI_Type; @@ -522,11 +592,11 @@ typedef struct { /*!< SPIS Structure __I uint32_t RESERVED9[7]; __IO uint32_t RXDPTR; /*!< RX data pointer. */ __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ - __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ + __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ __I uint32_t RESERVED10; __IO uint32_t TXDPTR; /*!< TX data pointer. */ __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ - __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ + __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ __I uint32_t RESERVED11; __IO uint32_t CONFIG; /*!< Configuration register. */ __I uint32_t RESERVED12; @@ -538,6 +608,59 @@ typedef struct { /*!< SPIS Structure } NRF_SPIS_Type; +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI master with easyDMA 1. (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction. */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM. */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ + __I uint32_t RESERVED11; + __I uint32_t RXDDATA; /*!< RXD register. */ + __IO uint32_t TXDDATA; /*!< TXD register. */ + __I uint32_t RESERVED12; + __IO uint32_t FREQUENCY; /*!< SPI frequency. */ + __I uint32_t RESERVED13[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ + __I uint32_t RESERVED14; + SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED16[26]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED17[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIM_Type; + + /* ================================================================================ */ /* ================ GPIOTE ================ */ /* ================================================================================ */ @@ -605,7 +728,8 @@ typedef struct { /*!< TIMER Structure __O uint32_t TASKS_STOP; /*!< Stop Timer. */ __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ - __I uint32_t RESERVED0[12]; + __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ + __I uint32_t RESERVED0[11]; __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ __I uint32_t RESERVED1[60]; __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ @@ -656,7 +780,7 @@ typedef struct { /*!< RTC Structure __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ __I uint32_t RESERVED4[110]; - __IO uint32_t COUNTER; /*!< Current COUNTER value. */ + __I uint32_t COUNTER; /*!< Current COUNTER value. */ __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ __I uint32_t RESERVED5[13]; @@ -705,7 +829,7 @@ typedef struct { /*!< RNG Structure __I uint32_t RESERVED0[62]; __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ @@ -775,8 +899,8 @@ typedef struct { /*!< AAR Structure __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ __I uint32_t RESERVED5; __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 3 bytes must be reserved. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 3 bytes must be reserved. */ __I uint32_t RESERVED6[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_AAR_Type; @@ -802,7 +926,7 @@ typedef struct { /*!< CCM Structure __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -811,11 +935,11 @@ typedef struct { /*!< CCM Structure __I uint32_t RESERVED4[63]; __IO uint32_t ENABLE; /*!< CCM enable. */ __IO uint32_t MODE; /*!< Operation mode. */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */ - __IO uint32_t INPTR; /*!< Pointer to input packet. */ - __IO uint32_t OUTPTR; /*!< Pointer to output packet. */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 43 bytes must be reserved. */ + __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ + __IO uint32_t INPTR; /*!< Pointer to the input packet. */ + __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 43 bytes must be reserved. */ __I uint32_t RESERVED5[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_CCM_Type; @@ -871,7 +995,7 @@ typedef struct { /*!< QDEC Structure ACC register different than zero. */ __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -904,7 +1028,7 @@ typedef struct { /*!< QDEC Structure /** - * @brief Wakeup Comparator. (LPCOMP) + * @brief Low power comparator. (LPCOMP) */ typedef struct { /*!< LPCOMP Structure */ @@ -917,7 +1041,7 @@ typedef struct { /*!< LPCOMP Structure __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -935,44 +1059,6 @@ typedef struct { /*!< LPCOMP Structure } NRF_LPCOMP_Type; -/* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Comparator. (COMP) - */ - -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start the comparator. */ - __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */ - __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ - __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ - __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable the COMP. */ - __IO uint32_t PSEL; /*!< Input pin select. */ - __IO uint32_t REFSEL; /*!< Reference select. */ - __IO uint32_t EXTREFSEL; /*!< External reference select. */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */ - __IO uint32_t MODE; /*!< Mode configuration. */ - __I uint32_t RESERVED6[689]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_COMP_Type; - - /* ================================================================================ */ /* ================ SWI ================ */ /* ================================================================================ */ @@ -1048,7 +1134,13 @@ typedef struct { /*!< FICR Structure __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ __I uint32_t RESERVED2; __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ - __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */ + + union { + __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is + kept for backward compatinility purposes. Use SIZERAMBLOCKS + instead. */ + __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ + }; __I uint32_t RESERVED3[5]; __I uint32_t CONFIGID; /*!< Configuration identifier. */ __I uint32_t DEVICEID[2]; /*!< Device identifier. */ @@ -1058,9 +1150,12 @@ typedef struct { /*!< FICR Structure __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ __I uint32_t DEVICEADDR[2]; /*!< Device address. */ __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ - __I uint32_t RESERVED5[15]; + __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit + mode. */ + __I uint32_t RESERVED5[10]; __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. */ + FICR_INFO_Type INFO; /*!< Device info */ } NRF_FICR_Type; @@ -1140,6 +1235,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1_BASE 0x40004000UL #define NRF_TWI1_BASE 0x40004000UL #define NRF_SPIS1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL #define NRF_GPIOTE_BASE 0x40006000UL #define NRF_ADC_BASE 0x40007000UL #define NRF_TIMER0_BASE 0x40008000UL @@ -1155,7 +1251,6 @@ typedef struct { /*!< GPIO Structure #define NRF_RTC1_BASE 0x40011000UL #define NRF_QDEC_BASE 0x40012000UL #define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_COMP_BASE 0x40013000UL #define NRF_SWI_BASE 0x40014000UL #define NRF_NVMC_BASE 0x4001E000UL #define NRF_PPI_BASE 0x4001F000UL @@ -1180,6 +1275,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) @@ -1195,7 +1291,6 @@ typedef struct { /*!< GPIO Structure #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) @@ -1214,3 +1309,4 @@ typedef struct { /*!< GPIO Structure #endif /* nRF51_H */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h deleted file mode 100644 index 43e6bd3c31..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h +++ /dev/null @@ -1,27 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef NRF_H -#define NRF_H - -#include "nordic_global.h" -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "nrf51_bitfields.h" -#endif /* NRF_H */ - diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h index 8f88a8e5f8..52aa653943 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h @@ -1,22 +1,38 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - - #ifndef __NRF51_BITS_H #define __NRF51_BITS_H /*lint ++flb "Enter library region */ -//#include +#include /* Peripheral: AAR */ /* Description: Accelerated Address Resolver. */ @@ -213,124 +229,604 @@ /* Register: AMLI_RAMPRI_CPU0 */ /* Description: Configurable priority configuration register for CPU0. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_SPIS1 */ /* Description: Configurable priority configuration register for SPIS1. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_RADIO */ /* Description: Configurable priority configuration register for RADIO. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_ECB */ /* Description: Configurable priority configuration register for ECB. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_CCM */ /* Description: Configurable priority configuration register for CCM. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_AAR */ /* Description: Configurable priority configuration register for AAR. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption. */ /* Register: CCM_SHORTS */ -/* Description: Shortcut for the CCM. */ +/* Description: Shortcuts for the CCM. */ -/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */ +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ @@ -486,6 +982,15 @@ #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + /* Register: CLOCK_HFCLKSTAT */ /* Description: High frequency clock status. */ @@ -501,6 +1006,15 @@ #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + /* Register: CLOCK_LFCLKSTAT */ /* Description: Low frequency clock status. */ @@ -517,6 +1031,16 @@ #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK clock. */ @@ -540,197 +1064,8 @@ /* Bits 7..0 : External Xtal frequency selection. */ #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */ - - -/* Peripheral: COMP */ -/* Description: Comparator. */ - -/* Register: COMP_SHORTS */ -/* Description: Shortcut for the COMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ -#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Short-cut between UP event and STOP task. */ -#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Short-cut between DOWN event and STOP task. */ -#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Short-cut between RADY event and STOP task. */ -#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ -#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: COMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: COMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: COMP_RESULT */ -/* Description: Compare result. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: COMP_ENABLE */ -/* Description: Enable the COMP. */ - -/* Bits 1..0 : Enable or disable COMP. */ -#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */ -#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */ - -/* Register: COMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: COMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */ -#define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */ - -/* Register: COMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: COMP_TH */ -/* Description: Threshold configuration for hysteresis unit. */ - -/* Bits 13..8 : VDOWN configuration. */ -#define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */ -#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ - -/* Bits 5..0 : VUP configuration. */ -#define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */ -#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ - -/* Register: COMP_MODE */ -/* Description: Mode configuration. */ - -/* Bit 8 : Main operation mode. */ -#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ -#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */ -#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */ - -/* Bits 1..0 : Speed and power mode. */ -#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ -#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */ -#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */ -#define COMP_MODE_SP_High (2UL) /*!< High speed mode. */ - -/* Register: COMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ /* Peripheral: ECB */ @@ -821,6 +1156,66 @@ #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */ +#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant */ + +/* Bits 31..0 : Part variant */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */ +#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */ +#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */ + /* Peripheral: GPIO */ /* Description: General purpose input and output. */ @@ -2477,36 +2872,36 @@ /* Peripheral: LPCOMP */ -/* Description: Wakeup Comparator. */ +/* Description: Low power comparator. */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut for the LPCOMP. */ +/* Description: Shortcuts for the LPCOMP. */ -/* Bit 4 : Short-cut between CROSS event and STOP task. */ +/* Bit 4 : Shortcut between CROSS event and STOP task. */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 3 : Short-cut between UP event and STOP task. */ +/* Bit 3 : Shortcut between UP event and STOP task. */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 2 : Short-cut between DOWN event and STOP task. */ +/* Bit 2 : Shortcut between DOWN event and STOP task. */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 1 : Short-cut between RADY event and STOP task. */ +/* Bit 1 : Shortcut between RADY event and STOP task. */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ @@ -2613,13 +3008,13 @@ /* Bits 2..0 : Reference select. */ #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ /* Register: LPCOMP_EXTREFSEL */ @@ -2669,11 +3064,11 @@ #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ -/* Bit 19 : LPCOMP_COMP region configuration. */ -#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Bit 18 : QDEC region configuration. */ #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ @@ -2784,7 +3179,7 @@ #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Register: MPU_PROTENSET0 */ -/* Description: Protection bit enable set register for low addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 31. */ #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ @@ -3011,7 +3406,7 @@ #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_PROTENSET1 */ -/* Description: Protection bit enable set register for high addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 63. */ #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ @@ -3238,7 +3633,7 @@ #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable protection mechanism in debug mode. */ +/* Description: Disable erase and write protection mechanism in debug mode. */ /* Bit 0 : Disable protection mechanism in debug mode. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ @@ -3246,6 +3641,14 @@ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + /* Peripheral: NVMC */ /* Description: Non Volatile Memory Controller. */ @@ -3342,6 +3745,33 @@ #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + /* Register: POWER_SYSTEMOFF */ /* Description: System off register. */ @@ -3377,18 +3807,6 @@ /* Register: POWER_RAMON */ /* Description: Ram on/off. */ -/* Bit 19 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 18 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - /* Bit 17 : RAM block 1 behaviour in OFF mode. */ #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ @@ -3401,18 +3819,6 @@ #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ -/* Bit 3 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */ -#define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 2 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - /* Bit 1 : RAM block 1 behaviour in ON mode. */ #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ @@ -3428,12 +3834,39 @@ /* Register: POWER_RESET */ /* Description: Pin reset functionality configuration register. This register is a retained register. */ -/* Bit 0 : Enable pin reset in debug interface mode. */ +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + /* Register: POWER_DCDCEN */ /* Description: DCDC converter enable configuration register. */ @@ -3443,6 +3876,21 @@ #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + /* Peripheral: PPI */ /* Description: PPI controller. */ @@ -4372,15 +4820,15 @@ /* Description: Rotary decoder. */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut for the QDEC. */ +/* Description: Shortcuts for the QDEC. */ -/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */ +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */ +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ @@ -4501,9 +4949,9 @@ /* Register: QDEC_LEDPRE */ /* Description: Time LED is switched ON before the sample. */ -/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */ +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ /* Register: QDEC_ACCDBL */ /* Description: Accumulated double (error) transitions register. */ @@ -4533,7 +4981,7 @@ /* Description: The radio. */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut for the radio. */ +/* Description: Shortcuts for the radio. */ /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ @@ -4724,6 +5172,13 @@ #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ +/* Register: RADIO_CD */ +/* Description: Carrier detect. */ + +/* Bit 0 : Carrier detect. */ +#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ +#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ + /* Register: RADIO_RXMATCH */ /* Description: Received address. */ @@ -4741,7 +5196,7 @@ /* Register: RADIO_DAI */ /* Description: Device address match index. */ -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */ +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ @@ -4920,10 +5375,10 @@ /* Description: CRC configuration. */ /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ /* Bits 1..0 : CRC length. Decision point: START task. */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ @@ -4936,9 +5391,9 @@ /* Register: RADIO_CRCPOLY */ /* Description: CRC polynomial. */ -/* Bits 23..1 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ /* Register: RADIO_CRCINIT */ /* Description: CRC initial value. */ @@ -4951,16 +5406,16 @@ /* Description: Test features enable register. */ /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ /* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ /* Register: RADIO_TIFS */ /* Description: Inter Frame Spacing in microseconds. */ @@ -4995,9 +5450,9 @@ /* Register: RADIO_DATAWHITEIV */ /* Description: Data whitening initial value. */ -/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ /* Register: RADIO_DAP */ /* Description: Device address prefix. */ @@ -5092,28 +5547,28 @@ /* Register: RADIO_OVERRIDE0 */ /* Description: Trim value override register 0. */ -/* Bits 31..0 : Trim value override register 0. */ +/* Bits 31..0 : Trim value override 0. */ #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ /* Register: RADIO_OVERRIDE1 */ /* Description: Trim value override register 1. */ -/* Bits 31..0 : Trim value override register 1. */ +/* Bits 31..0 : Trim value override 1. */ #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ /* Register: RADIO_OVERRIDE2 */ /* Description: Trim value override register 2. */ -/* Bits 31..0 : Trim value override register 2. */ +/* Bits 31..0 : Trim value override 2. */ #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ /* Register: RADIO_OVERRIDE3 */ /* Description: Trim value override register 3. */ -/* Bits 31..0 : Trim value override register 3. */ +/* Bits 31..0 : Trim value override 3. */ #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ @@ -5126,7 +5581,7 @@ #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ -/* Bits 27..0 : Trim value override register 4. */ +/* Bits 27..0 : Trim value override 4. */ #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ @@ -5144,9 +5599,9 @@ /* Description: Random Number Generator. */ /* Register: RNG_SHORTS */ -/* Description: Shortcut for the RNG. */ +/* Description: Shortcuts for the RNG. */ -/* Bit 0 : Short-cut between VALRDY event and STOP task. */ +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ @@ -5542,6 +5997,211 @@ #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts for SPIM. */ + +/* Bit 17 : Shortcut between END event and START task. */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on END event. */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on END event. */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_RXDDATA */ +/* Description: RXD register. */ + +/* Bits 7..0 : RX data received. Double buffered. */ +#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPIM_TXDDATA */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data to send. Double buffered. */ +#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + /* Peripheral: SPIS */ /* Description: SPI slave 1. */ @@ -5905,6 +6565,13 @@ /* Register: TWI_INTENSET */ /* Description: Interrupt enable set register. */ +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + /* Bit 14 : Enable interrupt on BB event. */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ @@ -5943,6 +6610,13 @@ /* Register: TWI_INTENCLR */ /* Description: Interrupt enable clear register. */ +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + /* Bit 14 : Disable interrupt on BB event. */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ @@ -6049,7 +6723,7 @@ /* Description: Universal Asynchronous Receiver/Transmitter. */ /* Register: UART_SHORTS */ -/* Description: Shortcuts for TWI. */ +/* Description: Shortcuts for UART. */ /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ @@ -6194,7 +6868,7 @@ #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ /* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ /* Bits 7..0 : RX data from previous transfer. Double buffered. */ #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h rename to libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h index b97e96924b..c9b0123341 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h @@ -47,7 +47,7 @@ __ASM ( #elif defined ( __GNUC__ ) static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) { - do + do { __ASM volatile ( "NOP\n\t" diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c similarity index 54% rename from libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c rename to libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c index 3664b28158..cb98405feb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c @@ -1,25 +1,42 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2015 Nordic Semiconductor. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. */ +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ #include #include -#include "nrf51822.h" -#include "system_nrf51822.h" +#include "nrf.h" +#include "system_nrf51.h" + +/*lint ++flb "Enter library region" */ #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ @@ -45,20 +62,20 @@ void SystemInit(void) /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. It can also be done in the application main() function. */ - // Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required - // to enable the use of peripherals" found at Product Anomaly document for your device found at - // https://www.nordicsemi.com/. The side effect of executing these instructions in the devices - // that do not need it is that the new peripherals in the second generation devices (LPCOMP for - // example) will not be available. + /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required + to enable the use of peripherals" found at Product Anomaly document for your device found at + https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + that do not need it is that the new peripherals in the second generation devices (LPCOMP for + example) will not be available. */ if (is_manual_peripheral_setup_needed()) { *(uint32_t volatile *)0x40000504 = 0xC007FFDF; *(uint32_t volatile *)0x40006C18 = 0x00008000; } - // Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - // register is incorrect" found at Product Anomaly document four your device found at - // https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG + register is incorrect" found at Product Anomaly document four your device found at + https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ if (is_disabled_in_debug_needed()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; @@ -114,3 +131,4 @@ static bool is_disabled_in_debug_needed(void) return false; } +/*lint --flb "Leave library region" */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h new file mode 100644 index 0000000000..ae613609dd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h @@ -0,0 +1,68 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef SYSTEM_NRF51_H +#define SYSTEM_NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF51_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h deleted file mode 100644 index 4c8ef343a6..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h old mode 100755 new mode 100644 similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h old mode 100755 new mode 100644 similarity index 85% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h index 53ff42df3d..05117cb48f --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h @@ -19,7 +19,7 @@ * @brief The scheduler is used for transferring execution from the interrupt context to the main * context. * - * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events * when using the Scheduler. * * @section app_scheduler_req Requirements: @@ -39,8 +39,10 @@ * scheduler's queue. The app_sched_execute() function will pull this event and call its * handler in the main context. * - * For an example usage of the scheduler, please see the implementations of + * @if (SD_S110 && !SD_S310) + * For an example usage of the scheduler, see the implementations of * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif * * @image html scheduler_working.jpg The high level design of the scheduler */ @@ -95,7 +97,7 @@ typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_si * @param[in] max_event_size Maximum size of events to be passed through the scheduler. * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of * events that can be scheduled for execution). - * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer * must be aligned to a 4 byte boundary. * @@ -120,7 +122,7 @@ void app_sched_execute(void); * @details Puts an event into the event queue. * * @param[in] p_event_data Pointer to event data to be scheduled. - * @param[in] p_event_size Size of event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. * @param[in] handler Event handler to receive the event. * * @return NRF_SUCCESS on success, otherwise an error code. @@ -129,6 +131,22 @@ uint32_t app_sched_event_put(void * p_event_data, uint16_t event_size, app_sched_event_handler_t handler); +#ifdef APP_SCHEDULER_WITH_PAUSE +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + */ +void app_sched_resume(void); +#endif #endif // APP_SCHEDULER_H__ /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h old mode 100755 new mode 100644 similarity index 67% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h index c4d0e9a974..616634c887 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h @@ -1,5 +1,6 @@ /* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. * + * The information contained herein is property of Nordic Semiconductor ASA. * Terms and conditions of usage are described in detail in NORDIC * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. * @@ -8,7 +9,7 @@ * the file. * */ - + /** @file * * @defgroup app_error Common application error handler @@ -25,36 +26,35 @@ #include #include "nrf_error.h" -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for error handling, which is called when an error has occurred. +/**@brief Function for error handling, which is called when an error has occurred. * * @param[in] error_code Error code supplied to the handler. * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. + * @param[in] p_file_name Pointer to the file name. */ void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); -#ifdef __cplusplus -} -#endif - -/**@brief Macro for calling error handler function. +/**@brief Macro for calling error handler function. * * @param[in] ERR_CODE Error code supplied to the error handler. */ +#ifdef DEBUG #define APP_ERROR_HANDLER(ERR_CODE) \ do \ { \ - /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \ + app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ } while (0) - -/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. +#else +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), 0, 0); \ + } while (0) +#endif +/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. * * @param[in] ERR_CODE Error code supplied to the error handler. - */ + */ #define APP_ERROR_CHECK(ERR_CODE) \ do \ { \ @@ -63,21 +63,21 @@ void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p { \ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ } \ - } while (0) - -/**@brief Macro for calling error handler function if supplied boolean value is false. + } while (0) + +/**@brief Macro for calling error handler function if supplied boolean value is false. * * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. */ -#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ - do \ - { \ - const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ - if (!LOCAL_BOOLEAN_VALUE) \ - { \ - APP_ERROR_HANDLER(0); \ - } \ - } while (0) +#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ + do \ + { \ + const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ + if (!LOCAL_BOOLEAN_VALUE) \ + { \ + APP_ERROR_HANDLER(0); \ + } \ + } while (0) #endif // APP_ERROR_H__ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h old mode 100755 new mode 100644 similarity index 97% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h index f6405439df..c4b1022eb1 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h @@ -86,9 +86,9 @@ typedef struct */ #define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) -/**@brief To convert ticks to millisecond - * @param[in] time Number of millseconds that needs to be converted. - * @param[in] resolution Units to be converted. +/**@brief To convert milliseconds to ticks. + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. */ #define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h deleted file mode 100755 index 5ddff8960d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h +++ /dev/null @@ -1,187 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_button Button Handler - * @{ - * @ingroup app_common - * - * @brief Buttons handling module. - * - * @details The button handler uses the @ref app_gpiote to detect that a button has been - * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler. - * The button will only be reported as pushed if the corresponding pin is still active when - * the timer expires. If there is a new GPIOTE event while the timer is running, the timer - * is restarted. - * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note The app_button module uses the app_timer module. The user must ensure that the queue in - * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations - * which will be executed on each event from GPIOTE module (2 operations), as well as other - * app_timer operations queued simultaneously in the application. - * - * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_BUTTON_H__ -#define APP_BUTTON_H__ - -#include -#include -#include "app_error.h" -#include "app_scheduler.h" -#include "nrf_gpio.h" - -#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */ -#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */ -#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */ -#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */ - -/**@brief Button event handler type. */ -typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action); - -/**@brief Type of function for passing events from the Button Handler module to the scheduler. */ -typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action); - -/**@brief Button configuration structure. */ -typedef struct -{ - uint8_t pin_no; /**< Pin to be used as a button. */ - uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */ - nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */ - app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */ -} app_button_cfg_t; - -/**@brief Pin transition direction struct. */ -typedef struct -{ - uint32_t high_to_low; /**Pin went from high to low */ - uint32_t low_to_high; /**Pin went from low to high */ -} pin_transition_t; - -/**@brief Macro for initializing the Button Handler module. - * - * @details It will initialize the specified pins as buttons, and configure the Button Handler - * module as a GPIOTE user (but it will not enable button detection). It will also connect - * the Button Handler module to the scheduler (if specified). - * - * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be - * static!). - * @param[in] BUTTON_COUNT Number of buttons. - * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - */ -/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \ - do \ - { \ - uint32_t ERR_CODE = app_button_init((BUTTONS), \ - (BUTTON_COUNT), \ - (DETECTION_DELAY), \ - (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the Buttons. - * - * @details This function will initialize the specified pins as buttons, and configure the Button - * Handler module as a GPIOTE user (but it will not enable button detection). - * - * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take - * care of connecting the Buttons module to the scheduler (if specified). - * - * @note app_button_enable() function must be called in order to enable the button detection. - * - * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!). - * @param[in] button_count Number of buttons. - * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to - * app_button_evt_schedule() to connect to the scheduler. Set to - * NULL to make the Buttons module call the event handler directly - * from the delayed button push detection timeout handler. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -uint32_t app_button_init(app_button_cfg_t * p_buttons, - uint8_t button_count, - uint32_t detection_delay, - app_button_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for enabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_enable(void); - -/**@brief Function for disabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_disable(void); - -/**@brief Function for checking if a button is currently being pushed. - * - * @param[in] pin_no Button pin to be checked. - * @param[out] p_is_pushed Button state. - * - * @retval NRF_SUCCESS State successfully read. - * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no. - */ -uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed); - - -// Type and functions for connecting the Buttons module to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_button_handler_t button_handler; - uint8_t pin_no; - uint8_t button_action; -} app_button_event_t; - -static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size) -{ - app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t)); - p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action); -} - -static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action) -{ - app_button_event_t buttons_event; - - buttons_event.button_handler = button_handler; - buttons_event.pin_no = pin_no; - buttons_event.button_action = button_action; - - return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get); -} -/**@endcond */ - -#endif // APP_BUTTON_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h deleted file mode 100755 index 4825379c61..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_fifo FIFO implementation - * @{ - * @ingroup app_common - * - * @brief FIFO implementation. - */ - -#ifndef APP_FIFO_H__ -#define APP_FIFO_H__ - -#include -#include -#include "nrf_error.h" - -/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next. - * Also it keeps the information about which memory is allocated for the buffer - * and its size. This needs to be initialized by app_fifo_init() before use. - */ -typedef struct -{ - uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ - uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ - volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ - volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ -} app_fifo_t; - -/**@brief Function for initializing the FIFO. - * - * @param[out] p_fifo FIFO object. - * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two. - * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. - * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. - */ -uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); - -/**@brief Function for adding an element to the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[in] byte Data byte to add to the FIFO. - * - * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. - * @retval NRF_ERROR_NO_MEM If the FIFO is full. - */ -uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); - -/**@brief Function for getting the next element from the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[out] p_byte Byte fetched from the FIFO. - * - * @retval NRF_SUCCESS If an element was returned. - * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue. - */ -uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); - -/**@brief Function for flushing the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * - * @retval NRF_SUCCESS If the FIFO flushed successfully. - */ -uint32_t app_fifo_flush(app_fifo_t * p_fifo); - -#endif // APP_FIFO_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h deleted file mode 100755 index 4a20776f53..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h +++ /dev/null @@ -1,226 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_gpiote GPIOTE Handler - * @{ - * @ingroup app_common - * - * @brief GPIOTE handler module. - * - * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt, - * each user defining a set of pins able to generate events to the user. - * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler - * of each user for which at least one of the pins generated an event. - * - * The GPIOTE users are responsible for configuring all their corresponding pins, except - * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled. - * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled, - * and also while it is enabled. - * - * The module specifies on which pins events should be generated if the pin(s) goes - * from low->high or high->low or both directions. - * - * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will - * be called directly from the GPIOTE interrupt handler. - * - * @warning If multiple users registers for the same pins the behavior for those pins are undefined. - */ - -#ifndef APP_GPIOTE_H__ -#define APP_GPIOTE_H__ - -#include -#include -// #include "nrf.h" -#include "app_error.h" -#include "app_util.h" - -#ifdef __cpluplus -extern "C" { -#endif - -#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */ -#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */ - -/**@brief Compute number of bytes required to hold the GPIOTE data structures. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @return Required buffer size (in bytes). - */ -#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE) - -typedef uint8_t app_gpiote_user_id_t; - -/**@brief GPIOTE event handler type. */ -typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high, - uint32_t event_pins_high_to_low); - -/**@brief GPIOTE input event handler type. */ -typedef void (*app_gpiote_input_event_handler_t)(void); - -/**@brief Macro for initializing the GPIOTE module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the module, - * making sure that the buffer is correctly aligned. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_GPIOTE_INIT(MAX_USERS) \ - do \ - { \ - static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\ - uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the GPIOTE module. - * - * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will - * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly). - * - * @param[in] max_users Maximum number of GPIOTE users. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote - * module. The size of the buffer can be computed using the - * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to - * a 4 byte boundary. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary). - */ -uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer); - -/**@brief Function for registering a GPIOTE user. - * - * @param[out] p_user_id Id for the new GPIOTE user. - * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user - * when state is changed from low->high. - * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user - * when state is changed from high->low. - * @param[in] event_handler Pointer to function to be executed when an event occurs. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary). - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users - * than defined when the GPIOTE module was initialized in - * @ref app_gpiote_init. - */ -uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id, - uint32_t pins_low_to_high_mask, - uint32_t pins_high_to_low_mask, - app_gpiote_event_handler_t event_handler); - -/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @retval NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id); - -/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id); - -/**@brief Function for getting the state of the pins which are registered for the specified user. - * - * @param[in] user_id Id of user to check. - * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to - * the specified user. All bits corresponding to pins in the state - * 'high' will have value '1', all others will have value '0'. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins); - -/**@brief Function for registering event handlers for GPIOTE IN events. - * - * @param[in] channel GPIOTE channel [0..3]. - * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events. - * @param[in] polarity Specify operation on input that shall trigger IN event. - * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_register(const uint8_t channel, - const uint32_t pin, - const uint32_t polarity, - app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handlers for GPIOTE IN events. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel); - -/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt. - * - * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_unregister(void); - -/**@brief Function for enabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_enable_interrupts(void); - -/**@brief Function for disabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_disable_interrupts(void); - -#ifdef __cpluplus -} -#endif - -#endif // APP_GPIOTE_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h deleted file mode 100755 index b2a3c75589..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h +++ /dev/null @@ -1,313 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_timer Application Timer - * @{ - * @ingroup app_common - * - * @brief Application timer functionality. - * - * @details It enables the application to create multiple timer instances based on the RTC1 - * peripheral. Checking for timeouts and invokation of user timeout handlers is performed - * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). - * Both interrupt handlers are running in APP_LOW priority level. - * - * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, - * and the software interrupt is triggered. The actual timer start/stop operation is - * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, - * if the application code calling the timer function is running in APP_LOW or APP_HIGH, - * the timer operation will not be performed until the application handler has returned. - * This will be the case e.g. when stopping a timer from a timeout handler when not using - * the scheduler. - * - * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_TIMER_H__ -#define APP_TIMER_H__ - -#include -#include -#include -#include "app_error.h" -#include "app_util.h" -#include "app_scheduler.h" -#include "compiler_abstraction.h" - -#ifdef __cplusplus -extern "C" { -#endif // #ifdef __cplusplus - -#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ -#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ - -#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */ - -#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ - -/**@brief Compute number of bytes required to hold the application timer data structures. - * - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution. - * NOTE: Due to the queue implementation, this size must be one more - * than the size that is actually needed. - * - * @return Required application timer buffer size (in bytes). - */ -#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \ - ( \ - ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \ - + \ - ( \ - APP_TIMER_INT_LEVELS \ - * \ - (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \ - ) \ - ) - -/**@brief Convert milliseconds to timer ticks. - * - * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are - * constants (i.e. defines), the computation will be done by the preprocessor. - * - * @param[in] MS Milliseconds. - * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was - * passed to APP_TIMER_INIT()). - * - * @note When using this macro, it is the responsibility of the developer to ensure that the - * values provided as input result in an output value that is supported by the - * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the - * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768. - * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a - * ticks value that is not supported by this module. - * - * @return Number of timer ticks. - */ -#define APP_TIMER_TICKS(MS, PRESCALER)\ - ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000)) - -/**@brief Timer id type. */ -typedef uint32_t app_timer_id_t; - -#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */ - -/**@brief Application timeout handler type. */ -typedef void (*app_timer_timeout_handler_t)(void * p_context); - -/**@brief Type of function for passing events from the timer module to the scheduler. */ -typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler, - void * p_context); - -/**@brief Timer modes. */ -typedef enum -{ - APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ - APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ -} app_timer_mode_t; - -/**@brief Macro for initializing the application timer module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the timer, - * making sure that the buffer is correctly aligned. It will also connect the timer module - * to the scheduler (if specified). - * - * @note This module assumes that the LFCLK is already running. If it isn't, the module will - * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll - * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function - * for an example of how to do this. If you use a softdevice, the LFCLK is started on - * softdevice init. - * - * - * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the - * timer tick rate. Set to 0 for no prescaling. - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \ - do \ - { \ - static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1), \ - sizeof(uint32_t))]; \ - uint32_t ERR_CODE = app_timer_init((PRESCALER), \ - (MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1, \ - APP_TIMER_BUF, \ - (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the timer module. - * - * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both - * allocate the buffers needed by the timer module (including aligning the buffers correctly, - * and also take care of connecting the timer module to the scheduler (if specified). - * - * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. - * @param[in] max_timers Maximum number of timers that can be created at any given time. - * @param[in] op_queues_size Size of queues holding timer operations that are pending - * execution. NOTE: Due to the queue implementation, this size must - * be one more than the size that is actually needed. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer - * module. The size of the buffer can be computed using the - * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a - * 4 byte boundary. - * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to - * app_timer_evt_schedule() to connect to the scheduler. Set to NULL - * to make the timer module call the timeout handler directly from - * the timer interrupt handler. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary or NULL). - */ -uint32_t app_timer_init(uint32_t prescaler, - uint8_t max_timers, - uint8_t op_queues_size, - void * p_buffer, - app_timer_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for creating a timer instance. - * - * @param[out] p_timer_id Id of the newly created timer. - * @param[in] mode Timer mode. - * @param[in] timeout_handler Function to be executed when the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully created. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached. - * - * @note This function does the timer allocation in the caller's context. It is also not protected - * by a critical region. Therefore care must be taken not to call it from several interrupt - * levels simultaneously. - */ -uint32_t app_timer_create(app_timer_id_t * p_timer_id, - app_timer_mode_t mode, - app_timer_timeout_handler_t timeout_handler); - -/**@brief Function for starting a timer. - * - * @param[in] timer_id Id of timer to start. - * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event - * (minimum 5 ticks). - * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when - * the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully started. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - * - * @note The minimum timeout_ticks value is 5. - * @note For multiple active timers, timeouts occurring in close proximity to each other (in the - * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. - * @note When calling this method on a timer which is already running, the second start operation - * will be ignored. - */ -uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); - -/**@brief Function for stopping the specified timer. - * - * @param[in] timer_id Id of timer to stop. - * - * @retval NRF_SUCCESS Timer was successfully stopped. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop(app_timer_id_t timer_id); - -/**@brief Function for stopping all running timers. - * - * @retval NRF_SUCCESS All timers were successfully stopped. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop_all(void); - -/**@brief Function for returning the current value of the RTC1 counter. The - * value includes overflow bits to extend the range to 64-bits. - * - * @param[out] p_ticks Current value of the RTC1 counter. - * - * @retval NRF_SUCCESS Counter was successfully read. - */ -uint32_t app_timer_cnt_get(uint64_t * p_ticks); - -/**@brief Function for computing the difference between two RTC1 counter values. - * - * @param[in] ticks_to Value returned by app_timer_cnt_get(). - * @param[in] ticks_from Value returned by app_timer_cnt_get(). - * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to. - * - * @retval NRF_SUCCESS Counter difference was successfully computed. - */ -uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, - uint32_t ticks_from, - uint32_t * p_ticks_diff); - - -// Type and functions for connecting the timer to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_timer_timeout_handler_t timeout_handler; - void * p_context; -} app_timer_event_t; - -static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size) -{ - app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); - p_timer_event->timeout_handler(p_timer_event->p_context); -} - -static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, - void * p_context) -{ - app_timer_event_t timer_event; - - timer_event.timeout_handler = timeout_handler; - timer_event.p_context = p_context; - - return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get); -} -/**@endcond */ - -#ifdef __cplusplus -} -#endif // #ifdef __cplusplus - -#endif // APP_TIMER_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h deleted file mode 100755 index 6e755b4b2c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef __DEBUG_H_ -#define __DEBUG_H_ - -#include -#include - -/** - * @defgroup app_trace Debug Logger - * @ingroup app_common - * @{ - * @brief Enables debug logs/ trace over UART. - * @details Enables debug logs/ trace over UART. Tracing is enabled only if - * ENABLE_DEBUG_LOG_SUPPORT is defined in the project. - */ -#ifdef ENABLE_DEBUG_LOG_SUPPORT -/** - * @brief Module Initialization. - * - * @details Initializes the module to use UART as trace output. - * - * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups). - * Do not call this function if UART is configured from a higher level in the application. - */ -void app_trace_init(void); - -/** - * @brief Log debug messages. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @note Though this is currently a macro, it should be used used and treated as function. - */ -#define app_trace_log printf - -/** - * @brief Dump auxiliary byte buffer to the debug trace. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @param[in] p_buffer Buffer to be dumped on the debug trace. - * @param[in] len Size of the buffer. - */ -void app_trace_dump(uint8_t * p_buffer, uint32_t len); - -#else // ENABLE_DEBUG_LOG_SUPPORT - -#define app_trace_init(...) -#define app_trace_log(...) -#define app_trace_dump(...) - -#endif // ENABLE_DEBUG_LOG_SUPPORT - -/** @} */ - -#endif //__DEBUG_H_ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h deleted file mode 100755 index 39ec3c1ce8..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h +++ /dev/null @@ -1,286 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_uart UART module - * @{ - * @ingroup app_common - * - * @brief UART module interface. - */ - -#ifndef APP_UART_H__ -#define APP_UART_H__ - -#include -#include -#include "app_util_platform.h" - -#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ - -/**@brief UART Flow Control modes for the peripheral. - */ -typedef enum -{ - APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ - APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ - APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */ -} app_uart_flow_control_t; - -/**@brief UART communication structure holding configuration settings for the peripheral. - */ -typedef struct -{ - uint8_t rx_pin_no; /**< RX pin number. */ - uint8_t tx_pin_no; /**< TX pin number. */ - uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ - uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ - app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ -} app_uart_comm_params_t; - -/**@brief UART buffer for transmitting/receiving data. - */ -typedef struct -{ - uint8_t * rx_buf; /**< Pointer to the RX buffer. */ - uint32_t rx_buf_size; /**< Size of the RX buffer. */ - uint8_t * tx_buf; /**< Pointer to the TX buffer. */ - uint32_t tx_buf_size; /**< Size of the TX buffer. */ -} app_uart_buffers_t; - -/**@brief Enumeration describing current state of the UART. - * - * @details The connection state can be fetched by the application using the function call - * @ref app_uart_get_connection_state. - * When hardware flow control is used - * - APP_UART_CONNECTED: Communication is ongoing. - * - APP_UART_DISCONNECTED: No communication is ongoing. - * - * When no hardware flow control is used - * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted. - */ -typedef enum -{ - APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */ - APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */ -} app_uart_connection_state_t; - -/**@brief Enumeration which defines events used by the UART module upon data reception or error. - * - * @details The event type is used to indicate the type of additional information in the event - * @ref app_uart_evt_t. - */ -typedef enum -{ - APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ - APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ - APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ - APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ - APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ -} app_uart_evt_type_t; - -/**@brief Struct containing events from the UART module. - * - * @details The app_uart_evt_t is used to notify the application of asynchronous events when data - * are received on the UART peripheral or in case an error occured during data reception. - */ -typedef struct -{ - app_uart_evt_type_t evt_type; /**< Type of event. */ - union - { - uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */ - uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - } data; -} app_uart_evt_t; - -/**@brief Function for handling app_uart event callback. - * - * @details Upon an event in the app_uart module this callback function will be called to notify - * the applicatioon about the event. - * - * @param[in] p_app_uart_event Pointer to UART event. - */ - - -typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); - -/**@brief Macro for safe initialization of the UART module in a single user instance when using - * a FIFO together with UART. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow - * control is enabled, it must only be called once. - */ -#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - app_uart_buffers_t buffers; \ - static uint8_t rx_buf[RX_BUF_SIZE]; \ - static uint8_t tx_buf[TX_BUF_SIZE]; \ - \ - buffers.rx_buf = rx_buf; \ - buffers.rx_buf_size = sizeof (rx_buf); \ - buffers.tx_buf = tx_buf; \ - buffers.tx_buf_size = sizeof (tx_buf); \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Macro for safe initialization of the UART module in a single user instance. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates registers the module as a GPIOTE user when flow control is - * enabled, it must only be called once. - */ -#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART - * module are needed. - * - * @details This initialization will return a UART user id for the caller. The UART user id must be - * used upon re-initialization of the UART or closing of the module for the user. - * If single instance usage is needed, the APP_UART_INIT() macro should be used instead. - * - * @note Normally single instance initialization should be done using the APP_UART_INIT() or - * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as - * that will allocate the buffers needed by the UART module (including aligning the buffer - * correctly). - - * @param[in] p_comm_params Pin and communication parameters. - * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. - * @param[in] error_handler Function to be called in case of an error. - * @param[in] app_irq_priority Interrupt priority level. - * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if - * re-initialization and/or closing of the UART module is needed. - * If the value pointed to by p_uart_uid is zero, this is - * considdered a first time initialization. Otherwise this is - * considered a re-initialization for the user with id *p_uart_uid. - * - * @retval NRF_SUCCESS If successful initialization. - * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. - * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. - * - * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow - * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur. - * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering - * the UART module as a user. - * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when - * registering the UART module as a user. - * Or the value pointed to by *p_uart_uid is not a valid - * GPIOTE number. - * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. - */ -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t error_handler, - app_irq_priority_t irq_priority, - uint16_t * p_uart_uid); - -/**@brief Function for getting a byte from the UART. - * - * @details This function will get the next byte from the RX buffer. If the RX buffer is empty - * an error code will be returned and the app_uart module will generate an event upon - * reception of the first byte which is added to the RX buffer. - * - * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. - * - * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. - * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. - */ -uint32_t app_uart_get(uint8_t * p_byte); - -/**@brief Function for putting a byte on the UART. - * - * @details This call is non-blocking. - * - * @param[in] byte Byte to be transmitted on the UART. - * - * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission. - * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. - * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal - * is high for a long period and the buffer fills up. - */ -uint32_t app_uart_put(uint8_t byte); - -/**@brief Function for getting the current state of the UART. - * - * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED. - * - * When using flow control the state will be controlled by the CTS. If CTS is set active - * by the remote side, or the app_uart module is in the process of transmitting a byte, - * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart - * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register - * is fully transmitted. - * - * Internal states in the state machine are mapped to the general connected/disconnected - * states in the following ways: - * - * - UART_ON = CONNECTED - * - UART_READY = CONNECTED - * - UART_WAIT = CONNECTED - * - UART_OFF = DISCONNECTED. - * - * @param[out] p_connection_state Current connection state of the UART. - * - * @retval NRF_SUCCESS The connection state was succesfully retrieved. - */ -uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state); - -/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). - * This function does nothing if FIFO is not used. - * - * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). - */ -uint32_t app_uart_flush(void); - -/**@brief Function for closing the UART module. - * - * @details This function will close any on-going UART transmissions and disable itself in the - * GPTIO module. - * - * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the - * UART id returned on initialization and which is currently in use. - - * @retval NRF_SUCCESS If successfully closed. - * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from - * the current active user. - */ -uint32_t app_uart_close(uint16_t app_uart_id); - - -#endif //APP_UART_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h deleted file mode 100755 index 8dcc025aab..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h +++ /dev/null @@ -1,227 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include -#include "nrf_error.h" - -#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */ - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc - * function. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through - * hci_transport_tx_alloc function. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h deleted file mode 100755 index bc178d0bac..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h +++ /dev/null @@ -1,132 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool Memory pool - * @{ - * @ingroup app_common - * - * @brief Memory pool implementation - * - * Memory pool implementation, based on circular buffer data structure, which supports asynchronous - * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers. - * The memory managed by the pool is allocated from static storage instead of heap. The internal - * design of the circular buffer implementing the RX memory layout is illustrated in the picture - * below. - * - * @image html memory_pool.png "Circular buffer design" - * - * The expected call order for the RX APIs is as follows: - * - hci_mem_pool_rx_produce - * - hci_mem_pool_rx_data_size_set - * - hci_mem_pool_rx_extract - * - hci_mem_pool_rx_consume - * - * @warning If the above mentioned expected call order is violated the end result can be undefined. - * - * \par Component specific configuration options - * - * The following compile time configuration options are available to suit various implementations: - * - TX_BUF_SIZE TX buffer size in bytes. - * - RX_BUF_SIZE RX buffer size in bytes. - * - RX_BUF_QUEUE_SIZE RX buffer element size. - */ - -#ifndef HCI_MEM_POOL_H__ -#define HCI_MEM_POOL_H__ - -#include -#include "nrf_error.h" - -/**@brief Function for opening the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_open(void); - -/**@brief Function for closing the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_close(void); - -/**@brief Function for allocating requested amount of TX memory. - * - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer); - -/**@brief Function for freeing previously allocated TX memory. - * - * @note Memory management follows the FIFO principle meaning that free() order must match the - * alloc(...) order, which is the reason for omitting exact memory block identifier as an - * input parameter. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_mem_pool_tx_free(void); - -/**@brief Function for producing a free RX memory block for usage. - * - * @note Upon produce request amount being 0, NRF_SUCCESS is returned. - * - * @param[in] length Amount, in bytes, of free memory to be produced. - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Free RX memory block produced. - * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer); - -/**@brief Function for setting the length of the last produced RX memory block. - * - * @warning If call to this API is omitted the end result is that the following call to - * mem_pool_rx_extract will return incorrect data in the p_length output parameter. - * - * @param[in] length Amount, in bytes, of actual memory used. - * - * @retval NRF_SUCCESS Operation success. Length was set. - */ -uint32_t hci_mem_pool_rx_data_size_set(uint32_t length); - -/**@brief Function for extracting a packet, which has been filled with read data, for further - * processing. - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for freeing previously extracted packet, which has been filled with read data. - * - * @param[in] p_buffer Pointer to consumed buffer. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer); - -#endif // HCI_MEM_POOL_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h deleted file mode 100755 index f1fa77fea6..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool_internal Memory Pool Internal - * @{ - * @ingroup memory_pool - * - * @brief Memory pool internal definitions - */ - -#ifndef MEM_POOL_INTERNAL_H__ -#define MEM_POOL_INTERNAL_H__ - -#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */ -#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */ - -#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */ - -#endif // MEM_POOL_INTERNAL_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h deleted file mode 100755 index ad26f3be20..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h +++ /dev/null @@ -1,129 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup hci_slip SLIP module - * @{ - * @ingroup app_common - * - * @brief SLIP layer for supporting packet framing in HCI transport. - * - * @details This module implements SLIP packet framing as described in the Bluetooth Core - * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer. - * - * SLIP framing ensures that all packets sent on the UART are framed as: - * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>. - * - * The SLIP layer uses events to notify the upper layer when data transmission is complete - * and when a SLIP packet is received. - */ - -#ifndef HCI_SLIP_H__ -#define HCI_SLIP_H__ - -#include - -/**@brief Event types from the SLIP Layer. */ -typedef enum -{ - HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */ - HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */ - HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */ - HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */ - HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_slip_evt_type_t; - -/**@brief Structure containing an event from the SLIP layer. - */ -typedef struct -{ - hci_slip_evt_type_t evt_type; /**< Type of event. */ - const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */ - uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */ -} hci_slip_evt_t; - -/**@brief Function for the SLIP layer event callback. - */ -typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event); - -/**@brief Function for registering the event handler provided as parameter and this event handler - * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t. - * - * @note Multiple registration requests will overwrite any existing registration. - * - * @param[in] event_handler This function is called by the SLIP layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler); - -/**@brief Function for opening the SLIP layer. This function must be called before - * \ref hci_slip_write and before any data can be received. - * - * @note Can be called multiple times. - * - * @retval NRF_SUCCESS Operation success. - * - * The SLIP layer module will propagate errors from underlying sub-modules. - * This implementation is using UART module as a physical transmission layer, and hci_slip_open - * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init . - */ -uint32_t hci_slip_open(void); - -/**@brief Function for closing the SLIP layer. After this function is called no data can be - * transmitted or received in this layer. - * - * @note This function can be called multiple times and also for an unopened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_close(void); - -/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when - * the HCI_SLIP_TX_DONE event is received by the function caller. - * - * @param[in] p_buffer Pointer to the packet to transmit. - * @param[in] length Packet length, in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the - * transmission queue and an event will be sent upon transmission - * completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. Application shall wait for - * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this - * function can be executed for transmission of next packet. - * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open. - */ -uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of - * received and SLIP decoded data. - * No data can be received by the SLIP layer until a receive buffer has been registered. - * - * @note The lifetime of the buffer must be valid during complete reception of data. A static - * buffer is recommended. - * - * @warning Multiple registration requests will overwrite any existing registration. - * - * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet - * will be placed in this buffer. - * @param[in] length Buffer length, in bytes. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length); - -#endif // HCI_SLIP_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h deleted file mode 100755 index 60d3d24c4f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include -#include "nrf_error.h" - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h deleted file mode 100755 index df0c8b3994..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h +++ /dev/null @@ -1,381 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup persistent_storage Persistent Storage Interface - * @{ - * @ingroup app_common - * @brief Abstracted flash interface. - * - * @details In order to ensure that the SDK and application be moved to alternate persistent storage - * options other than the default provided with NRF solution, an abstracted interface is provided - * by the module to ensure SDK modules and application can be ported to alternate option with ease. - */ - -#ifndef PSTORAGE_H__ -#define PSTORAGE_H__ - -#ifdef __cplusplus -extern "C" { -#endif /* #ifdef __cplusplus */ - -#include "pstorage_platform.h" - - -/**@defgroup ps_opcode Persistent Storage Access Operation Codes - * @{ - * @brief Persistent Storage Access Operation Codes. These are used to report any error during - * a persistent storage access operation or any general error that may occur in the - * interface. - * - * @details Persistent Storage Access Operation Codes used in error notification callback - * registered with the interface to report any error during an persistent storage access - * operation or any general error that may occur in the interface. - */ -#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */ -#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */ -#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */ -#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */ -#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */ - -/**@} */ - -/**@defgroup pstorage_data_types Persistent Memory Interface Data Types - * @{ - * @brief Data Types needed for interfacing with persistent memory. - * - * @details Data Types needed for interfacing with persistent memory. - */ - -/**@brief Persistent Storage Error Reporting Callback - * - * @details Persistent Storage Error Reporting Callback that is used by the interface to report - * success or failure of a flash operation. Therefore, for any operations, application - * can know when the procedure was complete. For store operation, since no data copy - * is made, receiving a success or failure notification, indicated by the reason - * parameter of callback is an indication that the resident memory could now be reused - * or freed, as the case may be. - * - * @param[in] handle Identifies module and block for which callback is received. - * @param[in] op_code Identifies the operation for which the event is notified. - * @param[in] result Identifies the result of flash access operation. - * NRF_SUCCESS implies, operation succeeded. - * @param[in] p_data Identifies the application data pointer. In case of store operation, this - * points to the resident source of application memory that application can now - * free or reuse. In case of clear, this is NULL as no application pointer is - * needed for this operation. - * @param[in] data_len Length data application had provided for the operation. - * - */ -typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle, - uint8_t op_code, - uint32_t result, - uint8_t * p_data, - uint32_t data_len); - - -typedef struct -{ - pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */ - pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes, - * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on - * how it would like to access or alter memory in persistent memory. - * First option is preferred when single entries that need to be updated often when having no impact on the other entries. - * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing - * data. */ - pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */ -} pstorage_module_param_t; - -/**@} */ - -/**@defgroup pstorage_routines Persistent Storage Access Routines - * @{ - * @brief Functions/Interface SDK modules use to persistently store data. - * - * @details Interface for Application & SDK module to load/store information persistently. - * Note: that while implementation of each of the persistent storage access function - * depends on the system and can specific to system/solution, the signature of the - * interface routines should not be altered. - */ - -/**@brief Module Initialization Routine. - * - * @details Initializes module. To be called once before any other APIs of the module are used. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - */ -uint32_t pstorage_init(void); - - -/**@brief Register with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. Maximum - * registrations permitted is determined by configuration parameter - * PSTORAGE_MAX_APPLICATIONS. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - - -/** - * @brief Function to get block id with reference to base block identifier provided at time of - * registration. - * - * @details Function to get block id with reference to base block identifier provided at time of - * registration. - * In case more than one memory blocks were requested when registering, the identifier - * provided here is the base identifier for the first block and to identify subsequent - * block, application shall use this routine to get block identifier providing input as - * base identifier and block number. Therefore if 10 blocks of size 64 are requested and - * application wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @param[in] p_base_id Base block id received at the time of registration. - * @param[in] block_num Block Number, with first block numbered zero. - * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - */ -uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id, - pstorage_size_t block_num, - pstorage_handle_t * p_block_id); - - -/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address. - * - * @param[in] p_dest Destination address where data is to be updated. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_update(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address - * to 'p_dest' address; Equivalent to Storage Read. - * - * @param[in] p_dest Destination address where persistently stored data is to be loaded. - * @param[in] p_src Source from where data is to be loaded from persistent memory. - * @param[in] size Size of data to be loaded from persistent memory expressed in bytes. - * Should be word aligned. - * @param[in] offset Offset in bytes to be applied when loading from the block. - * For example, if within a block of 100 bytes, application wishes to - * load 20 bytes from offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - */ -uint32_t pstorage_load(uint8_t * p_dest, - pstorage_handle_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to clear data in persistent memory. - * - * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This parameter is to provision for clearing of certain blocks - * of memory, or all memory blocks in a registered module. If the total size - * of the application module is used (blocks * block size) in combination with - * the identifier for the first block in the module, all blocks in the - * module will be erased. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size); - -/** - * @brief API to get status of number of pending operations with the module. - * - * @param[out] p_count Number of storage operations pending with the module, if 0, - * there are no outstanding requests. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - */ -uint32_t pstorage_access_status_get(uint32_t * p_count); - -#ifdef PSTORAGE_RAW_MODE_ENABLE - -/**@brief Function for registering with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - -/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src' - * address in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_raw_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Function for clearing data in persistent memory in raw mode. - * - * @param[in] p_dest Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This is currently unused. And a clear would mean clearing all blocks, - * however, this parameter is to provision for clearing of certain blocks - * of memory only and not all if need be. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size); - -#endif // PSTORAGE_RAW_MODE_ENABLE - -#ifdef __cplusplus -} -#endif /* #ifdef __cplusplus */ - - -/**@} */ -/**@} */ - -#endif // PSTORAGE_H__ - diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h deleted file mode 100644 index 44abff6e46..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h +++ /dev/null @@ -1,110 +0,0 @@ -/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_util_platform Utility Functions and Definitions (Platform) - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications when using SoftDevice. - */ - -#ifndef APP_UTIL_PLATFORM_H__ -#define APP_UTIL_PLATFORM_H__ - -#include -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "app_error.h" - -/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ -typedef enum -{ - APP_IRQ_PRIORITY_HIGH = 1, - APP_IRQ_PRIORITY_LOW = 3 -} app_irq_priority_t; - -#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */ - -/**@cond NO_DOXYGEN */ -#define EXTERNAL_INT_VECTOR_OFFSET 16 -/**@endcond */ - -#define PACKED(TYPE) __packed TYPE - -/**@brief Macro for entering a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_ENTER() \ - { \ - uint8_t IS_NESTED_CRITICAL_REGION = 0; \ - uint32_t CURRENT_INT_PRI = current_int_priority_get(); \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - __disable_irq(); \ - } \ - else \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } - -/**@brief Macro for leaving a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_EXIT() \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE; \ - __enable_irq(); \ - ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } \ - } - -/**@brief Function for finding the current interrupt level. - * - * @return Current interrupt level. - * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. - * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. - * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. - */ -static __INLINE uint8_t current_int_priority_get(void) -{ - uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); - if (isr_vector_num > 0) - { - int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); - return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); - } - else - { - return NRF_APP_PRIORITY_THREAD; - } -} - -#endif // APP_UTIL_PLATFORM_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c index 948c8424ff..8e3e8c34c7 100755 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c @@ -194,10 +194,10 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) if (enable) { switch (irq) { case RxIrq: - obj->uart->INTEN |= (UART_INTENSET_RXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk); break; case TxIrq: - obj->uart->INTEN |= (UART_INTENSET_TXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk); break; } NVIC_SetPriority(irq_n, 3); @@ -209,12 +209,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) int all_disabled = 0; switch (irq) { case RxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_RXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; break; case TxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_TXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; break; } diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index b6dba7b2c4..1d5164ffaf 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -763,6 +763,8 @@ class NRF51822(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"] + self.common_macros = ['NRF51'] + self.macros = self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["1070"] @@ -816,6 +818,7 @@ class NRF51822_BOOT(NRF51822): self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K", "NRF51822"] self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -826,6 +829,7 @@ class NRF51822_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K", "NRF51822"] self.macros = ['TARGET_NRF51822', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False @@ -834,6 +838,7 @@ class NRF51_DK(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class NRF51_DK_BOOT(NRF51822): @@ -842,6 +847,7 @@ class NRF51_DK_BOOT(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', 'NRF51_DK'] self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -852,6 +858,7 @@ class NRF51_DK_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K', 'NRF51_DK'] self.macros = ['TARGET_NRF51822', 'TARGET_NRF51_DK', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = False @@ -860,12 +867,14 @@ class NRF51_DONGLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_32K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class ARCH_BLE(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class SEEED_TINY_BLE(NRF51822): @@ -873,12 +882,14 @@ class SEEED_TINY_BLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class SEEED_TINY_BLE_BOOT(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'SEEED_TINY_BLE'] self.macros = ['TARGET_NRF51822', 'TARGET_SEEED_TINY_BLE', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True @@ -887,6 +898,7 @@ class SEEED_TINY_BLE_OTA(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'SEEED_TINY_BLE'] self.macros = ['TARGET_NRF51822', 'TARGET_SEEED_TINY_BLE', 'TARGET_OTA_ENABLED'] + self.macros += self.common_macros self.MERGE_SOFT_DEVICE = False class HRM1017(NRF51822): @@ -894,12 +906,14 @@ class HRM1017(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class RBLAB_NRF51822(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros self.supported_form_factors = ["ARDUINO"] class RBLAB_BLENANO(NRF51822): @@ -907,12 +921,14 @@ class RBLAB_BLENANO(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class NRF51822_Y5_MBUG(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class XADOW_M0(LPCTarget): def __init__(self): @@ -927,6 +943,7 @@ class WALLBOT_BLE(NRF51822): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class DELTA_DFCM_NNN40(NRF51822): def __init__(self): @@ -934,6 +951,7 @@ class DELTA_DFCM_NNN40(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] + self.macros += self.common_macros class DELTA_DFCM_NNN40_OTA(NRF51822): def __init__(self): @@ -941,13 +959,15 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False + self.macros += self.common_macros + class DELTA_DFCM_NNN40_OTA(NRF51822): def __init__(self): NRF51822.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False - + self.macros += self.common_macros ### ARM ### From 3e76f8cf2a9e0496244de78c1e7519326150dba6 Mon Sep 17 00:00:00 2001 From: Wim Date: Sat, 21 Mar 2015 14:59:21 +0100 Subject: [PATCH 007/143] Update us_ticker.c Fixed hardcoded MRT_Clock_MHz so that the code will also work at a SystemCoreClock different from 30MHz. Optimized time calculations for us_ticker_read. Same modifications as done previously for LPC812. --- .../hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c | 74 +++++++++++-------- 1 file changed, 44 insertions(+), 30 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c index 94b2318ca3..9b2fe130ce 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c @@ -13,77 +13,91 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" static int us_ticker_inited = 0; -static int ticker_expired = 0; +int MRT_Clock_MHz; +unsigned int ticker_fullcount_us; +unsigned long int ticker_expired_count_us = 0; #define US_TICKER_TIMER_IRQn MRT_IRQn -#define MRT_CLOCK_MHZ 30 -void us_ticker_init(void) -{ +void us_ticker_init(void) { + if (us_ticker_inited) return; us_ticker_inited = 1; + // Calculate MRT clock value (MRT has no prescaler) + MRT_Clock_MHz = (SystemCoreClock / 1000000); + // Calculate fullcounter value in us (MRT has 31 bits and clock is 30MHz) + ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz; + // Enable the MRT clock LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); // Clear peripheral reset the MRT LPC_SYSCON->PRESETCTRL |= (1 << 7); - // Force load interval value + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) LPC_MRT->INTVAL0 = 0xFFFFFFFFUL; - // Enable ch0 interrupt - LPC_MRT->CTRL0 = 1; + // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt + LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0); - // Force load interval value + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) LPC_MRT->INTVAL1 = 0x80000000UL; - // Disable ch1 interrupt - LPC_MRT->CTRL1 = 0; - + // Disable ch1 interrupt, Mode 0 is Repeat Interrupt + LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0); + // Set MRT interrupt vector NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); } -uint32_t us_ticker_read() -{ +//TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc) +uint32_t us_ticker_read() { + if (!us_ticker_inited) us_ticker_init(); // Generate ticker value - // MRT source clock is SystemCoreClock (30MHz) and 31-bit down count timer - // Calculate expected value using number of expired times - return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_CLOCK_MHZ + (ticker_expired * (0x80000000UL/MRT_CLOCK_MHZ)); + // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer + // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz + return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us; } - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Force load interval value - LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_CLOCK_MHZ) | 0x80000000UL); - +//TIMER1 is used for Timestamped interrupts (Ticker(), Timeout()) +void us_ticker_set_interrupt(timestamp_t timestamp) { + + // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer + // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) + // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz. + // The calculated counter interval until the next timestamp will be truncated and an + // 'early' interrupt will be generated in case the max required count interval exceeds + // the available 31 bits space. However, the mbed us_ticker interrupt handler will + // check current time against the next scheduled timestamp and simply re-issue the + // same interrupt again when needed. The calculated counter interval will now be smaller. + LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL); + // Enable interrupt LPC_MRT->CTRL1 |= 1; } -void us_ticker_disable_interrupt() -{ +//Disable Timestamped interrupts triggered by TIMER1 +void us_ticker_disable_interrupt() { + //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) LPC_MRT->CTRL1 &= ~1; } -void us_ticker_clear_interrupt() -{ +void us_ticker_clear_interrupt() { + + //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) if (LPC_MRT->STAT1 & 1) LPC_MRT->STAT1 = 1; + //Timer0 for us counter (31 bits downcounter @ SystemCoreClock) if (LPC_MRT->STAT0 & 1) { LPC_MRT->STAT0 = 1; - ticker_expired++; + ticker_expired_count_us += ticker_fullcount_us; } } From 8cfb41f56cb9a2187eb21e7cc78cbf985bf6c23e Mon Sep 17 00:00:00 2001 From: Wim Date: Sat, 21 Mar 2015 15:10:39 +0100 Subject: [PATCH 008/143] Update us_ticker.c --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c index 9b2fe130ce..dfb8debe52 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c @@ -13,6 +13,9 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" static int us_ticker_inited = 0; int MRT_Clock_MHz; From 52be993683b9b514c323ea1e6afd13941ccd999c Mon Sep 17 00:00:00 2001 From: Wim Date: Sat, 21 Mar 2015 15:25:13 +0100 Subject: [PATCH 009/143] Update i2c_api.c Replaced I2C ROM call by direct calls to I2C engines. The ROM code has some bugs and does not allow support for the mbed I2CSlave methods. The Slave methods have been added same as for LPC812. --- .../hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c | 568 +++++++++++++----- 1 file changed, 403 insertions(+), 165 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c index 3396c0e7f8..91044d4ab3 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c @@ -20,30 +20,19 @@ #include "cmsis.h" #include "pinmap.h" -#include "rom_i2c_8xx.h" +#define LPC824_I2C0_FMPLUS 1 #if DEVICE_I2C -typedef struct ROM_API { - const uint32_t unused[5]; - const I2CD_API_T *pI2CD; /*!< I2C driver routines functions table */ -} LPC_ROM_API_T; - - -/* Pointer to ROM API function address */ -#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8UL -#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC) - -/* Pointer to @ref I2CD_API_T functions in ROM */ -#define LPC_I2CD_API ((LPC_ROM_API)->pI2CD) - static const SWM_Map SWM_I2C_SDA[] = { - { 9, 8}, + //PINASSIGN Register ID, Pinselect bitfield position + { 9, 8}, { 9, 24}, {10, 8}, }; static const SWM_Map SWM_I2C_SCL[] = { + //PINASSIGN Register ID, Pinselect bitfield position { 9, 16}, {10, 0}, {10, 16}, @@ -52,36 +41,15 @@ static const SWM_Map SWM_I2C_SCL[] = { static int i2c_used = 0; static uint8_t repeated_start = 0; -static uint32_t *i2c_buffer; #define I2C_DAT(x) (x->i2c->MSTDAT) #define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07)) -static inline int i2c_status(i2c_t *obj) -{ - return I2C_STAT(obj); -} - -// Wait until the Serial Interrupt (SI) is set -static int i2c_wait_SI(i2c_t *obj) -{ - volatile int timeout = 0; - while (!(obj->i2c->STAT & (1 << 0))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - -static inline void i2c_interface_enable(i2c_t *obj) -{ - obj->i2c->CFG |= 1; -} - static inline void i2c_power_enable(int ch) { switch(ch) { case 0: + // I2C0, Same as for LPC812 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); LPC_SYSCON->PRESETCTRL &= ~(1 << 6); LPC_SYSCON->PRESETCTRL |= (1 << 6); @@ -89,6 +57,7 @@ static inline void i2c_power_enable(int ch) case 1: case 2: case 3: + // I2C1,I2C2 or I2C3. Not available for LPC812 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (20 + ch)); LPC_SYSCON->PRESETCTRL &= ~(1 << (13 + ch)); LPC_SYSCON->PRESETCTRL |= (1 << (13 + ch)); @@ -99,6 +68,12 @@ static inline void i2c_power_enable(int ch) } +static inline void i2c_interface_enable(i2c_t *obj) { + obj->i2c->CFG |= (1 << 0); // Enable Master mode +// obj->i2c->CFG &= ~(1 << 1); // Disable Slave mode +} + + static int get_available_i2c(void) { int i; for (i=0; i<3; i++) { @@ -113,11 +88,23 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) const SWM_Map *swm; uint32_t regVal; int i2c_ch = 0; - + + //LPC824 + //I2C0 can support FM+ but only on P0_11 and P0_10 if (sda == I2C_SDA && scl == I2C_SCL) { - LPC_SWM->PINENABLE0 &= ~(0x3 << 11); + //Select I2C mode for P0_11 and P0_10 + LPC_SWM->PINENABLE0 &= ~(0x3 << 11); + +#if(LPC824_I2C0_FMPLUS == 1) + // Enable FM+ mode on P0_11, P0_10 + LPC_IOCON->PIO0_10 &= ~(0x3 << 8); + LPC_IOCON->PIO0_10 |= (0x2 << 8); //FM+ mode + LPC_IOCON->PIO0_11 &= ~(0x3 << 8); + LPC_IOCON->PIO0_11 |= (0x2 << 8); //FM+ mode +#endif } else { + //Select any other pin for I2C1, I2C2 or I2C3 i2c_ch = get_available_i2c(); if (i2c_ch == -1) return; @@ -151,127 +138,213 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) // enable power i2c_power_enable(i2c_ch); - - uint32_t size_in_bytes = LPC_I2CD_API->i2c_get_mem_size(); - i2c_buffer = malloc(size_in_bytes); - obj->handler = LPC_I2CD_API->i2c_setup((uint32_t)(obj->i2c), i2c_buffer); - LPC_I2CD_API->i2c_set_bitrate(obj->handler, SystemCoreClock, 100000); - LPC_I2CD_API->i2c_set_timeout(obj->handler, 100000); - + // set default frequency at 100k + i2c_frequency(obj, 100000); i2c_interface_enable(obj); } -inline int i2c_start(i2c_t *obj) -{ + +static inline int i2c_status(i2c_t *obj) { + return I2C_STAT(obj); +} + +// Wait until the Master Serial Interrupt (SI) is set +// Timeout when it takes too long. +static int i2c_wait_SI(i2c_t *obj) { + int timeout = 0; + while (!(obj->i2c->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} + + +//Attention. Spec says: First store Address in DAT before setting STA ! +//Undefined state when using single byte I2C operations and too much delay +//between i2c_start and do_i2c_write(Address). +//Also note that lpc812/824 will immediately continue reading a byte when Address b0 == 1 +inline int i2c_start(i2c_t *obj) { int status = 0; if (repeated_start) { - obj->i2c->MSTCTL = (1 << 1) | (1 << 0); + obj->i2c->MSTCTL = (1 << 1) | (1 << 0); // STA bit and Continue bit to complete previous RD or WR repeated_start = 0; } else { - obj->i2c->MSTCTL = (1 << 1); + obj->i2c->MSTCTL = (1 << 1); // STA bit } return status; } -inline int i2c_stop(i2c_t *obj) -{ - volatile int timeout = 0; +//Generate Stop condition and wait until bus is Idle +//Will also send NAK for previous RD +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + // STP bit and Continue bit. Sends NAK to complete previous RD obj->i2c->MSTCTL = (1 << 2) | (1 << 0); - while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) { + + //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) + while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { timeout ++; if (timeout > 100000) return 1; } + // repeated_start = 0; // bus free return 0; } -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) -{ +//Spec says: first check Idle and status is Ok +static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { // write the data I2C_DAT(obj) = value; - + if (!addr) - obj->i2c->MSTCTL = (1 << 0); - + obj->i2c->MSTCTL = (1 << 0); //Set continue for data. Should not be set for addr since that uses STA + // wait and return status i2c_wait_SI(obj); return i2c_status(obj); } -static inline int i2c_do_read(i2c_t *obj, int last) -{ + +//Attention, correct Order: wait for data ready, read data, read status, continue, return +//Dont read DAT or STAT when not ready, so dont read after setting continue. +//Results may be invalid when next read is underway. +static inline int i2c_do_read(i2c_t *obj, int last) { // wait for it to arrive i2c_wait_SI(obj); if (!last) - obj->i2c->MSTCTL = (1 << 0); - + obj->i2c->MSTCTL = (1 << 0); //ACK and Continue + // return the data return (I2C_DAT(obj) & 0xFF); } -void i2c_frequency(i2c_t *obj, int hz) -{ - LPC_I2CD_API->i2c_set_bitrate(obj->handler, SystemCoreClock, hz); + +void i2c_frequency(i2c_t *obj, int hz) { + // No peripheral clock divider on the M0 + uint32_t PCLK = SystemCoreClock; + + uint32_t clkdiv = PCLK / (hz * 4) - 1; + + obj->i2c->CLKDIV = clkdiv; + obj->i2c->MSTTIME = 0; } -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - ErrorCode_t err; - I2C_PARAM_T i2c_param; - I2C_RESULT_T i2c_result; +// The I2C does a read or a write as a whole operation +// There are two types of error conditions it can encounter +// 1) it can not obtain the bus +// 2) it gets error responses at part of the transmission +// +// We tackle them as follows: +// 1) we retry until we get the bus. we could have a "timeout" if we can not get it +// which basically turns it in to a 2) +// 2) on error, we use the standard error mechanisms to report/debug +// +// Therefore an I2C transaction should always complete. If it doesn't it is usually +// because something is setup wrong (e.g. wiring), and we don't need to programatically +// check for that +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + + //Store the address+RD and then generate STA + I2C_DAT(obj) = address | 0x01; + i2c_start(obj); - uint8_t *buf = malloc(length + 1); - buf[0] = (uint8_t)((address | 0x01) & 0xFF); - i2c_param.buffer_ptr_rec = buf; - i2c_param.num_bytes_rec = length + 1; - i2c_param.stop_flag = stop; - err = LPC_I2CD_API->i2c_master_receive_poll(obj->handler, &i2c_param, &i2c_result); - memcpy(data, buf + 1, i2c_result.n_bytes_recd); - free(buf); - if (err == 0) - return i2c_result.n_bytes_recd - 1; - else - return -1; + // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status == 0x03) { // NAK on SlaveAddress + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length-1); count++) { + + // Wait for it to arrive, note that first byte read after address+RD is already waiting + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status != 0x01) { // RX RDY + i2c_stop(obj); + return count; + } + data[count] = I2C_DAT(obj) & 0xFF; // Store read byte + + obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read + } + + // Read final byte + // Wait for it to arrive + i2c_wait_SI(obj); + + status = i2c_status(obj); + if (status != 0x01) { // RX RDY + i2c_stop(obj); + return count; + } + data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); // Also sends NAK for last read byte + } else { + repeated_start = 1; + } + + return length; } -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - ErrorCode_t err; - I2C_PARAM_T i2c_param; - I2C_RESULT_T i2c_result; - uint8_t *buf = malloc(length + 1); - buf[0] = (uint8_t)(address & 0xFE); - memcpy(buf + 1, data, length); - i2c_param.buffer_ptr_send = buf; - i2c_param.num_bytes_send = length + 1; - i2c_param.stop_flag = stop; - err = LPC_I2CD_API->i2c_master_transmit_poll(obj->handler, &i2c_param, &i2c_result); - free(buf); - if (err == 0) - return i2c_result.n_bytes_sent - 1; - else - return -1; +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + + //Store the address+/WR and then generate STA + I2C_DAT(obj) = address & 0xFE; + i2c_start(obj); + + // Wait for completion of STA and Sending of SlaveAddress+/WR + i2c_wait_SI(obj); + status = i2c_status(obj); + if (status == 0x03) { // NAK SlaveAddress + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + //Write all bytes + for (i=0; ihandler = LPC_I2CD_API->i2c_setup((uint32_t)(obj->i2c), i2c_buffer); - if (enable_slave != 0) { - obj->i2c->CFG &= ~(1 << 0); - obj->i2c->CFG |= (1 << 1); - } - else { - obj->i2c->CFG |= (1 << 0); - obj->i2c->CFG &= ~(1 << 1); - } +#define I2C_SLVDAT(x) (x->i2c->SLVDAT) +#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03)) +#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01)) +//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0)) +//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1)) +#if(0) +// Wait until the Slave Serial Interrupt (SI) is set +// Timeout when it takes too long. +static int i2c_wait_slave_SI(i2c_t *obj) { + int timeout = 0; + while (!(obj->i2c->STAT & (1 << 8))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} +#endif + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + + if (enable_slave) { +// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode + obj->i2c->CFG |= (1 << 1); //Enable Slave mode + } + else { +// obj->i2c->CFG |= (1 << 0); //Enable Master mode + obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode + } } -int i2c_slave_receive(i2c_t *obj) -{ - CHIP_I2C_MODE_T mode; - int ret; +// Wait for next I2C event and find out what is going on +// +int i2c_slave_receive(i2c_t *obj) { + int addr; + + // Check if there is any data pending + if (! I2C_SLVSI(obj)) { + return 0; //NoData + }; + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + + // Get the received address + addr = I2C_SLVDAT(obj) & 0xFF; + // Send ACK on address and Continue + obj->i2c->SLVCTL = (1 << 0); + + if (addr == 0x00) { + return 2; //WriteGeneral + } + //check the RW bit + if ((addr & 0x01) == 0x01) { + return 1; //ReadAddressed + } + else { + return 3; //WriteAddressed + } + //break; - mode = LPC_I2CD_API->i2c_get_status(obj->handler); - switch(mode) { - case SLAVE_SEND: - ret = 1; - break; - case SLAVE_RECEIVE: - ret = 3; - break; - case MASTER_SEND: - case MASTER_RECEIVE: - default: - ret = 0; - break; - } - return ret; + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Oops, should never get here... + obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover... + return 0; //NoData + + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + // Oops, should never get here... + I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... + return 0; //NoData + + case 0x3: // Reserved. + default: // Oops, should never get here... + obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... + return 0; //NoData + //break; + } //switch status } -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - ErrorCode_t err; - I2C_PARAM_T i2c_param; - I2C_RESULT_T i2c_result; +// The dedicated I2C Slave byte read and byte write functions need to be called +// from 'common' mbed I2CSlave API for devices that have separate Master and +// Slave engines such as the lpc812 and lpc1549. - i2c_param.buffer_ptr_send = (uint8_t *)data; - i2c_param.num_bytes_send = length; - err = LPC_I2CD_API->i2c_slave_transmit_poll(obj->handler, &i2c_param, &i2c_result); - if (err == 0) - return i2c_result.n_bytes_sent; - else - return -1; +//Called when Slave is addressed for Write, Slave will receive Data in polling mode +//Parameter last=1 means received byte will be NACKed. +int i2c_slave_byte_read(i2c_t *obj, int last) { + int data; + + // Wait for data + while (!I2C_SLVSI(obj)); // Wait forever +//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Dont bother to check State, were not returning it anyhow.. +//if (I2C_SLVSTAT(obj)) == 0x01) { + // Slave receive. Received data is available (Slave Receiver mode). +//}; + + data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data + if (last) { + obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue + } + else { + obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read + } + + return data; } -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - ErrorCode_t err; - I2C_PARAM_T i2c_param; - I2C_RESULT_T i2c_result; - i2c_param.buffer_ptr_rec = (uint8_t *)data; - i2c_param.num_bytes_rec = length; - err = LPC_I2CD_API->i2c_slave_receive_poll(obj->handler, &i2c_param, &i2c_result); - if (err == 0) - return i2c_result.n_bytes_recd; - else - return -1; +//Called when Slave is addressed for Read, Slave will send Data in polling mode +// +int i2c_slave_byte_write(i2c_t *obj, int data) { + + // Wait until Ready + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Should not get here... + return -2; + //break; + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue to send + + return 1; + //break; + case 0x3: // Reserved. + default: + // Should not get here... + return -3; + //break; + } // switch status } -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - LPC_I2CD_API->i2c_set_slave_addr(obj->handler, address, 0); + +//Called when Slave is addressed for Write, Slave will receive Data in polling mode +//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed. +int i2c_slave_read(i2c_t *obj, char *data, int length) { + int count=0; + + // Read and ACK all expected bytes + while (count < length) { + // Wait for data + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data + obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read + break; + + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + case 0x3: // Reserved. + default: // Should never get here... + return -2; + //break; + } // switch status + + count++; + } // for all bytes + + return count; // Received the expected number of bytes +} + + +//Called when Slave is addressed for Read, Slave will send Data in polling mode +//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed. +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int count; + + // Send and all bytes or Exit on NAK + for (count=0; count < length; count++) { + // Wait until Ready for data + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Should not get here... + return -2; + //break; + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue to send + break; + case 0x3: // Reserved. + default: + // Should not get here... + return -3; + //break; + } // switch status + } // for all bytes + + return length; // Transmitted the max number of bytes +} + + +// Set the four slave addresses. +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register + obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register + obj->i2c->SLVADR2 = (0x01); // Disable address 2 register + obj->i2c->SLVADR3 = (0x01); // Disable address 3 register + obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match } #endif From 153d03cb2bb7082327b61c1460488dbce5ed8914 Mon Sep 17 00:00:00 2001 From: Wim Date: Sat, 21 Mar 2015 15:26:20 +0100 Subject: [PATCH 010/143] Update device.h Enabled I2CSlave --- .../targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h index be5981dc85..52d2e95d0e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h @@ -29,7 +29,7 @@ #define DEVICE_SERIAL_FC 0 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 From e6e51c33750e76ca354732f54289898a2005e873 Mon Sep 17 00:00:00 2001 From: Wim Date: Sat, 21 Mar 2015 15:26:57 +0100 Subject: [PATCH 011/143] Update device.h Enabled I2CSlave --- .../hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h index be5981dc85..52d2e95d0e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h @@ -29,7 +29,7 @@ #define DEVICE_SERIAL_FC 0 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 From 55b4a142a5e2ca9f9cba77915e189c2e4df47746 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sat, 21 Mar 2015 20:22:09 +0100 Subject: [PATCH 012/143] [NUCLEO_F070RB] exporter for CoIDE - Added exporter - Updated workspace_tools/export/README.md --- workspace_tools/export/README.md | 216 ++++++++++++++++-- workspace_tools/export/coide.py | 1 + .../export/coide_nucleo_f070rb.coproj.tmpl | 90 ++++++++ 3 files changed, 289 insertions(+), 18 deletions(-) create mode 100644 workspace_tools/export/coide_nucleo_f070rb.coproj.tmpl diff --git a/workspace_tools/export/README.md b/workspace_tools/export/README.md index bcce4f4ee7..2f98cfbb7d 100644 --- a/workspace_tools/export/README.md +++ b/workspace_tools/export/README.md @@ -14,6 +14,18 @@ Exporter IDE/Platform Support lpcxpresso uvision + + APPNEARME_MICRONFCBOARD + - + - + - + ✓ + - + - + - + - + - + ARCH_BLE - @@ -21,7 +33,7 @@ Exporter IDE/Platform Support - ✓ ✓ - - + ✓ - - ✓ @@ -41,7 +53,7 @@ Exporter IDE/Platform Support ARCH_MAX - - - + ✓ - ✓ ✓ @@ -75,19 +87,91 @@ Exporter IDE/Platform Support - - SEEED_TINY_BLE + ARM_MPS2_M0 + - + - + - + ✓ + - + - + - + - + - + + + ARM_MPS2_M0P + - + - + - + ✓ + - + - + - + - + - + + + ARM_MPS2_M1 + - + - + - + ✓ + - + - + - + - + - + + + ARM_MPS2_M3 + - + - + - + ✓ + - + - + - + - + - + + + ARM_MPS2_M4 + - + - + - + ✓ + - + - + - + - + - + + + ARM_MPS2_M7 + - + - + - + ✓ + - + - + - + - + - + + + DELTA_DFCM_NNN40 - - - ✓ ✓ - - + ✓ - - ✓ - SEEED_TINY_BLE_OTA + DELTA_DFCM_NNN40_OTA - - - @@ -201,7 +285,7 @@ Exporter IDE/Platform Support - ✓ ✓ - - + ✓ - - ✓ @@ -338,6 +422,18 @@ Exporter IDE/Platform Support - - + + LPC11U34_421 + - + - + - + ✓ + - + - + - + - + - + LPC11U35_401 - @@ -408,7 +504,7 @@ Exporter IDE/Platform Support - - ✓ - - + ✓ LPC1347 @@ -549,7 +645,7 @@ Exporter IDE/Platform Support - ✓ - - - + ✓ - ✓ - @@ -561,7 +657,7 @@ Exporter IDE/Platform Support - ✓ ✓ - ✓ + - - ✓ - @@ -621,10 +717,22 @@ Exporter IDE/Platform Support - ✓ ✓ + ✓ + - + - + ✓ + + + NRF51822_BOOT - - - ✓ + - + - + - + - + - NRF51822_OTA @@ -657,10 +765,22 @@ Exporter IDE/Platform Support - ✓ ✓ + ✓ + - + - + ✓ + + + NRF51_DK_BOOT - - - ✓ + - + - + - + - + - NRF51_DK_OTA @@ -681,7 +801,7 @@ Exporter IDE/Platform Support - ✓ ✓ - - + ✓ - - ✓ @@ -701,7 +821,7 @@ Exporter IDE/Platform Support NUCLEO_F070RB - - - + ✓ - ✓ ✓ @@ -761,11 +881,11 @@ Exporter IDE/Platform Support NUCLEO_F303RE - - - - - ✓ - ✓ + ✓ + ✓ - - ✓ @@ -818,6 +938,18 @@ Exporter IDE/Platform Support - ✓ + + NUCLEO_L073RZ + - + - + - + ✓ + ✓ + ✓ + - + - + ✓ + NUCLEO_L152RE - @@ -860,6 +992,42 @@ Exporter IDE/Platform Support - - ✓ + ✓ + - + - + - + ✓ + + + RZ_A1H + - + - + - + ✓ + ✓ + - + - + - + - + + + SEEED_TINY_BLE + - + - + - + ✓ + ✓ + ✓ + - + - + ✓ + + + SEEED_TINY_BLE_BOOT + - + - + - + ✓ - - - @@ -867,11 +1035,11 @@ Exporter IDE/Platform Support - - RZ_A1H - - + SEEED_TINY_BLE_OTA - - - + ✓ - - - @@ -909,7 +1077,7 @@ Exporter IDE/Platform Support - ✓ ✓ - ✓ + - - - - @@ -938,6 +1106,18 @@ Exporter IDE/Platform Support ✓ ✓ + + UBLOX_C029 + - + - + - + ✓ + - + - + - + - + - + WALLBOT_BLE - @@ -964,5 +1144,5 @@ Exporter IDE/Platform Support Total IDEs: 9 -
Total platforms: 78 -
Total permutations: 248 +
Total platforms: 94 +
Total permutations: 288 \ No newline at end of file diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py index c001d5dd5f..ff2c31ace3 100644 --- a/workspace_tools/export/coide.py +++ b/workspace_tools/export/coide.py @@ -32,6 +32,7 @@ class CoIDE(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L152RE', 'NUCLEO_F030R8', + 'NUCLEO_F070RB', 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', diff --git a/workspace_tools/export/coide_nucleo_f070rb.coproj.tmpl b/workspace_tools/export/coide_nucleo_f070rb.coproj.tmpl new file mode 100644 index 0000000000..9756fd2558 --- /dev/null +++ b/workspace_tools/export/coide_nucleo_f070rb.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + From d199416792c0a61eead553b32113cab3189e067f Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sat, 21 Mar 2015 20:32:47 +0100 Subject: [PATCH 013/143] [NUCLEO_F303RE] reorg hal --- .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/PeripheralPins.h | 0 .../{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PeripheralNames.h | 0 .../{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PeripheralPins.c | 0 .../{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PinNames.h | 0 .../{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PortNames.h | 0 .../TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/device.h | 0 .../{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/objects.h | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/analogin_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/analogout_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_irq_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_object.h | 0 .../TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/i2c_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/mbed_overrides.c | 0 .../TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/pinmap.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/port_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/pwmout_api.c | 0 .../TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/rtc_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/serial_api.c | 0 .../TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/sleep.c | 0 .../TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/spi_api.c | 0 .../{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/us_ticker.c | 0 22 files changed, 0 insertions(+), 0 deletions(-) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/PeripheralPins.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F303RE/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/analogout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/gpio_object.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/pinmap.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/port_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/rtc_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/sleep.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/spi_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F303RE => TARGET_STM32F3}/us_ticker.c (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pinmap.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/port_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/serial_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/sleep.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/sleep.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/sleep.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/spi_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/us_ticker.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/us_ticker.c From 5e9b323cec299a93dc8ae3e1dd59fb7ea2fa0847 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sat, 21 Mar 2015 23:09:44 +0100 Subject: [PATCH 014/143] [NUCLEO_F302R8] reorg hal part I --- .../TARGET_NUCLEO_F302R8/PeripheralPins.h | 66 --- .../TARGET_NUCLEO_F302R8/gpio_api.c | 79 ---- .../TARGET_NUCLEO_F302R8/gpio_irq_api.c | 332 ------------- .../TARGET_NUCLEO_F302R8/gpio_object.h | 75 --- .../TARGET_STM/TARGET_NUCLEO_F302R8/i2c_api.c | 442 ------------------ .../TARGET_NUCLEO_F302R8/mbed_overrides.c | 37 -- .../TARGET_NUCLEO_F302R8/port_api.c | 103 ---- .../TARGET_STM/TARGET_NUCLEO_F302R8/rtc_api.c | 201 -------- .../TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c | 61 --- .../TARGET_NUCLEO_F302R8/us_ticker.c | 70 --- .../TARGET_NUCLEO_F302R8/PeripheralNames.h | 0 .../TARGET_NUCLEO_F302R8/PeripheralPins.c | 0 .../TARGET_NUCLEO_F302R8/PinNames.h | 0 .../TARGET_NUCLEO_F302R8/PortNames.h | 0 .../TARGET_NUCLEO_F302R8/device.h | 0 .../TARGET_NUCLEO_F302R8/objects.h | 0 16 files changed, 1466 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/mbed_overrides.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/rtc_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/us_ticker.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/objects.h (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.h deleted file mode 100644 index cc2fcaaf11..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_api.c deleted file mode 100644 index b9ff5c114b..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRRL; - obj->reg_clr = &gpio->BSRRH; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_irq_api.c deleted file mode 100644 index f7772f5510..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_irq_api.c +++ /dev/null @@ -1,332 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15) -#define CHANNEL_NUM (7) - -// Max pins for one line (max with EXTI10_15) -#define MAX_PIN_LINE (6) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0 - 0, // pin 0 - // EXTI1 - 0, // pin 1 - // EXTI2 - 0, // pin 2 - // EXTI3 - 0, // pin 3 - // EXTI4 - 0, // pin 4 - // EXTI5_9 - 0, // pin 5 - 1, // pin 6 - 2, // pin 7 - 3, // pin 8 - 4, // pin 9 - // EXTI10_15 - 0, // pin 10 - 1, // pin 11 - 2, // pin 12 - 3, // pin 13 - 4, // pin 14 - 5 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI line 0 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 1); -} - -// EXTI line 1 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 1); -} - -// EXTI line 2 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 1); -} - -// EXTI line 3 -static void gpio_irq3(void) -{ - handle_interrupt_in(3, 1); -} - -// EXTI line 4 -static void gpio_irq4(void) -{ - handle_interrupt_in(4, 1); -} - -// EXTI lines 5 to 9 -static void gpio_irq5(void) -{ - handle_interrupt_in(5, 5); -} - -// EXTI lines 10 to 15 -static void gpio_irq6(void) -{ - handle_interrupt_in(6, 6); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_TSC_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h deleted file mode 100644 index bebf7db0c7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/i2c_api.c deleted file mode 100644 index 42ea4d57d6..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/i2c_api.c +++ /dev/null @@ -1,442 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x4000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; -int i2c3_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C1 pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C2 pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - if ((obj->i2c == I2C_3) && !i2c3_inited) { - i2c3_inited = 1; - __I2C3_CLK_ENABLE(); - // Configure I2C3 pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - uint32_t tim = 0; - - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE) - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - if (SystemCoreClock == 64000000) { - switch (hz) { - case 100000: - tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } else if (SystemCoreClock == 72000000) { - switch (hz) { - case 100000: - tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } - - // Enable the Fast Mode Plus capability - if (hz == 1000000) { - if (obj->i2c == I2C_1) { - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - } - if (obj->i2c == I2C_2) { - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2); - } - if (obj->i2c == I2C_3) { - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3); - } - } - - // I2C configuration - I2cHandle.Init.Timing = tim; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = LONG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; - -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/rtc_api.c deleted file mode 100644 index 6d49409b65..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ - RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // Note: The LSI clock can be measured precisely using a timer input capture. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/us_ticker.c deleted file mode 100644 index 07bcccc51f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h From 5c27455a813a1b5409ca4610a41632637a8775f3 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sat, 21 Mar 2015 23:30:16 +0100 Subject: [PATCH 015/143] [NUCLEO_F334R8] reorg hal part I --- .../TARGET_NUCLEO_F334R8/PeripheralPins.h | 66 ---- .../TARGET_NUCLEO_F334R8/gpio_api.c | 79 ----- .../TARGET_NUCLEO_F334R8/gpio_irq_api.c | 332 ------------------ .../TARGET_NUCLEO_F334R8/gpio_object.h | 75 ---- .../TARGET_NUCLEO_F334R8/mbed_overrides.c | 37 -- .../TARGET_STM/TARGET_NUCLEO_F334R8/pinmap.c | 139 -------- .../TARGET_NUCLEO_F334R8/port_api.c | 103 ------ .../TARGET_STM/TARGET_NUCLEO_F334R8/rtc_api.c | 201 ----------- .../TARGET_STM/TARGET_NUCLEO_F334R8/sleep.c | 61 ---- .../TARGET_STM/TARGET_NUCLEO_F334R8/spi_api.c | 285 --------------- .../TARGET_NUCLEO_F334R8/us_ticker.c | 70 ---- .../TARGET_NUCLEO_F334R8/PeripheralNames.h | 0 .../TARGET_NUCLEO_F334R8/PeripheralPins.c | 0 .../TARGET_NUCLEO_F334R8/PinNames.h | 0 .../TARGET_NUCLEO_F334R8/PortNames.h | 0 .../TARGET_NUCLEO_F334R8/device.h | 0 .../TARGET_NUCLEO_F334R8/objects.h | 0 17 files changed, 1448 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/mbed_overrides.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/rtc_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/spi_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/us_ticker.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/objects.h (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.h deleted file mode 100644 index cc2fcaaf11..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_api.c deleted file mode 100644 index b9ff5c114b..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRRL; - obj->reg_clr = &gpio->BSRRH; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_irq_api.c deleted file mode 100644 index f7772f5510..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_irq_api.c +++ /dev/null @@ -1,332 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15) -#define CHANNEL_NUM (7) - -// Max pins for one line (max with EXTI10_15) -#define MAX_PIN_LINE (6) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0 - 0, // pin 0 - // EXTI1 - 0, // pin 1 - // EXTI2 - 0, // pin 2 - // EXTI3 - 0, // pin 3 - // EXTI4 - 0, // pin 4 - // EXTI5_9 - 0, // pin 5 - 1, // pin 6 - 2, // pin 7 - 3, // pin 8 - 4, // pin 9 - // EXTI10_15 - 0, // pin 10 - 1, // pin 11 - 2, // pin 12 - 3, // pin 13 - 4, // pin 14 - 5 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI line 0 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 1); -} - -// EXTI line 1 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 1); -} - -// EXTI line 2 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 1); -} - -// EXTI line 3 -static void gpio_irq3(void) -{ - handle_interrupt_in(3, 1); -} - -// EXTI line 4 -static void gpio_irq4(void) -{ - handle_interrupt_in(4, 1); -} - -// EXTI lines 5 to 9 -static void gpio_irq5(void) -{ - handle_interrupt_in(5, 5); -} - -// EXTI lines 10 to 15 -static void gpio_irq6(void) -{ - handle_interrupt_in(6, 6); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_TSC_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h deleted file mode 100644 index bebf7db0c7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pinmap.c deleted file mode 100644 index 0070028644..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) { - pupd = 0; // Open-drain = No pull-up/No pull-down - } - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/rtc_api.c deleted file mode 100644 index 6d49409b65..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ - RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // Note: The LSI clock can be measured precisely using a timer input capture. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/spi_api.c deleted file mode 100644 index 2bf49f46a2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/spi_api.c +++ /dev/null @@ -1,285 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - __SPI1_CLK_ENABLE(); - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz (HSI) or 1.13 MHz (HSE) - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Values depend of APB2CLK : 64 MHz if HSI is used, 72 MHz if HSE is used - if (hz < 500000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 281 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 563 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz - } else if ((hz >= 16000000) && (hz < 32000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz - } else { // >= 32000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/us_ticker.c deleted file mode 100644 index 07bcccc51f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h From 20221e13766aa1255e52d411427539a88776716d Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sat, 21 Mar 2015 23:50:21 +0100 Subject: [PATCH 016/143] [DISCO_F334C8] reorg hal part I --- .../TARGET_DISCO_F334C8/analogin_api.c | 28 +-- .../TARGET_DISCO_F334C8/analogout_api.c | 8 +- .../TARGET_STM/TARGET_DISCO_F334C8/gpio_api.c | 79 ------- .../TARGET_DISCO_F334C8/gpio_object.h | 75 ------ .../TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c | 15 +- .../TARGET_DISCO_F334C8/mbed_overrides.c | 37 --- .../TARGET_STM/TARGET_DISCO_F334C8/pinmap.c | 139 ------------ .../TARGET_STM/TARGET_DISCO_F334C8/port_api.c | 103 --------- .../TARGET_DISCO_F334C8/pwmout_api.c | 66 +----- .../TARGET_STM/TARGET_DISCO_F334C8/rtc_api.c | 201 ----------------- .../TARGET_DISCO_F334C8/serial_api.c | 27 +-- .../TARGET_STM/TARGET_DISCO_F334C8/sleep.c | 61 ----- .../TARGET_STM/TARGET_DISCO_F334C8/spi_api.c | 25 +- .../TARGET_DISCO_F334C8/us_ticker.c | 70 ------ .../TARGET_DISCO_F334C8/PeripheralNames.h | 0 .../TARGET_DISCO_F334C8/PeripheralPins.c | 213 ++++++++++++++++++ .../TARGET_DISCO_F334C8/PinNames.h | 0 .../TARGET_DISCO_F334C8/PortNames.h | 0 .../TARGET_DISCO_F334C8/device.h | 0 .../TARGET_DISCO_F334C8/objects.h | 0 20 files changed, 219 insertions(+), 928 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/mbed_overrides.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/rtc_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/us_ticker.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/PeripheralNames.h (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralPins.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/objects.h (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c index 079d5058ff..7eb7958e93 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c @@ -33,33 +33,7 @@ #include "wait_api.h" #include "cmsis.h" #include "pinmap.h" - -static const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - ARDUINO - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - ARDUINO - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - ARDUINO - {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 - {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 - - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - ARDUINO - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 - {PB_12, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN13 - {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PB_14, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN14 - {PB_15, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN15 - - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - ARDUINO - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - ARDUINO - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 - {PC_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN11 - {NC, NC, 0} -}; +#include "PeripheralPins.h" ADC_HandleTypeDef AdcHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c index a1fa26a3c0..351c38a9a5 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c @@ -33,16 +33,10 @@ #include "cmsis.h" #include "pinmap.h" #include "mbed_error.h" +#include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits -static const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT2 (Warning: LED1 is also on this pin) - {PA_6, DAC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC2_OUT1 - {NC, NC, 0} -}; - static DAC_HandleTypeDef DacHandle; // These variables are used for the "free" function diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_api.c deleted file mode 100644 index b9ff5c114b..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRRL; - obj->reg_clr = &gpio->BSRRH; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h deleted file mode 100644 index bebf7db0c7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c index 345656aa57..1dd2b6060a 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c @@ -34,6 +34,7 @@ #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" /* Timeout values for flags and events waiting loops. These timeouts are not based on accurate values, they just guarantee that the application will @@ -41,20 +42,6 @@ #define FLAG_TIMEOUT ((int)0x4000) #define LONG_TIMEOUT ((int)0x8000) -static const PinMap PinMap_I2C_SDA[] = { - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - I2C_HandleTypeDef I2cHandle; int i2c1_inited = 0; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pinmap.c deleted file mode 100644 index 0070028644..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) { - pupd = 0; // Open-drain = No pull-up/No pull-down - } - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c index b2aa63a18e..3060fc085c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c @@ -34,71 +34,7 @@ #include "cmsis.h" #include "pinmap.h" #include "mbed_error.h" - -// TIM2 cannot be used because already used by the us_ticker -static const PinMap PinMap_PWM[] = { -// {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1N -// {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1 -// {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 - {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH2 - {PA_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 -// {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO -// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2 -// {PA_9, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3 -// {PA_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH4 -// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1)}, // TIM1_CH4 - {PA_12, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 -// {PA_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - {PA_13, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N -// {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - - {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 -// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 -// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N -// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO --> USED BY TIMER - {PB_4, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - ARDUINO -// {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO -// {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_5, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17)}, // TIM17_CH1 - {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N - ARDUINO -// {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1N - {PB_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3)}, // TIM3_CH4 - {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 -// {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO --> USED BY TIMER -// {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1 -// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2 -// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15)}, // TIM15_CH1N -// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH3N - - {PC_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1 - {PC_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2 - {PC_2, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3 - {PC_3, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4 - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PC_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH1N - - {PF_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N - {NC, NC, 0} -}; +#include "PeripheralPins.h" static TIM_HandleTypeDef TimHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/rtc_api.c deleted file mode 100644 index 6d49409b65..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ - RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // Note: The LSI clock can be measured precisely using a timer input capture. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c index 0f9b83ca57..5c8692a3d9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c @@ -34,34 +34,9 @@ #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" #include -static const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - #define UART_NUM (3) static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c index 32bc3a917b..c74a04d5ed 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c @@ -35,30 +35,7 @@ #include #include "cmsis.h" #include "pinmap.h" - -static const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; +#include "PeripheralPins.h" static SPI_HandleTypeDef SpiHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/us_ticker.c deleted file mode 100644 index 95f5a2c27f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralPins.c new file mode 100644 index 0000000000..00edef2cfe --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralPins.c @@ -0,0 +1,213 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - ARDUINO + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - ARDUINO + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - ARDUINO + {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 + {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 + {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 + + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - ARDUINO + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 + {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 + {PB_12, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN13 + {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 + {PB_14, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN14 + {PB_15, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN15 + + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - ARDUINO + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - ARDUINO + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {PC_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 + {PC_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN11 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT2 (Warning: LED1 is also on this pin) + {PA_6, DAC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC2_OUT1 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 +// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 + {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 + {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 + {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH2 + {PA_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 +// {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 +// {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO +// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2 +// {PA_9, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH3 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3 +// {PA_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH4 +// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1)}, // TIM1_CH4 + {PA_12, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 +// {PA_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + {PA_13, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N +// {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + + {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 +// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 +// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N +// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO --> USED BY TIMER + {PB_4, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - ARDUINO +// {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO +// {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PB_5, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17)}, // TIM17_CH1 + {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N - ARDUINO +// {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1N + {PB_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3)}, // TIM3_CH4 + {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 + {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO --> USED BY TIMER +// {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N + {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1 +// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2 +// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15)}, // TIM15_CH1N +// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH3N + + {PC_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1 + {PC_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2 + {PC_2, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3 + {PC_3, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4 + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH1N + + {PF_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h From e74074eba88807da6b0ce0ce22742af8eb528680 Mon Sep 17 00:00:00 2001 From: Sissors Date: Sun, 22 Mar 2015 15:15:40 +0100 Subject: [PATCH 017/143] [HAL][K20XX/KLXX] Fixed deepsleep power consumption when AnalogIn is used The power consumption was reported by Paul Staron to be 100uA higher when an AnalogIn was used previously. Problem 1 is that 40uA was used by the async ADC clock, which is never actually used, so it is disabled. Problem 2 is that setting it for high speed mode increased it by another 60uA while in deepsleep. This currently seems to me to be possibly a bug in the design, but the workaround is checking if this is the case before going to deepsleep, and if yes, disable it. Afterwards it is re-enabled. --- .../TARGET_Freescale/TARGET_K20XX/analogin_api.c | 1 - .../hal/TARGET_Freescale/TARGET_K20XX/sleep.c | 13 +++++++++++++ .../hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c | 1 - .../hal/TARGET_Freescale/TARGET_KLXX/sleep.c | 13 +++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c index 473c5d0394..f7c4cf1f90 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c @@ -51,7 +51,6 @@ void analogin_init(analogin_t *obj, PinName pin) { | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb or ADxxa channels - | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable | ADC_CFG2_ADHSC_MASK // High-Speed Configuration | ADC_CFG2_ADLSTS(0); // Long Sample Time Select diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c index 6ccb7e5d88..4a7dced648 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c @@ -29,6 +29,15 @@ void sleep(void) //Very low-power stop mode void deepsleep(void) { + //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA) + uint8_t ADC_HSC = 0; + if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) { + if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) { + ADC_HSC = 1; + ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK); + } + } + //Check if PLL/FLL is enabled: uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); @@ -67,4 +76,8 @@ void deepsleep(void) while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked #endif } + + if (ADC_HSC) { + ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK); + } } diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c index 4e3f52c35c..e9cad0db3d 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c @@ -58,7 +58,6 @@ void analogin_init(analogin_t *obj, PinName pin) { | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock: (Bus Clock)/2 ADC0->CFG2 = cfg2_muxsel // ADxxb or ADxxa channels - | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable | ADC_CFG2_ADHSC_MASK // High-Speed Configuration | ADC_CFG2_ADLSTS(0); // Long Sample Time Select diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c index 9645e30c53..c3ea772007 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c @@ -30,6 +30,15 @@ void sleep(void) //Very low-power stop mode void deepsleep(void) { + //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA) + uint8_t ADC_HSC = 0; + if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) { + if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) { + ADC_HSC = 1; + ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK); + } + } + #if ! defined(TARGET_KL43Z) //Check if PLL/FLL is enabled: uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); @@ -54,4 +63,8 @@ void deepsleep(void) MCG->C1 &= ~MCG_C1_CLKS_MASK; } #endif + + if (ADC_HSC) { + ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK); + } } From 8176b7c7739252b8f31bc09b27d59cdad3c56ffc Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 22 Mar 2015 16:35:00 +0100 Subject: [PATCH 018/143] [DISCO_F303VC] reorg hal part i --- .../TARGET_DISCO_F303VC/analogin_api.c | 29 +- .../TARGET_DISCO_F303VC/analogout_api.c | 7 +- .../TARGET_STM/TARGET_DISCO_F303VC/gpio_api.c | 79 ----- .../TARGET_DISCO_F303VC/gpio_object.h | 75 ----- .../TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c | 20 +- .../TARGET_DISCO_F303VC/mbed_overrides.c | 37 --- .../TARGET_STM/TARGET_DISCO_F303VC/pinmap.c | 143 --------- .../TARGET_STM/TARGET_DISCO_F303VC/port_api.c | 103 ------- .../TARGET_DISCO_F303VC/pwmout_api.c | 107 +------ .../TARGET_STM/TARGET_DISCO_F303VC/rtc_api.c | 201 ------------- .../TARGET_DISCO_F303VC/serial_api.c | 25 +- .../TARGET_STM/TARGET_DISCO_F303VC/sleep.c | 61 ---- .../TARGET_STM/TARGET_DISCO_F303VC/spi_api.c | 40 +-- .../TARGET_DISCO_F303VC/us_ticker.c | 70 ----- .../TARGET_DISCO_F303VC/PeripheralNames.h | 0 .../TARGET_DISCO_F303VC/PeripheralPins.c | 271 ++++++++++++++++++ .../TARGET_DISCO_F303VC/PinNames.h | 0 .../TARGET_DISCO_F303VC/PortNames.h | 0 .../TARGET_DISCO_F303VC/device.h | 0 .../TARGET_DISCO_F303VC/objects.h | 0 .../hal/TARGET_STM/TARGET_STM32F3/pinmap.c | 6 + 21 files changed, 283 insertions(+), 991 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/mbed_overrides.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/rtc_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/us_ticker.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/PeripheralNames.h (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralPins.c rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/objects.h (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c index c7414430b4..065b8a3969 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c @@ -33,34 +33,7 @@ #include "wait_api.h" #include "cmsis.h" #include "pinmap.h" - -static const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 - {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 - {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 - - {PB_0, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN12 - {PB_1, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 - {PB_11, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PB_13, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 - - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 - {PC_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN11 - - {PF_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PF_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {NC, NC, 0} -}; +#include "PeripheralPins.h" ADC_HandleTypeDef AdcHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c index 33881d6640..14ac79a42f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c @@ -33,15 +33,10 @@ #include "cmsis.h" #include "pinmap.h" #include "mbed_error.h" +#include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits -static const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT2 - {NC, NC, 0} -}; - static DAC_HandleTypeDef DacHandle; void analogout_init(dac_t *obj, PinName pin) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_api.c deleted file mode 100644 index b9ff5c114b..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRRL; - obj->reg_clr = &gpio->BSRRH; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h deleted file mode 100644 index bebf7db0c7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c index 77cb9b59ad..4f0965705a 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c @@ -34,6 +34,7 @@ #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" /* Timeout values for flags and events waiting loops. These timeouts are not based on accurate values, they just guarantee that the application will @@ -41,25 +42,6 @@ #define FLAG_TIMEOUT ((int)0x4000) #define LONG_TIMEOUT ((int)0x8000) -static const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_6, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - I2C_HandleTypeDef I2cHandle; int i2c1_inited = 0; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pinmap.c deleted file mode 100644 index 1d86ace8cc..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pinmap.c +++ /dev/null @@ -1,143 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortE: - gpio_add = GPIOE_BASE; - __GPIOE_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) { - pupd = 0; // Open-drain = No pull-up/No pull-down - } - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c index a4bde735c2..8a13ddec36 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c @@ -34,112 +34,7 @@ #include "cmsis.h" #include "pinmap.h" #include "mbed_error.h" - -// TIM2 cannot be used because already used by the us_ticker -static const PinMap PinMap_PWM[] = { - /* - * The lines below show all combinations to conect a port pin with a timer. Commented - * lines are alternative possibilities not used per default. But they can be changed - * manually instead of the suggested configuration. For example you can see that on - * PA_5 you can have a PWM using either Timer2/Channel1 or Timer8/Channel1N. Today I - * have decided to use Timer2/Channel1. But you can also notice that Timer2/Channel1 - * is also used on PA_0. That means that today you cannot output two different PWM - * signals on PA_0 and PA_5 at the same time. If someone wants this, he will need to - * change the timer that is used on PA_5. This is why the other possibilities are - * commented to make this change easier without looking deeply into the mcu datasheet. - */ - {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1N - {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1 - {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH2 - {PA_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - //{PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2 -// {PA_9, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1)}, // TIM1_CH4 -// {PA_11, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH1 -// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - {PA_12, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 -// {PA_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N -// {PA_12, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH2 - {PA_13, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N -// {PA_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - {PA_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH2 - - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - //{PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N - //{PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N - //{PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N - //{PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N - {PB_4, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - //{PB_4, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8)}, // TIM8_CH2N - //{PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PB_5, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17)},// TIM17_CH1 - //{PB_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)},// TIM8_CH3N - //{PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},// TIM3_CH2 - {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N - //{PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - //{PB_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH1 - {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1N - //{PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - //{PB_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3)}, // TIM3_CH4 - {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 - //{PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 - //{PB_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH2 - {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 - //{PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 - //{PB_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH3 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N - {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1 -// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N - {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2 -// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15)}, // TIM15_CH1N -// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH3N - - //{PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1 - //{PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2 - //{PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3 - //{PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4 - {PC_10, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N - {PC_11, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N - {PC_12, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N - {PC_13, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4N - - {PD_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4 - {PD_12, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 - - {PE_0, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM16)}, // TIM16_CH1 - {PE_1, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM17)}, // TIM17_CH1 - {PE_2, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PE_3, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PE_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PE_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PE_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4 - - {PF_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N - - {NC, NC, 0} -}; +#include "PeripheralPins.h" static TIM_HandleTypeDef TimHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/rtc_api.c deleted file mode 100644 index 6d49409b65..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */ - RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // Note: The LSI clock can be measured precisely using a timer input capture. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c index 1cce7782a8..42b8e3bbf7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c @@ -34,32 +34,9 @@ #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" #include -static const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, - {NC, NC, 0} -}; - #define UART_NUM (3) static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c index 38cdd88fea..7eea114271 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c @@ -35,45 +35,7 @@ #include #include "cmsis.h" #include "pinmap.h" - -static const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - //{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - //{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - //{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PF_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PF_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - //{PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - //{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PD_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, - {NC, NC, 0} -}; +#include "PeripheralPins.h" static SPI_HandleTypeDef SpiHandle; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/us_ticker.c deleted file mode 100644 index 95f5a2c27f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralPins.c new file mode 100644 index 0000000000..be94488565 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralPins.c @@ -0,0 +1,271 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 + {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 + {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 + {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 + + {PB_0, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN12 + {PB_1, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 + {PB_11, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 + {PB_13, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 + + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {PC_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN5 + {PC_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN11 + + {PF_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 + {PF_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_6, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + /* + * The lines below show all combinations to conect a port pin with a timer. Commented + * lines are alternative possibilities not used per default. But they can be changed + * manually instead of the suggested configuration. For example you can see that on + * PA_5 you can have a PWM using either Timer2/Channel1 or Timer8/Channel1N. Today I + * have decided to use Timer2/Channel1. But you can also notice that Timer2/Channel1 + * is also used on PA_0. That means that today you cannot output two different PWM + * signals on PA_0 and PA_5 at the same time. If someone wants this, he will need to + * change the timer that is used on PA_5. This is why the other possibilities are + * commented to make this change easier without looking deeply into the mcu datasheet. + */ + {PA_1, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1N + {PA_2, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH1 + {PA_3, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15)}, // TIM15_CH2 + {PA_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 + //{PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 +// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 +// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2 +// {PA_9, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2)}, // TIM2_CH3 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1)}, // TIM1_CH4 +// {PA_11, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH1 +// {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N + {PA_12, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 +// {PA_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N +// {PA_12, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4)}, // TIM4_CH2 + {PA_13, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N +// {PA_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + {PA_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH2 + + {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + //{PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N + //{PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N + //{PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N + //{PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PB_3, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N + {PB_4, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 + //{PB_4, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8)}, // TIM8_CH2N + //{PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PB_5, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17)},// TIM17_CH1 + //{PB_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)},// TIM8_CH3N + //{PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},// TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1N + //{PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 + //{PB_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8)}, // TIM8_CH1 + {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1N + //{PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + //{PB_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3)}, // TIM3_CH4 + {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16)}, // TIM16_CH1 + //{PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 + //{PB_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH2 + {PB_9, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17)}, // TIM17_CH1 + //{PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 + //{PB_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8)}, // TIM8_CH3 + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH1N + {PB_14, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH1 +// {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH2N + {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15)}, // TIM15_CH2 +// {PB_15, PWM_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15)}, // TIM15_CH1N +// {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1)}, // TIM1_CH3N + + //{PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1 + //{PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2 + //{PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3 + //{PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4 + {PC_10, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH1N + {PC_11, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH2N + {PC_12, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH3N + {PC_13, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4N + + {PD_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 + + {PE_0, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM16)}, // TIM16_CH1 + {PE_1, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM17)}, // TIM17_CH1 + {PE_2, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PE_3, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PE_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PE_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PE_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1)}, // TIM1_CH4 + + {PF_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1)}, // TIM1_CH3N + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, + {NC, NC, 0} +}; + + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + //{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + //{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + //{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PF_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + //{PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + //{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c index e3e1fb9c81..3532124c4c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c @@ -71,6 +71,12 @@ uint32_t Set_GPIO_Clock(uint32_t port_idx) gpio_add = GPIOD_BASE; __GPIOD_CLK_ENABLE(); break; +#if defined(GPIOE_BASE) + case PortE: + gpio_add = GPIOE_BASE; + __GPIOE_CLK_ENABLE(); + break; +#endif case PortF: gpio_add = GPIOF_BASE; __GPIOF_CLK_ENABLE(); From 5e01a14bf1c2bc03a82361bda1c08d56bb89352f Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 23 Mar 2015 01:01:30 +0100 Subject: [PATCH 019/143] [DISCO_F303VC] reorg hal part II --- .../TARGET_DISCO_F303VC/analogout_api.c | 123 ----- .../TARGET_DISCO_F303VC/gpio_irq_api.c | 262 ----------- .../TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c | 428 ------------------ .../TARGET_DISCO_F303VC/serial_api.c | 352 -------------- .../TARGET_STM/TARGET_DISCO_F303VC/spi_api.c | 297 ------------ .../TARGET_DISCO_F303VC/PeripheralNames.h | 4 +- .../hal/TARGET_STM/TARGET_STM32F3/i2c_api.c | 4 + .../TARGET_STM/TARGET_STM32F3/serial_api.c | 20 +- .../hal/TARGET_STM/TARGET_STM32F3/spi_api.c | 35 +- 9 files changed, 58 insertions(+), 1467 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c deleted file mode 100644 index 14ac79a42f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogout_api.c +++ /dev/null @@ -1,123 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -void analogout_init(dac_t *obj, PinName pin) -{ - DAC_ChannelConfTypeDef sConfig; - - // Get the peripheral name from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the pin for future use - obj->pin = pin; - - // Enable DAC clock - __DAC1_CLK_ENABLE(); - - // Configure DAC - DacHandle.Instance = (DAC_TypeDef *)(obj->dac); - - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) -{ - // Reset DAC and disable clock - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); - - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); -} - -static inline int dac_read(dac_t *obj) -{ - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_irq_api.c deleted file mode 100644 index a32e1f5f02..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_irq_api.c +++ /dev/null @@ -1,262 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -#define CHANNEL_NUM (7) - -static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index) -{ - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]); - uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - } - - if (channel_ids[irq_index] == 0) return; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(channel_ids[irq_index], IRQ_FALL); - } else { - irq_handler(channel_ids[irq_index], IRQ_RISE); - } -} - -// The irq_index is passed to the function -// EXTI line 0 -static void gpio_irq0(void) -{ - handle_interrupt_in(0); -} -// EXTI line 1 -static void gpio_irq1(void) -{ - handle_interrupt_in(1); -} -// EXTI line 2 -static void gpio_irq2(void) -{ - handle_interrupt_in(2); -} -// EXTI line 3 -static void gpio_irq3(void) -{ - handle_interrupt_in(3); -} -// EXTI line 4 -static void gpio_irq4(void) -{ - handle_interrupt_in(4); -} -// EXTI lines 5 to 9 -static void gpio_irq5(void) -{ - handle_interrupt_in(5); -} -// EXTI lines 10 to 15 -static void gpio_irq6(void) -{ - handle_interrupt_in(6); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_TSC_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - channel_ids[irq_index] = id; - channel_gpio[irq_index] = gpio_add; - channel_pin[irq_index] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->irq_index] = 0; - channel_gpio[obj->irq_index] = 0; - channel_pin[obj->irq_index] = 0; - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c deleted file mode 100644 index 4f0965705a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/i2c_api.c +++ /dev/null @@ -1,428 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x4000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C1 pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C2 pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - uint32_t tim = 0; - - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE) - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - if (SystemCoreClock == 64000000) { - switch (hz) { - case 100000: - tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } else if (SystemCoreClock == 72000000) { - switch (hz) { - case 100000: - tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } - - // Enable the Fast Mode Plus capability - if (hz == 1000000) { - if (obj->i2c == I2C_1) { - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - } - if (obj->i2c == I2C_2) { - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2); - } - } - - // I2C configuration - I2cHandle.Init.Timing = tim; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = LONG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // wait before reset - timeout = LONG_TIMEOUT; - while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; - -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c deleted file mode 100644 index 42b8e3bbf7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/serial_api.c +++ /dev/null @@ -1,352 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock + switch to SystemClock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK); - obj->index = 0; - } - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK); - obj->index = 1; - } - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); - obj->index = 2; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->RDR & (uint8_t)0xFF); - } else { - return (int)(uart->RDR & (uint16_t)0x1FF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->TDR = (uint8_t)(c & (uint8_t)0xFF); - } else { - uart->TDR = (uint16_t)(c & (uint16_t)0x1FF); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); -} - -void serial_break_clear(serial_t *obj) -{ -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c deleted file mode 100644 index 7eea114271..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/spi_api.c +++ /dev/null @@ -1,297 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - if (obj->spi == SPI_3) { - __SPI3_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz (HSI) or 1.13 MHz (HSE) - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - if (obj->spi == SPI_3) { - __SPI3_FORCE_RESET(); - __SPI3_RELEASE_RESET(); - __SPI3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Values depend of APB1CLK : 32 MHz if HSI is used, 36 MHz if HSE is used - if (hz < 250000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz - } else if ((hz >= 250000) && (hz < 500000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 280 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 560 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz - } else { // >= 16000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h index ad058fe05a..619f275f67 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h @@ -50,8 +50,8 @@ typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, UART_3 = (int)USART3_BASE, - UART_4 = (int)USART3_BASE, - UART_5 = (int)USART3_BASE + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE } UARTName; #define STDIO_UART_TX PA_2 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c index 42ea4d57d6..b7e50133c1 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c @@ -79,6 +79,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(scl, OpenDrain); } +#if defined(I2C3_BASE) if ((obj->i2c == I2C_3) && !i2c3_inited) { i2c3_inited = 1; __I2C3_CLK_ENABLE(); @@ -88,6 +89,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(sda, OpenDrain); pin_mode(scl, OpenDrain); } +#endif // Reset to clear pending flags if any i2c_reset(obj); @@ -160,9 +162,11 @@ void i2c_frequency(i2c_t *obj, int hz) if (obj->i2c == I2C_2) { __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2); } +#if defined(I2C3_BASE) if (obj->i2c == I2C_3) { __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3); } +#endif } // I2C configuration diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c index 9205f5d3f1..9c3b5a6b88 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c @@ -37,9 +37,9 @@ #include #include "PeripheralPins.h" -#define UART_NUM (3) +#define UART_NUM (5) -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0}; static uart_irq_handler irq_handler; @@ -99,16 +99,20 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); obj->index = 2; } +#if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_CLK_ENABLE(); __HAL_RCC_UART4_CONFIG(RCC_UART4CLKSOURCE_SYSCLK); obj->index = 3; } +#endif +#if defined(UART5_BASE) if (obj->uart == UART_5) { __UART5_CLK_ENABLE(); __HAL_RCC_UART5_CONFIG(RCC_UART5CLKSOURCE_SYSCLK); obj->index = 4; } +#endif // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); @@ -156,16 +160,20 @@ void serial_free(serial_t *obj) __USART3_RELEASE_RESET(); __USART3_CLK_DISABLE(); } +#if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_FORCE_RESET(); __UART4_RELEASE_RESET(); __UART4_CLK_DISABLE(); } +#endif +#if defined(UART5_BASE) if (obj->uart == UART_5) { __UART5_FORCE_RESET(); __UART5_RELEASE_RESET(); __UART5_CLK_DISABLE(); } +#endif // Configure GPIOs pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -245,15 +253,19 @@ static void uart3_irq(void) uart_irq(UART_3, 2); } +#if defined(UART4_BASE) static void uart4_irq(void) { uart_irq(UART_4, 3); } +#endif +#if defined(UART5_BASE) static void uart5_irq(void) { uart_irq(UART_5, 4); } +#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -283,15 +295,19 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart3_irq; } +#if defined(UART4_BASE) if (obj->uart == UART_4) { irq_n = UART4_IRQn; vector = (uint32_t)&uart4_irq; } +#endif +#if defined(UART5_BASE) if (obj->uart == UART_5) { irq_n = UART5_IRQn; vector = (uint32_t)&uart5_irq; } +#endif if (enable) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c index e05cbce570..3993e0a17e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -81,13 +81,17 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel __SPI1_CLK_ENABLE(); } +#if defined(SPI2_BASE) if (obj->spi == SPI_2) { __SPI2_CLK_ENABLE(); } +#endif +#if defined(SPI3_BASE) if (obj->spi == SPI_3) { __SPI3_CLK_ENABLE(); } +#endif // Configure the SPI pins pinmap_pinout(mosi, PinMap_SPI_MOSI); @@ -98,7 +102,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->bits = SPI_DATASIZE_8BIT; obj->cpol = SPI_POLARITY_LOW; obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_32; +#if defined(TARGET_STM32F334C8) + obj->br_presc = SPI_BAUDRATEPRESCALER_256; +#else + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz (HSI) or 1.13 MHz (HSE) +#endif obj->pin_miso = miso; obj->pin_mosi = mosi; @@ -126,17 +134,21 @@ void spi_free(spi_t *obj) __SPI1_CLK_DISABLE(); } +#if defined(SPI2_BASE) if (obj->spi == SPI_2) { __SPI2_FORCE_RESET(); __SPI2_RELEASE_RESET(); __SPI2_CLK_DISABLE(); } +#endif +#if defined(SPI3_BASE) if (obj->spi == SPI_3) { __SPI3_FORCE_RESET(); __SPI3_RELEASE_RESET(); __SPI3_CLK_DISABLE(); } +#endif // Configure GPIOs pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -186,6 +198,26 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) void spi_frequency(spi_t *obj, int hz) { +#if defined(TARGET_STM32F334C8) + // Values depend of APB2CLK : 64 MHz if HSI is used, 72 MHz if HSE is used + if (hz < 500000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 281 kHz + } else if ((hz >= 500000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 563 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz + } else if ((hz >= 2000000) && (hz < 4000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz + } else if ((hz >= 4000000) && (hz < 8000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz + } else if ((hz >= 8000000) && (hz < 16000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz + } else if ((hz >= 16000000) && (hz < 32000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz + } else { // >= 32000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz + } +#else // Values depend of APB1CLK and APB2CLK : 32 MHz if HSI is used, 36 MHz if HSE is used if (obj->spi == SPI_1) { if (hz < 500000) { @@ -224,6 +256,7 @@ void spi_frequency(spi_t *obj, int hz) obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz } } +#endif init_spi(obj); } From 42408ce533288347248fff413afdcc7cb516d35e Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 23 Mar 2015 01:32:32 +0100 Subject: [PATCH 020/143] [DISCO_NUCLEO_F334xx] reorg hal part II --- .../TARGET_DISCO_F334C8/analogout_api.c | 168 ------- .../TARGET_DISCO_F334C8/gpio_irq_api.c | 262 ----------- .../TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c | 410 ----------------- .../TARGET_DISCO_F334C8/serial_api.c | 349 --------------- .../TARGET_STM/TARGET_DISCO_F334C8/spi_api.c | 285 ------------ .../TARGET_NUCLEO_F334R8/analogout_api.c | 169 ------- .../TARGET_STM/TARGET_NUCLEO_F334R8/i2c_api.c | 411 ------------------ .../TARGET_NUCLEO_F334R8/serial_api.c | 349 --------------- .../TARGET_STM/TARGET_STM32F3/analogout_api.c | 23 +- .../hal/TARGET_STM/TARGET_STM32F3/i2c_api.c | 4 + 10 files changed, 24 insertions(+), 2406 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c deleted file mode 100644 index 351c38a9a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogout_api.c +++ /dev/null @@ -1,168 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -// These variables are used for the "free" function -static int pa4_used = 0; -static int pa5_used = 0; - -void analogout_init(dac_t *obj, PinName pin) -{ - DAC_ChannelConfTypeDef sConfig; - - // Get the peripheral name (DAC_1, DAC_2...) from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the pin for future use - obj->pin = pin; - - // Enable DAC clock - if (obj->dac == DAC_1) { - __DAC1_CLK_ENABLE(); - } - if (obj->dac == DAC_2) { - __DAC2_CLK_ENABLE(); - } - - // Configure DAC - DacHandle.Instance = (DAC_TypeDef *)(obj->dac); - - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - - if (pin == PA_4) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - pa4_used = 1; - } - - if (pin == PA_5) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2); - pa5_used = 1; - } - - if (pin == PA_6) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - } - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) -{ - // Reset DAC and disable clock - if (obj->pin == PA_4) pa4_used = 0; - if (obj->pin == PA_5) pa5_used = 0; - - if ((pa4_used == 0) && (pa5_used == 0)) { - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); - } - - if (obj->pin == PA_6) { - __DAC2_FORCE_RESET(); - __DAC2_RELEASE_RESET(); - __DAC2_CLK_DISABLE(); - } - - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ - if ((obj->pin == PA_4) || (obj->pin == PA_6)) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); - } - - if (obj->pin == PA_5) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); - } -} - -static inline int dac_read(dac_t *obj) -{ - if ((obj->pin == PA_4) || (obj->pin == PA_6)) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); - } else if (obj->pin == PA_5) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); - } else { - return 0; - } -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_irq_api.c deleted file mode 100644 index a32e1f5f02..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_irq_api.c +++ /dev/null @@ -1,262 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -#define CHANNEL_NUM (7) - -static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index) -{ - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]); - uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - } - - if (channel_ids[irq_index] == 0) return; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(channel_ids[irq_index], IRQ_FALL); - } else { - irq_handler(channel_ids[irq_index], IRQ_RISE); - } -} - -// The irq_index is passed to the function -// EXTI line 0 -static void gpio_irq0(void) -{ - handle_interrupt_in(0); -} -// EXTI line 1 -static void gpio_irq1(void) -{ - handle_interrupt_in(1); -} -// EXTI line 2 -static void gpio_irq2(void) -{ - handle_interrupt_in(2); -} -// EXTI line 3 -static void gpio_irq3(void) -{ - handle_interrupt_in(3); -} -// EXTI line 4 -static void gpio_irq4(void) -{ - handle_interrupt_in(4); -} -// EXTI lines 5 to 9 -static void gpio_irq5(void) -{ - handle_interrupt_in(5); -} -// EXTI lines 10 to 15 -static void gpio_irq6(void) -{ - handle_interrupt_in(6); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_TSC_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - channel_ids[irq_index] = id; - channel_gpio[irq_index] = gpio_add; - channel_pin[irq_index] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->irq_index] = 0; - channel_gpio[obj->irq_index] = 0; - channel_pin[obj->irq_index] = 0; - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c deleted file mode 100644 index 1dd2b6060a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/i2c_api.c +++ /dev/null @@ -1,410 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x4000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C1 clock and pinout if not done - if ((obj->i2c == I2C_1)&& !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - uint32_t tim = 0; - - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE) - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - if (SystemCoreClock == 64000000) { - switch (hz) { - case 100000: - tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - // Enable the Fast Mode Plus capability - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - break; - default: - break; - } - } else if (SystemCoreClock == 72000000) { - switch (hz) { - case 100000: - tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - // Enable the Fast Mode Plus capability - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - break; - default: - break; - } - } - - // I2C configuration - I2cHandle.Init.Timing = tim; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = LONG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // wait before reset - timeout = LONG_TIMEOUT; - while((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; - -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c deleted file mode 100644 index 5c8692a3d9..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/serial_api.c +++ /dev/null @@ -1,349 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - obj->index = 2; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->RDR & (uint8_t)0xFF); - } else { - return (int)(uart->RDR & (uint16_t)0x1FF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->TDR = (uint8_t)(c & (uint8_t)0xFF); - } else { - uart->TDR = (uint16_t)(c & (uint16_t)0x1FF); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); -} - -void serial_break_clear(serial_t *obj) -{ -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c deleted file mode 100644 index c74a04d5ed..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/spi_api.c +++ /dev/null @@ -1,285 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - __SPI1_CLK_ENABLE(); - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Values depend of APB2CLK : 64 MHz if HSI is used, 72 MHz if HSE is used - if (hz < 500000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 281 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 563 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz - } else if ((hz >= 16000000) && (hz < 32000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz - } else { // >= 32000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogout_api.c deleted file mode 100644 index b798b4c2f2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogout_api.c +++ /dev/null @@ -1,169 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -// These variables are used for the "free" function -static int pa4_used = 0; -static int pa5_used = 0; - -void analogout_init(dac_t *obj, PinName pin) -{ - DAC_ChannelConfTypeDef sConfig; - - // Get the peripheral name from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the pin for future use - obj->pin = pin; - - // Enable DAC clock - if (obj->dac == DAC_1) { - __DAC1_CLK_ENABLE(); - } - - if (obj->dac == DAC_2) { - __DAC2_CLK_ENABLE(); - } - - // Configure DAC - DacHandle.Instance = (DAC_TypeDef *)(obj->dac); - - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - - if (pin == PA_4) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - pa4_used = 1; - } - - if (pin == PA_5) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2); - pa5_used = 1; - } - - if (pin == PA_6) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - } - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) -{ - // Reset DAC and disable clock - if (obj->pin == PA_4) pa4_used = 0; - if (obj->pin == PA_5) pa5_used = 0; - - if ((pa4_used == 0) && (pa5_used == 0)) { - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); - } - - if (obj->pin == PA_6) { - __DAC2_FORCE_RESET(); - __DAC2_RELEASE_RESET(); - __DAC2_CLK_DISABLE(); - } - - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ - if ((obj->pin == PA_4) || (obj->pin == PA_6)) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); - } - - if (obj->pin == PA_5) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); - } -} - -static inline int dac_read(dac_t *obj) -{ - if ((obj->pin == PA_4) || (obj->pin == PA_6)) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); - } else if (obj->pin == PA_5) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); - } else { - return 0; - } -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/i2c_api.c deleted file mode 100644 index 52c387c2b9..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/i2c_api.c +++ /dev/null @@ -1,411 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x4000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - uint32_t tim = 0; - - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE) - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - if (SystemCoreClock == 64000000) { - switch (hz) { - case 100000: - tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - // Enable the Fast Mode Plus capability - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - break; - default: - break; - } - } else if (SystemCoreClock == 72000000) { - switch (hz) { - case 100000: - tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - // Enable the Fast Mode Plus capability - __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); - break; - default: - break; - } - } - - // I2C configuration - I2cHandle.Init.Timing = tim; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = LONG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - /* update CR2 register */ - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - /* Wait until STOPF flag is set */ - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; - -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/serial_api.c deleted file mode 100644 index ef17f8903a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/serial_api.c +++ /dev/null @@ -1,349 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - obj->index = 2; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->RDR & (uint8_t)0xFF); - } else { - return (int)(uart->RDR & (uint16_t)0x1FF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->TDR = (uint8_t)(c & (uint8_t)0xFF); - } else { - uart->TDR = (uint16_t)(c & (uint16_t)0x1FF); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); -} - -void serial_break_clear(serial_t *obj) -{ -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c index 794f3990ec..0ef508d82f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c @@ -58,7 +58,12 @@ void analogout_init(dac_t *obj, PinName pin) obj->pin = pin; // Enable DAC clock - __DAC1_CLK_ENABLE(); + if (obj->dac == DAC_1) { + __DAC1_CLK_ENABLE(); + } + if (obj->dac == DAC_2) { + __DAC2_CLK_ENABLE(); + } // Configure DAC DacHandle.Instance = (DAC_TypeDef *)(obj->dac); @@ -76,6 +81,10 @@ void analogout_init(dac_t *obj, PinName pin) pa5_used = 1; } + if (pin == PA_6) { + HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); + } + analogout_write_u16(obj, 0); } @@ -91,13 +100,21 @@ void analogout_free(dac_t *obj) __DAC1_CLK_DISABLE(); } +#if defined(__DAC2_FORCE_RESET) + if (obj->pin == PA_6) { + __DAC2_FORCE_RESET(); + __DAC2_RELEASE_RESET(); + __DAC2_CLK_DISABLE(); + } +#endif + // Configure GPIO pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } static inline void dac_write(dac_t *obj, uint16_t value) { - if (obj->pin == PA_4) { + if ((obj->pin == PA_4) || (obj->pin == PA_6)) { HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } @@ -110,7 +127,7 @@ static inline void dac_write(dac_t *obj, uint16_t value) static inline int dac_read(dac_t *obj) { - if (obj->pin == PA_4) { + if ((obj->pin == PA_4) || (obj->pin == PA_6)) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } else if (obj->pin == PA_5) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c index b7e50133c1..c4e0dbde88 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c @@ -69,6 +69,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(scl, OpenDrain); } +#if defined(I2C2_BASE) if ((obj->i2c == I2C_2) && !i2c2_inited) { i2c2_inited = 1; __I2C2_CLK_ENABLE(); @@ -78,6 +79,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(sda, OpenDrain); pin_mode(scl, OpenDrain); } +#endif #if defined(I2C3_BASE) if ((obj->i2c == I2C_3) && !i2c3_inited) { @@ -159,9 +161,11 @@ void i2c_frequency(i2c_t *obj, int hz) if (obj->i2c == I2C_1) { __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1); } +#if defined(I2C2_BASE) if (obj->i2c == I2C_2) { __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2); } +#endif #if defined(I2C3_BASE) if (obj->i2c == I2C_3) { __HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3); From 5a2cd98407848cd43568c52084ca1d7a19522619 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 23 Mar 2015 01:37:56 +0100 Subject: [PATCH 021/143] [NUCLEO_F302R8] reorg hal part II --- .../TARGET_NUCLEO_F302R8/analogout_api.c | 123 ------ .../TARGET_STM/TARGET_NUCLEO_F302R8/pinmap.c | 139 ------- .../TARGET_NUCLEO_F302R8/serial_api.c | 352 ------------------ .../TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c | 299 --------------- 4 files changed, 913 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogout_api.c deleted file mode 100644 index 14ac79a42f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogout_api.c +++ /dev/null @@ -1,123 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -void analogout_init(dac_t *obj, PinName pin) -{ - DAC_ChannelConfTypeDef sConfig; - - // Get the peripheral name from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the pin for future use - obj->pin = pin; - - // Enable DAC clock - __DAC1_CLK_ENABLE(); - - // Configure DAC - DacHandle.Instance = (DAC_TypeDef *)(obj->dac); - - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) -{ - // Reset DAC and disable clock - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); - - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); -} - -static inline int dac_read(dac_t *obj) -{ - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pinmap.c deleted file mode 100644 index 0070028644..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) { - pupd = 0; // Open-drain = No pull-up/No pull-down - } - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c deleted file mode 100644 index 4f83268bf0..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c +++ /dev/null @@ -1,352 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock + switch to SystemClock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK); - obj->index = 0; - } - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK); - obj->index = 1; - } - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); - obj->index = 2; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->RDR & (uint8_t)0xFF); - } else { - return (int)(uart->RDR & (uint16_t)0x1FF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->TDR = (uint8_t)(c & (uint8_t)0xFF); - } else { - uart->TDR = (uint16_t)(c & (uint16_t)0x1FF); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); -} - -void serial_break_clear(serial_t *obj) -{ -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c deleted file mode 100644 index 2799b5bbd4..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c +++ /dev/null @@ -1,299 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - if (obj->spi == SPI_3) { - __SPI3_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz (HSI) or 1.13 MHz (HSE) - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - if (obj->spi == SPI_3) { - __SPI3_FORCE_RESET(); - __SPI3_RELEASE_RESET(); - __SPI3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Values depend of APB1CLK : 32 MHz if HSI is used, 36 MHz if HSE is used - if (hz < 250000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz - } else if ((hz >= 250000) && (hz < 500000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 280 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 560 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz - } else { // >= 16000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif From 88ee51cecd34232e151f8aa926e802df74e3a22b Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 23 Mar 2015 02:00:32 +0100 Subject: [PATCH 022/143] [STM32F3xx] reorg hal - build.py -t GCC_ARM -m xxx OK - make.py -t GCC_ARM -p 26 -m xxx OK --- .../TARGET_DISCO_F303VC/analogin_api.c | 0 .../TARGET_DISCO_F303VC/pwmout_api.c | 0 .../TARGET_DISCO_F334C8/analogin_api.c | 0 .../TARGET_DISCO_F334C8/pwmout_api.c | 0 .../TARGET_NUCLEO_F302R8/analogin_api.c | 0 .../TARGET_NUCLEO_F302R8/pwmout_api.c | 0 .../TARGET_NUCLEO_F303RE/PortNames.h | 1 + .../{ => TARGET_NUCLEO_F303RE}/analogin_api.c | 0 .../{ => TARGET_NUCLEO_F303RE}/pwmout_api.c | 0 .../TARGET_NUCLEO_F334R8/PortNames.h | 1 + .../TARGET_NUCLEO_F334R8/analogin_api.c | 0 .../TARGET_NUCLEO_F334R8/pwmout_api.c | 0 .../TARGET_STM/TARGET_STM32F3/analogout_api.c | 8 +++++++ .../hal/TARGET_STM/TARGET_STM32F3/spi_api.c | 23 +++++++++++++++++++ 14 files changed, 33 insertions(+) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F303VC/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_DISCO_F334C8/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F302R8/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/{ => TARGET_NUCLEO_F303RE}/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/{ => TARGET_NUCLEO_F303RE}/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F3}/TARGET_NUCLEO_F334R8/pwmout_api.c (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h index b1d7307ed0..867090c41c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h @@ -39,6 +39,7 @@ typedef enum { PortB = 1, PortC = 2, PortD = 3, + PortE = 4, PortF = 5 } PortName; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h index b1d7307ed0..867090c41c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h @@ -39,6 +39,7 @@ typedef enum { PortB = 1, PortC = 2, PortD = 3, + PortE = 4, PortF = 5 } PortName; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c index 0ef508d82f..d16411bebc 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c @@ -61,9 +61,11 @@ void analogout_init(dac_t *obj, PinName pin) if (obj->dac == DAC_1) { __DAC1_CLK_ENABLE(); } +#if defined(__DAC2_FORCE_RESET) if (obj->dac == DAC_2) { __DAC2_CLK_ENABLE(); } +#endif // Configure DAC DacHandle.Instance = (DAC_TypeDef *)(obj->dac); @@ -76,10 +78,12 @@ void analogout_init(dac_t *obj, PinName pin) pa4_used = 1; } +#if defined(DAC_CHANNEL_2) if (pin == PA_5) { HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2); pa5_used = 1; } +#endif if (pin == PA_6) { HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); @@ -119,18 +123,22 @@ static inline void dac_write(dac_t *obj, uint16_t value) HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } +#if defined(DAC_CHANNEL_2) if (obj->pin == PA_5) { HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } +#endif } static inline int dac_read(dac_t *obj) { if ((obj->pin == PA_4) || (obj->pin == PA_6)) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); +#if defined(DAC_CHANNEL_2) } else if (obj->pin == PA_5) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); +#endif } else { return 0; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c index 3993e0a17e..af0e058e35 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -77,9 +77,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(obj->spi != (SPIName)NC); // Enable SPI clock +#if defined(SPI1_BASE) if (obj->spi == SPI_1) { __SPI1_CLK_ENABLE(); } +#endif #if defined(SPI2_BASE) if (obj->spi == SPI_2) { @@ -128,11 +130,13 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel void spi_free(spi_t *obj) { // Reset SPI and disable clock +#if defined(SPI1_BASE) if (obj->spi == SPI_1) { __SPI1_FORCE_RESET(); __SPI1_RELEASE_RESET(); __SPI1_CLK_DISABLE(); } +#endif #if defined(SPI2_BASE) if (obj->spi == SPI_2) { @@ -217,6 +221,25 @@ void spi_frequency(spi_t *obj, int hz) } else { // >= 32000000 obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz } +#elif defined(TARGET_STM32F302R8) + if (hz < 250000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz + } else if ((hz >= 250000) && (hz < 500000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 280 kHz + } else if ((hz >= 500000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 560 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz + } else if ((hz >= 2000000) && (hz < 4000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz + } else if ((hz >= 4000000) && (hz < 8000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz + } else if ((hz >= 8000000) && (hz < 16000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz + } else { // >= 16000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz + } + #else // Values depend of APB1CLK and APB2CLK : 32 MHz if HSI is used, 36 MHz if HSE is used if (obj->spi == SPI_1) { From 608f7b368509e2f3af068c54a9eb3d5ba1b53c3f Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 23 Mar 2015 02:10:25 +0100 Subject: [PATCH 023/143] [NUCLEO_L152RE] reorg hal no code changes, only new file/path structure --- .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/PeripheralPins.h | 0 .../{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PeripheralNames.h | 0 .../{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PeripheralPins.c | 0 .../{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PinNames.h | 0 .../{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PortNames.h | 0 .../TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/device.h | 0 .../{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/objects.h | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/analogin_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/analogout_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_irq_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_object.h | 0 .../TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/i2c_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/mbed_overrides.c | 0 .../TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/pinmap.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/port_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/pwmout_api.c | 0 .../TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/rtc_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/serial_api.c | 0 .../TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/sleep.c | 0 .../TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/spi_api.c | 0 .../{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/us_ticker.c | 0 22 files changed, 0 insertions(+), 0 deletions(-) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/PeripheralPins.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32L1}/TARGET_NUCLEO_L152RE/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/analogout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/gpio_object.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/pinmap.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/port_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/rtc_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/sleep.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/spi_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_L152RE => TARGET_STM32L1}/us_ticker.c (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/us_ticker.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/us_ticker.c From 095a9439585d355def6055583435a9ab5cff667a Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 19:56:55 +0900 Subject: [PATCH 024/143] Increase main thread stack size. When the user makes a program , it is often continue to add the process to the main thread . For this reason, increase main thread stack size. --- libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c index faccf7899d..debb4bc2d7 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c @@ -61,7 +61,7 @@ // Defines stack size for main thread. // Default: 200 #ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 512 + #define OS_MAINSTKSIZE 2048 #endif // Number of threads with user-provided stack size <0-250> From aba45564fc279db70ca9419431f8dfcb90fa955f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 19:58:14 +0900 Subject: [PATCH 025/143] Add NVIC wrapper. Add NVIC wrapper because Cortex-A9 use GIC. --- .../TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h | 2 + .../TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c | 42 ++++ .../TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h | 46 ++++ .../TARGET_RZ_A1H/nvic_wrapper.c | 229 ++++++++++++++++++ .../TARGET_RZ_A1H/nvic_wrapper.h | 84 +++++++ 5 files changed, 403 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h index 29af1241af..d60ea44847 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h @@ -644,6 +644,8 @@ typedef enum IRQn #include "pl310.h" #include "gic.h" +#include "nvic_wrapper.h" +#include "cmsis_nvic.h" #include "ostm_iodefine.h" #include "gpio_iodefine.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c new file mode 100644 index 0000000000..052c30c74b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "MBRZA1H.h" + +extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InterruptHandlerRegister(IRQn, (IRQHandler)vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t vectors = (uint32_t)IRQTable[IRQn]; + return vectors; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h new file mode 100644 index 0000000000..2ded075dbe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c new file mode 100644 index 0000000000..6a09dcf067 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c @@ -0,0 +1,229 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file nvic_wrapper.c +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA1H.h" +#include "wdt_iodefine.h" +#include "nvic_wrapper.h" +#include "gic.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */ +#define WDT_WTCNT_WRITE (0x5A00) +#define WDT_WTCSR_WRITE (0xA500) +#define WDT_WRCSR_WOVF_WRITE (0xA500) +#define WDT_WRCSR_RSTE_WRITE (0x5A00) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + + + +/* ########################## NVIC functions #################################### */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_SetBinaryPoint(PriorityGroup); +} + + +uint32_t NVIC_GetPriorityGrouping(void) +{ + return GIC_GetBinaryPoint(0); +} + + +void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_EnableIRQ(IRQn); +} + + +void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_DisableIRQ(IRQn); +} + + +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pending; + + pending = GIC_GetIRQStatus(IRQn); + pending = (pending & 0x00000001); + + return pending; +} + + +void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GIC_SetPendingIRQ(IRQn); +} + + +void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GIC_ClearPendingIRQ(IRQn); +} + + +uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + uint32_t active; + + active = GIC_GetIRQStatus(IRQn); + active = ((active >> 1) & 0x00000001); + + return active; +} + + +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_SetPriority(IRQn, (priority << 3)); +} + + +uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + uint32_t priority_field; + + priority_field = GIC_GetPriority(IRQn); + priority_field = (priority_field >> 3); + return priority_field; +} + + +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + +void NVIC_SystemReset(void) +{ + uint16_t reg; + uint8_t dummy_read; + /* Use Watch Dog Timer to system reset */ + + /* Set WT/IT bit of WTCSR to 1 = Watch Dog */ + /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */ + reg = (WDT_WTCSR_WRITE | 0x0058); + WDTWTCSR = reg; + + /* Clear Count reg */ + reg = (WDT_WTCNT_WRITE | 0x0000); + WDTWTCNT = reg; + + /* Clear WOVF flag */ + dummy_read = WDTWRCSR; + reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000)); + WDTWRCSR = reg; + /* Enable Internal Reset */ + reg = (WDT_WRCSR_RSTE_WRITE | 0x005F); + WDTWRCSR = reg; + + /* Watch Dog start */ + reg = (WDT_WTCSR_WRITE | 0x0078); + WDTWTCSR = reg; + + while(1); /* wait Internal Reset */ +} + +/* ################################## SysTick function ############################################ */ +uint32_t SysTick_Config(uint32_t ticks) +{ + /* Not support this function */ + /* Use mbed Ticker */ + return (1); /* impossible */ +} + + +/* ##################################### Debug In/Output function ########################################### */ +uint32_t ITM_SendChar (uint32_t ch) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (ch); +} + + +int32_t ITM_ReceiveChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (-1); /* no character available */ +} + + +int32_t ITM_CheckChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (0); /* no character available */ +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h new file mode 100644 index 0000000000..fcdf554bb8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file nvic_wrapper.h +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +#ifndef NVIC_WRAPPER_H +#define NVIC_WRAPPER_H + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +/* NVIC functions */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +uint32_t NVIC_GetPriorityGrouping(void); +void NVIC_EnableIRQ(IRQn_Type IRQn); +void NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); +void NVIC_SetPendingIRQ(IRQn_Type IRQn); +void NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetActive(IRQn_Type IRQn); +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); +uint32_t NVIC_GetPriority(IRQn_Type IRQn); +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +void NVIC_SystemReset(void); +/* SysTick function */ +uint32_t SysTick_Config(uint32_t ticks); +/* Debug In/Output function */ +uint32_t ITM_SendChar (uint32_t ch); +int32_t ITM_ReceiveChar (void); +int32_t ITM_CheckChar (void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NVIC_WRAPPER_H */ From 85bc418da2699ed26e761591fd6f8e55b08525cd Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:00:08 +0900 Subject: [PATCH 026/143] Change terminal settings. Change terminal settings for new GR-PEACH board(board update). --- .../TARGET_RZ_A1H/PeripheralNames.h | 30 +--------------- .../TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h | 34 ++++++------------- .../TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c | 18 ++++++---- .../TARGET_RZ_A1H/gpio_object.h | 5 +-- .../TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c | 3 ++ .../TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c | 4 +++ .../TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c | 4 +++ 7 files changed, 35 insertions(+), 63 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h index dea3408eff..4040be4fd0 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h @@ -68,6 +68,7 @@ typedef enum { PWM10_PIN, PWM11_PIN, PWM12_PIN, + PWM13_PIN, } PWMName; typedef enum { @@ -99,35 +100,6 @@ typedef enum { #define STDIO_UART_RX USBRX #define STDIO_UART UART2 -// Default peripherals -#define MBED_SPI0 p5, p6, p7, p8 -#define MBED_SPI1 p11, p12, p13, p14 - -#define MBED_UART0 p9, p10 -#define MBED_UART1 p13, p14 -#define MBED_UART2 p28, p27 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 p28, p27 -#define MBED_I2C1 p9, p10 - -#define MBED_CAN0 p30, p29 - -#define MBED_ANALOGOUT0 p18 - -#define MBED_ANALOGIN0 p15 -#define MBED_ANALOGIN1 p16 -#define MBED_ANALOGIN2 p17 -#define MBED_ANALOGIN3 p18 -#define MBED_ANALOGIN4 p19 -#define MBED_ANALOGIN5 p20 - -#define MBED_PWMOUT0 p26 -#define MBED_PWMOUT1 p25 -#define MBED_PWMOUT2 p24 -#define MBED_PWMOUT3 p23 -#define MBED_PWMOUT4 p22 -#define MBED_PWMOUT5 p21 #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h index 9da5226b99..c002401af4 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h @@ -44,22 +44,11 @@ typedef enum { P10_0,P10_1,P10_2,P10_3,P10_4,P10_5,P10_6,P10_7,P10_8,P10_9,P10_10,P10_11,P10_12,P10_13,P10_14,P10_15, P11_0,P11_1,P11_2,P11_3,P11_4,P11_5,P11_6,P11_7,P11_8,P11_9,P11_10,P11_11,P11_12,P11_13,P11_14,P11_15, - // mbed DIP Pin Names - p10 = P0_1, - p21 = P2_5, - p22 = P2_4, - p23 = P2_3, - p24 = P2_2, - p25 = P2_1, - p26 = P2_0, - p29 = P0_5, - p30 = P0_4, - - // Other mbed Pin Names - LED1 = P4_4, - LED2 = P3_2, - LED3 = P4_6, - LED4 = P4_7, + // mbed Pin Names + LED1 = P6_13, + LED2 = P6_14, + LED3 = P6_15, + LED4 = P6_12, LED_RED = LED1, LED_GREEN= LED2, @@ -72,12 +61,12 @@ typedef enum { // Arduiono Pin Names D0 = P2_15, D1 = P2_14, - D2 = P11_15, - D3 = P11_14, - D4 = P11_13, - D5 = P11_12, - D6 = P8_11, - D7 = P8_13, + D2 = P4_7, + D3 = P4_6, + D4 = P4_5, + D5 = P4_4, + D6 = P8_13, + D7 = P8_11, D8 = P8_15, D9 = P8_14, D10 = P10_13, @@ -98,7 +87,6 @@ typedef enum { I2C_SDA = D14, USER_BUTTON0 = P6_0, - USER_BUTTON1 = P6_1, // Not connected NC = (int)0xFFFFFFFF diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c index 4061325fd0..19f7876829 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c @@ -33,21 +33,25 @@ void gpio_init(gpio_t *obj, PinName pin) { group = PINGROUP(pin); if (group > 11) return; - obj->reg_set = (volatile uint32_t *)PORT(group); + obj->reg_set = (volatile uint32_t *) PSR(group); obj->reg_in = (volatile uint32_t *) PPR(group); - obj->reg_dir = (volatile uint32_t *) PM(group); + obj->reg_dir = (volatile uint32_t *)PMSR(group); obj->reg_buf = (volatile uint32_t *)PIBC(group); } void gpio_mode(gpio_t *obj, PinMode mode) { -// pullup, pulldown, open...etc +/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */ } void gpio_dir(gpio_t *obj, PinDirection direction) { switch (direction) { - case PIN_INPUT : *obj->reg_dir |= obj->mask; - *obj->reg_buf |= obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir &= ~obj->mask; - *obj->reg_buf &= ~obj->mask; break; + case PIN_INPUT : + *obj->reg_dir = (obj->mask << 16) | obj->mask; + *obj->reg_buf |= obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir = (obj->mask << 16) | 0; + *obj->reg_buf &= ~obj->mask; + break; } } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h index 8bf5b45cba..211a4c870d 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -33,10 +33,7 @@ typedef struct { } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set |= obj->mask; - else - *obj->reg_set &= ~obj->mask; + *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0); } static inline int gpio_read(gpio_t *obj) { diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c index 771d0c038a..00936a66b2 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c @@ -36,6 +36,7 @@ static const PinMap PinMap_PWM[] = { {P8_12 , PWM10_PIN, 6}, {P8_9 , PWM11_PIN, 6}, {P8_10 , PWM12_PIN, 6}, + {P4_5 , PWM13_PIN, 4}, {NC, NC, 0} }; @@ -53,6 +54,7 @@ static PWMType PORT[] = { PWM1E, // PWM10_PIN PWM1B, // PWM11_PIN PWM1C, // PWM12_PIN + PWM2F, // PWM13_PIN }; static __IO uint16_t *PWM_MATCH[] = { @@ -69,6 +71,7 @@ static __IO uint16_t *PWM_MATCH[] = { &PWMPWBFR_1E, // PWM10_PIN &PWMPWBFR_1A, // PWM11_PIN &PWMPWBFR_1C, // PWM12_PIN + &PWMPWBFR_2E, // PWM13_PIN }; static uint16_t init_period_ch1 = 0; diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index 461a5b119f..56c306e70a 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -56,7 +56,9 @@ static void uart7_rx_irq(void); static const PinMap PinMap_UART_TX[] = { {P2_14 , UART0, 6}, {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, {P6_3 , UART2, 7}, + {P4_14 , UART2, 7}, {P5_3 , UART3, 5}, {P8_8 , UART3, 7}, {P5_0 , UART4, 5}, @@ -73,7 +75,9 @@ static const PinMap PinMap_UART_TX[] = { static const PinMap PinMap_UART_RX[] = { {P2_15 , UART0, 6}, {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, {P6_2 , UART2, 7}, + {P4_15 , UART2, 7}, {P5_4 , UART3, 5}, {P8_9 , UART3, 7}, {P5_1 , UART4, 5}, diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c index 16486127db..6758ebe976 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c @@ -24,6 +24,7 @@ static const PinMap PinMap_SPI_SCLK[] = { {P10_12, SPI_0, 4}, + {P4_4 , SPI_1, 2}, {P11_12, SPI_1, 2}, {P8_3 , SPI_2, 3}, {NC , NC , 0} @@ -31,6 +32,7 @@ static const PinMap PinMap_SPI_SCLK[] = { static const PinMap PinMap_SPI_SSEL[] = { {P10_13, SPI_0, 4}, + {P4_5 , SPI_1, 2}, {P11_13, SPI_1, 2}, {P8_4 , SPI_2, 3}, {NC , NC , 0} @@ -38,6 +40,7 @@ static const PinMap PinMap_SPI_SSEL[] = { static const PinMap PinMap_SPI_MOSI[] = { {P10_14, SPI_0, 4}, + {P4_6 , SPI_1, 2}, {P11_14, SPI_1, 2}, {P8_5 , SPI_2, 3}, {NC , NC , 0} @@ -45,6 +48,7 @@ static const PinMap PinMap_SPI_MOSI[] = { static const PinMap PinMap_SPI_MISO[] = { {P10_15, SPI_0, 4}, + {P4_7 , SPI_1, 2}, {P11_15, SPI_1, 2}, {P8_6 , SPI_2, 3}, {NC , NC , 0} From b5815ef60e0b1b08acc053449c5faed36c941e9f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:06:49 +0900 Subject: [PATCH 027/143] Delete some needless USBHost files to add 2Port function. --- .../TARGET_RZ_A1H/inc/usb0_host.h | 156 - .../TARGET_RZ_A1H/inc/usb0_host_api.h | 112 - .../TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h | 139 - .../src/common/usb0_host_dataio.c | 2835 ----------------- .../TARGET_RZ_A1H/src/common/usb0_host_dma.c | 355 --- .../src/common/usb0_host_intrn.c | 285 -- .../TARGET_RZ_A1H/src/common/usb0_host_lib.c | 1580 --------- .../src/host/usb0_host_controlrw.c | 434 --- .../src/host/usb0_host_drv_api.c | 889 ------ .../TARGET_RZ_A1H/src/host/usb0_host_global.c | 137 - .../TARGET_RZ_A1H/src/host/usb0_host_usbint.c | 496 --- .../TARGET_RZ_A1H/src/host/usb0_host_usbsig.c | 637 ---- .../src/userdef/usb0_host_dmacdrv.c | 698 ---- .../src/userdef/usb0_host_ohci_wrapp_pipe.c | 156 - .../src/userdef/usb0_host_userdef.c | 770 ----- 15 files changed, 9679 deletions(-) delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c delete mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h deleted file mode 100644 index 70e5c21151..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h +++ /dev/null @@ -1,156 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_HOST_H -#define USB0_HOST_H - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "devdrv_usb_host_api.h" -#include "usb_host.h" - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -extern const uint16_t g_usb0_host_bit_set[]; -extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; -extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; - -extern uint16_t g_usb0_host_PipeIgnore[]; -extern uint16_t g_usb0_host_PipeTbl[]; -extern uint16_t g_usb0_host_pipe_status[]; -extern uint32_t g_usb0_host_PipeDataSize[]; - -extern USB_HOST_DMA_t g_usb0_host_DmaInfo[]; -extern uint16_t g_usb0_host_DmaPipe[]; -extern uint16_t g_usb0_host_DmaBval[]; -extern uint16_t g_usb0_host_DmaStatus[]; - -extern uint16_t g_usb0_host_driver_state; -extern uint16_t g_usb0_host_ConfigNum; -extern uint16_t g_usb0_host_CmdStage; -extern uint16_t g_usb0_host_bchg_flag; -extern uint16_t g_usb0_host_detach_flag; -extern uint16_t g_usb0_host_attach_flag; - -extern uint16_t g_usb0_host_UsbAddress; -extern uint16_t g_usb0_host_setUsbAddress; -extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; -extern uint16_t g_usb0_host_UsbDeviceSpeed; -extern uint16_t g_usb0_host_SupportUsbDeviceSpeed; - -extern uint16_t g_usb0_host_SavReq; -extern uint16_t g_usb0_host_SavVal; -extern uint16_t g_usb0_host_SavIndx; -extern uint16_t g_usb0_host_SavLen; - -extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; - -/******************************************************************************* -Functions Prototypes -*******************************************************************************/ -/* ==== common ==== */ -void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain); -void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain); -uint16_t usb0_host_is_hispeed(void); -uint16_t usb0_host_is_hispeed_enable(void); -uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -uint16_t usb0_host_write_buffer(uint16_t pipe); -uint16_t usb0_host_write_buffer_c(uint16_t pipe); -uint16_t usb0_host_write_buffer_d0(uint16_t pipe); -uint16_t usb0_host_write_buffer_d1(uint16_t pipe); -void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -uint16_t usb0_host_read_buffer(uint16_t pipe); -uint16_t usb0_host_read_buffer_c(uint16_t pipe); -uint16_t usb0_host_read_buffer_d0(uint16_t pipe); -uint16_t usb0_host_read_buffer_d1(uint16_t pipe); -uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); -void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); -void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); -uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr); -uint16_t usb0_host_read_dma(uint16_t pipe); -void usb0_host_stop_transfer(uint16_t pipe); -void usb0_host_brdy_int(uint16_t status, uint16_t int_enb); -void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb); -void usb0_host_bemp_int(uint16_t status, uint16_t int_enb); -void usb0_host_setting_interrupt(uint8_t level); -void usb0_host_reset_module(uint16_t clockmode); -uint16_t usb0_host_get_buf_size(uint16_t pipe); -uint16_t usb0_host_get_mxps(uint16_t pipe); -void usb0_host_enable_brdy_int(uint16_t pipe); -void usb0_host_disable_brdy_int(uint16_t pipe); -void usb0_host_clear_brdy_sts(uint16_t pipe); -void usb0_host_enable_bemp_int(uint16_t pipe); -void usb0_host_disable_bemp_int(uint16_t pipe); -void usb0_host_clear_bemp_sts(uint16_t pipe); -void usb0_host_enable_nrdy_int(uint16_t pipe); -void usb0_host_disable_nrdy_int(uint16_t pipe); -void usb0_host_clear_nrdy_sts(uint16_t pipe); -void usb0_host_set_pid_buf(uint16_t pipe); -void usb0_host_set_pid_nak(uint16_t pipe); -void usb0_host_set_pid_stall(uint16_t pipe); -void usb0_host_clear_pid_stall(uint16_t pipe); -uint16_t usb0_host_get_pid(uint16_t pipe); -void usb0_host_set_sqclr(uint16_t pipe); -void usb0_host_set_sqset(uint16_t pipe); -void usb0_host_set_csclr(uint16_t pipe); -void usb0_host_aclrm(uint16_t pipe); -void usb0_host_set_aclrm(uint16_t pipe); -void usb0_host_clr_aclrm(uint16_t pipe); -uint16_t usb0_host_get_sqmon(uint16_t pipe); -uint16_t usb0_host_get_inbuf(uint16_t pipe); - -/* ==== host ==== */ -void usb0_host_init_pipe_status(void); -int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); -void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); -void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table); -uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table); -void usb0_host_StatusStage(void); -void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd); -void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd); -void usb0_host_InitModule(void); -uint16_t usb0_host_CheckAttach(void); -void usb0_host_UsbDetach(void); -void usb0_host_UsbDetach2(void); -void usb0_host_UsbAttach(void); -uint16_t usb0_host_UsbBusReset(void); -int32_t usb0_host_UsbResume(void); -int32_t usb0_host_UsbSuspend(void); -void usb0_host_Enable_DetachINT(void); -void usb0_host_Disable_DetachINT(void); -void usb0_host_UsbStateManager(void); - - -#endif /* USB0_HOST_H */ - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h deleted file mode 100644 index dbdd64d6d9..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_api.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_HOST_API_H -#define USB0_HOST_API_H - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Variable Externs -*******************************************************************************/ - - -/******************************************************************************* -Functions Prototypes -*******************************************************************************/ -void usb0_host_interrupt(uint32_t int_sense); -void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense); -void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense); - -uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); -int32_t usb0_api_host_enumeration(uint16_t devadr); -int32_t usb0_api_host_detach(void); -int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); -int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); -int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); -int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); -int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table); -int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); -uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table); -int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count); - -int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); -int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); -int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum); -int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); -int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir); -uint16_t usb0_api_host_GetUsbDeviceState(void); - -void usb0_api_host_elt_4_4(void); -void usb0_api_host_elt_4_5(void); -void usb0_api_host_elt_4_6(void); -void usb0_api_host_elt_4_7(void); -void usb0_api_host_elt_4_8(void); -void usb0_api_host_elt_4_9(void); -void usb0_api_host_elt_get_desc(void); - -void usb0_host_EL_ModeInit(void); -void usb0_host_EL_SetUACT(void); -void usb0_host_EL_ClearUACT(void); -void usb0_host_EL_SetTESTMODE(uint16_t mode); -void usb0_host_EL_ClearNRDYSTS(uint16_t pipe); -uint16_t usb0_host_EL_GetINTSTS1(void); -void usb0_host_EL_UsbBusReset(void); -void usb0_host_EL_UsbAttach(void); -void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); -void usb0_host_EL_StatusStage(void); -void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table); -int32_t usb0_host_EL_UsbSuspend(void); -int32_t usb0_host_EL_UsbResume(void); - -#if 0 /* prototype in devdrv_usb_host_api.h */ -uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void); -uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void); -void Userdef_USB_usb0_host_attach(void); -void Userdef_USB_usb0_host_detach(void); -void Userdef_USB_usb0_host_delay_1ms(void); -void Userdef_USB_usb0_host_delay_xms(uint32_t msec); -void Userdef_USB_usb0_host_delay_10us(uint32_t usec); -void Userdef_USB_usb0_host_delay_500ns(void); -void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc); -uint32_t Userdef_USB_usb0_host_stop_dma0(void); -uint32_t Userdef_USB_usb0_host_stop_dma1(void); -#endif - -#endif /* USB0_HOST_API_H */ - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h deleted file mode 100644 index 3e5e40c3bb..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h +++ /dev/null @@ -1,139 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_dmacdrv.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_HOST_DMACDRV_H -#define USB0_HOST_DMACDRV_H - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ -typedef struct dmac_transinfo -{ - uint32_t src_addr; /* Transfer source address */ - uint32_t dst_addr; /* Transfer destination address */ - uint32_t count; /* Transfer byte count */ - uint32_t src_size; /* Transfer source data size */ - uint32_t dst_size; /* Transfer destination data size */ - uint32_t saddr_dir; /* Transfer source address direction */ - uint32_t daddr_dir; /* Transfer destination address direction */ -} dmac_transinfo_t; - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -/* ==== Transfer specification of the sample program ==== */ -#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ -#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ - -/* ==== DMA modes ==== */ -#define DMAC_MODE_REGISTER (0) /* Register mode */ -#define DMAC_MODE_LINK (1) /* Link mode */ - -/* ==== Transfer requests ==== */ -#define DMAC_REQ_MODE_EXT (0) /* External request */ -#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ -#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ - -/* ==== DMAC transfer sizes ==== */ -#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ -#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ -#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ -#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ -#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ -#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ -#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ -#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ - -/* ==== Address increment for transferring ==== */ -#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ -#define DMAC_TRANS_ADR_INC (0) /* Increment */ - -/* ==== Method for detecting DMA request ==== */ -#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ -#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ -#define DMAC_REQ_DET_LOW (2) /* Low level detection */ -#define DMAC_REQ_DET_HIGH (3) /* High level detection */ - -/* ==== Request Direction ==== */ -#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ -#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ - -/* ==== Descriptors ==== */ -#define DMAC_DESC_HEADER (0) /* Header */ -#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ -#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ -#define DMAC_DESC_COUNT (3) /* Transaction Byte */ -#define DMAC_DESC_CHCFG (4) /* Channel Confg */ -#define DMAC_DESC_CHITVL (5) /* Channel Interval */ -#define DMAC_DESC_CHEXT (6) /* Channel Extension */ -#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ - -/* ==== On-chip peripheral module requests ===== */ -typedef enum dmac_request_factor -{ - DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ - DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ - DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ - DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ - DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ - DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ - DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ - DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ -} dmac_request_factor_t; - - -/******************************************************************************* -Variable Externs -*******************************************************************************/ - - -/******************************************************************************* -Functions Prototypes -*******************************************************************************/ -void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction); -int32_t usb0_host_DMAC1_Open(uint32_t req); -void usb0_host_DMAC1_Close(uint32_t * remain); -void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); - -void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction); -int32_t usb0_host_DMAC2_Open(uint32_t req); -void usb0_host_DMAC2_Close(uint32_t * remain); -void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); - -#endif /* USB0_HOST_DMACDRV_H */ - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c deleted file mode 100644 index bb7b68f2bf..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c +++ /dev/null @@ -1,2835 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_dataio.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)]; - -static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); -static uint16_t usb0_host_read_dma_d0(uint16_t pipe); -static uint16_t usb0_host_read_dma_d1(uint16_t pipe); -static uint16_t usb0_host_write_dma_d0(uint16_t pipe); -static uint16_t usb0_host_write_dma_d1(uint16_t pipe); - -static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count); -static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count); -static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count); -static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count); -static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count); -static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count); - -static void usb0_host_clear_transaction_counter(uint16_t pipe); -static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count); - -static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr); - -static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count); -static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count); - - -/******************************************************************************* -* Function Name: usb0_host_start_send_transfer -* Description : Starts the USB data communication using pipe specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data data Address -* Return Value : USB_HOST_WRITEEND ; Write end -* : USB_HOST_WRITESHRT ; short data -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_WRITEDMA ; Write DMA -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t status; - uint16_t usefifo; - uint16_t mbw; - - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - usb0_host_clear_bemp_sts(pipe); - usb0_host_clear_brdy_sts(pipe); - usb0_host_clear_nrdy_sts(pipe); - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - - usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - switch (usefifo) - { - case USB_HOST_D0FIFO_USE: - case USB_HOST_D0FIFO_DMA: - usefifo = USB_HOST_D0USE; - break; - - case USB_HOST_D1FIFO_USE: - case USB_HOST_D1FIFO_DMA: - usefifo = USB_HOST_D1USE; - break; - - default: - usefifo = USB_HOST_CUSE; - break; - }; - - usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw); - - usb0_host_clear_transaction_counter(pipe); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - status = usb0_host_write_buffer(pipe); - - if (status != USB_HOST_FIFOERROR) - { - usb0_host_set_pid_buf(pipe); - } - - return status; -} - -/******************************************************************************* -* Function Name: usb0_host_write_buffer -* Description : Writes data in the buffer allocated in the pipe specified by -* : the argument. The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND ; Write end -* : USB_HOST_WRITESHRT ; short data -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_WRITEDMA ; Write DMA -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_write_buffer (uint16_t pipe) -{ - uint16_t status; - uint16_t usefifo; - - g_usb0_host_PipeIgnore[pipe] = 0; - usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - switch (usefifo) - { - case USB_HOST_D0FIFO_USE: - status = usb0_host_write_buffer_d0(pipe); - break; - - case USB_HOST_D1FIFO_USE: - status = usb0_host_write_buffer_d1(pipe); - break; - - case USB_HOST_D0FIFO_DMA: - status = usb0_host_write_dma_d0(pipe); - break; - - case USB_HOST_D1FIFO_DMA: - status = usb0_host_write_dma_d1(pipe); - break; - - default: - status = usb0_host_write_buffer_c(pipe); - break; - }; - - switch (status) - { - case USB_HOST_WRITING: /* Continue of data write */ - usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */ - break; - - case USB_HOST_WRITEEND: /* End of data write */ - case USB_HOST_WRITESHRT: /* End of data write */ - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - - usb0_host_clear_nrdy_sts(pipe); - usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - - /* for last transfer */ - usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */ - break; - - case USB_HOST_WRITEDMA: /* DMA write */ - usb0_host_clear_nrdy_sts(pipe); - usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - break; - - case USB_HOST_FIFOERROR: /* FIFO access status */ - default: - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_write_buffer_c -* Description : Writes data in the buffer allocated in the pipe specified in -* : the argument. Writes data by CPU transfer using CFIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND ; Write end -* : USB_HOST_WRITESHRT ; short data -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_WRITEDMA ; Write DMA -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_write_buffer_c (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - - if (pipe == USB_HOST_PIPE0) - { - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw); - } - else - { - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); - } - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] <= (uint32_t)size) - { - status = USB_HOST_WRITEEND; /* write continues */ - count = g_usb0_host_data_count[pipe]; - - if (count == 0) - { - status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = USB_HOST_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_host_write_c_fifo(pipe, (uint16_t)count); - - if (g_usb0_host_data_count[pipe] < (uint32_t)size) - { - g_usb0_host_data_count[pipe] = 0; - - if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, - USB_CFIFOCTR_BVAL_SHIFT, - USB_CFIFOCTR_BVAL) == 0) - { - USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ - } - } - else - { - g_usb0_host_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_write_buffer_d0 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by CPU transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND ; Write end -* : USB_HOST_WRITESHRT ; short data -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_WRITEDMA ; Write DMA -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_write_buffer_d0 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] <= (uint32_t)size) - { - status = USB_HOST_WRITEEND; /* write continues */ - count = g_usb0_host_data_count[pipe]; - - if (count == 0) - { - status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = USB_HOST_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_host_write_d0_fifo(pipe, (uint16_t)count); - - if (g_usb0_host_data_count[pipe] < (uint32_t)size) - { - g_usb0_host_data_count[pipe] = 0; - - if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL) == 0) - { - USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ - } - } - else - { - g_usb0_host_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_write_buffer_d1 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by CPU transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND ; Write end -* : USB_HOST_WRITESHRT ; short data -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_WRITEDMA ; Write DMA -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_write_buffer_d1 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] <= (uint32_t)size) - { - status = USB_HOST_WRITEEND; /* write continues */ - count = g_usb0_host_data_count[pipe]; - - if (count == 0) - { - status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = USB_HOST_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_host_write_d1_fifo(pipe, (uint16_t)count); - - if (g_usb0_host_data_count[pipe] < (uint32_t)size) - { - g_usb0_host_data_count[pipe] = 0; - - if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL) == 0) - { - USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ - } - } - else - { - g_usb0_host_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_write_dma_d0 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by DMA transfer using D0FIFO. -* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND : Write end -* : USB_HOST_WRITESHRT : short data -* : USB_HOST_WRITING : Continue of data write -* : USB_HOST_WRITEDMA : Write DMA -* : USB_HOST_FIFOERROR : FIFO status -*******************************************************************************/ -static uint16_t usb0_host_write_dma_d0 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - count = g_usb0_host_data_count[pipe]; - - if (count != 0) - { - g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; - - if ((count % size) != 0) - { - g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1; - } - else - { - g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; - } - - dfacc = usb0_host_set_dfacc_d0(mbw, count); - - if (mbw == USB_HOST_BITMBW_32) - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_HOST_BITMBW_16) - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; - - Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); - - usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - - g_usb0_host_data_count[pipe] = 0; - g_usb0_host_data_pointer[pipe] += count; - - status = USB_HOST_WRITEDMA; /* DMA write */ - } - else - { - if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL) == 0) - { - RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); /* Short Packet */ - } - status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_write_dma_d1 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by DMA transfer using D1FIFO. -* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_WRITEEND : Write end -* : USB_HOST_WRITESHRT : short data -* : USB_HOST_WRITING : Continue of data write -* : USB_HOST_WRITEDMA : Write DMA -* : USB_HOST_FIFOERROR : FIFO status -*******************************************************************************/ -static uint16_t usb0_host_write_dma_d1 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - count = g_usb0_host_data_count[pipe]; - - if (count != 0) - { - g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; - - if ((count % size) != 0) - { - g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1; - } - else - { - g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; - } - - dfacc = usb0_host_set_dfacc_d1(mbw, count); - - if (mbw == USB_HOST_BITMBW_32) - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_HOST_BITMBW_16) - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; - - Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); - - usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - - g_usb0_host_data_count[pipe] = 0; - g_usb0_host_data_pointer[pipe] += count; - - status = USB_HOST_WRITEDMA; /* DMA write */ - } - else - { - if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL) == 0) - { - RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); /* Short Packet */ - } - status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_transfer -* Description : Starts USB data reception using the pipe specified in the argument. -* : The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t usefifo; - - usb0_host_clear_bemp_sts(pipe); - usb0_host_clear_brdy_sts(pipe); - usb0_host_clear_nrdy_sts(pipe); - - usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - switch (usefifo) - { - case USB_HOST_D0FIFO_USE: - usb0_host_start_receive_trns_d0(pipe, size, data); - break; - - case USB_HOST_D1FIFO_USE: - usb0_host_start_receive_trns_d1(pipe, size, data); - break; - - case USB_HOST_D0FIFO_DMA: - usb0_host_start_receive_dma_d0(pipe, size, data); - break; - - case USB_HOST_D1FIFO_DMA: - usb0_host_start_receive_dma_d1(pipe, size, data); - break; - - default: - usb0_host_start_receive_trns_c(pipe, size, data); - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_trns_c -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using CFIFO. -* : When storing data in the buffer allocated in the pipe specified in the -* : argument, BRDY interrupt is generated to read data -* : in the interrupt. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_host_set_pid_nak(pipe); - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_PipeIgnore[pipe] = 0; - - g_usb0_host_PipeDataSize[pipe] = size; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw); - USB200.CFIFOCTR = USB_HOST_BITBCLR; - - usb0_host_set_transaction_counter(pipe, size); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - - usb0_host_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_trns_d0 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, BRDY interrupt is generated to read data in the -* : interrupt. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_host_set_pid_nak(pipe); - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_PipeIgnore[pipe] = 0; - - g_usb0_host_PipeDataSize[pipe] = size; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); - - usb0_host_set_transaction_counter(pipe, size); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - - usb0_host_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_trns_d1 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using D1FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, BRDY interrupt is generated to read data. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_host_set_pid_nak(pipe); - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_PipeIgnore[pipe] = 0; - - g_usb0_host_PipeDataSize[pipe] = size; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); - - usb0_host_set_transaction_counter(pipe, size); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - - usb0_host_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_dma_d0 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by DMA transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, delivered read request to DMAC to read data from -* : the buffer by DMAC. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_host_set_pid_nak(pipe); - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_PipeIgnore[pipe] = 0; - - g_usb0_host_PipeDataSize[pipe] = 0; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); - - usb0_host_set_transaction_counter(pipe, size); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - usb0_host_read_dma(pipe); - - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - } - else - { - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - } - - usb0_host_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_start_receive_dma_d1 -* Description : Read data from the buffer allocated in the pipe specified in the argument. -* : Reads data by DMA transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, delivered read request to DMAC to read data from -* : the buffer by DMAC. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_host_set_pid_nak(pipe); - g_usb0_host_data_count[pipe] = size; - g_usb0_host_data_pointer[pipe] = (uint8_t *)data; - g_usb0_host_PipeIgnore[pipe] = 0; - - g_usb0_host_PipeDataSize[pipe] = 0; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; - - mbw = usb0_host_get_mbw(size, (uint32_t)data); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); - - usb0_host_set_transaction_counter(pipe, size); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - usb0_host_read_dma(pipe); - - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - } - else - { - usb0_host_enable_nrdy_int(pipe); - usb0_host_enable_brdy_int(pipe); - } - - usb0_host_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_read_buffer -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Uses FIF0 set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_read_buffer (uint16_t pipe) -{ - uint16_t status; - - g_usb0_host_PipeIgnore[pipe] = 0; - - if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) - { - status = usb0_host_read_buffer_d0(pipe); - } - else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) - { - status = usb0_host_read_buffer_d1(pipe); - } - else - { - status = usb0_host_read_buffer_c(pipe); - } - - switch (status) - { - case USB_HOST_READING: /* Continue of data read */ - break; - - case USB_HOST_READEND: /* End of data read */ - case USB_HOST_READSHRT: /* End of data read */ - usb0_host_disable_brdy_int(pipe); - g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - break; - - case USB_HOST_READOVER: /* buffer over */ - if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) - { - USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) - { - USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - else - { - USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; -#else - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; -#endif - g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; - break; - - case USB_HOST_FIFOERROR: /* FIFO access status */ - default: - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_buffer_c -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using CFIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_read_buffer_c (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_HOST_READOVER; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_host_data_count[pipe]; - } - else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_HOST_READEND; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_HOST_READING; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_host_read_c_fifo(pipe, (uint16_t)count); - } - - g_usb0_host_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_buffer_d0 -* Description : Reads data from the buffer allocated in the pipe specified in -* : the argument. -* : Reads data by CPU transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_read_buffer_d0 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t pipebuf_size; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_HOST_READOVER; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_host_data_count[pipe]; - } - else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_HOST_READEND; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_HOST_READING; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - else - { - pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - - if (count != pipebuf_size) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_host_read_d0_fifo(pipe, (uint16_t)count); - } - - g_usb0_host_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_buffer_d1 -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by CPU transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_read_buffer_d1 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t pipebuf_size; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_HOST_READOVER; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_host_data_count[pipe]; - } - else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_HOST_READEND; - usb0_host_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) !=0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_HOST_READING; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - else - { - pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - if (count != pipebuf_size) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - usb0_host_set_pid_nak(pipe); /* Set NAK */ - } - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_host_read_d1_fifo(pipe, (uint16_t)count); - } - - g_usb0_host_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_dma -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by DMA transfer using D0FIFO or D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READZERO ; zero data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_host_read_dma (uint16_t pipe) -{ - uint16_t status; - - g_usb0_host_PipeIgnore[pipe] = 0; - - if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) - { - status = usb0_host_read_dma_d0(pipe); - } - else - { - status = usb0_host_read_dma_d1(pipe); - } - - switch (status) - { - case USB_HOST_READING: /* Continue of data read */ - break; - - case USB_HOST_READZERO: /* End of data read */ - usb0_host_disable_brdy_int(pipe); - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - break; - - case USB_HOST_READEND: /* End of data read */ - case USB_HOST_READSHRT: /* End of data read */ - usb0_host_disable_brdy_int(pipe); - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; - } - break; - - case USB_HOST_READOVER: /* buffer over */ - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; - } -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; -#else - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; -#endif - break; - - case USB_HOST_FIFOERROR: /* FIFO access status */ - default: - usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_dma_d0 -* Description : Writes data in the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by DMA transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READZERO ; zero data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -static uint16_t usb0_host_read_dma_d0 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - uint16_t pipebuf_size; - - g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - count = g_usb0_host_data_count[pipe]; - status = USB_HOST_READING; - } - else - { - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_HOST_READOVER; - count = g_usb0_host_data_count[pipe]; - } - else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_HOST_READEND; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_HOST_READING; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - else - { - pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - - if (count != pipebuf_size) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - } - } - - if (count == 0) /* 0 length packet */ - { - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */ - status = USB_HOST_READZERO; /* Null Packet receive */ - } - else - { - usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); - /* transaction counter No set */ - /* FRDY = 1, DTLN = 0 -> BRDY */ - } - } - else - { - dfacc = usb0_host_set_dfacc_d0(mbw, count); - - if (mbw == USB_HOST_BITMBW_32) - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_HOST_BITMBW_16) - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */ - g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */ - - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; - g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; - - if (status == USB_HOST_READING) - { - g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY; - } - else - { - g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND; - } - - Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); - - usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - g_usb0_host_data_count[pipe] -= count; - g_usb0_host_data_pointer[pipe] += count; - g_usb0_host_PipeDataSize[pipe] += count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_read_dma_d1 -* Description : Reads data from the buffer allocated in the pipe specified in -* : the argument. -* : Reads data by DMA transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_HOST_READEND ; Read end -* : USB_HOST_READSHRT ; short data -* : USB_HOST_READZERO ; zero data -* : USB_HOST_READING ; Continue of data read -* : USB_HOST_READOVER ; buffer over -* : USB_HOST_FIFOERROR ; FIFO status -*******************************************************************************/ -static uint16_t usb0_host_read_dma_d1 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - uint16_t pipebuf_size; - - g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - count = g_usb0_host_data_count[pipe]; - status = USB_HOST_READING; - } - else - { - buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); - - if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ - { - return USB_HOST_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_HOST_READOVER; - count = g_usb0_host_data_count[pipe]; - } - else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_HOST_READEND; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_HOST_READING; - count = dtln; - - if (count == 0) - { - status = USB_HOST_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - else - { - pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ - - if (count != pipebuf_size) - { - status = USB_HOST_READSHRT; /* Short Packet receive */ - } - } - } - } - - if (count == 0) /* 0 length packet */ - { - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ - status = USB_HOST_READZERO; /* Null Packet receive */ - } - else - { - usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); - /* transaction counter No set */ - /* FRDY = 1, DTLN = 0 -> BRDY */ - } - } - else - { - dfacc = usb0_host_set_dfacc_d1(mbw, count); - - if (mbw == USB_HOST_BITMBW_32) - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_HOST_BITMBW_16) - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */ - g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */ - - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; - g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; - - if (status == USB_HOST_READING) - { - g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY; - } - else - { - g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND; - } - - Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); - - usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - g_usb0_host_data_count[pipe] -= count; - g_usb0_host_data_pointer[pipe] += count; - g_usb0_host_PipeDataSize[pipe] += count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_change_fifo_port -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument. After allocating FIF0, waits in the software -* : till the corresponding pipe becomes ready. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* Return Value : USB_HOST_FIFOERROR ; Error -* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value -*******************************************************************************/ -uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) -{ - uint16_t buffer; - uint32_t loop; - volatile uint32_t loop2; - - usb0_host_set_curpipe(pipe, fifosel, isel, mbw); - - for (loop = 0; loop < 4; loop++) - { - switch (fifosel) - { - case USB_HOST_CUSE: - buffer = USB200.CFIFOCTR; - break; - - case USB_HOST_D0USE: - case USB_HOST_D0DMA: - buffer = USB200.D0FIFOCTR; - break; - - case USB_HOST_D1USE: - case USB_HOST_D1DMA: - buffer = USB200.D1FIFOCTR; - break; - - default: - buffer = 0; - break; - } - - if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY) - { - return buffer; - } - - loop2 = 25; - - while (loop2-- > 0) - { - /* wait */ - } - } - - return USB_HOST_FIFOERROR; -} - -/******************************************************************************* -* Function Name: usb0_host_set_curpipe -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* Return Value : none -*******************************************************************************/ -void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) -{ - uint16_t buffer; - uint32_t loop; - volatile uint32_t loop2; - - g_usb0_host_mbw[pipe] = mbw; - - switch (fifosel) - { - case USB_HOST_CUSE: - buffer = USB200.CFIFOSEL; - buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); - buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) - == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - - buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(isel | pipe | mbw); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) - == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_HOST_D0DMA: - case USB_HOST_D0USE: - buffer = USB200.D0FIFOSEL; - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_HOST_D1DMA: - case USB_HOST_D1USE: - buffer = USB200.D1FIFOSEL; - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - default: - break; - } - - /* Cautions !!! - * Depending on the external bus speed of CPU, you may need to wait for 450ns here. - * For details, please look at the data sheet. */ - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } -} - -/******************************************************************************* -* Function Name: usb0_host_set_curpipe2 -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument.(DFACC) -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* : uint16_t dfacc ; DFACC Access mode -* Return Value : none -*******************************************************************************/ -void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) -{ - uint16_t buffer; - uint32_t loop; -#ifdef __USB_HOST_DF_ACC_ENABLE__ - uint32_t dummy; -#endif - volatile uint32_t loop2; - - g_usb0_host_mbw[pipe] = mbw; - - switch (fifosel) - { - case USB_HOST_CUSE: - buffer = USB200.CFIFOSEL; - buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); - buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) - == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - - buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(isel | pipe | mbw); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) - == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_HOST_D0DMA: - case USB_HOST_D0USE: - buffer = USB200.D0FIFOSEL; -#ifdef __USB_HOST_DF_ACC_ENABLE__ - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - - if (dfacc != 0) - { - buffer |= (uint16_t)(USB_HOST_BITMBW_32); - } -#else - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); -#endif - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - -#ifdef __USB_HOST_DF_ACC_ENABLE__ - if (dfacc != 0) - { - dummy = USB200.D0FIFO.UINT32; - } -#endif - - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_HOST_D1DMA: - case USB_HOST_D1USE: - buffer = USB200.D1FIFOSEL; -#ifdef __USB_HOST_DF_ACC_ENABLE__ - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - - if (dfacc != 0) - { - buffer |= (uint16_t)(USB_HOST_BITMBW_32); - } -#else - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); -#endif - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - -#ifdef __USB_HOST_DF_ACC_ENABLE__ - if (dfacc != 0) - { - dummy = USB200.D1FIFO.UINT32; - loop = dummy; // avoid warning. - } -#endif - - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - default: - break; - } - - /* Cautions !!! - * Depending on the external bus speed of CPU, you may need to wait for 450ns here. - * For details, please look at the data sheet. */ - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } -} - -/******************************************************************************* -* Function Name: usb0_host_write_c_fifo -* Description : Writes data in CFIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb1_host_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_read_c_fifo -* Description : Reads data from CFIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_host_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H]; - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32; - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_write_d0_fifo -* Description : Writes data in D0FIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_host_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_read_d0_fifo -* Description : Reads data from D0FIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating DOFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_host_mbw[]. -* Arguments : uint16_t Pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H]; - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32; - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_write_d1_fifo -* Description : Writes data in D1FIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating D1FIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb1_host_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_read_d1_fifo -* Description : Reads data from D1FIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating D1FIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb1_host_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH]; - g_usb0_host_data_pointer[pipe] += 1; - } - } - else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H]; - g_usb0_host_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32; - g_usb0_host_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_com_get_dmasize -* Description : Calculates access width of DMA transfer by the argument to - return as the Return Value. -* Arguments : uint32_t trncount : transfer byte -* : uint32_t dtptr : transfer data pointer -* Return Value : DMA transfer size : 0 8bit -* : : 1 16bit -* : : 2 32bit -*******************************************************************************/ -static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr) -{ - uint32_t size; - - if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) - { - /* When transfer byte count is odd */ - /* or transfer data area is 8-bit alignment */ - size = 0; /* 8bit */ - } - else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) - { - /* When the transfer byte count is multiples of 2 */ - /* or the transfer data area is 16-bit alignment */ - size = 1; /* 16bit */ - } - else - { - /* When the transfer byte count is multiples of 4 */ - /* or the transfer data area is 32-bit alignment */ - size = 2; /* 32bit */ - } - - return size; -} - -/******************************************************************************* -* Function Name: usb0_host_get_mbw -* Description : Calculates access width of DMA to return the value set in MBW. -* Arguments : uint32_t trncount : transfer byte -* : uint32_t dtptr : transfer data pointer -* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit -* : : USB_HOST_BITMBW_16 16bit -* : : USB_HOST_BITMBW_32 32bit -*******************************************************************************/ -uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr) -{ - uint32_t size; - uint16_t mbw; - - size = usb0_host_com_get_dmasize(trncount, dtptr); - - if (size == 0) - { - /* 8bit */ - mbw = USB_HOST_BITMBW_8; - } - else if (size == 1) - { - /* 16bit */ - mbw = USB_HOST_BITMBW_16; - } - else - { - /* 32bit */ - mbw = USB_HOST_BITMBW_32; - } - - return mbw; -} - -/******************************************************************************* -* Function Name: usb0_host_set_transaction_counter -* Description : Sets transaction counter by the argument(PIPEnTRN). -* : Clears transaction before setting to enable transaction counter setting. -* Arguments : uint16_t pipe ; Pipe number -* : uint32_t bsize : Data transfer size -* Return Value : none -*******************************************************************************/ -static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize) -{ - uint16_t mxps; - uint16_t cnt; - - if (bsize == 0) - { - return; - } - - mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ - - if ((bsize % mxps) == 0) - { - cnt = (uint16_t)(bsize / mxps); - } - else - { - cnt = (uint16_t)((bsize / mxps) + 1); - } - - switch (pipe) - { - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE1TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE2TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE3TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE4TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE5TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE9TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_clear_transaction_counter -* Description : Clears the transaction counter by the argument. -* : After executing this function, the transaction counter is invalid. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_host_clear_transaction_counter (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_stop_transfer -* Description : Stops the USB transfer in the pipe specified by the argument. -* : After stopping the USB transfer, clears the buffer allocated in -* : the pipe. -* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0; -* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt -* : in the corresponding pipe becomes invalid. Sequence bit is also -* : cleared. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_stop_transfer (uint16_t pipe) -{ - uint16_t usefifo; - uint32_t remain; - - usb0_host_set_pid_nak(pipe); - - usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - switch (usefifo) - { - case USB_HOST_D0FIFO_USE: - usb0_host_clear_transaction_counter(pipe); - USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - break; - - case USB_HOST_D1FIFO_USE: - usb0_host_clear_transaction_counter(pipe); - USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - break; - - case USB_HOST_D0FIFO_DMA: - remain = Userdef_USB_usb0_host_stop_dma0(); - usb0_host_dma_stop_d0(pipe, remain); - usb0_host_clear_transaction_counter(pipe); - USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - break; - - case USB_HOST_D1FIFO_DMA: - remain = Userdef_USB_usb0_host_stop_dma1(); - usb0_host_dma_stop_d1(pipe, remain); - usb0_host_clear_transaction_counter(pipe); - USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - break; - - default: - usb0_host_clear_transaction_counter(pipe); - USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - break; - } - - /* Interrupt of pipe set is disabled */ - usb0_host_disable_brdy_int(pipe); - usb0_host_disable_nrdy_int(pipe); - usb0_host_disable_bemp_int(pipe); - -#if(1) /* ohci_wrapp */ -#else - usb0_host_aclrm(pipe); -#endif - usb0_host_set_csclr(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_set_dfacc_d0 -* Description : Sets the DFACC setting value in D0FIFO using the transfer size. -* Arguments : uint16_t mbw ; MBW -* : uint16_t count ; data count -* Return Value : DFACC Access mode -*******************************************************************************/ -static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count) -{ - uint16_t dfacc = 0; - -#ifndef __USB_HOST_DF_ACC_ENABLE__ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; -#else - if (mbw == USB_HOST_BITMBW_32) - { - if ((count % 32) == 0) - { - /* 32byte transfer */ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 2, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 2; - } - else if ((count % 16) == 0) - { - /* 16byte transfer */ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 1, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 1; - } - else - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - } - else if (mbw == USB_HOST_BITMBW_16) - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - else - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } -#endif - - return dfacc; -} - -/******************************************************************************* -* Function Name: usb0_host_set_dfacc_d1 -* Description : Sets the DFACC setting value in D1FIFO using the transfer size. -* Arguments : uint16_t mbw ; MBW -* : uint16_t count ; data count -* Return Value : DFACC Access mode -*******************************************************************************/ -static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count) -{ - uint16_t dfacc = 0; - -#ifndef __USB_HOST_DF_ACC_ENABLE__ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; -#else - if (mbw == USB_HOST_BITMBW_32) - { - if ((count % 32) == 0) - { - /* 32byte transfer */ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 2, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 2; - } - else if ((count % 16) == 0) - { - /* 16byte transfer */ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 1, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 1; - } - else - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - } - else if (mbw == USB_HOST_BITMBW_16) - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - else - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } -#endif - - return dfacc; -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c deleted file mode 100644 index 57e6e5a084..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c +++ /dev/null @@ -1,355 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_dma.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -/* #include "usb0_host_dmacdrv.h" */ - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -static void usb0_host_dmaint(uint16_t fifo); -static void usb0_host_dmaint_buf2fifo(uint16_t pipe); -static void usb0_host_dmaint_fifo2buf(uint16_t pipe); - - -/******************************************************************************* -* Function Name: usb0_host_dma_stop_d0 -* Description : D0FIFO DMA stop -* Arguments : uint16_t pipe : pipe number -* : uint32_t remain : transfer byte -* Return Value : none -*******************************************************************************/ -void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain) -{ - uint16_t dtln; - uint16_t dfacc; - uint16_t buffer; - uint16_t sds_b = 1; - - dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - if (dfacc == 2) - { - sds_b = 32; - } - else if (dfacc == 1) - { - sds_b = 16; - } - else - { - if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2) - { - sds_b = 4; - } - else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1) - { - sds_b = 2; - } - else - { - sds_b = 1; - } - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) - { - buffer = USB200.D0FIFOCTR; - dtln = (buffer & USB_HOST_BITDTLN); - - if ((dtln % sds_b) != 0) - { - remain += (sds_b - (dtln % sds_b)); - } - g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); - g_usb0_host_data_count[pipe] = remain; - } - } - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, - 0, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); -} - -/******************************************************************************* -* Function Name: usb0_host_dma_stop_d1 -* Description : D1FIFO DMA stop -* Arguments : uint16_t pipe : pipe number -* : uint32_t remain : transfer byte -* Return Value : none -*******************************************************************************/ -void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain) -{ - uint16_t dtln; - uint16_t dfacc; - uint16_t buffer; - uint16_t sds_b = 1; - - dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - if (dfacc == 2) - { - sds_b = 32; - } - else if (dfacc == 1) - { - sds_b = 16; - } - else - { - if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2) - { - sds_b = 4; - } - else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1) - { - sds_b = 2; - } - else - { - sds_b = 1; - } - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) - { - buffer = USB200.D1FIFOCTR; - dtln = (buffer & USB_HOST_BITDTLN); - - if ((dtln % sds_b) != 0) - { - remain += (sds_b - (dtln % sds_b)); - } - g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); - g_usb0_host_data_count[pipe] = remain; - } - } - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, - 0, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); -} - -/******************************************************************************* -* Function Name: usb0_host_dma_interrupt_d0fifo -* Description : This function is DMA interrupt handler entry. -* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function. -* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is -* : specified by dma->fifo. -* : Register this function as DMA complete interrupt. -* Arguments : uint32_t int_sense ; Interrupts detection mode -* : ; INTC_LEVEL_SENSITIVE : Level sense -* : ; INTC_EDGE_TRIGGER : Edge trigger -* Return Value : none -*******************************************************************************/ -void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense) -{ - usb0_host_dmaint(USB_HOST_D0FIFO); - g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; -} - -/******************************************************************************* -* Function Name: usb0_host_dma_interrupt_d1fifo -* Description : This function is DMA interrupt handler entry. -* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function. -* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is -* : specified by dma->fifo. -* : Register this function as DMA complete interrupt. -* Arguments : uint32_t int_sense ; Interrupts detection mode -* : ; INTC_LEVEL_SENSITIVE : Level sense -* : ; INTC_EDGE_TRIGGER : Edge trigger -* Return Value : none -*******************************************************************************/ -void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense) -{ - usb0_host_dmaint(USB_HOST_D1FIFO); - g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; -} - -/******************************************************************************* -* Function Name: usb0_host_dmaint -* Description : This function is DMA transfer end interrupt -* Arguments : uint16_t fifo ; fifo number -* : ; USB_HOST_D0FIFO -* : ; USB_HOST_D1FIFO -* Return Value : none -*******************************************************************************/ -static void usb0_host_dmaint (uint16_t fifo) -{ - uint16_t pipe; - - pipe = g_usb0_host_DmaPipe[fifo]; - - if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO) - { - usb0_host_dmaint_buf2fifo(pipe); - } - else - { - usb0_host_dmaint_fifo2buf(pipe); - } -} - -/******************************************************************************* -* Function Name: usb0_host_dmaint_fifo2buf -* Description : Executes read completion from FIFO by DMAC. -* Arguments : uint16_t pipe : pipe number -* Return Value : none -*******************************************************************************/ -static void usb0_host_dmaint_fifo2buf (uint16_t pipe) -{ - uint32_t remain; - uint16_t useport; - - if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) - { - useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - if (useport == USB_HOST_D0FIFO_DMA) - { - remain = Userdef_USB_usb0_host_stop_dma0(); - usb0_host_dma_stop_d0(pipe, remain); - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND) - { - USB200.D0FIFOCTR = USB_HOST_BITBCLR; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - } - else - { - usb0_host_enable_brdy_int(pipe); - } - } - } - else - { - remain = Userdef_USB_usb0_host_stop_dma1(); - usb0_host_dma_stop_d1(pipe, remain); - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND) - { - USB200.D1FIFOCTR = USB_HOST_BITBCLR; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - } - else - { - usb0_host_enable_brdy_int(pipe); - } - } - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_dmaint_buf2fifo -* Description : Executes write completion in FIFO by DMAC. -* Arguments : uint16_t pipe : pipe number -* Return Value : none -*******************************************************************************/ -static void usb0_host_dmaint_buf2fifo (uint16_t pipe) -{ - uint16_t useport; - uint32_t remain; - - useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); - - if (useport == USB_HOST_D0FIFO_DMA) - { - remain = Userdef_USB_usb0_host_stop_dma0(); - usb0_host_dma_stop_d0(pipe, remain); - - if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0) - { - RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); - } - } - else - { - remain = Userdef_USB_usb0_host_stop_dma1(); - usb0_host_dma_stop_d1(pipe, remain); - - if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0) - { - RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); - } - } - - usb0_host_enable_bemp_int(pipe); -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c deleted file mode 100644 index 968a513526..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c +++ /dev/null @@ -1,285 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_intrn.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#if(1) /* ohci_wrapp */ -#include "ohci_wrapp_RZ_A1_local.h" -#endif - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_brdy_int -* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9). -* : According to the pipe that interrupt is generated in, -* : reads/writes buffer allocated in the pipe. -* : This function is executed in the BRDY interrupt handler. -* : This function clears BRDY interrupt status and BEMP interrupt -* : status. -* Arguments : uint16_t status ; BRDYSTS Register Value -* : uint16_t int_enb ; BRDYENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_brdy_int (uint16_t status, uint16_t int_enb) -{ - uint32_t int_sense = 0; - uint16_t pipe; - uint16_t pipebit; - - for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) - { - pipebit = g_usb0_host_bit_set[pipe]; - - if ((status & pipebit) && (int_enb & pipebit)) - { - USB200.BRDYSTS = (uint16_t)~pipebit; - USB200.BEMPSTS = (uint16_t)~pipebit; - - if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) - { - if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY) - { - usb0_host_dma_interrupt_d0fifo(int_sense); - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - usb0_host_read_dma(pipe); - usb0_host_disable_brdy_int(pipe); - } - else - { - USB200.D0FIFOCTR = USB_HOST_BITBCLR; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - } - } - else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA) - { - if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY) - { - usb0_host_dma_interrupt_d1fifo(int_sense); - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - usb0_host_read_dma(pipe); - usb0_host_disable_brdy_int(pipe); - } - else - { - USB200.D1FIFOCTR = USB_HOST_BITBCLR; - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; - } - } - else - { - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) - { - usb0_host_read_buffer(pipe); - } - else - { - usb0_host_write_buffer(pipe); - } - } -#if(1) /* ohci_wrapp */ - switch (g_usb0_host_pipe_status[pipe]) - { - case USB_HOST_PIPE_DONE: - ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); - break; - case USB_HOST_PIPE_NORES: - case USB_HOST_PIPE_STALL: - case USB_HOST_PIPE_ERROR: - ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); - break; - default: - /* Do Nothing */ - break; - } -#endif - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_nrdy_int -* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9). -* : Checks NRDY interrupt cause by PID. When the cause if STALL, -* : regards the pipe state as STALL and ends the processing. -* : Then the cause is not STALL, increments the error count to -* : communicate again. When the error count is 3, determines -* : the pipe state as USB_HOST_PIPE_NORES and ends the processing. -* : This function is executed in the NRDY interrupt handler. -* : This function clears NRDY interrupt status. -* Arguments : uint16_t status ; NRDYSTS Register Value -* : uint16_t int_enb ; NRDYENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb) -{ - uint16_t pid; - uint16_t pipe; - uint16_t bitcheck; - - bitcheck = (uint16_t)(status & int_enb); - - USB200.NRDYSTS = (uint16_t)~status; - - for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) - { - if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) - { - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, - USB_SYSCFG_DCFM_SHIFT, - USB_SYSCFG_DCFM) == 1) - { - if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT) - { - pid = usb0_host_get_pid(pipe); - - if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) - { - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; -#if(1) /* ohci_wrapp */ - ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); -#endif - } - else - { -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; - ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); -#else - g_usb0_host_PipeIgnore[pipe]++; - - if (g_usb0_host_PipeIgnore[pipe] == 3) - { - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; - } - else - { - usb0_host_set_pid_buf(pipe); - } -#endif - } - } - } - else - { - /* USB Function */ - } - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_bemp_int -* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9). -* Arguments : uint16_t status ; BEMPSTS Register Value -* : uint16_t int_enb ; BEMPENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_bemp_int (uint16_t status, uint16_t int_enb) -{ - uint16_t pid; - uint16_t pipe; - uint16_t bitcheck; - uint16_t inbuf; - - bitcheck = (uint16_t)(status & int_enb); - - USB200.BEMPSTS = (uint16_t)~status; - - for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) - { - if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) - { - pid = usb0_host_get_pid(pipe); - - if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) - { - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; -#if(1) /* ohci_wrapp */ - ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); -#endif - } - else - { - inbuf = usb0_host_get_inbuf(pipe); - - if (inbuf == 0) - { - usb0_host_disable_bemp_int(pipe); - usb0_host_set_pid_nak(pipe); - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; -#if(1) /* ohci_wrapp */ - ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); -#endif - } - } - } - } -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c deleted file mode 100644 index eb3359e286..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c +++ /dev/null @@ -1,1580 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_lib.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#if(1) /* ohci_wrapp */ -#include "MBRZA1H.h" /* INTC Driver Header */ -#else -#include "devdrv_intc.h" /* INTC Driver Header */ -#endif - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_enable_brdy_int -* Description : Enables BRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : BRDY. Enables BRDY interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_enable_brdy_int (uint16_t pipe) -{ - /* enable brdy interrupt */ - USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_host_disable_brdy_int -* Description : Disables BRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : BRDY. Enables BRDY interrupt in the pipe specified by the argument -* : in the disabled status. After disabling BRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_disable_brdy_int (uint16_t pipe) -{ - /* disable brdy interrupt */ - USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_clear_brdy_sts -* Description : Clear BRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_clear_brdy_sts (uint16_t pipe) -{ - /* clear brdy status */ - USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_enable_bemp_int -* Description : Enables BEMP interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : BEMP. Enables BEMP interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BEMP, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_enable_bemp_int (uint16_t pipe) -{ - /* enable bemp interrupt */ - USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_host_disable_bemp_int -* Description : Disables BEMP interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : BEMP. Enables BEMP interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BEMP, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_disable_bemp_int (uint16_t pipe) -{ - /* disable bemp interrupt */ - USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_clear_bemp_sts -* Description : Clear BEMP interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_clear_bemp_sts (uint16_t pipe) -{ - /* clear bemp status */ - USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_enable_nrdy_int -* Description : Enables NRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : NRDY. Enables NRDY interrupt in the pipe specified by the argument -* : in the disabled status. After enabling NRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_enable_nrdy_int (uint16_t pipe) -{ - /* enable nrdy interrupt */ - USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_host_disable_nrdy_int -* Description : Disables NRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : NRDY. Disables NRDY interrupt in the pipe specified by the argument -* : in the disabled status. After disabling NRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_disable_nrdy_int (uint16_t pipe) -{ - /* disable nrdy interrupt */ - USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_clear_nrdy_sts -* Description : Clear NRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_clear_nrdy_sts (uint16_t pipe) -{ - /* clear nrdy status */ - USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_host_is_hispeed -* Description : Returns the result of USB reset hand shake (RHST) as -* : return value. -* Arguments : none -* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed -* : USB_HOST_FULL_SPEED ; Full-Speed -* : USB_HOST_LOW_SPEED ; Low-Speed -* : USB_HOST_NON_SPEED ; error -*******************************************************************************/ -uint16_t usb0_host_is_hispeed (void) -{ - uint16_t rhst; - uint16_t speed; - - rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, - USB_DVSTCTR0_RHST_SHIFT, - USB_DVSTCTR0_RHST); - if (rhst == USB_HOST_HSMODE) - { - speed = USB_HOST_HIGH_SPEED; - } - else if (rhst == USB_HOST_FSMODE) - { - speed = USB_HOST_FULL_SPEED; - } - else if (rhst == USB_HOST_LSMODE) - { - speed = USB_HOST_LOW_SPEED; - } - else - { - speed = USB_HOST_NON_SPEED; - } - - return speed; -} - -/******************************************************************************* -* Function Name: usb0_host_is_hispeed_enable -* Description : Returns the USB High-Speed connection enabled status as -* : return value. -* Arguments : none -* Return Value : USB_HOST_YES : Hi-Speed Enable -* : USB_HOST_NO : Hi-Speed Disable -*******************************************************************************/ -uint16_t usb0_host_is_hispeed_enable (void) -{ - uint16_t ret; - - ret = USB_HOST_NO; - - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE) == 1) - { - ret = USB_HOST_YES; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_host_set_pid_buf -* Description : Enables communicaqtion in the pipe specified by the argument -* : (BUF). -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_pid_buf (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_host_get_pid(pipe); - - if (pid == USB_HOST_PID_STALL2) - { - usb0_host_set_pid_nak(pipe); - } - - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - USB_HOST_PID_BUF, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - USB_HOST_PID_BUF, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_set_pid_nak -* Description : Disables communication (NAK) in the pipe specified by the argument. -* : When the pipe status was enabling communication (BUF) before -* : executing before executing this function, waits in the software -* : until the pipe becomes ready after setting disabled. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_pid_nak (uint16_t pipe) -{ - uint16_t pid; - uint16_t pbusy; - uint32_t loop; - - pid = usb0_host_get_pid(pipe); - - if (pid == USB_HOST_PID_STALL2) - { - usb0_host_set_pid_stall(pipe); - } - - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - USB_HOST_PID_NAK, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - USB_HOST_PID_NAK, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - default: - break; - } - - if (pid == USB_HOST_PID_BUF) - { - for (loop = 0; loop < 200; loop++) - { - switch (pipe) - { - case USB_HOST_PIPE0: - pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_PBUSY_SHIFT, - USB_DCPCTR_PBUSY); - break; - - case USB_HOST_PIPE1: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_HOST_PIPE2: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_HOST_PIPE3: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_HOST_PIPE4: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_HOST_PIPE5: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_HOST_PIPE6: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_HOST_PIPE7: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_HOST_PIPE8: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_HOST_PIPE9: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_PBUSY_SHIFT, - USB_PIPEnCTR_9_PBUSY); - break; - - default: - pbusy = 1; - break; - } - - if (pbusy == 0) - { - break; - } - - Userdef_USB_usb0_host_delay_500ns(); - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_set_pid_stall -* Description : Disables communication (STALL) in the pipe specified by the -* : argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_pid_stall (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_host_get_pid(pipe); - - if (pid == USB_HOST_PID_BUF) - { - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - USB_HOST_PID_STALL2, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - USB_HOST_PID_STALL2, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - default: - break; - } - } - else - { - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - USB_HOST_PID_STALL, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - USB_HOST_PID_STALL, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name: usb0_host_clear_pid_stall -* Description : Disables communication (NAK) in the pipe specified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_clear_pid_stall (uint16_t pipe) -{ - usb0_host_set_pid_nak(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_get_pid -* Description : Returns the pipe state specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : PID -*******************************************************************************/ -uint16_t usb0_host_get_pid (uint16_t pipe) -{ - uint16_t pid; - - switch (pipe) - { - case USB_HOST_PIPE0: - pid = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_HOST_PIPE1: - pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE2: - pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE3: - pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE4: - pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE5: - pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_HOST_PIPE6: - pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE7: - pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE8: - pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_HOST_PIPE9: - pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - default: - pid = 0; - break; - } - - return pid; -} - -/******************************************************************************* -* Function Name: usb0_host_set_csclr -* Description : CSPLIT status clear setting of sprit transaction in specified -* : pipe is performed. -* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit -* : in DCPCTR register are continuously changed (when the sequence -* : toggle bit of data PID is continuously changed over two or more pipes), -* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. -* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. -* : In addition, both bits should be operated after PID is set to NAK. -* : However, when it is set to the isochronous transfer as the transfer type -* : (TYPE=11), writing in SQSET bit is disabled. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_csclr (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_CSCLR_SHIFT, - USB_DCPCTR_CSCLR); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_CSCLR_SHIFT, - USB_PIPEnCTR_9_CSCLR); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_set_sqclr -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA0. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_sqclr (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_SQCLR_SHIFT, - USB_DCPCTR_SQCLR); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_SQCLR_SHIFT, - USB_PIPEnCTR_9_SQCLR); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_set_sqset -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA1. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_host_set_sqset (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_SQSET_SHIFT, - USB_DCPCTR_SQSET); - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_SQSET_SHIFT, - USB_PIPEnCTR_9_SQSET); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_get_sqmon -* Description : Toggle bit of specified pipe is obtained -* Arguments : uint16_t pipe ; Pipe number -* Return Value : sqmon -*******************************************************************************/ -uint16_t usb0_host_get_sqmon (uint16_t pipe) -{ - uint16_t sqmon; - - switch (pipe) - { - case USB_HOST_PIPE0: - sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_SQMON_SHIFT, - USB_DCPCTR_SQMON); - break; - - case USB_HOST_PIPE1: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_HOST_PIPE2: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_HOST_PIPE3: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_HOST_PIPE4: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_HOST_PIPE5: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_HOST_PIPE6: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_HOST_PIPE7: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_HOST_PIPE8: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_HOST_PIPE9: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_SQMON_SHIFT, - USB_PIPEnCTR_9_SQMON); - break; - - default: - sqmon = 0; - break; - } - - return sqmon; -} - -/******************************************************************************* -* Function Name: usb0_host_aclrm -* Description : The buffer of specified pipe is initialized -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_host_aclrm (uint16_t pipe) -{ - usb0_host_set_aclrm(pipe); - usb0_host_clr_aclrm(pipe); -} - -/******************************************************************************* -* Function Name: usb0_host_set_aclrm -* Description : The auto buffer clear mode of specified pipe is enabled -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_host_set_aclrm (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE0: - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_ACLRM_SHIFT, - USB_PIPEnCTR_9_ACLRM); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_clr_aclrm -* Description : The auto buffer clear mode of specified pipe is enabled -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_host_clr_aclrm (uint16_t pipe) -{ - switch (pipe) - { - case USB_HOST_PIPE0: - break; - - case USB_HOST_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_HOST_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_HOST_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 0, - USB_PIPEnCTR_9_ACLRM_SHIFT, - USB_PIPEnCTR_9_ACLRM); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_get_inbuf -* Description : Returns INBUFM of the pipe specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : inbuf -*******************************************************************************/ -uint16_t usb0_host_get_inbuf (uint16_t pipe) -{ - uint16_t inbuf; - - switch (pipe) - { - case USB_HOST_PIPE0: - inbuf = 0; - break; - - case USB_HOST_PIPE1: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_HOST_PIPE2: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_HOST_PIPE3: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_HOST_PIPE4: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_HOST_PIPE5: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_HOST_PIPE6: - inbuf = 0; - break; - - case USB_HOST_PIPE7: - inbuf = 0; - break; - - case USB_HOST_PIPE8: - inbuf = 0; - break; - - case USB_HOST_PIPE9: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_INBUFM_SHIFT, - USB_PIPEnCTR_9_INBUFM); - break; - - default: - inbuf = 0; - break; - } - - return inbuf; -} - -/******************************************************************************* -* Function Name: usb0_host_setting_interrupt -* Description : Sets the USB module interrupt level. -* Arguments : uint8_t level ; interrupt level -* Return Value : none -*******************************************************************************/ -void usb0_host_setting_interrupt (uint8_t level) -{ -#if(1) /* ohci_wrapp */ - IRQn_Type d0fifo_dmaintid; - IRQn_Type d1fifo_dmaintid; - - InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt); - GIC_SetPriority(USBI0_IRQn, level); - GIC_EnableIRQ(USBI0_IRQn); - - d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid(); - - if (d0fifo_dmaintid != 0xFFFF) - { - InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); - GIC_SetPriority(d0fifo_dmaintid, level); - GIC_EnableIRQ(d0fifo_dmaintid); - } - - d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid(); - - if (d1fifo_dmaintid != 0xFFFF) - { - InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); - GIC_SetPriority(d1fifo_dmaintid, level); - GIC_EnableIRQ(d1fifo_dmaintid); - } -#else - uint16_t d0fifo_dmaintid; - uint16_t d1fifo_dmaintid; - - R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt); - R_INTC_SetPriority(INTC_ID_USBI0, level); - R_INTC_Enable(INTC_ID_USBI0); - - d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid(); - - if (d0fifo_dmaintid != 0xFFFF) - { - R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); - R_INTC_SetPriority(d0fifo_dmaintid, level); - R_INTC_Enable(d0fifo_dmaintid); - } - - d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid(); - - if (d1fifo_dmaintid != 0xFFFF) - { - R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); - R_INTC_SetPriority(d1fifo_dmaintid, level); - R_INTC_Enable(d1fifo_dmaintid); - } -#endif -} - -/******************************************************************************* -* Function Name: usb0_host_reset_module -* Description : Initializes the USB module. -* : Enables providing clock to the USB module. -* : Sets USB bus wait register. -* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ -* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ -* Return Value : none -*******************************************************************************/ -void usb0_host_reset_module (uint16_t clockmode) -{ - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, - USB_SYSCFG_UPLLE_SHIFT, - USB_SYSCFG_UPLLE) == 1) - { - if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode) - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - USB200.SYSCFG0 = 0; - USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); - Userdef_USB_usb0_host_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - else - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - Userdef_USB_usb0_host_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - } - else - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - USB200.SYSCFG0 = 0; - USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); - Userdef_USB_usb0_host_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - - USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT); -} - -/******************************************************************************* -* Function Name: usb0_host_get_buf_size -* Description : Obtains pipe buffer size specified by the argument and -* : maximum packet size of the USB device in use. -* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum -* : packet size of the USB device using the corresponding pipe. -* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the -* : corresponding pipe is in continuous transfer mode, -* : obtains the buffer size allocated in the corresponcing pipe, -* : when incontinuous transfer, obtains maximum packet size. -* Arguments : uint16_t ; pipe Number -* Return Value : Maximum packet size or buffer size -*******************************************************************************/ -uint16_t usb0_host_get_buf_size (uint16_t pipe) -{ - uint16_t size; - uint16_t bufsize; - - if (pipe == USB_HOST_PIPE0) - { - size = RZA_IO_RegRead_16(&USB200.DCPMAXP, - USB_DCPMAXP_MXPS_SHIFT, - USB_DCPMAXP_MXPS); - } - else - { - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) - { - bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); - size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF); - } - else - { - size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); - } - } - return size; -} - -/******************************************************************************* -* Function Name: usb0_host_get_mxps -* Description : Obtains maximum packet size of the USB device using the pipe -* : specified by the argument. -* Arguments : uint16_t ; Pipe Number -* Return Value : Max Packet Size -*******************************************************************************/ -uint16_t usb0_host_get_mxps (uint16_t pipe) -{ - uint16_t size; - - if (pipe == USB_HOST_PIPE0) - { - size = RZA_IO_RegRead_16(&USB200.DCPMAXP, - USB_DCPMAXP_MXPS_SHIFT, - USB_DCPMAXP_MXPS); - } - else - { - size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); - } - - return size; -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c deleted file mode 100644 index 2f8ef12a38..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c +++ /dev/null @@ -1,434 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_controlrw.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#include "dev_drv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_CtrlTransStart -* Description : Executes USB control transfer. -* Arguments : uint16_t devadr ; device address -* : uint16_t Req ; bmRequestType & bRequest -* : uint16_t Val ; wValue -* : uint16_t Indx ; wIndex -* : uint16_t Len ; wLength -* : uint8_t *Buf ; Data buffer -* Return Value : DEVDRV_SUCCESS ; SUCCESS -* : DEVDRV_ERROR ; ERROR -*******************************************************************************/ -int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val, - uint16_t Indx, uint16_t Len, uint8_t * Buf) -{ - if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED) - { - RZA_IO_RegWrite_16(&USB200.SOFCFG, - 1, - USB_SOFCFG_TRNENSEL_SHIFT, - USB_SOFCFG_TRNENSEL); - } - else - { - RZA_IO_RegWrite_16(&USB200.SOFCFG, - 0, - USB_SOFCFG_TRNENSEL_SHIFT, - USB_SOFCFG_TRNENSEL); - } - - USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]); - - if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE) - { - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; - g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ - g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); - - if (Len == 0) - { - g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */ - } - else - { - if ((Req & 0x0080) != 0) - { - g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */ - } - else - { - g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */ - } - } - - g_usb0_host_SavReq = Req; /* save request */ - g_usb0_host_SavVal = Val; - g_usb0_host_SavIndx = Indx; - g_usb0_host_SavLen = Len; - } - else - { - if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val) - || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len)) - { - return DEVDRV_ERROR; - } - } - - switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) - { - /* --------------- SETUP STAGE --------------- */ - case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE): - usb0_host_SetupStage(Req, Val, Indx, Len); - break; - - case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING): - /* do nothing */ - break; - - case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */ - g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ - switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) - { - case USB_HOST_MODE_WRITE: - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; - break; - - case USB_HOST_MODE_READ: - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; - break; - - case USB_HOST_MODE_NO_DATA: - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; - break; - - default: - break; - } - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; - break; - - case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES): - if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) - { - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ - } - else - { - g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; - } - break; - - /* --------------- DATA STAGE --------------- */ - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE): - switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) - { - case USB_HOST_MODE_WRITE: - usb0_host_CtrlWriteStart((uint32_t)Len, Buf); - break; - - case USB_HOST_MODE_READ: - usb0_host_CtrlReadStart((uint32_t)Len, Buf); - break; - - default: - break; - } - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): - /* do nothing */ - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */ - g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES): - if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) - { - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ - } - else - { - g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; - usb0_host_clear_pid_stall(USB_HOST_PIPE0); - usb0_host_set_pid_buf(USB_HOST_PIPE0); - } - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL): - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ - break; - - /* --------------- STATUS STAGE --------------- */ - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE): - usb0_host_StatusStage(); - break; - - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - /* do nothing */ - break; - - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */ - usb0_host_set_pid_nak(USB_HOST_PIPE0); - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */ - break; - - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES): - if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) - { - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ - } - else - { - g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; - usb0_host_clear_pid_stall(USB_HOST_PIPE0); - usb0_host_set_pid_buf(USB_HOST_PIPE0); - } - break; - - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL): - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ - break; - - default: - break; - } - - if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT) - { - RZA_IO_RegWrite_16(&USB200.SOFCFG, - 0, - USB_SOFCFG_TRNENSEL_SHIFT, - USB_SOFCFG_TRNENSEL); - } - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_host_SetupStage -* Description : Executes USB control transfer/set up stage. -* Arguments : uint16_t Req ; bmRequestType & bRequest -* : uint16_t Val ; wValue -* : uint16_t Indx ; wIndex -* : uint16_t Len ; wLength -* Return Value : none -*******************************************************************************/ -void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len) -{ - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; - - USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */ - USB200.USBREQ = Req; - USB200.USBVAL = Val; - USB200.USBINDX = Indx; - USB200.USBLENG = Len; - USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */ -} - -/******************************************************************************* -* Function Name: usb0_host_StatusStage -* Description : Executes USB control transfer/status stage. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_StatusStage (void) -{ - uint8_t Buf1[16]; - - switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) - { - case USB_HOST_MODE_READ: - usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1); - break; - - case USB_HOST_MODE_WRITE: - usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); - break; - - case USB_HOST_MODE_NO_DATA: - usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_host_CtrlWriteStart -* Description : Executes USB control transfer/data stage(write). -* Arguments : uint32_t Bsize ; Data Size -* : uint8_t *Table ; Data Table Address -* Return Value : USB_HOST_WRITESHRT ; End of data write -* : USB_HOST_WRITEEND ; End of data write (not null) -* : USB_HOST_WRITING ; Continue of data write -* : USB_HOST_FIFOERROR ; FIFO access error -*******************************************************************************/ -uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table) -{ - uint16_t EndFlag_K; - uint16_t mbw; - - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; - - usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ - g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ - g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ - - USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ -#if(1) /* ohci_wrapp */ - Userdef_USB_usb0_host_delay_10us(3); -#endif - RZA_IO_RegWrite_16(&USB200.DCPCFG, - 1, - USB_DCPCFG_DIR_SHIFT, - USB_DCPCFG_DIR); - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw); - USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - - usb0_host_clear_pid_stall(USB_HOST_PIPE0); - EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0); - /* Host Control sequence */ - switch (EndFlag_K) - { - case USB_HOST_WRITESHRT: /* End of data write */ - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; - usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ - usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ - break; - - case USB_HOST_WRITEEND: /* End of data write (not null) */ - case USB_HOST_WRITING: /* Continue of data write */ - usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ - usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ - break; - - case USB_HOST_FIFOERROR: /* FIFO access error */ - break; - - default: - break; - } - usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ - return (EndFlag_K); /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_host_CtrlReadStart -* Description : Executes USB control transfer/data stage(read). -* Arguments : uint32_t Bsize ; Data Size -* : uint8_t *Table ; Data Table Address -* Return Value : none -*******************************************************************************/ -void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table) -{ - uint16_t mbw; - - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; - - usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ - g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ - g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ - - USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ -#if(1) /* ohci_wrapp */ - Userdef_USB_usb0_host_delay_10us(3); -#endif - RZA_IO_RegWrite_16(&USB200.DCPCFG, - 0, - USB_DCPCFG_DIR_SHIFT, - USB_DCPCFG_DIR); - - mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); - usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw); - USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ - - usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ - usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */ - usb0_host_clear_pid_stall(USB_HOST_PIPE0); - usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c deleted file mode 100644 index baa39adaac..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c +++ /dev/null @@ -1,889 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_drv_api.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#include "dev_drv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_api_host_init -* Description : Initializes USB module in the USB host mode. -* : USB connection is executed when executing this function in -* : the states that USB device isconnected to the USB port. -* Arguments : uint8_t int_level : USB Module interrupt level -* : USBU16 mode : USB_HOST_HIGH_SPEED -* : USB_HOST_FULL_SPEED -* : uint16_t clockmode : USB Clock mode -* Return Value : USB detach or attach -* : USB_HOST_ATTACH -* : USB_HOST_DETACH -*******************************************************************************/ -uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) -{ - uint16_t connect; - volatile uint8_t dummy_buf; - - CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */ - dummy_buf = CPG.STBCR7; /* (Dummy read) */ - - g_usb0_host_SupportUsbDeviceSpeed = mode; - - usb0_host_setting_interrupt(int_level); - usb0_host_reset_module(clockmode); - - g_usb0_host_bchg_flag = USB_HOST_NO; - g_usb0_host_detach_flag = USB_HOST_NO; - g_usb0_host_attach_flag = USB_HOST_NO; - - g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; - g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; - - usb0_host_InitModule(); - - connect = usb0_host_CheckAttach(); - - if (connect == USB_HOST_ATTACH) - { - g_usb0_host_attach_flag = USB_HOST_YES; - } - else - { - usb0_host_UsbDetach2(); - } - - return connect; -} - -#if(1) /* ohci_wrapp */ -#else -/******************************************************************************* -* Function Name: usb0_api_host_enumeration -* Description : Initializes USB module in the USB host mode. -* : USB connection is executed when executing this function in -* : the states that USB device isconnected to the USB port. -* Arguments : uint16_t devadr : device address -* Return Value : DEVDRV_USBH_DETACH_ERR : device detach -* : DEVDRV_SUCCESS : device enumeration success -* : DEVDRV_ERROR : device enumeration error -*******************************************************************************/ -int32_t usb0_api_host_enumeration (uint16_t devadr) -{ - int32_t ret; - uint16_t driver_sts; - - g_usb0_host_setUsbAddress = devadr; - - while (1) - { - driver_sts = usb0_api_host_GetUsbDeviceState(); - - if (driver_sts == USB_HOST_DRV_DETACHED) - { - ret = DEVDRV_USBH_DETACH_ERR; - break; - } - else if (driver_sts == USB_HOST_DRV_CONFIGURED) - { - ret = DEVDRV_SUCCESS; - break; - } - else if (driver_sts == USB_HOST_DRV_STALL) - { - ret = DEVDRV_ERROR; - break; - } - else if (driver_sts == USB_HOST_DRV_NORES) - { - ret = DEVDRV_ERROR; - break; - } - else - { - /* Do Nothing */ - } - } - - if (driver_sts == USB_HOST_DRV_NORES) - { - while (1) - { - driver_sts = usb0_api_host_GetUsbDeviceState(); - - if (driver_sts == USB_HOST_DRV_DETACHED) - { - break; - } - } - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_api_host_detach -* Description : USB detach routine -* Arguments : none -* Return Value : USB_HOST_DETACH : USB detach -* : USB_HOST_ATTACH : USB attach -* : DEVDRV_ERROR : error -*******************************************************************************/ -int32_t usb0_api_host_detach (void) -{ - int32_t ret; - uint16_t driver_sts; - - while (1) - { - driver_sts = usb0_api_host_GetUsbDeviceState(); - - if (driver_sts == USB_HOST_DRV_DETACHED) - { - ret = USB_HOST_DETACH; - break; - } - else if (driver_sts == USB_HOST_DRV_CONFIGURED) - { - ret = USB_HOST_ATTACH; - break; - } - else if (driver_sts == USB_HOST_DRV_STALL) - { - ret = DEVDRV_ERROR; - break; - } - else if (driver_sts == USB_HOST_DRV_NORES) - { - ret = DEVDRV_ERROR; - break; - } - else - { - /* Do Nothing */ - } - } - - if (driver_sts == USB_HOST_DRV_NORES) - { - while (1) - { - driver_sts = usb0_api_host_GetUsbDeviceState(); - - if (driver_sts == USB_HOST_DRV_DETACHED) - { - break; - } - } - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_api_host_data_in -* Description : Executes USB transfer as data-in in the argument specified pipe. -* Arguments : uint16_t devadr ; device address -* : uint16_t Pipe ; Pipe Number -* : uint32_t Size ; Data Size -* : uint8_t *data_buf ; Data data_buf Address -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) -{ - int32_t ret; - - if (Pipe == USB_HOST_PIPE0) - { - return DEVDRV_ERROR; - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) - { - return DEVDRV_ERROR; - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1) - { - return DEVDRV_ERROR; - } - - if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) - { - usb0_host_start_receive_transfer(Pipe, Size, data_buf); - } - else - { - return DEVDRV_ERROR; /* Now pipe is busy */ - } - - /* waiting for completing routine */ - do - { - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - break; - } - - if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) - { - break; - } - - } while (1); - - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - return DEVDRV_USBH_DETACH_ERR; - } - - switch (g_usb0_host_pipe_status[Pipe]) - { - case USB_HOST_PIPE_DONE: - ret = DEVDRV_SUCCESS; - break; - - case USB_HOST_PIPE_STALL: - ret = DEVDRV_USBH_STALL; - break; - - case USB_HOST_PIPE_NORES: - ret = DEVDRV_USBH_COM_ERR; - break; - - default: - ret = DEVDRV_ERROR; - break; - } - - usb0_host_stop_transfer(Pipe); - - g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_api_host_data_out -* Description : Executes USB transfer as data-out in the argument specified pipe. -* Arguments : uint16_t devadr ; device address -* : uint16_t Pipe ; Pipe Number -* : uint32_t Size ; Data Size -* : uint8_t *data_buf ; Data data_buf Address -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) -{ - int32_t ret; - - if (Pipe == USB_HOST_PIPE0) - { - return DEVDRV_ERROR; - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) - { - return DEVDRV_ERROR; - } - - if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) - { - return DEVDRV_ERROR; - } - - if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) - { - usb0_host_start_send_transfer(Pipe, Size, data_buf); - } - else - { - return DEVDRV_ERROR; /* Now pipe is busy */ - } - - /* waiting for completing routine */ - do - { - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - break; - } - - if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) - { - break; - } - - } while (1); - - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - return DEVDRV_USBH_DETACH_ERR; - } - - switch (g_usb0_host_pipe_status[Pipe]) - { - case USB_HOST_PIPE_DONE: - ret = DEVDRV_SUCCESS; - break; - - case USB_HOST_PIPE_STALL: - ret = DEVDRV_USBH_STALL; - break; - - case USB_HOST_PIPE_NORES: - ret = DEVDRV_USBH_COM_ERR; - break; - - default: - ret = DEVDRV_ERROR; - break; - } - - usb0_host_stop_transfer(Pipe); - - g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_api_host_control_transfer -* Description : Executes USB control transfer. -* Arguments : uint16_t devadr ; device address -* : uint16_t Req ; bmRequestType & bRequest -* : uint16_t Val ; wValue -* : uint16_t Indx ; wIndex -* : uint16_t Len ; wLength -* : uint8_t *buf ; Buffer -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_USBH_DETACH_ERR ; device detach -* : DEVDRV_USBH_CTRL_COM_ERR ; device no response -* : DEVDRV_USBH_STALL ; STALL -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, - uint16_t Len, uint8_t * Buf) -{ - int32_t ret; - - do - { - ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf); - - if (ret == DEVDRV_SUCCESS) - { - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - break; - } - - if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE) - && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)) - { - break; - } - } - else - { - return DEVDRV_ERROR; - } - } while (1); - - if (g_usb0_host_detach_flag == USB_HOST_YES) - { - return DEVDRV_USBH_DETACH_ERR; - } - - switch (g_usb0_host_pipe_status[USB_HOST_PIPE0]) - { - case USB_HOST_PIPE_DONE: - ret = DEVDRV_SUCCESS; - break; - - case USB_HOST_PIPE_STALL: - ret = DEVDRV_USBH_STALL; - break; - - case USB_HOST_PIPE_NORES: - ret = DEVDRV_USBH_CTRL_COM_ERR; - break; - - default: - ret = DEVDRV_ERROR; - break; - } - - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_api_host_set_endpoint -* Description : Sets end point on the information specified in the argument. -* Arguments : uint16_t devadr ; device address -* : uint8_t *configdescriptor ; device configration descriptor -* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor) -{ - uint16_t ret; - uint32_t end_point; - uint32_t offset; - uint32_t totalLength; - USB_HOST_CFG_PIPETBL_t * pipe_table; - - /* End Point Search */ - end_point = 0; - offset = configdescriptor[0]; - totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8)); - - do - { - if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC) - { - pipe_table = &user_table[end_point]; - - if (pipe_table->pipe_number == 0xffff) - { - break; - } - - ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]); - - if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT)) - { - return DEVDRV_ERROR; - } - - ++end_point; - } - - /* Next End Point Search */ - offset += configdescriptor[offset]; - - } while (offset < totalLength); - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_api_host_clear_endpoint -* Description : Clears the pipe definition table specified in the argument. -* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table) -{ - uint16_t pipe; - - for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) - { - if (user_table->pipe_number == 0xffff) - { - break; - } - user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); - user_table->pipe_max_pktsize = 0; - user_table->pipe_cycle = 0; - - user_table++; - } - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_api_host_clear_endpoint_pipe -* Description : Clears the pipe definition table specified in the argument. -* Arguments : uint16_t pipe_sel : Pipe Number -* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table) -{ - uint16_t pipe; - - for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) - { - if (user_table->pipe_number == 0xffff) - { - break; - } - - if (user_table->pipe_number == pipe_sel) - { - user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); - user_table->pipe_max_pktsize = 0; - user_table->pipe_cycle = 0; - break; - } - - user_table++; - } - - return DEVDRV_SUCCESS; -} -#endif - -/******************************************************************************* -* Function Name: usb0_api_host_SetEndpointTable -* Description : Sets the end point on the information specified by the argument. -* Arguments : uint16_t devadr : device address -* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table -* : uint8_t *Table : Endpoint descriptor -* Return Value : USB_HOST_DIR_H_IN ; IN endpoint -* : USB_HOST_DIR_H_OUT ; OUT endpoint -* : USB_END_POINT_ERROR ; error -*******************************************************************************/ -uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table) -{ - uint16_t PipeCfg; - uint16_t PipeMaxp; - uint16_t pipe_number; - uint16_t ret; - uint16_t ret_flag = 0; // avoid warning. - - pipe_number = user_table->pipe_number; - - if (Table[1] != USB_HOST_ENDPOINT_DESC) - { - return USB_END_POINT_ERROR; - } - - switch (Table[3] & USB_HOST_EP_TYPE) - { - case USB_HOST_EP_CNTRL: - ret_flag = USB_END_POINT_ERROR; - break; - - case USB_HOST_EP_ISO: - if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2)) - { - return USB_END_POINT_ERROR; - } - - PipeCfg = USB_HOST_ISO; - break; - - case USB_HOST_EP_BULK: - if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5)) - { - return USB_END_POINT_ERROR; - } - - PipeCfg = USB_HOST_BULK; - break; - - case USB_HOST_EP_INT: - if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9)) - { - return USB_END_POINT_ERROR; - } - - PipeCfg = USB_HOST_INTERRUPT; - break; - - default: - ret_flag = USB_END_POINT_ERROR; - break; - } - - if (ret_flag == USB_END_POINT_ERROR) - { - return ret_flag; - } - - /* Set pipe configuration table */ - if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */ - { - if (PipeCfg == USB_HOST_ISO) - { - /* Transfer Type is ISO*/ - PipeCfg |= USB_HOST_DIR_H_IN; - - switch (user_table->fifo_port) - { - case USB_HOST_CUSE: - case USB_HOST_D0USE: - case USB_HOST_D1USE: - case USB_HOST_D0DMA: - case USB_HOST_D1DMA: - PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); - break; - - default: - ret_flag = USB_END_POINT_ERROR; - break; - } - - if (ret_flag == USB_END_POINT_ERROR) - { - return ret_flag; - } - } - else - { - /* Transfer Type is BULK or INT */ - PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */ - - switch (user_table->fifo_port) - { - case USB_HOST_CUSE: - case USB_HOST_D0USE: - case USB_HOST_D1USE: - PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); - break; - - case USB_HOST_D0DMA: - case USB_HOST_D1DMA: - PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); -#ifdef __USB_DMA_BFRE_ENABLE__ - /* this routine cannnot be perfomred if read operation is executed in buffer size */ - PipeCfg |= USB_HOST_BFREON; -#endif - break; - - default: - ret_flag = USB_END_POINT_ERROR; - break; - } - - if (ret_flag == USB_END_POINT_ERROR) - { - return ret_flag; - } - } - ret = USB_HOST_PIPE_IN; - } - else /* OUT(send) */ - { - if (PipeCfg == USB_HOST_ISO) - { - /* Transfer Type is ISO*/ - PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); - } - else - { - /* Transfer Type is BULK or INT */ - PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); - } - PipeCfg |= USB_HOST_DIR_H_OUT; - ret = USB_HOST_PIPE_OUT; - } - - switch (user_table->fifo_port) - { - case USB_HOST_CUSE: - g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE; - break; - - case USB_HOST_D0USE: - g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE; - break; - - case USB_HOST_D1USE: - g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE; - break; - - case USB_HOST_D0DMA: - g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA; - break; - - case USB_HOST_D1DMA: - g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA; - break; - - default: - ret_flag = USB_END_POINT_ERROR; - break; - } - - if (ret_flag == USB_END_POINT_ERROR) - { - return ret_flag; - } - - /* Endpoint number set */ - PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); - g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); - - /* Max packet size set */ - PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8)); - - if (PipeMaxp == 0u) - { - return USB_END_POINT_ERROR; - } - - /* Set device address */ - PipeMaxp |= (uint16_t)(devadr << 12); - - user_table->pipe_cfg = PipeCfg; - user_table->pipe_max_pktsize = PipeMaxp; - - usb0_host_resetEP(user_table); - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_host_resetEP -* Description : Sets the end point on the information specified by the argument. -* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table -* Return Value : none -*******************************************************************************/ -static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl) -{ - - uint16_t pipe; - - /* Host pipe */ - /* The pipe number of pipe definition table is obtained */ - pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */ - - /* FIFO port access pipe is set to initial value */ - /* The connection with FIFO should be cut before setting the pipe */ - if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, - USB_CFIFOSEL_CURPIPE_SHIFT, - USB_CFIFOSEL_CURPIPE) == pipe) - { - usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16); - } - - if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE) == pipe) - { - usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16); - } - - if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE) == pipe) - { - usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16); - } - - /* Interrupt of pipe set is disabled */ - usb0_host_disable_brdy_int(pipe); - usb0_host_disable_nrdy_int(pipe); - usb0_host_disable_bemp_int(pipe); - - /* Pipe to set is set to NAK */ - usb0_host_set_pid_nak(pipe); - - /* Pipe is set */ - USB200.PIPESEL = pipe; - - USB200.PIPECFG = tbl->pipe_cfg; - USB200.PIPEBUF = tbl->pipe_buf; - USB200.PIPEMAXP = tbl->pipe_max_pktsize; - USB200.PIPEPERI = tbl->pipe_cycle; - - g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg; - g_usb0_host_pipebuf[pipe] = tbl->pipe_buf; - g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize; - g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle; - - /* Sequence bit clear */ - usb0_host_set_sqclr(pipe); - - usb0_host_aclrm(pipe); - usb0_host_set_csclr(pipe); - - /* Pipe window selection is set to unused */ - USB200.PIPESEL = USB_HOST_PIPE0; - -} - -#if(1) /* ohci_wrapp */ -#else -/******************************************************************************* -* Function Name: usb0_api_host_data_count -* Description : Get g_usb0_host_data_count[pipe] -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t *data_count ; return g_usb0_data_count[pipe] -* Return Value : DEVDRV_SUCCESS ; success -* : DEVDRV_ERROR ; error -*******************************************************************************/ -int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count) -{ - if (pipe > USB_HOST_MAX_PIPE_NO) - { - return DEVDRV_ERROR; - } - - *data_count = g_usb0_host_PipeDataSize[pipe]; - - return DEVDRV_SUCCESS; -} -#endif - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c deleted file mode 100644 index 2d1d5f5fc4..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_global.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -const uint16_t g_usb0_host_bit_set[16] = -{ - 0x0001, 0x0002, 0x0004, 0x0008, - 0x0010, 0x0020, 0x0040, 0x0080, - 0x0100, 0x0200, 0x0400, 0x0800, - 0x1000, 0x2000, 0x4000, 0x8000 -}; - -uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; -uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; - -uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1]; -uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1]; -uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1]; -uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1]; - -USB_HOST_DMA_t g_usb0_host_DmaInfo[2]; - -uint16_t g_usb0_host_DmaPipe[2]; -uint16_t g_usb0_host_DmaBval[2]; -uint16_t g_usb0_host_DmaStatus[2]; - -uint16_t g_usb0_host_driver_state; -uint16_t g_usb0_host_ConfigNum; -uint16_t g_usb0_host_CmdStage; -uint16_t g_usb0_host_bchg_flag; -uint16_t g_usb0_host_detach_flag; -uint16_t g_usb0_host_attach_flag; - -uint16_t g_usb0_host_UsbAddress; -uint16_t g_usb0_host_setUsbAddress; -uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; -uint16_t g_usb0_host_UsbDeviceSpeed; -uint16_t g_usb0_host_SupportUsbDeviceSpeed; - -uint16_t g_usb0_host_SavReq; -uint16_t g_usb0_host_SavVal; -uint16_t g_usb0_host_SavIndx; -uint16_t g_usb0_host_SavLen; - -uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; -uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; -uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; -uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_init_pipe_status -* Description : Initialize pipe status. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_init_pipe_status (void) -{ - uint16_t loop; - - g_usb0_host_ConfigNum = 0; - - for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop) - { - g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE; - g_usb0_host_PipeDataSize[loop] = 0; - - /* pipe configuration in usb0_host_resetEP() */ - g_usb0_host_pipecfg[loop] = 0; - g_usb0_host_pipebuf[loop] = 0; - g_usb0_host_pipemaxp[loop] = 0; - g_usb0_host_pipeperi[loop] = 0; - } -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c deleted file mode 100644 index f4e5a27c77..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c +++ /dev/null @@ -1,496 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_usbint.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#if(1) /* ohci_wrapp */ -#include "ohci_wrapp_RZ_A1_local.h" -#endif - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_host_interrupt1(void); -static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl); -static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl); -static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_interrupt -* Description : Executes USB interrupt. -* : Register this function in the USB interrupt handler. -* : Set CFIF0 in the pipe set before the interrupt after executing -* : this function. -* Arguments : uint32_t int_sense ; Interrupts detection mode -* : ; INTC_LEVEL_SENSITIVE : Level sense -* : ; INTC_EDGE_TRIGGER : Edge trigger -* Return Value : none -*******************************************************************************/ -void usb0_host_interrupt (uint32_t int_sense) -{ - uint16_t savepipe1; - uint16_t savepipe2; - uint16_t buffer; - - savepipe1 = USB200.CFIFOSEL; - savepipe2 = USB200.PIPESEL; - usb0_host_interrupt1(); - - /* Control transmission changes ISEL within interruption processing. */ - /* For this reason, write return of ISEL cannot be performed. */ - buffer = USB200.CFIFOSEL; - buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); - buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE); - USB200.CFIFOSEL = buffer; - USB200.PIPESEL = savepipe2; -} - -/******************************************************************************* -* Function Name: usb0_host_interrupt1 -* Description : Execue the USB interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_interrupt1 (void) -{ - uint16_t intsts0; - uint16_t intsts1; - uint16_t intenb0; - uint16_t intenb1; - uint16_t brdysts; - uint16_t nrdysts; - uint16_t bempsts; - uint16_t brdyenb; - uint16_t nrdyenb; - uint16_t bempenb; - volatile uint16_t dumy_sts; - - intsts0 = USB200.INTSTS0; - intsts1 = USB200.INTSTS1; - intenb0 = USB200.INTENB0; - intenb1 = USB200.INTENB1; - - if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE)) - { - USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG; - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_BCHGE_SHIFT, - USB_INTENB1_BCHGE); - g_usb0_host_bchg_flag = USB_HOST_YES; - } - else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE)) - { - USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK; -#if(1) /* ohci_wrapp */ - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); -#else - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; -#endif - } - else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE)) - { - USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN; -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); -#else - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; -#endif - } - else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH) - && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE)) - { - USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH; - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_DTCHE_SHIFT, - USB_INTENB1_DTCHE); - g_usb0_host_detach_flag = USB_HOST_YES; - - Userdef_USB_usb0_host_detach(); - - usb0_host_UsbDetach2(); - } - else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH) - && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE)) - { - USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH; - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_ATTCHE_SHIFT, - USB_INTENB1_ATTCHE); - g_usb0_host_attach_flag = USB_HOST_YES; - - Userdef_USB_usb0_host_attach(); - - usb0_host_UsbAttach(); - } - else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY))) - { - brdysts = USB200.BRDYSTS; - nrdysts = USB200.NRDYSTS; - bempsts = USB200.BEMPSTS; - brdyenb = USB200.BRDYENB; - nrdyenb = USB200.NRDYENB; - bempenb = USB200.BEMPENB; - - if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb)) - { - usb0_host_BRDYInterrupt(brdysts, brdyenb); - } - else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb)) - { - usb0_host_BEMPInterrupt(bempsts, bempenb); - } - else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb)) - { - usb0_host_NRDYInterrupt(nrdysts, nrdyenb); - } - else - { - /* Do Nothing */ - } - } - else - { - /* Do Nothing */ - } - - /* Three dummy read for clearing interrupt requests */ - dumy_sts = USB200.INTSTS0; - dumy_sts = USB200.INTSTS1; - -} - -/******************************************************************************* -* Function Name: usb0_host_BRDYInterrupt -* Description : Executes USB BRDY interrupt. -* Arguments : uint16_t Status ; BRDYSTS Register Value -* : uint16_t Int_enbl ; BRDYENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl) -{ - uint16_t buffer; - volatile uint16_t dumy_sts; - - if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) - { - USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; - -#if(1) /* ohci_wrapp */ - switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) - { - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): - buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); - switch (buffer) - { - case USB_HOST_READING: /* Continue of data read */ - break; - - case USB_HOST_READEND: /* End of data read */ - case USB_HOST_READSHRT: /* End of data read */ - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); - break; - - case USB_HOST_READOVER: /* buffer over */ - USB200.CFIFOCTR = USB_HOST_BITBCLR; - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); - break; - - case USB_HOST_FIFOERROR: /* FIFO access error */ - default: - break; - } - break; - - default: - break; - } -#else - switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) - { - case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - break; - - case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): - buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); - - switch (buffer) - { - case USB_HOST_READING: /* Continue of data read */ - break; - - case USB_HOST_READEND: /* End of data read */ - case USB_HOST_READSHRT: /* End of data read */ - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - break; - - case USB_HOST_READOVER: /* buffer over */ - USB200.CFIFOCTR = USB_HOST_BITBCLR; - usb0_host_disable_brdy_int(USB_HOST_PIPE0); - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - break; - - case USB_HOST_FIFOERROR: /* FIFO access error */ - default: - break; - } - break; - - default: - break; - } -#endif - } - else - { - usb0_host_brdy_int(Status, Int_enbl); - } - - /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BRDYSTS; -} - -/******************************************************************************* -* Function Name: usb0_host_NRDYInterrupt -* Description : Executes USB NRDY interrupt. -* Arguments : uint16_t Status ; NRDYSTS Register Value -* : uint16_t Int_enbl ; NRDYENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl) -{ - uint16_t pid; - volatile uint16_t dumy_sts; - - if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) - { - USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; - pid = usb0_host_get_pid(USB_HOST_PIPE0); - - if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) - { - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); -#endif - } - else if (pid == USB_HOST_PID_NAK) - { - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); -#endif - } - else - { - /* Do Nothing */ - } - } - else - { - usb0_host_nrdy_int(Status, Int_enbl); - } - - /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.NRDYSTS; -} - -/******************************************************************************* -* Function Name: usb0_host_BEMPInterrupt -* Description : Executes USB BEMP interrupt. -* Arguments : uint16_t Status ; BEMPSTS Register Value -* : uint16_t Int_enbl ; BEMPENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl) -{ - uint16_t buffer; - uint16_t pid; - volatile uint16_t dumy_sts; - - if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) - { - USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; - pid = usb0_host_get_pid(USB_HOST_PIPE0); - - if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) - { - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; -#if(1) /* ohci_wrapp */ - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); -#endif - } - else - { -#if(1) /* ohci_wrapp */ - switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) - { - case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); - break; - - case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): - buffer = usb0_host_write_buffer(USB_HOST_PIPE0); - switch (buffer) - { - case USB_HOST_WRITING: /* Continue of data write */ - case USB_HOST_WRITEEND: /* End of data write (zero-length) */ - break; - - case USB_HOST_WRITESHRT: /* End of data write */ - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; - ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); - break; - - case USB_HOST_FIFOERROR: /* FIFO access error */ - default: - break; - } - break; - - default: - /* do nothing */ - break; - } -#else - switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) - { - case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; - break; - - case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): - buffer = usb0_host_write_buffer(USB_HOST_PIPE0); - switch (buffer) - { - case USB_HOST_WRITING: /* Continue of data write */ - case USB_HOST_WRITEEND: /* End of data write (zero-length) */ - break; - - case USB_HOST_WRITESHRT: /* End of data write */ - g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); - g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; - break; - - case USB_HOST_FIFOERROR: /* FIFO access error */ - default: - break; - } - break; - - case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; - break; - - default: - /* do nothing */ - break; - } -#endif - } - } - else - { - usb0_host_bemp_int(Status, Int_enbl); - } - - /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BEMPSTS; -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c deleted file mode 100644 index 4c5f810db3..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c +++ /dev/null @@ -1,637 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_usbsig.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_host.h" -#include "dev_drv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_host_EnableINT_Module(void); -static void usb0_host_Enable_AttachINT(void); -static void usb0_host_Disable_AttachINT(void); -static void usb0_host_Disable_BchgINT(void); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_host_InitModule -* Description : Initializes the USB module in USB host module. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_InitModule (void) -{ - uint16_t buf1; - uint16_t buf2; - uint16_t buf3; - - usb0_host_init_pipe_status(); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_DCFM_SHIFT, - USB_SYSCFG_DCFM); /* HOST mode */ - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_DRPD_SHIFT, - USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */ - - do - { - buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - Userdef_USB_usb0_host_delay_xms(50); - buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - Userdef_USB_usb0_host_delay_xms(50); - buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - - } while ((buf1 != buf2) || (buf1 != buf3)); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_USBE_SHIFT, - USB_SYSCFG_USBE); - - USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); - USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); - USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); -} - -/******************************************************************************* -* Function Name: usb0_host_CheckAttach -* Description : Returns the USB device connection state. -* Arguments : none -* Return Value : uint16_t ; USB_HOST_ATTACH : Attached -* : ; USB_HOST_DETACH : not Attached -*******************************************************************************/ -uint16_t usb0_host_CheckAttach (void) -{ - uint16_t buf1; - uint16_t buf2; - uint16_t buf3; - uint16_t rhst; - - do - { - buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - Userdef_USB_usb0_host_delay_xms(50); - buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - Userdef_USB_usb0_host_delay_xms(50); - buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - - } while ((buf1 != buf2) || (buf1 != buf3)); - - rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, - USB_DVSTCTR0_RHST_SHIFT, - USB_DVSTCTR0_RHST); - if (rhst == USB_HOST_UNDECID) - { - if (buf1 == USB_HOST_FS_JSTS) - { - if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED) - { - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE); - } - else - { - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE); - } - return USB_HOST_ATTACH; - } - else if (buf1 == USB_HOST_LS_JSTS) - { - /* Low Speed Device */ - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE); - return USB_HOST_ATTACH; - } - else - { - /* Do Nothing */ - } - } - else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE)) - { - return USB_HOST_ATTACH; - } - else if (rhst == USB_HOST_LSMODE) - { - return USB_HOST_ATTACH; - } - else - { - /* Do Nothing */ - } - - return USB_HOST_DETACH; -} - -/******************************************************************************* -* Function Name: usb0_host_UsbAttach -* Description : Connects the USB device. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_UsbAttach (void) -{ - usb0_host_EnableINT_Module(); - usb0_host_Disable_BchgINT(); - usb0_host_Disable_AttachINT(); - usb0_host_Enable_DetachINT(); -} - -/******************************************************************************* -* Function Name: usb0_host_UsbDetach -* Description : Disconnects the USB device. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_UsbDetach (void) -{ - uint16_t pipe; - uint16_t devadr; - - g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; - - /* Terminate all the pipes in which communications on port */ - /* are currently carried out */ - for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe) - { - if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE) - { - if (pipe == USB_HOST_PIPE0) - { - devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP, - USB_DCPMAXP_DEVSEL_SHIFT, - USB_DCPMAXP_DEVSEL); - } - else - { - devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL); - } - - if (devadr == g_usb0_host_UsbAddress) - { - usb0_host_stop_transfer(pipe); - } - - g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE; - } - } - - g_usb0_host_ConfigNum = 0; - g_usb0_host_UsbAddress = 0; - g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; - - usb0_host_UsbDetach2(); -} - -/******************************************************************************* -* Function Name: usb0_host_UsbDetach2 -* Description : Disconnects the USB device. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_UsbDetach2 (void) -{ - usb0_host_Disable_DetachINT(); - usb0_host_Disable_BchgINT(); - usb0_host_Enable_AttachINT(); -} - -/******************************************************************************* -* Function Name: usb0_host_UsbBusReset -* Description : Issues the USB bus reset signal. -* Arguments : none -* Return Value : uint16_t ; RHST -*******************************************************************************/ -uint16_t usb0_host_UsbBusReset (void) -{ - uint16_t buffer; - uint16_t loop; - - RZA_IO_RegWrite_16(&USB200.DVSTCTR0, - 1, - USB_DVSTCTR0_USBRST_SHIFT, - USB_DVSTCTR0_USBRST); - RZA_IO_RegWrite_16(&USB200.DVSTCTR0, - 0, - USB_DVSTCTR0_UACT_SHIFT, - USB_DVSTCTR0_UACT); - - Userdef_USB_usb0_host_delay_xms(50); - - buffer = USB200.DVSTCTR0; - buffer &= (uint16_t)(~(USB_HOST_BITRST)); - buffer |= USB_HOST_BITUACT; - USB200.DVSTCTR0 = buffer; - - Userdef_USB_usb0_host_delay_xms(20); - - for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop) - { - buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0, - USB_DVSTCTR0_RHST_SHIFT, - USB_DVSTCTR0_RHST); - if (buffer == USB_HOST_HSPROC) - { - Userdef_USB_usb0_host_delay_xms(10); - } - else - { - break; - } - } - - return buffer; -} - -/******************************************************************************* -* Function Name: usb0_host_UsbResume -* Description : Issues the USB resume signal. -* Arguments : none -* Return Value : int32_t ; DEVDRV_SUCCESS -* : ; DEVDRV_ERROR -*******************************************************************************/ -int32_t usb0_host_UsbResume (void) -{ - uint16_t buf; - - if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0) - { - /* not SUSPEND */ - return DEVDRV_ERROR; - } - - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_BCHGE_SHIFT, - USB_INTENB1_BCHGE); - RZA_IO_RegWrite_16(&USB200.DVSTCTR0, - 1, - USB_DVSTCTR0_RESUME_SHIFT, - USB_DVSTCTR0_RESUME); - Userdef_USB_usb0_host_delay_xms(20); - - buf = USB200.DVSTCTR0; - buf &= (uint16_t)(~(USB_HOST_BITRESUME)); - buf |= USB_HOST_BITUACT; - USB200.DVSTCTR0 = buf; - - g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND; - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_host_UsbSuspend -* Description : Issues the USB suspend signal. -* Arguments : none -* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND -* : ; DEVDRV_ERROR :SUSPEND -*******************************************************************************/ -int32_t usb0_host_UsbSuspend (void) -{ - uint16_t buf; - - if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0) - { - /* SUSPEND */ - return DEVDRV_ERROR; - } - - RZA_IO_RegWrite_16(&USB200.DVSTCTR0, - 0, - USB_DVSTCTR0_UACT_SHIFT, - USB_DVSTCTR0_UACT); - - Userdef_USB_usb0_host_delay_xms(5); - - buf = RZA_IO_RegRead_16(&USB200.SYSSTS0, - USB_SYSSTS0_LNST_SHIFT, - USB_SYSSTS0_LNST); - if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS)) - { - usb0_host_UsbDetach(); - } - else - { - g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND; - } - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_host_Enable_DetachINT -* Description : Enables the USB disconnection interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_Enable_DetachINT (void) -{ - USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); - RZA_IO_RegWrite_16(&USB200.INTENB1, - 1, - USB_INTENB1_DTCHE_SHIFT, - USB_INTENB1_DTCHE); -} - -/******************************************************************************* -* Function Name: usb0_host_Disable_DetachINT -* Description : Disables the USB disconnection interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_Disable_DetachINT (void) -{ - USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_DTCHE_SHIFT, - USB_INTENB1_DTCHE); -} - -/******************************************************************************* -* Function Name: usb0_host_Enable_AttachINT -* Description : Enables the USB connection detection interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_Enable_AttachINT (void) -{ - USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); - RZA_IO_RegWrite_16(&USB200.INTENB1, - 1, - USB_INTENB1_ATTCHE_SHIFT, - USB_INTENB1_ATTCHE); -} - -/******************************************************************************* -* Function Name: usb0_host_Disable_AttachINT -* Description : Disables the USB connection detection interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_Disable_AttachINT (void) -{ - USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_ATTCHE_SHIFT, - USB_INTENB1_ATTCHE); -} - -/******************************************************************************* -* Function Name: usb0_host_Disable_BchgINT -* Description : Disables the USB bus change detection interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_Disable_BchgINT (void) -{ - USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG)); - RZA_IO_RegWrite_16(&USB200.INTENB1, - 0, - USB_INTENB1_BCHGE_SHIFT, - USB_INTENB1_BCHGE); -} - -/******************************************************************************* -* Function Name: usb0_host_set_devadd -* Description : DEVADDn register is set by specified value -* Arguments : uint16_t addr : Device address -* : uint16_t *devadd : Set value -* Return Value : none -*******************************************************************************/ -void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd) -{ - uint16_t * ptr; - uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. - - switch (addr) - { - case USB_HOST_DEVICE_0: - ptr = (uint16_t *)&USB200.DEVADD0; - break; - - case USB_HOST_DEVICE_1: - ptr = (uint16_t *)&USB200.DEVADD1; - break; - - case USB_HOST_DEVICE_2: - ptr = (uint16_t *)&USB200.DEVADD2; - break; - - case USB_HOST_DEVICE_3: - ptr = (uint16_t *)&USB200.DEVADD3; - break; - - case USB_HOST_DEVICE_4: - ptr = (uint16_t *)&USB200.DEVADD4; - break; - - case USB_HOST_DEVICE_5: - ptr = (uint16_t *)&USB200.DEVADD5; - break; - - case USB_HOST_DEVICE_6: - ptr = (uint16_t *)&USB200.DEVADD6; - break; - - case USB_HOST_DEVICE_7: - ptr = (uint16_t *)&USB200.DEVADD7; - break; - - case USB_HOST_DEVICE_8: - ptr = (uint16_t *)&USB200.DEVADD8; - break; - - case USB_HOST_DEVICE_9: - ptr = (uint16_t *)&USB200.DEVADD9; - break; - - case USB_HOST_DEVICE_10: - ptr = (uint16_t *)&USB200.DEVADDA; - break; - - default: - ret_flag = DEVDRV_FLAG_OFF; - break; - } - - if (ret_flag == DEVDRV_FLAG_ON) - { - *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK); - } -} - -/******************************************************************************* -* Function Name: usb0_host_get_devadd -* Description : DEVADDn register is obtained -* Arguments : uint16_t addr : Device address -* : uint16_t *devadd : USB_HOST_DEVADD register value -* Return Value : none -*******************************************************************************/ -void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd) -{ - uint16_t * ptr; - uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. - - switch (addr) - { - case USB_HOST_DEVICE_0: - ptr = (uint16_t *)&USB200.DEVADD0; - break; - - case USB_HOST_DEVICE_1: - ptr = (uint16_t *)&USB200.DEVADD1; - break; - - case USB_HOST_DEVICE_2: - ptr = (uint16_t *)&USB200.DEVADD2; - break; - - case USB_HOST_DEVICE_3: - ptr = (uint16_t *)&USB200.DEVADD3; - break; - - case USB_HOST_DEVICE_4: - ptr = (uint16_t *)&USB200.DEVADD4; - break; - - case USB_HOST_DEVICE_5: - ptr = (uint16_t *)&USB200.DEVADD5; - break; - - case USB_HOST_DEVICE_6: - ptr = (uint16_t *)&USB200.DEVADD6; - break; - - case USB_HOST_DEVICE_7: - ptr = (uint16_t *)&USB200.DEVADD7; - break; - - case USB_HOST_DEVICE_8: - ptr = (uint16_t *)&USB200.DEVADD8; - break; - - case USB_HOST_DEVICE_9: - ptr = (uint16_t *)&USB200.DEVADD9; - break; - - case USB_HOST_DEVICE_10: - ptr = (uint16_t *)&USB200.DEVADDA; - break; - - default: - ret_flag = DEVDRV_FLAG_OFF; - break; - } - - if (ret_flag == DEVDRV_FLAG_ON) - { - *devadd = *ptr; - } -} - -/******************************************************************************* -* Function Name: usb0_host_EnableINT_Module -* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt. -* : Enables NRDY/BEMP interrupt in the pipe0. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_host_EnableINT_Module (void) -{ - uint16_t buf; - - buf = USB200.INTENB0; - buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE); - USB200.INTENB0 = buf; - - buf = USB200.INTENB1; - buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE); - USB200.INTENB1 = buf; - - usb0_host_enable_nrdy_int(USB_HOST_PIPE0); - usb0_host_enable_bemp_int(USB_HOST_PIPE0); -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c deleted file mode 100644 index 8f081a618f..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c +++ /dev/null @@ -1,698 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_dmacdrv.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "r_typedefs.h" -#include "iodefine.h" -#include "rza_io_regrw.h" -#include "usb0_host_dmacdrv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ - -/* ==== Request setting information for on-chip peripheral module ==== */ -typedef enum dmac_peri_req_reg_type -{ - DMAC_REQ_MID, - DMAC_REQ_RID, - DMAC_REQ_AM, - DMAC_REQ_LVL, - DMAC_REQ_REQD -} dmac_peri_req_reg_type_t; - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -/* ==== Prototype declaration ==== */ - -/* ==== Global variable ==== */ -/* On-chip peripheral module request setting table */ -static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] = -{ - /* MID,RID, AM,LVL,REQD */ - { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ - { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ - { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ - { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ - { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ - { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ - { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ - { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ -}; - - -/******************************************************************************* -* Function Name: usb0_host_DMAC1_PeriReqInit -* Description : Sets the register mode for DMA mode and the on-chip peripheral -* : module request for transfer request for DMAC channel 1. -* : Executes DMAC initial setting using the DMA information -* : specified by the argument *trans_info and the enabled/disabled -* : continuous transfer specified by the argument continuation. -* : Registers DMAC channel 1 interrupt handler function and sets -* : the interrupt priority level. Then enables transfer completion -* : interrupt. -* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC -* : : register -* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) -* : uint32_t continuation : Set continuous transfer to be valid -* : : after DMA transfer has been completed -* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer -* : DMAC_SAMPLE_SINGLE : Do not execute continuous -* : : transfer -* : uint32_t request_factor : Factor for on-chip peripheral module -* : : request -* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match -* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match -* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match -* : : -* : uint32_t req_direction : Setting value of CHCFG_n register -* : : REQD bit -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction) -{ - /* ==== Register mode ==== */ - if (DMAC_MODE_REGISTER == dmamode) - { - /* ==== Next0 register set ==== */ - DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ - DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ - DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */ - - /* DAD : Transfer destination address counting direction */ - /* SAD : Transfer source address counting direction */ - /* DDS : Transfer destination transfer size */ - /* SDS : Transfer source transfer size */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->daddr_dir, - DMAC1_CHCFG_n_DAD_SHIFT, - DMAC1_CHCFG_n_DAD); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->saddr_dir, - DMAC1_CHCFG_n_SAD_SHIFT, - DMAC1_CHCFG_n_SAD); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->dst_size, - DMAC1_CHCFG_n_DDS_SHIFT, - DMAC1_CHCFG_n_DDS); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->src_size, - DMAC1_CHCFG_n_SDS_SHIFT, - DMAC1_CHCFG_n_SDS); - - /* DMS : Register mode */ - /* RSEL : Select Next0 register set */ - /* SBE : No discharge of buffer data when aborted */ - /* DEM : No DMA interrupt mask */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_DMS_SHIFT, - DMAC1_CHCFG_n_DMS); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_RSEL_SHIFT, - DMAC1_CHCFG_n_RSEL); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_SBE_SHIFT, - DMAC1_CHCFG_n_SBE); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_DEM_SHIFT, - DMAC1_CHCFG_n_DEM); - - /* ---- Continuous transfer ---- */ - if (DMAC_SAMPLE_CONTINUATION == continuation) - { - /* REN : Execute continuous transfer */ - /* RSW : Change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_REN_SHIFT, - DMAC1_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_RSW_SHIFT, - DMAC1_CHCFG_n_RSW); - } - /* ---- Single transfer ---- */ - else - { - /* REN : Do not execute continuous transfer */ - /* RSW : Do not change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_REN_SHIFT, - DMAC1_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_RSW_SHIFT, - DMAC1_CHCFG_n_RSW); - } - - /* TM : Single transfer */ - /* SEL : Channel setting */ - /* HIEN, LOEN : On-chip peripheral module request */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_TM_SHIFT, - DMAC1_CHCFG_n_TM); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_SEL_SHIFT, - DMAC1_CHCFG_n_SEL); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_HIEN_SHIFT, - DMAC1_CHCFG_n_HIEN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_LOEN_SHIFT, - DMAC1_CHCFG_n_LOEN); - - /* ---- Set factor by specified on-chip peripheral module request ---- */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], - DMAC1_CHCFG_n_AM_SHIFT, - DMAC1_CHCFG_n_AM); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], - DMAC1_CHCFG_n_LVL_SHIFT, - DMAC1_CHCFG_n_LVL); - if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) - { - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], - DMAC1_CHCFG_n_REQD_SHIFT, - DMAC1_CHCFG_n_REQD); - } - else - { - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - req_direction, - DMAC1_CHCFG_n_REQD_SHIFT, - DMAC1_CHCFG_n_REQD); - } - RZA_IO_RegWrite_32(&DMAC01.DMARS, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], - DMAC01_DMARS_CH1_RID_SHIFT, - DMAC01_DMARS_CH1_RID); - RZA_IO_RegWrite_32(&DMAC01.DMARS, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], - DMAC01_DMARS_CH1_MID_SHIFT, - DMAC01_DMARS_CH1_MID); - - /* PR : Round robin mode */ - RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, - 1, - DMAC07_DCTRL_0_7_PR_SHIFT, - DMAC07_DCTRL_0_7_PR); - } -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC1_Open -* Description : Enables DMAC channel 1 transfer. -* Arguments : uint32_t req : DMAC request mode -* Return Value : 0 : Succeeded in enabling DMA transfer -* : -1 : Failed to enable DMA transfer (due to DMA operation) -*******************************************************************************/ -int32_t usb0_host_DMAC1_Open (uint32_t req) -{ - int32_t ret; - volatile uint8_t dummy; - - /* Transferable? */ - if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_EN_SHIFT, - DMAC1_CHSTAT_n_EN)) && - (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_TACT_SHIFT, - DMAC1_CHSTAT_n_TACT))) - { - /* Clear Channel Status Register */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_SWRST_SHIFT, - DMAC1_CHCTRL_n_SWRST); - dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n, - DMAC1_CHCTRL_n_SWRST_SHIFT, - DMAC1_CHCTRL_n_SWRST); - /* Enable DMA transfer */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_SETEN_SHIFT, - DMAC1_CHCTRL_n_SETEN); - - /* ---- Request by software ---- */ - if (DMAC_REQ_MODE_SOFT == req) - { - /* DMA transfer Request by software */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_STG_SHIFT, - DMAC1_CHCTRL_n_STG); - } - - ret = 0; - } - else - { - ret = -1; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC1_Close -* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer -* : byte count at the time of DMA transfer abort to the argument -* : *remain. -* Arguments : uint32_t * remain : Remaining transfer byte count when -* : : DMA transfer is aborted -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC1_Close (uint32_t * remain) -{ - - /* ==== Abort transfer ==== */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_CLREN_SHIFT, - DMAC1_CHCTRL_n_CLREN); - - while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_TACT_SHIFT, - DMAC1_CHSTAT_n_TACT)) - { - /* Loop until transfer is aborted */ - } - - while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_EN_SHIFT, - DMAC1_CHSTAT_n_EN)) - { - /* Loop until 0 is set in EN before checking the remaining transfer byte count */ - } - /* ==== Obtain remaining transfer byte count ==== */ - *remain = DMAC1.CRTB_n; -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC1_Load_Set -* Description : Sets the transfer source address, transfer destination -* : address, and total transfer byte count respectively -* : specified by the argument src_addr, dst_addr, and count to -* : DMAC channel 1 as DMA transfer information. -* : Sets the register set selected by the CHCFG_n register -* : RSEL bit from the Next0 or Next1 register set. -* : This function should be called when DMA transfer of DMAC -* : channel 1 is aboted. -* Arguments : uint32_t src_addr : Transfer source address -* : uint32_t dst_addr : Transfer destination address -* : uint32_t count : Total transfer byte count -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) -{ - uint8_t reg_set; - - /* Obtain register set in use */ - reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_SR_SHIFT, - DMAC1_CHSTAT_n_SR); - - /* ==== Load ==== */ - if (0 == reg_set) - { - /* ---- Next0 Register Set ---- */ - DMAC1.N0SA_n = src_addr; /* Start address of transfer source */ - DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */ - DMAC1.N0TB_n = count; /* Total transfer byte count */ - } - else - { - /* ---- Next1 Register Set ---- */ - DMAC1.N1SA_n = src_addr; /* Start address of transfer source */ - DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */ - DMAC1.N1TB_n = count; /* Total transfer byte count */ - } -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC2_PeriReqInit -* Description : Sets the register mode for DMA mode and the on-chip peripheral -* : module request for transfer request for DMAC channel 2. -* : Executes DMAC initial setting using the DMA information -* : specified by the argument *trans_info and the enabled/disabled -* : continuous transfer specified by the argument continuation. -* : Registers DMAC channel 2 interrupt handler function and sets -* : the interrupt priority level. Then enables transfer completion -* : interrupt. -* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC -* : : register -* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) -* : uint32_t continuation : Set continuous transfer to be valid -* : : after DMA transfer has been completed -* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer -* : DMAC_SAMPLE_SINGLE : Do not execute continuous -* : : transfer -* : uint32_t request_factor : Factor for on-chip peripheral module -* : : request -* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match -* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match -* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match -* : : -* : uint32_t req_direction : Setting value of CHCFG_n register -* : : REQD bit -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction) -{ - /* ==== Register mode ==== */ - if (DMAC_MODE_REGISTER == dmamode) - { - /* ==== Next0 register set ==== */ - DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ - DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ - DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */ - - /* DAD : Transfer destination address counting direction */ - /* SAD : Transfer source address counting direction */ - /* DDS : Transfer destination transfer size */ - /* SDS : Transfer source transfer size */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->daddr_dir, - DMAC2_CHCFG_n_DAD_SHIFT, - DMAC2_CHCFG_n_DAD); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->saddr_dir, - DMAC2_CHCFG_n_SAD_SHIFT, - DMAC2_CHCFG_n_SAD); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->dst_size, - DMAC2_CHCFG_n_DDS_SHIFT, - DMAC2_CHCFG_n_DDS); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->src_size, - DMAC2_CHCFG_n_SDS_SHIFT, - DMAC2_CHCFG_n_SDS); - - /* DMS : Register mode */ - /* RSEL : Select Next0 register set */ - /* SBE : No discharge of buffer data when aborted */ - /* DEM : No DMA interrupt mask */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_DMS_SHIFT, - DMAC2_CHCFG_n_DMS); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_RSEL_SHIFT, - DMAC2_CHCFG_n_RSEL); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_SBE_SHIFT, - DMAC2_CHCFG_n_SBE); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_DEM_SHIFT, - DMAC2_CHCFG_n_DEM); - - /* ---- Continuous transfer ---- */ - if (DMAC_SAMPLE_CONTINUATION == continuation) - { - /* REN : Execute continuous transfer */ - /* RSW : Change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_REN_SHIFT, - DMAC2_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_RSW_SHIFT, - DMAC2_CHCFG_n_RSW); - } - /* ---- Single transfer ---- */ - else - { - /* REN : Do not execute continuous transfer */ - /* RSW : Do not change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_REN_SHIFT, - DMAC2_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_RSW_SHIFT, - DMAC2_CHCFG_n_RSW); - } - - /* TM : Single transfer */ - /* SEL : Channel setting */ - /* HIEN, LOEN : On-chip peripheral module request */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_TM_SHIFT, - DMAC2_CHCFG_n_TM); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 2, - DMAC2_CHCFG_n_SEL_SHIFT, - DMAC2_CHCFG_n_SEL); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_HIEN_SHIFT, - DMAC2_CHCFG_n_HIEN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_LOEN_SHIFT, - DMAC2_CHCFG_n_LOEN); - - /* ---- Set factor by specified on-chip peripheral module request ---- */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], - DMAC2_CHCFG_n_AM_SHIFT, - DMAC2_CHCFG_n_AM); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], - DMAC2_CHCFG_n_LVL_SHIFT, - DMAC2_CHCFG_n_LVL); - if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) - { - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], - DMAC2_CHCFG_n_REQD_SHIFT, - DMAC2_CHCFG_n_REQD); - } - else - { - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - req_direction, - DMAC2_CHCFG_n_REQD_SHIFT, - DMAC2_CHCFG_n_REQD); - } - RZA_IO_RegWrite_32(&DMAC23.DMARS, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], - DMAC23_DMARS_CH2_RID_SHIFT, - DMAC23_DMARS_CH2_RID); - RZA_IO_RegWrite_32(&DMAC23.DMARS, - usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], - DMAC23_DMARS_CH2_MID_SHIFT, - DMAC23_DMARS_CH2_MID); - - /* PR : Round robin mode */ - RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, - 1, - DMAC07_DCTRL_0_7_PR_SHIFT, - DMAC07_DCTRL_0_7_PR); - } -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC2_Open -* Description : Enables DMAC channel 2 transfer. -* Arguments : uint32_t req : DMAC request mode -* Return Value : 0 : Succeeded in enabling DMA transfer -* : -1 : Failed to enable DMA transfer (due to DMA operation) -*******************************************************************************/ -int32_t usb0_host_DMAC2_Open (uint32_t req) -{ - int32_t ret; - volatile uint8_t dummy; - - /* Transferable? */ - if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_EN_SHIFT, - DMAC2_CHSTAT_n_EN)) && - (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_TACT_SHIFT, - DMAC2_CHSTAT_n_TACT))) - { - /* Clear Channel Status Register */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_SWRST_SHIFT, - DMAC2_CHCTRL_n_SWRST); - dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n, - DMAC2_CHCTRL_n_SWRST_SHIFT, - DMAC2_CHCTRL_n_SWRST); - /* Enable DMA transfer */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_SETEN_SHIFT, - DMAC2_CHCTRL_n_SETEN); - - /* ---- Request by software ---- */ - if (DMAC_REQ_MODE_SOFT == req) - { - /* DMA transfer Request by software */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_STG_SHIFT, - DMAC2_CHCTRL_n_STG); - } - - ret = 0; - } - else - { - ret = -1; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC2_Close -* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer -* : byte count at the time of DMA transfer abort to the argument -* : *remain. -* Arguments : uint32_t * remain : Remaining transfer byte count when -* : : DMA transfer is aborted -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC2_Close (uint32_t * remain) -{ - - /* ==== Abort transfer ==== */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_CLREN_SHIFT, - DMAC2_CHCTRL_n_CLREN); - - while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_TACT_SHIFT, - DMAC2_CHSTAT_n_TACT)) - { - /* Loop until transfer is aborted */ - } - - while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_EN_SHIFT, - DMAC2_CHSTAT_n_EN)) - { - /* Loop until 0 is set in EN before checking the remaining transfer byte count */ - } - /* ==== Obtain remaining transfer byte count ==== */ - *remain = DMAC2.CRTB_n; -} - -/******************************************************************************* -* Function Name: usb0_host_DMAC2_Load_Set -* Description : Sets the transfer source address, transfer destination -* : address, and total transfer byte count respectively -* : specified by the argument src_addr, dst_addr, and count to -* : DMAC channel 2 as DMA transfer information. -* : Sets the register set selected by the CHCFG_n register -* : RSEL bit from the Next0 or Next1 register set. -* : This function should be called when DMA transfer of DMAC -* : channel 2 is aboted. -* Arguments : uint32_t src_addr : Transfer source address -* : uint32_t dst_addr : Transfer destination address -* : uint32_t count : Total transfer byte count -* Return Value : none -*******************************************************************************/ -void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) -{ - uint8_t reg_set; - - /* Obtain register set in use */ - reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_SR_SHIFT, - DMAC2_CHSTAT_n_SR); - - /* ==== Load ==== */ - if (0 == reg_set) - { - /* ---- Next0 Register Set ---- */ - DMAC2.N0SA_n = src_addr; /* Start address of transfer source */ - DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */ - DMAC2.N0TB_n = count; /* Total transfer byte count */ - } - else - { - /* ---- Next1 Register Set ---- */ - DMAC2.N1SA_n = src_addr; /* Start address of transfer source */ - DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */ - DMAC2.N1TB_n = count; /* Total transfer byte count */ - } -} - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c deleted file mode 100644 index b69b0b2783..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c +++ /dev/null @@ -1,156 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "devdrv_usb_host_api.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/********************************************************************************************************/ -/* Endpoint Configuration Data Format */ -/********************************************************************************************************/ -/* LINE1: Pipe Window Select Register */ -/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */ -/* LINE2: Pipe Configuration Register */ -/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ -/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ -/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* LINE3: Pipe Buffer Configuration Register */ -/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */ -/* [ ### SET ### ] */ -/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */ -/* LINE4: Pipe Maxpacket Size Register */ -/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* LINE5: Pipe Cycle Configuration Register (0x6C) */ -/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* LINE6: use FIFO port */ -/* : USB_HOST_CUSE [ ### SET ### ] */ -/* : USB_HOST_D0USE / USB_HOST_D1USE */ -/* : USB_HOST_D0DMA / USB_HOST_D0DMA */ -/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */ -/********************************************************************************************************/ - -/* Device Address 1 */ -USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[ ] = -{ - { - USB_HOST_PIPE1, - /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8), - USB_HOST_NONE, - USB_HOST_NONE, - USB_HOST_D0USE - }, - - { - /* Pipe end */ - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF - } -}; - -USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[ ] = -{ - { - USB_HOST_PIPE6, - /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40), - USB_HOST_NONE, - USB_HOST_NONE, - USB_HOST_D1USE - }, - - { - USB_HOST_PIPE7, - /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41), - USB_HOST_NONE, - USB_HOST_NONE, - USB_HOST_D1USE - }, - - { - USB_HOST_PIPE8, - /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42), - USB_HOST_NONE, - USB_HOST_NONE, - USB_HOST_D1USE - }, - - { - USB_HOST_PIPE9, - /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43), - USB_HOST_NONE, - USB_HOST_NONE, - USB_HOST_D1USE - }, - - { - /* Pipe end */ - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF, - 0xFFFF - } -}; - -/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c deleted file mode 100644 index a1271cb0f3..0000000000 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c +++ /dev/null @@ -1,770 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_host_userdef.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include "cmsis_os.h" -#include "r_typedefs.h" -#include "iodefine.h" -#include "devdrv_usb_host_api.h" -#include "usb0_host.h" -#include "MBRZA1H.h" /* INTC Driver Header */ -#include "usb0_host_dmacdrv.h" -#include "ohci_wrapp_RZ_A1_local.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define DUMMY_ACCESS OSTM0CNT - -/* #define CACHE_WRITEBACK */ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -extern int32_t io_cwb(unsigned long start, unsigned long end); - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); -static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); -static void Userdef_USB_usb0_host_delay_10us_2(void); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid -* Description : get D0FIFO DMA Interrupt ID -* Arguments : none -* Return Value : D0FIFO DMA Interrupt ID -*******************************************************************************/ -uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void) -{ - return DMAINT1_IRQn; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid -* Description : get D1FIFO DMA Interrupt ID -* Arguments : none -* Return Value : D1FIFO DMA Interrupt ID -*******************************************************************************/ -uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void) -{ - return DMAINT2_IRQn; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_attach -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_attach (void) -{ -// printf("\n"); -// printf("channel 0 attach device\n"); -// printf("\n"); - ohciwrapp_loc_Connect(1); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_detach -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_detach (void) -{ -// printf("\n"); -// printf("channel 0 detach device\n"); -// printf("\n"); - ohciwrapp_loc_Connect(0); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_delay_1ms -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_delay_1ms (void) -{ - osDelay(1); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_delay_xms -* Description : Wait for the software in the period of time specified by the -* : argument. -* : Alter this function according to the user's system. -* Arguments : uint32_t msec ; Wait Time (msec) -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_delay_xms (uint32_t msec) -{ - osDelay(msec); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_delay_10us -* Description : Waits for software for the period specified by the argument. -* : Alter this function according to the user's system. -* Arguments : uint32_t usec ; Wait Time(x 10usec) -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_delay_10us (uint32_t usec) -{ - volatile int i; - - /* Wait 10us (Please change for your MCU) */ - for (i = 0; i < usec; ++i) - { - Userdef_USB_usb0_host_delay_10us_2(); - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_delay_10us_2 -* Description : Waits for software for the period specified by the argument. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -static void Userdef_USB_usb0_host_delay_10us_2 (void) -{ - volatile int i; - volatile unsigned long tmp; - - /* Wait 1us (Please change for your MCU) */ - for (i = 0; i < 14; ++i) - { - tmp = DUMMY_ACCESS; - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_delay_500ns -* Description : Wait for software for 500ns. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_delay_500ns (void) -{ - volatile int i; - volatile unsigned long tmp; - - /* Wait 500ns (Please change for your MCU) */ - /* Wait 500ns I clock 266MHz */ - tmp = DUMMY_ACCESS; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_start_dma -* Description : Enables DMA transfer on the information specified by the argument. -* : Set DMAC register by this function to enable DMA transfer. -* : After executing this function, USB module is set to start DMA -* : transfer. DMA transfer should not wait for DMA transfer complete. -* Arguments : USB_HOST_DMA_t *dma : DMA parameter -* : typedef struct{ -* : uint32_t fifo; FIFO for using -* : uint32_t buffer; Start address of transfer source/destination -* : uint32_t bytes; Transfer size(Byte) -* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) -* : uint32_t size; DMA transfer size -* : } USB_HOST_DMA_t; -* : uint16_t dfacc ; 0 : cycle steal mode -* : 1 : 16byte continuous mode -* : 2 : 32byte continuous mode -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc) -{ - uint32_t trncount; - uint32_t src; - uint32_t dst; - uint32_t size; - uint32_t dir; -#ifdef CACHE_WRITEBACK - uint32_t ptr; -#endif - - trncount = dma->bytes; - dir = dma->dir; - - if (dir == USB_HOST_FIFO2BUF) - { - /* DxFIFO determination */ - dst = dma->buffer; -#ifndef __USB_HOST_DF_ACC_ENABLE__ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - size = dma->size; - - if (size == 0) - { - src += 3; /* byte access */ - } - else if (size == 1) - { - src += 2; /* short access */ - } - else - { - /* Do Nothing */ - } -#else - size = dma->size; - - if (size == 2) - { - /* 32bit access */ - if (dfacc == 2) - { - /* 32byte access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - src = (uint32_t)(&USB200.D1FIFOB0); - } - } - else if (dfacc == 1) - { - /* 16byte access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - src = (uint32_t)(&USB200.D1FIFOB0); - } - } - else - { - /* normal access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - } - } - else if (size == 1) - { - /* 16bit access */ - dfacc = 0; /* force normal access */ - - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - src += 2; /* short access */ - } - else - { - /* 8bit access */ - dfacc = 0; /* force normal access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - src += 3; /* byte access */ - } -#endif - } - else - { - /* DxFIFO determination */ - src = dma->buffer; -#ifndef __USB_HOST_DF_ACC_ENABLE__ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - size = dma->size; - - if (size == 0) - { - dst += 3; /* byte access */ - } - else if (size == 1) - { - dst += 2; /* short access */ - } - else - { - /* Do Nothing */ - } -#else - size = dma->size; - if (size == 2) - { - /* 32bit access */ - if (dfacc == 2) - { - /* 32byte access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - dst = (uint32_t)(&USB200.D1FIFOB0); - } - } - else if (dfacc == 1) - { - /* 16byte access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - dst = (uint32_t)(&USB200.D1FIFOB0); - } - } - else - { - /* normal access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - } - } - else if (size == 1) - { - /* 16bit access */ - dfacc = 0; /* force normal access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - dst += 2; /* short access */ - } - else - { - /* 8bit access */ - dfacc = 0; /* force normal access */ - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - dst += 3; /* byte access */ - } -#endif - } - -#ifdef CACHE_WRITEBACK - ptr = (uint32_t)dma->buffer; - if ((ptr & 0x20000000ul) == 0) - { - io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount); - } -#endif - - if (dma->fifo == USB_HOST_D0FIFO_DMA) - { - usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); - } - else - { - usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); - } -} - -/******************************************************************************* -* Function Name: usb0_host_enable_dmac0 -* Description : Enables DMA transfer on the information specified by the argument. -* Arguments : uint32_t src : src address -* : uint32_t dst : dst address -* : uint32_t count : transfer byte -* : uint32_t size : transfer size -* : uint32_t dir : direction -* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) -* : uint16_t dfacc : 0 : normal access -* : : 1 : 16byte access -* : : 2 : 32byte access -* Return Value : none -*******************************************************************************/ -static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) -{ - dmac_transinfo_t trans_info; - uint32_t request_factor = 0; - int32_t ret; - - /* ==== Variable setting for DMAC initialization ==== */ - trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ - trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ - trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ -#ifndef __USB_HOST_DF_ACC_ENABLE__ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { -// printf("size error!!\n"); - } -#else - if (dfacc == 2) - { - /* 32byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ - } - else if (dfacc == 1) - { - /* 16byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ - } - else - { - /* normal access */ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { -// printf("size error!!\n"); - } - } -#endif - - if (dir == USB_HOST_FIFO2BUF) - { - request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ - trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ - } - else if (dir == USB_HOST_BUF2FIFO) - { - request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ - trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ - } - else - { - /* Do Nothing */ - } - - /* ==== DMAC initialization ==== */ - usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info, - DMAC_MODE_REGISTER, - DMAC_SAMPLE_SINGLE, - request_factor, - 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */ - - /* ==== DMAC startup ==== */ - ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI); - - if (ret != 0) - { -// printf("DMAC1 Open error!!\n"); - } - - return; -} - -/******************************************************************************* -* Function Name: usb0_host_enable_dmac1 -* Description : Enables DMA transfer on the information specified by the argument. -* Arguments : uint32_t src : src address -* : uint32_t dst : dst address -* : uint32_t count : transfer byte -* : uint32_t size : transfer size -* : uint32_t dir : direction -* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) -* : uint16_t dfacc : 0 : normal access -* : : 1 : 16byte access -* : : 2 : 32byte access -* Return Value : none -*******************************************************************************/ -static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) -{ - dmac_transinfo_t trans_info; - uint32_t request_factor = 0; - int32_t ret; - - /* ==== Variable setting for DMAC initialization ==== */ - trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ - trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ - trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ -#ifndef __USB_HOST_DF_ACC_ENABLE__ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { -// printf("size error!!\n"); - } -#else - if (dfacc == 2) - { - /* 32byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ - } - else if (dfacc == 1) - { - /* 16byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ - } - else - { - /* normal access */ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { -// printf("size error!!\n"); - } - } -#endif - - if (dir == USB_HOST_FIFO2BUF) - { - request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ - trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ - } - else if (dir == USB_HOST_BUF2FIFO) - { - request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ - trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ - } - else - { - /* Do Nothing */ - } - - /* ==== DMAC initialization ==== */ - usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info, - DMAC_MODE_REGISTER, - DMAC_SAMPLE_SINGLE, - request_factor, - 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */ - - /* ==== DMAC startup ==== */ - ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI); - - if (ret != 0) - { -// printf("DMAC2 Open error!!\n"); - } - - return; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_stop_dma0 -* Description : Disables DMA transfer. -* Arguments : none -* Return Value : uint32_t return Transfer Counter register(DMATCRn) value -* : regarding to the bus width. -* Notice : This function should be executed to DMAC executed at the time -* : of specification of D0_FIF0_DMA in dma->fifo. -*******************************************************************************/ -uint32_t Userdef_USB_usb0_host_stop_dma0 (void) -{ - uint32_t remain; - - /* ==== DMAC release ==== */ - usb0_host_DMAC1_Close(&remain); - - return remain; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_stop_dma1 -* Description : Disables DMA transfer. -* : This function should be executed to DMAC executed at the time -* : of specification of D1_FIF0_DMA in dma->fifo. -* Arguments : none -* Return Value : uint32_t return Transfer Counter register(DMATCRn) value -* : regarding to the bus width. -*******************************************************************************/ -uint32_t Userdef_USB_usb0_host_stop_dma1 (void) -{ - uint32_t remain; - - /* ==== DMAC release ==== */ - usb0_host_DMAC2_Close(&remain); - - return remain; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_notice -* Description : Notice of USER -* Arguments : const char *format -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_notice (const char * format) -{ -// printf(format); - - return; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_host_user_rdy -* Description : This function notify a user and wait for trigger -* Arguments : const char *format -* : uint16_t data -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data) -{ -// printf(format, data); - getchar(); - - return; -} - -/* End of File */ From 5b179989c36ebebf915611976c09932f67edc568 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:07:59 +0900 Subject: [PATCH 028/143] Delete some needless USBDevice files to add 2Port function. --- .../TARGET_RZ_A1H/inc/usb0_function.h | 171 - .../TARGET_RZ_A1H/inc/usb0_function_api.h | 104 - .../TARGET_RZ_A1H/inc/usb0_function_dmacdrv.h | 142 - .../src/common/usb0_function_dataio.c | 2933 ----------------- .../src/common/usb0_function_dma.c | 346 -- .../src/common/usb0_function_intrn.c | 249 -- .../src/common/usb0_function_lib.c | 2026 ------------ .../src/function/usb0_function_api.c | 441 --- .../src/function/usb0_function_controlrw.c | 142 - .../src/function/usb0_function_global.c | 144 - .../src/function/usb0_function_sig.c | 330 -- .../src/function/usb0_function_sub.c | 453 --- .../src/userdef/usb0_function_dmacdrv.c | 698 ---- .../src/userdef/usb0_function_userdef.c | 762 ----- 14 files changed, 8941 deletions(-) delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function.h delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_api.h delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_dmacdrv.h delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dataio.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dma.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_intrn.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_lib.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_api.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_controlrw.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_global.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sig.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sub.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_dmacdrv.c delete mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_userdef.c diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function.h deleted file mode 100644 index 02855eb13e..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function.h +++ /dev/null @@ -1,171 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_FUNCTION_H -#define USB0_FUNCTION_H - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "devdrv_usb_function_api.h" -#include "usb_function.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -extern const uint16_t g_usb0_function_bit_set[]; -extern uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; -extern uint8_t *g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; - -extern uint16_t g_usb0_function_PipeIgnore[]; -extern uint16_t g_usb0_function_PipeTbl[]; -extern uint16_t g_usb0_function_pipe_status[]; -extern uint32_t g_usb0_function_PipeDataSize[]; - -extern USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[]; -extern uint16_t g_usb0_function_DmaPipe[]; -extern uint16_t g_usb0_function_DmaBval[]; -extern uint16_t g_usb0_function_DmaStatus[]; - -extern uint16_t g_usb0_function_CtrZeroLengthFlag; - -extern uint16_t g_usb0_function_ConfigNum; -extern uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO]; -extern uint16_t g_usb0_function_RemoteWakeupFlag; -extern uint16_t g_usb0_function_TestModeFlag; -extern uint16_t g_usb0_function_TestModeSelectors; - -extern uint16_t g_usb0_function_ReqType; -extern uint16_t g_usb0_function_ReqTypeType; -extern uint16_t g_usb0_function_ReqTypeRecip; -extern uint16_t g_usb0_function_ReqRequest; -extern uint16_t g_usb0_function_ReqValue; -extern uint16_t g_usb0_function_ReqIndex; -extern uint16_t g_usb0_function_ReqLength; - -extern uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; - -extern uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; -extern uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -/* ==== common ==== */ -void usb0_function_dma_stop_d0(uint16_t pipe, uint32_t remain); -void usb0_function_dma_stop_d1(uint16_t pipe, uint32_t remain); -uint16_t usb0_function_is_hispeed(void); -uint16_t usb0_function_is_hispeed_enable(void); -uint16_t usb0_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -uint16_t usb0_function_write_buffer(uint16_t pipe); -uint16_t usb0_function_write_buffer_c(uint16_t pipe); -uint16_t usb0_function_write_buffer_d0(uint16_t pipe); -uint16_t usb0_function_write_buffer_d1(uint16_t pipe); -void usb0_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -uint16_t usb0_function_read_buffer(uint16_t pipe); -uint16_t usb0_function_read_buffer_c(uint16_t pipe); -uint16_t usb0_function_read_buffer_d0(uint16_t pipe); -uint16_t usb0_function_read_buffer_d1(uint16_t pipe); -uint16_t usb0_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); -void usb0_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); -void usb0_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); -uint16_t usb0_function_get_mbw(uint32_t trncount, uint32_t dtptr); -uint16_t usb0_function_read_dma(uint16_t pipe); -void usb0_function_brdy_int(uint16_t status, uint16_t int_enb); -void usb0_function_nrdy_int(uint16_t status, uint16_t int_enb); -void usb0_function_bemp_int(uint16_t status, uint16_t int_enb); -void usb0_function_setting_interrupt(uint8_t level); -void usb0_function_reset_module(uint16_t clockmode); -uint16_t usb0_function_get_buf_size(uint16_t pipe); -uint16_t usb0_function_get_mxps(uint16_t pipe); -void usb0_function_clear_brdy_sts(uint16_t pipe); -void usb0_function_clear_bemp_sts(uint16_t pipe); -void usb0_function_clear_nrdy_sts(uint16_t pipe); -void usb0_function_set_pid_buf(uint16_t pipe); -void usb0_function_set_pid_nak(uint16_t pipe); -void usb0_function_set_pid_stall(uint16_t pipe); -void usb0_function_clear_pid_stall(uint16_t pipe); -uint16_t usb0_function_get_pid(uint16_t pipe); -void usb0_function_set_sqclr(uint16_t pipe); -void usb0_function_set_sqset(uint16_t pipe); -void usb0_function_set_csclr(uint16_t pipe); -void usb0_function_aclrm(uint16_t pipe); -void usb0_function_set_aclrm(uint16_t pipe); -void usb0_function_clr_aclrm(uint16_t pipe); -uint16_t usb0_function_get_sqmon(uint16_t pipe); -uint16_t usb0_function_get_inbuf(uint16_t pipe); - -/* ==== function ==== */ -void usb0_function_init_status(void); -void usb0_function_InitModule(uint16_t mode); -uint16_t usb0_function_CheckVBUStaus(void); -void usb0_function_USB_FUNCTION_Attach(void); -void usb0_function_USB_FUNCTION_Detach(void); -void usb0_function_USB_FUNCTION_BusReset(void); -void usb0_function_USB_FUNCTION_Resume(void); -void usb0_function_USB_FUNCTION_Suspend(void); -void usb0_function_USB_FUNCTION_TestMode(void); -void usb0_function_ResetDCP(void); -void usb0_function_ResetEP(uint16_t num); -uint16_t usb0_function_EpToPipe(uint16_t ep); -void usb0_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num); -uint16_t usb0_function_GetConfigNum(void); -uint16_t usb0_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num); -uint16_t usb0_function_CheckRemoteWakeup(void); -void usb0_function_clear_alt(void); -void usb0_function_clear_pipe_tbl(void); -void usb0_function_clear_ep_table_index(void); -uint16_t usb0_function_GetInterfaceNum(uint16_t num); - -#ifdef __cplusplus -} -#endif - - -#endif /* USB0_FUNCTION_H */ - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_api.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_api.h deleted file mode 100644 index c33b3e63ea..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_api.h +++ /dev/null @@ -1,104 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_api.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_FUNCTION_API_H -#define USB0_FUNCTION_API_H - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Variable Externs -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void usb0_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); -uint16_t usb0_api_function_IsConfigured(void); -uint16_t usb0_function_GetDeviceState(void); -uint16_t usb0_api_function_CtrlReadStart(uint32_t size, uint8_t *data); -void usb0_api_function_CtrlWriteStart(uint32_t size, uint8_t *data); -uint16_t usb0_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -uint16_t usb0_api_function_check_pipe_status(uint16_t pipe, uint32_t *size); -void usb0_api_function_clear_pipe_status(uint16_t pipe); -void usb0_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); -void usb0_api_function_set_pid_buf(uint16_t pipe); -void usb0_api_function_set_pid_nak(uint16_t pipe); -void usb0_api_function_set_pid_stall(uint16_t pipe); -void usb0_api_function_clear_pid_stall(uint16_t pipe); -uint16_t usb0_api_function_get_pid(uint16_t pipe); -int32_t usb0_api_function_check_stall(uint16_t pipe); -void usb0_api_function_set_sqclr(uint16_t pipe); -void usb0_api_function_set_sqset(uint16_t pipe); -void usb0_api_function_set_csclr(uint16_t pipe); -void usb0_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); -void usb0_api_function_clear_brdy_sts(uint16_t pipe); -void usb0_api_function_clear_bemp_sts(uint16_t pipe); -void usb0_api_function_clear_nrdy_sts(uint16_t pipe); - -void usb0_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length); -void usb0_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length); - -#ifdef __cplusplus -} -#endif - -#endif /* USB0_FUNCTION_API_H */ - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_dmacdrv.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_dmacdrv.h deleted file mode 100644 index d74bac718c..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_function_dmacdrv.h +++ /dev/null @@ -1,142 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_dmacdrv.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : RZ/A1H R7S72100 USB Sample Program -*******************************************************************************/ -#ifndef USB0_FUNCTION_DMACDRV_H -#define USB0_FUNCTION_DMACDRV_H - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ -typedef struct dmac_transinfo -{ - uint32_t src_addr; /* Transfer source address */ - uint32_t dst_addr; /* Transfer destination address */ - uint32_t count; /* Transfer byte count */ - uint32_t src_size; /* Transfer source data size */ - uint32_t dst_size; /* Transfer destination data size */ - uint32_t saddr_dir; /* Transfer source address direction */ - uint32_t daddr_dir; /* Transfer destination address direction */ -} dmac_transinfo_t; - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -/* ==== Transfer specification of the sample program ==== */ -#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ -#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ - -/* ==== DMA modes ==== */ -#define DMAC_MODE_REGISTER (0) /* Register mode */ -#define DMAC_MODE_LINK (1) /* Link mode */ - -/* ==== Transfer requests ==== */ -#define DMAC_REQ_MODE_EXT (0) /* External request */ -#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ -#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ - -/* ==== DMAC transfer sizes ==== */ -#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ -#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ -#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ -#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ -#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ -#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ -#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ -#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ - -/* ==== Address increment for transferring ==== */ -#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ -#define DMAC_TRANS_ADR_INC (0) /* Increment */ - -/* ==== Method for detecting DMA request ==== */ -#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ -#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ -#define DMAC_REQ_DET_LOW (2) /* Low level detection */ -#define DMAC_REQ_DET_HIGH (3) /* High level detection */ - -/* ==== Request Direction ==== */ -#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ -#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ - -/* ==== Descriptors ==== */ -#define DMAC_DESC_HEADER (0) /* Header */ -#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ -#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ -#define DMAC_DESC_COUNT (3) /* Transaction Byte */ -#define DMAC_DESC_CHCFG (4) /* Channel Confg */ -#define DMAC_DESC_CHITVL (5) /* Channel Interval */ -#define DMAC_DESC_CHEXT (6) /* Channel Extension */ -#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ - -/* ==== On-chip peripheral module requests ===== */ -typedef enum dmac_request_factor -{ - DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ - DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ - DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ - DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ - DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ - DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ - DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ - DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ -} dmac_request_factor_t; - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void usb0_function_DMAC1_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction); -int32_t usb0_function_DMAC1_Open(uint32_t req); -void usb0_function_DMAC1_Close(uint32_t *remain); -void usb0_function_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); - -void usb0_function_DMAC2_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction); -int32_t usb0_function_DMAC2_Open(uint32_t req); -void usb0_function_DMAC2_Close(uint32_t *remain); -void usb0_function_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); - -#ifdef __cplusplus -} -#endif - -#endif /* USB0_FUNCTION_DMACDRV_H */ - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dataio.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dataio.c deleted file mode 100644 index 2f283c7389..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dataio.c +++ /dev/null @@ -1,2933 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_dataio.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -static uint16_t g_usb0_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)]; - -static void usb0_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); -static void usb0_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); -static uint16_t usb0_function_read_dma_d0(uint16_t pipe); -static uint16_t usb0_function_read_dma_d1(uint16_t pipe); -static uint16_t usb0_function_write_dma_d0(uint16_t pipe); -static uint16_t usb0_function_write_dma_d1(uint16_t pipe); - -static void usb0_function_read_c_fifo(uint16_t pipe, uint16_t count); -static void usb0_function_write_c_fifo(uint16_t Pipe, uint16_t count); -static void usb0_function_read_d0_fifo(uint16_t pipe, uint16_t count); -static void usb0_function_write_d0_fifo(uint16_t pipe, uint16_t count); -static void usb0_function_read_d1_fifo(uint16_t pipe, uint16_t count); -static void usb0_function_write_d1_fifo(uint16_t pipe, uint16_t count); - -static void usb0_function_clear_transaction_counter(uint16_t pipe); -static void usb0_function_set_transaction_counter(uint16_t pipe, uint32_t count); - -static uint32_t usb0_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr); - -static uint16_t usb0_function_set_dfacc_d0(uint16_t mbw, uint32_t count); -static uint16_t usb0_function_set_dfacc_d1(uint16_t mbw, uint32_t count); - - -/******************************************************************************* -* Function Name: usb0_function_start_send_transfer -* Description : Starts the USB data communication using pipe specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t status; - uint16_t usefifo; - uint16_t mbw; - - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - usb0_function_clear_bemp_sts(pipe); - usb0_function_clear_brdy_sts(pipe); - usb0_function_clear_nrdy_sts(pipe); - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - - usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - - switch (usefifo) - { - case USB_FUNCTION_D0FIFO_USE: - case USB_FUNCTION_D0FIFO_DMA: - usefifo = USB_FUNCTION_D0USE; - break; - - case USB_FUNCTION_D1FIFO_USE: - case USB_FUNCTION_D1FIFO_DMA: - usefifo = USB_FUNCTION_D1USE; - break; - - default: - usefifo = USB_FUNCTION_CUSE; - break; - }; - - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw); - - usb0_function_clear_transaction_counter(pipe); - - usb0_function_aclrm(pipe); - - status = usb0_function_write_buffer(pipe); - - if (status != DEVDRV_USBF_FIFOERROR) - { - usb0_function_set_pid_buf(pipe); - } - - return status; -} - -/******************************************************************************* -* Function Name: usb0_function_write_buffer -* Description : Writes data in the buffer allocated in the pipe specified by -* : the argument. The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_write_buffer (uint16_t pipe) -{ - uint16_t status; - uint16_t usefifo; - - g_usb0_function_PipeIgnore[pipe] = 0; - usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - - switch (usefifo) - { - case USB_FUNCTION_D0FIFO_USE: - status = usb0_function_write_buffer_d0(pipe); - break; - - case USB_FUNCTION_D1FIFO_USE: - status = usb0_function_write_buffer_d1(pipe); - break; - - case USB_FUNCTION_D0FIFO_DMA: - status = usb0_function_write_dma_d0(pipe); - break; - - case USB_FUNCTION_D1FIFO_DMA: - status = usb0_function_write_dma_d1(pipe); - break; - - default: - status = usb0_function_write_buffer_c(pipe); - break; - }; - - switch (status) - { - case DEVDRV_USBF_WRITING: /* Continue of data write */ - usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - usb0_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */ - break; - - case DEVDRV_USBF_WRITEEND: /* End of data write */ - case DEVDRV_USBF_WRITESHRT: /* End of data write */ - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - usb0_function_clear_nrdy_sts(pipe); - usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - /* for last transfer */ - usb0_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */ - break; - - case DEVDRV_USBF_WRITEDMA: /* DMA write */ - usb0_function_clear_nrdy_sts(pipe); - usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ - break; - - case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ - default: - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - usb0_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_write_buffer_c -* Description : Writes data in the buffer allocated in the pipe specified in -* : the argument. Writes data by CPU transfer using CFIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_write_buffer_c (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - if (g_usb0_function_CtrZeroLengthFlag == 1) - { - g_usb0_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */ - return DEVDRV_USBF_WRITEEND; - } - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - if (pipe == USB_FUNCTION_PIPE0) - { - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); - } - else - { - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); - } - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] <= (uint32_t)size) - { - status = DEVDRV_USBF_WRITEEND; /* write continues */ - count = g_usb0_function_data_count[pipe]; - - if (count == 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = DEVDRV_USBF_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_function_write_c_fifo(pipe, (uint16_t)count); - - if (g_usb0_function_data_count[pipe] < (uint32_t)size) - { - g_usb0_function_data_count[pipe] = 0; - - if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0) - { - USB200.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ - g_usb0_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */ - } - } - else - { - g_usb0_function_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_write_buffer_d0 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by CPU transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_write_buffer_d0 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] <= (uint32_t)size) - { - status = DEVDRV_USBF_WRITEEND; /* write continues */ - count = g_usb0_function_data_count[pipe]; - - if (count == 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = DEVDRV_USBF_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_function_write_d0_fifo(pipe, (uint16_t)count); - - if (g_usb0_function_data_count[pipe] < (uint32_t)size) - { - g_usb0_function_data_count[pipe] = 0; - if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ - } - } - else - { - g_usb0_function_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_write_buffer_d1 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by CPU transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_write_buffer_d1 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] <= (uint32_t)size) - { - status = DEVDRV_USBF_WRITEEND; /* write continues */ - count = g_usb0_function_data_count[pipe]; - - if (count == 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ - } - - if ((count % mxps) != 0) - { - status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ - } - } - else - { - status = DEVDRV_USBF_WRITING; /* write continues */ - count = (uint32_t)size; - } - - usb0_function_write_d1_fifo(pipe, (uint16_t)count); - - if (g_usb0_function_data_count[pipe] < (uint32_t)size) - { - g_usb0_function_data_count[pipe] = 0; - - if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ - } - } - else - { - g_usb0_function_data_count[pipe] -= count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_write_dma_d0 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by DMA transfer using D0FIFO. -* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma(). -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND : Write end -* : DEVDRV_USBF_WRITESHRT : short data -* : DEVDRV_USBF_WRITING : Continue of data write -* : DEVDRV_USBF_WRITEDMA : Write DMA -* : DEVDRV_USBF_FIFOERROR : FIFO status -*******************************************************************************/ -static uint16_t usb0_function_write_dma_d0 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - count = g_usb0_function_data_count[pipe]; - - if (count != 0) - { - g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; - - if ((count % size) != 0) - { - g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 1; - } - else - { - g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; - } - - dfacc = usb0_function_set_dfacc_d0(mbw, count); - - if (mbw == USB_FUNCTION_BITMBW_32) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; - - Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); - - usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); - - g_usb0_function_data_count[pipe] = 0; - g_usb0_function_data_pointer[pipe] += count; - status = DEVDRV_USBF_WRITEDMA; /* DMA write */ - } - else - { - if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) - { - RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ - } - status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_write_dma_d1 -* Description : Writes data in the buffer allocated in the pipe specified in the argument. -* : Writes data by DMA transfer using D1FIFO. -* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma(). -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : DEVDRV_USBF_WRITEEND : Write end -* : DEVDRV_USBF_WRITESHRT : short data -* : DEVDRV_USBF_WRITING : Continue of data write -* : DEVDRV_USBF_WRITEDMA : Write DMA -* : DEVDRV_USBF_FIFOERROR : FIFO status -*******************************************************************************/ -static uint16_t usb0_function_write_dma_d1 (uint16_t pipe) -{ - uint32_t count; - uint16_t size; - uint16_t buffer; - uint16_t status; - uint16_t mbw; - uint16_t dfacc=0; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - count = g_usb0_function_data_count[pipe]; - - if (count != 0) - { - g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; - if ((count % size) != 0) - { - g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 1; - } - else - { - g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; - } - - dfacc = usb0_function_set_dfacc_d1(mbw, count); - - if (mbw == USB_FUNCTION_BITMBW_32) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; - - Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); - - usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); - - g_usb0_function_data_count[pipe] = 0; - g_usb0_function_data_pointer[pipe] += count; - - status = DEVDRV_USBF_WRITEDMA; /* DMA write */ - } - else - { - if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) - { - RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ - } - status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_transfer -* Description : Starts USB data reception using the pipe specified in the argument. -* : The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -void usb0_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t usefifo; - - usb0_function_clear_bemp_sts(pipe); - usb0_function_clear_brdy_sts(pipe); - usb0_function_clear_nrdy_sts(pipe); - - usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - - switch (usefifo) - { - case USB_FUNCTION_D0FIFO_USE: - usb0_function_start_receive_trns_d0(pipe, size, data); - break; - - case USB_FUNCTION_D1FIFO_USE: - usb0_function_start_receive_trns_d1(pipe, size, data); - break; - - case USB_FUNCTION_D0FIFO_DMA: - usb0_function_start_receive_dma_d0(pipe, size, data); - break; - - case USB_FUNCTION_D1FIFO_DMA: - usb0_function_start_receive_dma_d1(pipe, size, data); - break; - - default: - usb0_function_start_receive_trns_c(pipe, size, data); - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_trns_c -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using CFIFO. -* : When storing data in the buffer allocated in the pipe specified in the -* : argument, BRDY interrupt is generated to read data -* : in the interrupt. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(pipe); - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_PipeIgnore[pipe] = 0; - - g_usb0_function_PipeDataSize[pipe] = size; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw); - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; - - usb0_function_set_transaction_counter(pipe, size); - - usb0_function_aclrm(pipe); - - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_trns_d0 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, BRDY interrupt is generated to read data in the -* : interrupt. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(pipe); - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_PipeIgnore[pipe] = 0; - - g_usb0_function_PipeDataSize[pipe] = size; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); - - usb0_function_set_transaction_counter(pipe, size); - - usb0_function_aclrm(pipe); - - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_trns_d1 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using D1FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, BRDY interrupt is generated to read data. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(pipe); - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_PipeIgnore[pipe] = 0; - - g_usb0_function_PipeDataSize[pipe] = size; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); - - usb0_function_set_transaction_counter(pipe, size); - - usb0_function_aclrm(pipe); - - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_dma_d0 -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by DMA transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, delivered read request to DMAC to read data from -* : the buffer by DMAC. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(pipe); - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_PipeIgnore[pipe] = 0; - - g_usb0_function_PipeDataSize[pipe] = 0; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); - - usb0_function_set_transaction_counter(pipe, size); - - usb0_function_aclrm(pipe); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - usb0_function_read_dma(pipe); - - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - } - else - { - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - } - - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_start_receive_dma_d1 -* Description : Read data from the buffer allocated in the pipe specified in the argument. -* : Reads data by DMA transfer using D0FIFO. -* : This function does not read data from the buffer. -* : When storing data in the buffer allocated in the pipe specified -* : in the argument, delivered read request to DMAC to read data from -* : the buffer by DMAC. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -static void usb0_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(pipe); - g_usb0_function_data_count[pipe] = size; - g_usb0_function_data_pointer[pipe] = (uint8_t *)data; - g_usb0_function_PipeIgnore[pipe] = 0; - - g_usb0_function_PipeDataSize[pipe] = 0; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; - - mbw = usb0_function_get_mbw(size, (uint32_t)data); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); - - usb0_function_set_transaction_counter(pipe, size); - - usb0_function_aclrm(pipe); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - usb0_function_read_dma(pipe); - - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - } - else - { - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); - } - - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_read_buffer -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Uses FIF0 set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_read_buffer (uint16_t pipe) -{ - uint16_t status; - - g_usb0_function_PipeIgnore[pipe] = 0; - - if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) - { - status = usb0_function_read_buffer_d0(pipe); - } - else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) - { - status = usb0_function_read_buffer_d1(pipe); - } - else - { - status = usb0_function_read_buffer_c(pipe); - } - - switch (status) - { - case USB_FUNCTION_READING: /* Continue of data read */ - break; - - case USB_FUNCTION_READEND: /* End of data read */ - case USB_FUNCTION_READSHRT: /* End of data read */ - usb0_function_disable_brdy_int(pipe); - g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - break; - - case USB_FUNCTION_READOVER: /* buffer over */ - if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - else - { - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; - break; - - case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ - default: - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_buffer_c -* Description : Reads data from the buffer allocated in the pipe specified in the argument. -* : Reads data by CPU transfer using CFIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_read_buffer_c (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_FUNCTION_READOVER; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_function_data_count[pipe]; - } - else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_FUNCTION_READEND; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_FUNCTION_READING; - count = dtln; - - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_function_read_c_fifo(pipe, (uint16_t)count); - } - - g_usb0_function_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_buffer_d0 -* Description : Reads data from the buffer allocated in the pipe specified in -* : the argument. -* : Reads data by CPU transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_read_buffer_d0 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t pipebuf_size; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_FUNCTION_READOVER; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_function_data_count[pipe]; - } - else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_FUNCTION_READEND; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_FUNCTION_READING; - count = dtln; - - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - else - { - pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - - if (count != pipebuf_size) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_function_read_d0_fifo(pipe, (uint16_t)count); - } - - g_usb0_function_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_buffer_d1 -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by CPU transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_read_buffer_d1 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t pipebuf_size; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_FUNCTION_READOVER; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = g_usb0_function_data_count[pipe]; - } - else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_FUNCTION_READEND; - usb0_function_set_pid_nak(pipe); /* Set NAK */ - count = dtln; - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_FUNCTION_READING; - count = dtln; - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - else - { - pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - - if (count != pipebuf_size) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - usb0_function_set_pid_nak(pipe); /* Set NAK */ - } - } - } - - if (count == 0) /* 0 length packet */ - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - } - else - { - usb0_function_read_d1_fifo(pipe, (uint16_t)count); - } - - g_usb0_function_data_count[pipe] -= count; - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_dma -* Description : Reads data from the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by DMA transfer using D0FIFO or D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_function_read_dma (uint16_t pipe) -{ - uint16_t status; - - g_usb0_function_PipeIgnore[pipe] = 0; - if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) - { - status = usb0_function_read_dma_d0(pipe); - } - else - { - status = usb0_function_read_dma_d1(pipe); - } - - switch (status) - { - case USB_FUNCTION_READING: /* Continue of data read */ - break; - - case USB_FUNCTION_READZERO: /* End of data read */ - usb0_function_disable_brdy_int(pipe); - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - break; - - case USB_FUNCTION_READEND: /* End of data read */ - case USB_FUNCTION_READSHRT: /* End of data read */ - usb0_function_disable_brdy_int(pipe); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; - } - break; - - case USB_FUNCTION_READOVER: /* buffer over */ - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; - } - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; - break; - - case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ - default: - usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_dma_d0 -* Description : Writes data in the buffer allocated in the pipe specified -* : in the argument. -* : Reads data by DMA transfer using D0FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READZERO ; zero data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -static uint16_t usb0_function_read_dma_d0 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t dfacc = 0; - uint16_t pipebuf_size; - - g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - count = g_usb0_function_data_count[pipe]; - status = USB_FUNCTION_READING; - } - else - { - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); - - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_FUNCTION_READOVER; - count = g_usb0_function_data_count[pipe]; - } - else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_FUNCTION_READEND; - count = dtln; - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_FUNCTION_READING; - count = dtln; - - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - else - { - pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - if (count != pipebuf_size) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - } - } - - if (count == 0) /* 0 length packet */ - { - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - status = USB_FUNCTION_READZERO; /* Null Packet receive */ - } - else - { - usb0_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); - /* transaction counter No set */ - /* FRDY = 1, DTLN = 0 -> BRDY */ - } - } - else - { - dfacc = usb0_function_set_dfacc_d0(mbw, count); - - if (mbw == USB_FUNCTION_BITMBW_32) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */ - g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */ - - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; - g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; - - if (status == USB_FUNCTION_READING) - { - g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY; - } - else - { - g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND; - } - - Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); - - usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - g_usb0_function_data_count[pipe] -= count; - g_usb0_function_data_pointer[pipe] += count; - g_usb0_function_PipeDataSize[pipe] += count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_read_dma_d1 -* Description : Reads data from the buffer allocated in the pipe specified in -* : the argument. -* : Reads data by DMA transfer using D1FIFO. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : USB_FUNCTION_READEND ; Read end -* : USB_FUNCTION_READSHRT ; short data -* : USB_FUNCTION_READZERO ; zero data -* : USB_FUNCTION_READING ; Continue of data read -* : USB_FUNCTION_READOVER ; buffer over -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -static uint16_t usb0_function_read_dma_d1 (uint16_t pipe) -{ - uint32_t count; - uint32_t dtln; - uint16_t buffer; - uint16_t mxps; - uint16_t status; - uint16_t mbw; - uint16_t dfacc=0; - uint16_t pipebuf_size; - - g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - count = g_usb0_function_data_count[pipe]; - status = USB_FUNCTION_READING; - } - else - { - buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); - if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ - { - return DEVDRV_USBF_FIFOERROR; - } - - dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ - { - status = USB_FUNCTION_READOVER; - count = g_usb0_function_data_count[pipe]; - } - else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ - { - status = USB_FUNCTION_READEND; - count = dtln; - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - else /* continue Receive data */ - { - status = USB_FUNCTION_READING; - count = dtln; - if (count == 0) - { - status = USB_FUNCTION_READSHRT; /* Null Packet receive */ - } - - if ((count % mxps) != 0) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - else - { - pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ - if (count != pipebuf_size) - { - status = USB_FUNCTION_READSHRT; /* Short Packet receive */ - } - } - } - } - - if (count == 0) /* 0 length packet */ - { - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ - status = USB_FUNCTION_READZERO; /* Null Packet receive */ - } - else - { - usb0_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); - /* transaction counter No set */ - /* FRDY = 1, DTLN = 0 -> BRDY */ - } - } - else - { - dfacc = usb0_function_set_dfacc_d1(mbw, count); - - if (mbw == USB_FUNCTION_BITMBW_32) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ - } - else - { - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ - } - - g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */ - g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */ - - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; - g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; - - if (status == USB_FUNCTION_READING) - { - g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY; - } - else - { - g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND; - } - - Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); - - usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, - 1, - USB_DnFIFOSEL_DREQE_SHIFT, - USB_DnFIFOSEL_DREQE); - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - g_usb0_function_data_count[pipe] -= count; - g_usb0_function_data_pointer[pipe] += count; - g_usb0_function_PipeDataSize[pipe] += count; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_function_change_fifo_port -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument. After allocating FIF0, waits in the software -* : till the corresponding pipe becomes ready. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* Return Value : DEVDRV_USBF_FIFOERROR ; Error -* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value -*******************************************************************************/ -uint16_t usb0_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) -{ - uint16_t buffer; - uint32_t loop; - volatile uint32_t loop2; - - usb0_function_set_curpipe(pipe, fifosel, isel, mbw); - - for (loop = 0; loop < 4; loop++) - { - switch (fifosel) - { - case USB_FUNCTION_CUSE: - buffer = USB200.CFIFOCTR; - break; - - case USB_FUNCTION_D0USE: - case USB_FUNCTION_D0DMA: - buffer = USB200.D0FIFOCTR; - break; - - case USB_FUNCTION_D1USE: - case USB_FUNCTION_D1DMA: - buffer = USB200.D1FIFOCTR; - break; - - default: - buffer = 0; - break; - } - - if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY) - { - return buffer; - } - - loop2 = 25; - while (loop2-- > 0) - { - /* wait */ - } - } - - return DEVDRV_USBF_FIFOERROR; -} - -/******************************************************************************* -* Function Name: usb0_function_set_curpipe -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* Return Value : none -*******************************************************************************/ -void usb0_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) -{ - uint16_t buffer; - uint32_t loop; - volatile uint32_t loop2; - - g_usb0_function_mbw[pipe] = mbw; - - switch (fifosel) - { - case USB_FUNCTION_CUSE: - buffer = USB200.CFIFOSEL; - buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); - buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == - (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(isel | pipe | mbw); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == - (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_FUNCTION_D0DMA: - case USB_FUNCTION_D0USE: - buffer = USB200.D0FIFOSEL; - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == - (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == - (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_FUNCTION_D1DMA: - case USB_FUNCTION_D1USE: - buffer = USB200.D1FIFOSEL; - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == - (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == - (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - default: - break; - } - - /* Cautions !!! - * Depending on the external bus speed of CPU, you may need to wait for 450ns here. - * For details, please look at the data sheet. */ - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } -} - -/******************************************************************************* -* Function Name: usb0_function_set_curpipe2 -* Description : Allocates FIF0 specified by the argument in the pipe assigned -* : by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* : uint16_t dfacc ; DFACC Access mode -* Return Value : none -*******************************************************************************/ -void usb0_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) -{ - uint16_t buffer; - uint32_t loop; -#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ - uint32_t dummy; -#endif - volatile uint32_t loop2; - - g_usb0_function_mbw[pipe] = mbw; - - switch (fifosel) - { - case USB_FUNCTION_CUSE: - buffer = USB200.CFIFOSEL; - buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); - buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == - (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) - { - break; - } - - loop2 = 100; - while (loop2-- > 0) - { - /* wait */ - } - } - buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(isel | pipe | mbw); - USB200.CFIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == - (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_FUNCTION_D0DMA: - case USB_FUNCTION_D0USE: - buffer = USB200.D0FIFOSEL; -#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - - if (dfacc != 0) - { - buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); - } -#else - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); -#endif - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - -#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ - if (dfacc != 0) - { - dummy = USB200.D0FIFO.UINT32; - } -#endif - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D0FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - case USB_FUNCTION_D1DMA: - case USB_FUNCTION_D1USE: - buffer = USB200.D1FIFOSEL; -#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - - if (dfacc != 0) - { - buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); - } -#else - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); -#endif - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } -#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ - if (dfacc != 0) - { - dummy = USB200.D1FIFO.UINT32; - loop = dummy; // avoid warning. - } -#endif - buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); - buffer |= (uint16_t)(pipe | mbw); - USB200.D1FIFOSEL = buffer; - - for (loop = 0; loop < 4; loop++) - { - if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) - { - break; - } - - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } - } - break; - - default: - break; - } - - /* Cautions !!! - * Depending on the external bus speed of CPU, you may need to wait for 450ns here. - * For details, please look at the data sheet. */ - loop2 = 100; - - while (loop2-- > 0) - { - /* wait */ - } -} - -/******************************************************************************* -* Function Name: usb0_function_write_c_fifo -* Description : Writes data in CFIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_write_c_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.CFIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_read_c_fifo -* Description : Reads data from CFIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_read_c_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_function_data_pointer[pipe] = USB200.CFIFO.UINT8[HH]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT16[H]; - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT32; - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_write_d0_fifo -* Description : Writes data in D0FIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating CFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_write_d0_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.D0FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_read_d0_fifo -* Description : Reads data from D0FIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating DOFIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_read_d0_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_function_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H]; - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT32; - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_write_d1_fifo -* Description : Writes data in D1FIFO. -* : Writes data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating D1FIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_write_d1_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - USB200.D1FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)(count / 2); even; --even) - { - USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)(count / 4); even; --even) - { - USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_read_d1_fifo -* Description : Reads data from D1FIFO. -* : Reads data by BYTE/WORD/LONG according to access size -* : to the pipe specified by the arguments. -* : Before executing this function, allocating D1FIF0 in the specified pipe -* : should be completed. -* : Before executing this function, access size to the specified pipe -* : should be fixed and set in g_usb0_function_mbw[]. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t count ; Data Size(Byte) -* Return Value : none -*******************************************************************************/ -static void usb0_function_read_d1_fifo (uint16_t pipe, uint16_t count) -{ - uint16_t even; - - if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) - { - for (even = count; even; --even) - { - *g_usb0_function_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH]; - g_usb0_function_data_pointer[pipe] += 1; - } - } - else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) - { - for (even = (uint16_t)((count + 1) / 2); even; --even) - { - *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H]; - g_usb0_function_data_pointer[pipe] += 2; - } - } - else - { - for (even = (uint16_t)((count + 3) / 4); even; --even) - { - *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT32; - g_usb0_function_data_pointer[pipe] += 4; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_com_get_dmasize -* Description : Calculates access width of DMA transfer by the argument to -* : return as the Return Value. -* Arguments : uint32_t trncount : transfer byte -* : uint32_t dtptr : transfer data pointer -* Return Value : DMA transfer size : 0 8bit -* : : 1 16bit -* : : 2 32bit -*******************************************************************************/ -static uint32_t usb0_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr) -{ - uint32_t size; - - if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) - { - /* When transfer byte count is odd */ - /* or transfer data area is 8-bit alignment */ - size = 0; /* 8bit */ - } - else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) - { - /* When the transfer byte count is multiples of 2 */ - /* or the transfer data area is 16-bit alignment */ - size = 1; /* 16bit */ - } - else - { - /* When the transfer byte count is multiples of 4 */ - /* or the transfer data area is 32-bit alignment */ - size = 2; /* 32bit */ - } - - return size; -} - -/******************************************************************************* -* Function Name: usb0_function_get_mbw -* Description : Calculates access width of DMA to return the value set in MBW. -* Arguments : uint32_t trncount : transfer byte -* : uint32_t dtptr : transfer data pointer -* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit -* : : USB_FUNCTION_BITMBW_16 16bit -* : : USB_FUNCTION_BITMBW_32 32bit -*******************************************************************************/ -uint16_t usb0_function_get_mbw (uint32_t trncount, uint32_t dtptr) -{ - uint32_t size; - uint16_t mbw; - - size = usb0_function_com_get_dmasize(trncount, dtptr); - - if (size == 0) - { - /* 8bit */ - mbw = USB_FUNCTION_BITMBW_8; - } - else if (size == 1) - { - /* 16bit */ - mbw = USB_FUNCTION_BITMBW_16; - } - else - { - /* 32bit */ - mbw = USB_FUNCTION_BITMBW_32; - } - - return mbw; -} - -/******************************************************************************* -* Function Name: usb0_function_set_transaction_counter -* Description : Sets transaction counter by the argument(PIPEnTRN). -* : Clears transaction before setting to enable transaction counter setting. -* Arguments : uint16_t pipe ; Pipe number -* : uint32_t bsize : Data transfer size -* Return Value : none -*******************************************************************************/ -static void usb0_function_set_transaction_counter (uint16_t pipe, uint32_t bsize) -{ - uint16_t mxps; - uint16_t cnt; - - if (bsize == 0) - { - return; - } - - mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ - - if ((bsize % mxps) == 0) - { - cnt = (uint16_t)(bsize / mxps); - } - else - { - cnt = (uint16_t)((bsize / mxps) + 1); - } - - switch (pipe) - { - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE1TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE2TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE3TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE4TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE5TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPE9TRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEATRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPEATRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPEATRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPEBTRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPEBTRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPECTRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPECTRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPEDTRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPEDTRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEETRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPEETRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPEETRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - USB200.PIPEFTRN = cnt; - RZA_IO_RegWrite_16(&USB200.PIPEFTRE, - 1, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_clear_transaction_counter -* Description : Clears the transaction counter by the argument. -* : After executing this function, the transaction counter is invalid. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_transaction_counter (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE1TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE2TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE3TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE4TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE5TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPE9TRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEATRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPEATRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBTRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPEBTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECTRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPECTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDTRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPEDTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEETRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPEETRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFTRE, - 0, - USB_PIPEnTRE_TRENB_SHIFT, - USB_PIPEnTRE_TRENB); - RZA_IO_RegWrite_16(&USB200.PIPEFTRE, - 1, - USB_PIPEnTRE_TRCLR_SHIFT, - USB_PIPEnTRE_TRCLR); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_stop_transfer -* Description : Stops the USB transfer in the pipe specified by the argument. -* : After stopping the USB transfer, clears the buffer allocated in -* : the pipe. -* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0; -* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt -* : in the corresponding pipe becomes invalid. Sequence bit is also -* : cleared. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_stop_transfer (uint16_t pipe) -{ - uint16_t usefifo; - uint32_t remain; - uint16_t fifo; - - usb0_function_set_pid_nak(pipe); - - usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - switch (usefifo) - { - case USB_FUNCTION_D0FIFO_USE: - usb0_function_clear_transaction_counter(pipe); - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ - fifo = USB_FUNCTION_D0USE; - break; - - case USB_FUNCTION_D1FIFO_USE: - usb0_function_clear_transaction_counter(pipe); - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ - fifo = USB_FUNCTION_D1USE; - break; - - case USB_FUNCTION_D0FIFO_DMA: - remain = Userdef_USB_usb0_function_stop_dma0(); - usb0_function_dma_stop_d0(pipe, remain); - usb0_function_clear_transaction_counter(pipe); - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ - fifo = USB_FUNCTION_D0DMA; - break; - - case USB_FUNCTION_D1FIFO_DMA: - remain = Userdef_USB_usb0_function_stop_dma1(); - usb0_function_dma_stop_d1(pipe, remain); - usb0_function_clear_transaction_counter(pipe); - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ - fifo = USB_FUNCTION_D1DMA; - break; - - default: - usb0_function_clear_transaction_counter(pipe); - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ - fifo = USB_FUNCTION_CUSE; - break; - } - - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16); - - /* Interrupt of pipe set is disabled */ - usb0_function_disable_brdy_int(pipe); - usb0_function_disable_nrdy_int(pipe); - usb0_function_disable_bemp_int(pipe); - - usb0_function_aclrm(pipe); - usb0_function_set_csclr(pipe); - - if ( g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT ) - { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; - } - -} - -/******************************************************************************* -* Function Name: usb0_function_set_dfacc_d0 -* Description : Sets the DFACC setting value in D0FIFO using the transfer size. -* Arguments : uint16_t mbw ; MBW -* : uint16_t count ; data count -* Return Value : DFACC Access mode -*******************************************************************************/ -static uint16_t usb0_function_set_dfacc_d0 (uint16_t mbw, uint32_t count) -{ - uint16_t dfacc = 0; - -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; -#else - if (mbw == USB_FUNCTION_BITMBW_32) - { - if ((count % 32) == 0) - { - /* 32byte transfer */ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 2, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 2; - } - else if ((count % 16) == 0) - { - /* 16byte transfer */ - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 1, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 1; - } - else - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - else - { - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D0FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } -#endif - return dfacc; -} - -/******************************************************************************* -* Function Name: usb0_function_set_dfacc_d1 -* Description : Set the DFACC setting value in D1FIFO using the transfer size. -* Arguments : uint16_t mbw ; MBW -* : uint16_t count ; data count -* Return Value : DFACC Access mode -*******************************************************************************/ -static uint16_t usb0_function_set_dfacc_d1 (uint16_t mbw, uint32_t count) -{ - uint16_t dfacc = 0; - -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; -#else - if (mbw == USB_FUNCTION_BITMBW_32) - { - if ((count % 32) == 0) - { - /* 32byte transfer */ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 2, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 2; - } - else if ((count % 16) == 0) - { - /* 16byte transfer */ - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 1, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 1; - } - else - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - } - else if (mbw == USB_FUNCTION_BITMBW_16) - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } - else - { - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_DFACC_SHIFT, - USB_DnFBCFG_DFACC); - RZA_IO_RegWrite_16(&USB200.D1FBCFG, - 0, - USB_DnFBCFG_TENDE_SHIFT, - USB_DnFBCFG_TENDE); - dfacc = 0; - } -#endif - - return dfacc; -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dma.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dma.c deleted file mode 100644 index cfc8d0f492..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_dma.c +++ /dev/null @@ -1,346 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_dma.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -static void usb0_function_dmaint(uint16_t fifo); -static void usb0_function_dmaint_buf2fifo(uint16_t pipe); -static void usb0_function_dmaint_fifo2buf(uint16_t pipe); - - -/******************************************************************************* -* Function Name: usb0_function_dma_stop_d0 -* Description : D0FIFO DMA stop -* Arguments : uint16_t pipe : pipe number -* : uint32_t remain : transfer byte -* Return Value : none -*******************************************************************************/ -void usb0_function_dma_stop_d0 (uint16_t pipe, uint32_t remain) -{ - uint16_t dtln; - uint16_t dfacc; - uint16_t buffer; - uint16_t sds_b = 1; - - dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); - - if (dfacc == 2) - { - sds_b = 32; - } - else if (dfacc == 1) - { - sds_b = 16; - } - else - { - if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2) - { - sds_b = 4; - } - else if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1) - { - sds_b = 2; - } - else - { - sds_b = 1; - } - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) - { - buffer = USB200.D0FIFOCTR; - dtln = (buffer & USB_FUNCTION_BITDTLN); - - if ((dtln % sds_b) != 0) - { - remain += (sds_b - (dtln % sds_b)); - } - g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain); - g_usb0_function_data_count[pipe] = remain; - } - } - - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); -} - -/******************************************************************************* -* Function Name: usb0_function_dma_stop_d1 -* Description : D1FIFO DMA stop -* Arguments : uint16_t pipe : pipe number -* : uint32_t remain : transfer byte -* Return Value : none -*******************************************************************************/ -void usb0_function_dma_stop_d1 (uint16_t pipe, uint32_t remain) -{ - uint16_t dtln; - uint16_t dfacc; - uint16_t buffer; - uint16_t sds_b = 1; - - dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); - - if (dfacc == 2) - { - sds_b = 32; - } - else if (dfacc == 1) - { - sds_b = 16; - } - else - { - if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2) - { - sds_b = 4; - } - else if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1) - { - sds_b = 2; - } - else - { - sds_b = 1; - } - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) - { - if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) - { - buffer = USB200.D1FIFOCTR; - dtln = (buffer & USB_FUNCTION_BITDTLN); - - if ((dtln % sds_b) != 0) - { - remain += (sds_b - (dtln % sds_b)); - } - g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain); - g_usb0_function_data_count[pipe] = remain; - } - } - - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); -} - -/******************************************************************************* -* Function Name: usb0_function_dma_interrupt_d0fifo -* Description : This function is DMA interrupt handler entry. -* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function. -* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is -* : specified by dma->fifo. -* : Register this function as DMA complete interrupt. -* Arguments : uint32_t int_sense ; Interrupts detection mode -* : ; INTC_LEVEL_SENSITIVE : Level sense -* : ; INTC_EDGE_TRIGGER : Edge trigger -* Return Value : none -*******************************************************************************/ -void usb0_function_dma_interrupt_d0fifo (uint32_t int_sense) -{ - usb0_function_dmaint(USB_FUNCTION_D0FIFO); - g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; -} - -/******************************************************************************* -* Function Name: usb0_function_dma_interrupt_d1fifo -* Description : This function is DMA interrupt handler entry. -* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function. -* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is -* : specified by dma->fifo. -* : Register this function as DMA complete interrupt. -* Arguments : uint32_t int_sense ; Interrupts detection mode -* : ; INTC_LEVEL_SENSITIVE : Level sense -* : ; INTC_EDGE_TRIGGER : Edge trigger -* Return Value : none -*******************************************************************************/ -void usb0_function_dma_interrupt_d1fifo (uint32_t int_sense) -{ - usb0_function_dmaint(USB_FUNCTION_D1FIFO); - g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; -} - -/******************************************************************************* -* Function Name: usb0_function_dmaint -* Description : This function is DMA transfer end interrupt -* Arguments : uint16_t fifo ; fifo number -* : ; USB_FUNCTION_D0FIFO -* : ; USB_FUNCTION_D1FIFO -* Return Value : none -*******************************************************************************/ -static void usb0_function_dmaint (uint16_t fifo) -{ - uint16_t pipe; - - pipe = g_usb0_function_DmaPipe[fifo]; - - if (g_usb0_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO) - { - usb0_function_dmaint_buf2fifo(pipe); - } - else - { - usb0_function_dmaint_fifo2buf(pipe); - } -} - -/******************************************************************************* -* Function Name: usb0_function_dmaint_fifo2buf -* Description : Executes read completion from FIFO by DMAC. -* Arguments : uint16_t pipe : pipe number -* Return Value : none -*******************************************************************************/ -static void usb0_function_dmaint_fifo2buf (uint16_t pipe) -{ - uint32_t remain; - uint16_t useport; - - if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) - { - useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - - if (useport == USB_FUNCTION_D0FIFO_DMA) - { - remain = Userdef_USB_usb0_function_stop_dma0(); - usb0_function_dma_stop_d0(pipe, remain); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND) - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - } - else - { - usb0_function_enable_brdy_int(pipe); - } - } - } - else - { - remain = Userdef_USB_usb0_function_stop_dma1(); - usb0_function_dma_stop_d1(pipe, remain); - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND) - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - } - else - { - usb0_function_enable_brdy_int(pipe); - } - } - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_dmaint_buf2fifo -* Description : Executes write completion in FIFO by DMAC. -* Arguments : uint16_t pipe : pipe number -* Return Value : none -*******************************************************************************/ -static void usb0_function_dmaint_buf2fifo (uint16_t pipe) -{ - uint32_t remain; - uint16_t useport; - - useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); - - if (useport == USB_FUNCTION_D0FIFO_DMA) - { - remain = Userdef_USB_usb0_function_stop_dma0(); - usb0_function_dma_stop_d0(pipe, remain); - - if (g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] != 0) - { - RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); - } - } - else - { - remain = Userdef_USB_usb0_function_stop_dma1(); - usb0_function_dma_stop_d1(pipe, remain); - - if (g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] != 0) - { - RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, - 1, - USB_DnFIFOCTR_BVAL_SHIFT, - USB_DnFIFOCTR_BVAL); - } - } - - usb0_function_enable_bemp_int(pipe); -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_intrn.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_intrn.c deleted file mode 100644 index 827efaed71..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_intrn.c +++ /dev/null @@ -1,249 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_intrn.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_function_brdy_int -* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). -* : According to the pipe that interrupt is generated in, -* : reads/writes buffer allocated in the pipe. -* : This function is executed in the BRDY interrupt handler. -* : This function clears BRDY interrupt status and BEMP interrupt -* : status. -* Arguments : uint16_t Status ; BRDYSTS Register Value -* : uint16_t Int_enbl ; BRDYENB Register Value -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_brdy_int (uint16_t status, uint16_t int_enb) -{ - uint32_t int_sense = 0; - uint16_t pipe; - uint16_t pipebit; - - for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) - { - pipebit = g_usb0_function_bit_set[pipe]; - - if ((status & pipebit) && (int_enb & pipebit)) - { - USB200.BRDYSTS = (uint16_t)~pipebit; - USB200.BEMPSTS = (uint16_t)~pipebit; - if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) - { - if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) - { - usb0_function_dma_interrupt_d0fifo(int_sense); - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - usb0_function_read_dma(pipe); - usb0_function_disable_brdy_int(pipe); - } - else - { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - } - } - else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA) - { - if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) - { - usb0_function_dma_interrupt_d1fifo(int_sense); - } - - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) - { - usb0_function_read_dma(pipe); - usb0_function_disable_brdy_int(pipe); - } - else - { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - } - } - else - { - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) - { - usb0_function_read_buffer(pipe); - } - else - { - usb0_function_write_buffer(pipe); - } - } - } - } -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_nrdy_int -* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9). -* : Checks NRDY interrupt cause by PID. When the cause if STALL, -* : regards the pipe state as STALL and ends the processing. -* : Then the cause is not STALL, increments the error count to -* : communicate again. When the error count is 3, determines -* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing. -* : This function is executed in the NRDY interrupt handler. -* : This function clears NRDY interrupt status. -* Arguments : uint16_t status ; NRDYSTS Register Value -* : uint16_t int_enb ; NRDYENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_function_nrdy_int (uint16_t status, uint16_t int_enb) -{ - uint16_t pid; - uint16_t pipe; - uint16_t bitcheck; - - bitcheck = (uint16_t)(status & int_enb); - - USB200.NRDYSTS = (uint16_t)~status; - - for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) - { - if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe]) - { - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) - { - if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT) - { - pid = usb0_function_get_pid(pipe); - if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) - { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; - } - else - { - g_usb0_function_PipeIgnore[pipe]++; - if (g_usb0_function_PipeIgnore[pipe] == 3) - { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; - } - else - { - usb0_function_set_pid_buf(pipe); - } - } - } - } - else - { - /* USB Function */ - } - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_bemp_int -* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9). -* Arguments : uint16_t status ; BEMPSTS Register Value -* : uint16_t int_enb ; BEMPENB Register Value -* Return Value : none -*******************************************************************************/ -void usb0_function_bemp_int (uint16_t status, uint16_t int_enb) -{ - uint16_t pid; - uint16_t pipe; - uint16_t bitcheck; - uint16_t inbuf; - - bitcheck = (uint16_t)(status & int_enb); - - USB200.BEMPSTS = (uint16_t)~status; - - for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) - { - if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe]) - { - pid = usb0_function_get_pid(pipe); - - if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) - { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; - } - else - { - inbuf = usb0_function_get_inbuf(pipe); - - if (inbuf == 0) - { - usb0_function_disable_bemp_int(pipe); - usb0_function_set_pid_nak(pipe); - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - } - } - } - } -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_lib.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_lib.c deleted file mode 100644 index e3d318b984..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_function_lib.c +++ /dev/null @@ -1,2026 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_lib.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_function_enable_brdy_int -* Description : Enables BRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : BRDY. Enables BRDY interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_enable_brdy_int (uint16_t pipe) -{ - /* enable brdy interrupt */ - USB200.BRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_function_disable_brdy_int -* Description : Disables BRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : BRDY. Enables BRDY interrupt in the pipe specified by the argument -* : in the disabled status. After disabling BRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_disable_brdy_int (uint16_t pipe) -{ - /* disable brdy interrupt */ - USB200.BRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_clear_brdy_sts -* Description : Clear BRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_brdy_sts (uint16_t pipe) -{ - /* clear brdy status */ - USB200.BRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_enable_bemp_int -* Description : Enables BEMP interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : BEMP. Enables BEMP interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BEMP, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_enable_bemp_int (uint16_t pipe) -{ - /* enable bemp interrupt */ - USB200.BEMPENB |= (uint16_t)g_usb0_function_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_function_disable_bemp_int -* Description : Disables BEMP interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : BEMP. Enables BEMP interrupt in the pipe specified by the argument -* : in the disabled status. After enabling BEMP, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_disable_bemp_int (uint16_t pipe) -{ - /* disable bemp interrupt */ - USB200.BEMPENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_clear_bemp_sts -* Description : Clear BEMP interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_bemp_sts (uint16_t pipe) -{ - /* clear bemp status */ - USB200.BEMPSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_enable_nrdy_int -* Description : Enables NRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling -* : NRDY. Enables NRDY interrupt in the pipe specified by the argument -* : in the disabled status. After enabling NRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_enable_nrdy_int (uint16_t pipe) -{ - /* enable nrdy interrupt */ - USB200.NRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_function_disable_nrdy_int -* Description : Disables NRDY interrupt in the pipe spceified by the argument. -* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling -* : NRDY. Disables NRDY interrupt in the pipe specified by the argument -* : in the disabled status. After disabling NRDY, recover all -* : BEMP/NRDY/BRDY disabled/enabled status. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_disable_nrdy_int (uint16_t pipe) -{ - /* disable nrdy interrupt */ - USB200.NRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_clear_nrdy_sts -* Description : Clear NRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_nrdy_sts (uint16_t pipe) -{ - /* clear nrdy status */ - USB200.NRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); -} - -/******************************************************************************* -* Function Name: usb0_function_is_hispeed -* Description : Returns the result of USB reset hand shake (RHST) as -* : return value. -* Arguments : none -* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed -* : USB_FUNCTION_FULL_SPEED ; Full-Speed -* : LOW_SPEED ; Low-Speed -* : USB_FUNCTION_NON_SPEED ; error -*******************************************************************************/ -uint16_t usb0_function_is_hispeed (void) -{ - uint16_t rhst; - uint16_t speed; - - rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST); - - if (rhst == USB_FUNCTION_HSMODE) - { - speed = USB_FUNCTION_HIGH_SPEED; - } - else if (rhst == USB_FUNCTION_FSMODE) - { - speed = USB_FUNCTION_FULL_SPEED; - } - else if (rhst == USB_FUNCTION_LSMODE) - { - speed = USB_FUNCTION_LOW_SPEED; - } - else - { - speed = USB_FUNCTION_NON_SPEED; - } - - return speed; -} - -/******************************************************************************* -* Function Name: usb0_function_is_hispeed_enable -* Description : Returns the USB High-Speed connection enabled status as -* : return value. -* Arguments : none -* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable -* : DEVDRV_USBF_NO : Hi-Speed Disable -*******************************************************************************/ -uint16_t usb0_function_is_hispeed_enable (void) -{ - uint16_t ret; - - ret = DEVDRV_USBF_NO; - - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1) - { - ret = DEVDRV_USBF_YES; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_function_set_pid_buf -* Description : Enables communicaqtion in the pipe specified by the argument -* : (BUF). -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_pid_buf (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_function_get_pid(pipe); - - if (pid == DEVDRV_USBF_PID_STALL2) - { - usb0_function_set_pid_nak(pipe); - } - - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - DEVDRV_USBF_PID_BUF, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - DEVDRV_USBF_PID_BUF, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_set_pid_nak -* Description : Disables communication (NAK) in the pipe specified by the argument. -* : When the pipe status was enabling communication (BUF) before -* : executing before executing this function, waits in the software -* : until the pipe becomes ready after setting disabled. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_pid_nak (uint16_t pipe) -{ - uint16_t pid; - uint16_t pbusy; - uint32_t loop; - - pid = usb0_function_get_pid(pipe); - - if (pid == DEVDRV_USBF_PID_STALL2) - { - usb0_function_set_pid_stall(pipe); - } - - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - DEVDRV_USBF_PID_NAK, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - DEVDRV_USBF_PID_NAK, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - default: - break; - } - - if (pid == DEVDRV_USBF_PID_BUF) - { - for (loop = 0; loop < 200; loop++) - { - switch (pipe) - { - case USB_FUNCTION_PIPE0: - pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_PBUSY_SHIFT, - USB_DCPCTR_PBUSY); - break; - - case USB_FUNCTION_PIPE1: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_FUNCTION_PIPE2: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_FUNCTION_PIPE3: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_FUNCTION_PIPE4: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_FUNCTION_PIPE5: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_PBUSY_SHIFT, - USB_PIPEnCTR_1_5_PBUSY); - break; - - case USB_FUNCTION_PIPE6: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_FUNCTION_PIPE7: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_FUNCTION_PIPE8: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_PBUSY_SHIFT, - USB_PIPEnCTR_6_8_PBUSY); - break; - - case USB_FUNCTION_PIPE9: - pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_PBUSY_SHIFT, - USB_PIPEnCTR_9_PBUSY); - break; - - case USB_FUNCTION_PIPEA: - pbusy = RZA_IO_RegRead_16(&USB200.PIPEACTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - case USB_FUNCTION_PIPEB: - pbusy = RZA_IO_RegRead_16(&USB200.PIPEBCTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - case USB_FUNCTION_PIPEC: - pbusy = RZA_IO_RegRead_16(&USB200.PIPECCTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - case USB_FUNCTION_PIPED: - pbusy = RZA_IO_RegRead_16(&USB200.PIPEDCTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - case USB_FUNCTION_PIPEE: - pbusy = RZA_IO_RegRead_16(&USB200.PIPEECTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - case USB_FUNCTION_PIPEF: - pbusy = RZA_IO_RegRead_16(&USB200.PIPEFCTR, - USB_PIPEnCTR_A_F_PBUSY_SHIFT, - USB_PIPEnCTR_A_F_PBUSY); - break; - - default: - pbusy = 1; - break; - } - - if (pbusy == 0) - { - break; - } - Userdef_USB_usb0_function_delay_500ns(); - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_set_pid_stall -* Description : Disables communication (STALL) in the pipe specified by the -* : argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_pid_stall (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_function_get_pid(pipe); - if (pid == DEVDRV_USBF_PID_BUF) - { - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - DEVDRV_USBF_PID_STALL2, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - DEVDRV_USBF_PID_STALL2, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - default: - break; - } - } - else - { - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - DEVDRV_USBF_PID_STALL, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - DEVDRV_USBF_PID_STALL, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name: usb0_function_clear_pid_stall -* Description : Disables communication (NAK) in the pipe specified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_pid_stall (uint16_t pipe) -{ - usb0_function_set_pid_nak(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_get_pid -* Description : Returns the pipe state specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : PID -*******************************************************************************/ -uint16_t usb0_function_get_pid (uint16_t pipe) -{ - uint16_t pid; - - switch (pipe) - { - case USB_FUNCTION_PIPE0: - pid = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_PID_SHIFT, - USB_DCPCTR_PID); - break; - - case USB_FUNCTION_PIPE1: - pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE2: - pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE3: - pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE4: - pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE5: - pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_PID_SHIFT, - USB_PIPEnCTR_1_5_PID); - break; - - case USB_FUNCTION_PIPE6: - pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE7: - pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE8: - pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_PID_SHIFT, - USB_PIPEnCTR_6_8_PID); - break; - - case USB_FUNCTION_PIPE9: - pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_PID_SHIFT, - USB_PIPEnCTR_9_PID); - break; - - case USB_FUNCTION_PIPEA: - pid = RZA_IO_RegRead_16(&USB200.PIPEACTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEB: - pid = RZA_IO_RegRead_16(&USB200.PIPEBCTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEC: - pid = RZA_IO_RegRead_16(&USB200.PIPECCTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPED: - pid = RZA_IO_RegRead_16(&USB200.PIPEDCTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEE: - pid = RZA_IO_RegRead_16(&USB200.PIPEECTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - case USB_FUNCTION_PIPEF: - pid = RZA_IO_RegRead_16(&USB200.PIPEFCTR, - USB_PIPEnCTR_A_F_PID_SHIFT, - USB_PIPEnCTR_A_F_PID); - break; - - default: - pid = 0; - break; - } - - return pid; -} - -/******************************************************************************* -* Function Name: usb0_function_set_csclr -* Description : CSPLIT status clear setting of sprit transaction in specified -* : pipe is performed. -* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit -* : in DCPCTR register are continuously changed (when the sequence -* : toggle bit of data PID is continuously changed over two or more pipes), -* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. -* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. -* : In addition, both bits should be operated after PID is set to NAK. -* : However, when it is set to the isochronous transfer as the transfer type -* : (TYPE=11), writing in SQSET bit is disabled. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_csclr (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_CSCLR_SHIFT, - USB_DCPCTR_CSCLR); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_CSCLR_SHIFT, - USB_PIPEnCTR_1_5_CSCLR); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_CSCLR_SHIFT, - USB_PIPEnCTR_6_8_CSCLR); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_CSCLR_SHIFT, - USB_PIPEnCTR_9_CSCLR); - break; - - default: - /* PIPEA-F have not CSCLR */ - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_set_sqclr -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA0. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_sqclr (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_SQCLR_SHIFT, - USB_DCPCTR_SQCLR); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_SQCLR_SHIFT, - USB_PIPEnCTR_1_5_SQCLR); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_SQCLR_SHIFT, - USB_PIPEnCTR_6_8_SQCLR); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_SQCLR_SHIFT, - USB_PIPEnCTR_9_SQCLR); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - 1, - USB_PIPEnCTR_A_F_SQCLR_SHIFT, - USB_PIPEnCTR_A_F_SQCLR); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_set_sqset -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA1. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_function_set_sqset (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE0: - RZA_IO_RegWrite_16(&USB200.DCPCTR, - 1, - USB_DCPCTR_SQSET_SHIFT, - USB_DCPCTR_SQSET); - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_SQSET_SHIFT, - USB_PIPEnCTR_1_5_SQSET); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_SQSET_SHIFT, - USB_PIPEnCTR_6_8_SQSET); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_SQSET_SHIFT, - USB_PIPEnCTR_9_SQSET); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - 1, - USB_PIPEnCTR_A_F_SQSET_SHIFT, - USB_PIPEnCTR_A_F_SQSET); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_get_sqmon -* Description : Toggle bit of specified pipe is obtained -* Arguments : uint16_t pipe ; Pipe number -* Return Value : sqmon -*******************************************************************************/ -uint16_t usb0_function_get_sqmon (uint16_t pipe) -{ - uint16_t sqmon; - - switch (pipe) - { - case USB_FUNCTION_PIPE0: - sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR, - USB_DCPCTR_SQMON_SHIFT, - USB_DCPCTR_SQMON); - break; - - case USB_FUNCTION_PIPE1: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_FUNCTION_PIPE2: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_FUNCTION_PIPE3: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_FUNCTION_PIPE4: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_FUNCTION_PIPE5: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_SQMON_SHIFT, - USB_PIPEnCTR_1_5_SQMON); - break; - - case USB_FUNCTION_PIPE6: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_FUNCTION_PIPE7: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_FUNCTION_PIPE8: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR, - USB_PIPEnCTR_6_8_SQMON_SHIFT, - USB_PIPEnCTR_6_8_SQMON); - break; - - case USB_FUNCTION_PIPE9: - sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_SQMON_SHIFT, - USB_PIPEnCTR_9_SQMON); - break; - - case USB_FUNCTION_PIPEA: - sqmon = RZA_IO_RegRead_16(&USB200.PIPEACTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - case USB_FUNCTION_PIPEB: - sqmon = RZA_IO_RegRead_16(&USB200.PIPEBCTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - case USB_FUNCTION_PIPEC: - sqmon = RZA_IO_RegRead_16(&USB200.PIPECCTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - case USB_FUNCTION_PIPED: - sqmon = RZA_IO_RegRead_16(&USB200.PIPEDCTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - case USB_FUNCTION_PIPEE: - sqmon = RZA_IO_RegRead_16(&USB200.PIPEECTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - case USB_FUNCTION_PIPEF: - sqmon = RZA_IO_RegRead_16(&USB200.PIPEFCTR, - USB_PIPEnCTR_A_F_SQMON_SHIFT, - USB_PIPEnCTR_A_F_SQMON); - break; - - default: - sqmon = 0; - break; - } - - return sqmon; -} - -/******************************************************************************* -* Function Name: usb0_function_aclrm -* Description : The buffer of specified pipe is initialized -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_function_aclrm (uint16_t pipe) -{ - usb0_function_set_aclrm(pipe); - usb0_function_clr_aclrm(pipe); -} - -/******************************************************************************* -* Function Name: usb0_function_set_aclrm -* Description : The auto buffer clear mode of specified pipe is enabled -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_function_set_aclrm (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE0: - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 1, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 1, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 1, - USB_PIPEnCTR_9_ACLRM_SHIFT, - USB_PIPEnCTR_9_ACLRM); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - 1, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_clr_aclrm -* Description : The auto buffer clear mode of specified pipe is enabled -* Arguments : uint16_t pipe : Pipe -* Return Value : none -*******************************************************************************/ -void usb0_function_clr_aclrm (uint16_t pipe) -{ - switch (pipe) - { - case USB_FUNCTION_PIPE0: - break; - - case USB_FUNCTION_PIPE1: - RZA_IO_RegWrite_16(&USB200.PIPE1CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE2: - RZA_IO_RegWrite_16(&USB200.PIPE2CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE3: - RZA_IO_RegWrite_16(&USB200.PIPE3CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE4: - RZA_IO_RegWrite_16(&USB200.PIPE4CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE5: - RZA_IO_RegWrite_16(&USB200.PIPE5CTR, - 0, - USB_PIPEnCTR_1_5_ACLRM_SHIFT, - USB_PIPEnCTR_1_5_ACLRM); - break; - - case USB_FUNCTION_PIPE6: - RZA_IO_RegWrite_16(&USB200.PIPE6CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE7: - RZA_IO_RegWrite_16(&USB200.PIPE7CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE8: - RZA_IO_RegWrite_16(&USB200.PIPE8CTR, - 0, - USB_PIPEnCTR_6_8_ACLRM_SHIFT, - USB_PIPEnCTR_6_8_ACLRM); - break; - - case USB_FUNCTION_PIPE9: - RZA_IO_RegWrite_16(&USB200.PIPE9CTR, - 0, - USB_PIPEnCTR_9_ACLRM_SHIFT, - USB_PIPEnCTR_9_ACLRM); - break; - - case USB_FUNCTION_PIPEA: - RZA_IO_RegWrite_16(&USB200.PIPEACTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEB: - RZA_IO_RegWrite_16(&USB200.PIPEBCTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEC: - RZA_IO_RegWrite_16(&USB200.PIPECCTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPED: - RZA_IO_RegWrite_16(&USB200.PIPEDCTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEE: - RZA_IO_RegWrite_16(&USB200.PIPEECTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - case USB_FUNCTION_PIPEF: - RZA_IO_RegWrite_16(&USB200.PIPEFCTR, - 0, - USB_PIPEnCTR_A_F_ACLRM_SHIFT, - USB_PIPEnCTR_A_F_ACLRM); - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_get_inbuf -* Description : Returns INBUFM of the pipe specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : inbuf -*******************************************************************************/ -uint16_t usb0_function_get_inbuf (uint16_t pipe) -{ - uint16_t inbuf; - - switch (pipe) - { - case USB_FUNCTION_PIPE0: - inbuf = 0; - break; - - case USB_FUNCTION_PIPE1: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_FUNCTION_PIPE2: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_FUNCTION_PIPE3: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_FUNCTION_PIPE4: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_FUNCTION_PIPE5: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR, - USB_PIPEnCTR_1_5_INBUFM_SHIFT, - USB_PIPEnCTR_1_5_INBUFM); - break; - - case USB_FUNCTION_PIPE6: - inbuf = 0; - break; - - case USB_FUNCTION_PIPE7: - inbuf = 0; - break; - - case USB_FUNCTION_PIPE8: - inbuf = 0; - break; - - case USB_FUNCTION_PIPE9: - inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR, - USB_PIPEnCTR_9_INBUFM_SHIFT, - USB_PIPEnCTR_9_INBUFM); - break; - - case USB_FUNCTION_PIPEA: - inbuf = RZA_IO_RegRead_16(&USB200.PIPEACTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - case USB_FUNCTION_PIPEB: - inbuf = RZA_IO_RegRead_16(&USB200.PIPEBCTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - case USB_FUNCTION_PIPEC: - inbuf = RZA_IO_RegRead_16(&USB200.PIPECCTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - case USB_FUNCTION_PIPED: - inbuf = RZA_IO_RegRead_16(&USB200.PIPEDCTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - case USB_FUNCTION_PIPEE: - inbuf = RZA_IO_RegRead_16(&USB200.PIPEECTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - case USB_FUNCTION_PIPEF: - inbuf = RZA_IO_RegRead_16(&USB200.PIPEFCTR, - USB_PIPEnCTR_A_F_INBUFM_SHIFT, - USB_PIPEnCTR_A_F_INBUFM); - break; - - default: - inbuf = 0; - break; - } - - return inbuf; -} - -/******************************************************************************* -* Function Name: usb0_function_setting_interrupt -* Description : Sets the USB module interrupt level. -* Arguments : uint8_t level ;interrupt level -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_setting_interrupt (uint8_t level) -{ - uint16_t d0fifo_dmaintid; - uint16_t d1fifo_dmaintid; - - R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_function_interrupt); - R_INTC_SetPriority(INTC_ID_USBI0, level); - R_INTC_Enable(INTC_ID_USBI0); - - d0fifo_dmaintid = Userdef_USB_usb0_function_d0fifo_dmaintid(); - - if (d0fifo_dmaintid != 0xFFFF) - { - R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_function_dma_interrupt_d0fifo); - R_INTC_SetPriority(d0fifo_dmaintid, level); - R_INTC_Enable(d0fifo_dmaintid); - } - - d1fifo_dmaintid = Userdef_USB_usb0_function_d1fifo_dmaintid(); - - if (d1fifo_dmaintid != 0xFFFF) - { - R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_function_dma_interrupt_d1fifo); - R_INTC_SetPriority(d1fifo_dmaintid, level); - R_INTC_Enable(d1fifo_dmaintid); - } -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_reset_module -* Description : Initializes the USB module. -* : Enables providing clock to the USB module. -* : Sets USB bus wait register. -* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ -* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ -* Return Value : none -*******************************************************************************/ -void usb0_function_reset_module (uint16_t clockmode) -{ - /* UPLLE bit is only USB0 */ - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, - USB_SYSCFG_UPLLE_SHIFT, - USB_SYSCFG_UPLLE) == 1) - { - if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode) - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - USB200.SYSCFG0 = 0; - USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); - Userdef_USB_usb0_function_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - else - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - Userdef_USB_usb0_function_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - } - else - { - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 0, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - USB200.SYSCFG0 = 0; - USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); - Userdef_USB_usb0_function_delay_xms(1); - RZA_IO_RegWrite_16(&USB200.SUSPMODE, - 1, - USB_SUSPMODE_SUSPM_SHIFT, - USB_SUSPMODE_SUSPM); - } - - USB200.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT); -} - -/******************************************************************************* -* Function Name: usb0_function_get_buf_size -* Description : Obtains pipe buffer size specified by the argument and -* : maximum packet size of the USB device in use. -* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum -* : packet size of the USB device using the corresponding pipe. -* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the -* : corresponding pipe is in continuous transfer mode, -* : obtains the buffer size allocated in the corresponcing pipe, -* : when incontinuous transfer, obtains maximum packet size. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : Maximum packet size or buffer size -*******************************************************************************/ -uint16_t usb0_function_get_buf_size (uint16_t pipe) -{ - uint16_t size; - uint16_t bufsize; - - if (pipe == USB_FUNCTION_PIPE0) - { - size = RZA_IO_RegRead_16(&USB200.DCPMAXP, - USB_DCPMAXP_MXPS_SHIFT, - USB_DCPMAXP_MXPS); - } - else - { - if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) - { - bufsize = RZA_IO_RegRead_16(&g_usb0_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); - size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF); - } - else - { - size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); - } - } - return size; -} - -/******************************************************************************* -* Function Name: usb0_function_get_mxps -* Description : Obtains maximum packet size of the USB device using the pipe -* : specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : Max Packet Size -*******************************************************************************/ -uint16_t usb0_function_get_mxps (uint16_t pipe) -{ - uint16_t size; - - if (pipe == USB_FUNCTION_PIPE0) - { - size = RZA_IO_RegRead_16(&USB200.DCPMAXP, - USB_DCPMAXP_MXPS_SHIFT, - USB_DCPMAXP_MXPS); - } - else - { - size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); - } - return size; -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_api.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_api.c deleted file mode 100644 index 369b2bea60..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_api.c +++ /dev/null @@ -1,441 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_api.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" -#include "dev_drv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_api_function_init -* Description : Initializes the USB module in the USB function mode. -* Arguments : uint8_t int_level ; interruput level -* : uint16_t mode : Speed modes -* : : USB_FUCNTION_HIGH_SPEED: High-speed device -* : : USB_FUCNTION_FULL_SPEED: Full-speed device -* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ -* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) -{ - volatile uint8_t dummy_buf; - - CPG.STBCR7 &= 0xfd; /* The clock of USB0 modules is permitted */ - dummy_buf = CPG.STBCR7; /* (Dummy read) */ - - usb0_function_setting_interrupt(int_level); - - usb0_function_reset_module(clockmode); /* reset USB module with setting tranciever */ - /* and HSE=1 */ - - usb0_function_init_status(); /* clear variables */ - - usb0_function_InitModule(mode); /* select USB Function and Interrupt Enable */ - /* Detect USB Device to attach or detach */ -} -#endif - -/******************************************************************************* -* Function Name: usb0_api_function_IsConfigured -* Description : Checks if the USB device is configured to return the result as -* : the return value. -* Arguments : none -* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend -* : DEVDRV_USBF_NO : not Configured -*******************************************************************************/ -uint16_t usb0_api_function_IsConfigured (void) -{ - uint16_t dvst; - - dvst = usb0_function_GetDeviceState(); - - if ((dvst == USB_FUNCTION_DVST_CONFIGURED) || - (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND)) - { - return DEVDRV_USBF_YES; - } - - return DEVDRV_USBF_NO; -} - -/******************************************************************************* -* Function Name: usb0_function_GetDeviceState -* Description : Returns the state of USB device. -* Arguments : none -* Return Value : Device States -*******************************************************************************/ -uint16_t usb0_function_GetDeviceState (void) -{ - uint16_t dvsq; - uint16_t dvst; - - dvsq = USB200.INTSTS0; - switch(dvsq & USB_FUNCTION_BITDVSQ) - { - case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */ - dvst = USB_FUNCTION_DVST_POWERED; - break; - - case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */ - dvst = USB_FUNCTION_DVST_DEFAULT; - break; - - case USB_FUNCTION_DS_ADDS: /* Address state */ - dvst = USB_FUNCTION_DVST_ADDRESS; - break; - - case USB_FUNCTION_DS_CNFG: /* Configured state */ - dvst = USB_FUNCTION_DVST_CONFIGURED; - break; - - case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */ - dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND; - break; - - case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */ - case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */ - case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */ - dvst = USB_FUNCTION_DVST_SUSPEND; - break; - - default: /* error */ - dvst = USB_FUNCTION_DVST_SUSPEND; - break; - } - - return dvst; -} - -/******************************************************************************* -* Function Name: usb0_api_function_start_receive_transfer -* Description : Starts USB data reception using the pipe specified in the argument. -* : The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data data Address -* Return Value : none -*******************************************************************************/ -void usb0_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - usb0_function_start_receive_transfer(pipe, size, data); -} - -/******************************************************************************* -* Function Name: usb0_api_function_start_send_transfer -* Description : Starts the USB data communication using pipe specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t size ; Data Size -* : uint8_t *data ; Data data Address -* Return Value : DEVDRV_USBF_WRITEEND ; Write end -* : DEVDRV_USBF_WRITESHRT ; short data -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_WRITEDMA ; Write DMA -* : DEVDRV_USBF_FIFOERROR ; FIFO status -*******************************************************************************/ -uint16_t usb0_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) -{ - uint16_t status; - - status = usb0_function_start_send_transfer(pipe, size, data); - - return status; -} - -/******************************************************************************* -* Function Name: usb0_api_function_check_pipe_status -* Description : Starts USB data reception using the pipe specified in the argument. -* : The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* : uint32_t *size ; Data Size -* Return Value : Pipe Status -*******************************************************************************/ -uint16_t usb0_api_function_check_pipe_status (uint16_t pipe, uint32_t * size) -{ - if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE) - { - *size = g_usb0_function_PipeDataSize[pipe]; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - - return DEVDRV_USBF_PIPE_DONE; - } - else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES) - { - *size = 0; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - - return DEVDRV_USBF_PIPE_NORES; - } - else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL) - { - *size = 0; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - - return DEVDRV_USBF_PIPE_STALL; - } - else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR) - { - *size = 0; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - - return DEVDRV_USBF_FIFOERROR; - } - else - { - /* Do Nothing */ - } - - return g_usb0_function_pipe_status[pipe]; -} - -/******************************************************************************* -* Function Name: usb0_api_function_clear_pipe_status -* Description : Starts USB data reception using the pipe specified in the argument. -* : The FIFO for using is set in the pipe definition table. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : Pipe Status -*******************************************************************************/ -void usb0_api_function_clear_pipe_status (uint16_t pipe) -{ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - g_usb0_function_PipeDataSize[pipe] = 0; -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_pid_buf -* Description : Enables communicaqtion in the pipe specified by the argument -* : (BUF). -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_pid_buf (uint16_t pipe) -{ - usb0_function_set_pid_buf(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_pid_nak -* Description : Disables communication (NAK) in the pipe specified by the argument. -* : When the pipe status was enabling communication (BUF) before -* : executing before executing this function, waits in the software -* : until the pipe becomes ready after setting disabled. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_pid_nak (uint16_t pipe) -{ - usb0_function_set_pid_nak(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_pid_stall -* Description : Disables communication (STALL) in the pipe specified by the -* : argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_pid_stall (uint16_t pipe) -{ - usb0_function_set_pid_stall(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_clear_pid_stall -* Description : Disables communication (NAK) in the pipe specified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_clear_pid_stall (uint16_t pipe) -{ - usb0_function_clear_pid_stall(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_get_pid -* Description : Returns the pipe state specified by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : PID -*******************************************************************************/ -uint16_t usb0_api_function_get_pid (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_function_get_pid(pipe); - - return pid; -} - -/******************************************************************************* -* Function Name: usb0_api_function_check_stall -* Description : -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : PID -*******************************************************************************/ -int32_t usb0_api_function_check_stall (uint16_t pipe) -{ - uint16_t pid; - - pid = usb0_function_get_pid(pipe); - - if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL) - { - return DEVDRV_USBF_STALL; - } - - return DEVDRV_SUCCESS; -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_sqclr -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA0. -* Arguments : uint16_t pipe ; Pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_sqclr (uint16_t pipe) -{ - usb0_function_set_sqclr(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_sqset -* Description : Sets the sequence bit of the pipe specified by the argument to -* : DATA1. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_sqset (uint16_t pipe) -{ - usb0_function_set_sqset(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_csclr -* Description : CSPLIT status clear setting of sprit transaction in specified -* : pipe is performed. -* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit -* : in DCPCTR register are continuously changed (when the sequence -* : toggle bit of data PID is continuously changed over two or more pipes), -* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. -* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. -* : In addition, both bits should be operated after PID is set to NAK. -* : However, when it is set to the isochronous transfer as the transfer type -* : (TYPE=11), writing in SQSET bit is disabled. -* Arguments : uint16_t pipe ; Pipe number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_csclr (uint16_t pipe) -{ - usb0_function_set_csclr(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_set_curpipe -* Description : Allocates FIF0 specifed by the argument in the pipe assigned -* : by the argument. -* Arguments : uint16_t pipe ; Pipe Number -* : uint16_t fifosel ; Select FIFO -* : uint16_t isel ; FIFO Access Direction -* : uint16_t mbw ; FIFO Port Access Bit Width -* Return Value : none -*******************************************************************************/ -void usb0_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) -{ - usb0_function_set_curpipe(pipe, fifosel, isel, mbw); -} - -/******************************************************************************* -* Function Name: usb0_api_function_clear_brdy_sts -* Description : Clear BRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_clear_brdy_sts (uint16_t pipe) -{ - usb0_function_clear_brdy_sts(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_clear_bemp_sts -* Description : Clear BEMP interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_clear_bemp_sts (uint16_t pipe) -{ - usb0_function_clear_bemp_sts(pipe); -} - -/******************************************************************************* -* Function Name: usb0_api_function_clear_nrdy_sts -* Description : Clear NRDY interrupt status in the pipe spceified by the argument. -* Arguments : uint16_t pipe ; pipe Number -* Return Value : none -*******************************************************************************/ -void usb0_api_function_clear_nrdy_sts (uint16_t pipe) -{ - usb0_function_clear_nrdy_sts(pipe); -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_controlrw.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_controlrw.c deleted file mode 100644 index 0a9121ab8e..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_controlrw.c +++ /dev/null @@ -1,142 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_controlrw.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_api_function_CtrlReadStart -* Description : Executes the USB control read transfer. -* : USB host controller <- USB device -* Arguments : uint16_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : DEVDRV_USBF_WRITEEND ; End of data write -* : DEVDRV_USBF_WRITESHRT ; End of short data write -* : DEVDRV_USBF_WRITING ; Continue of data write -* : DEVDRV_USBF_FIFOERROR ; FIFO access error -*******************************************************************************/ -uint16_t usb0_api_function_CtrlReadStart (uint32_t size, uint8_t * data) -{ - uint16_t status; - uint16_t mbw; - - usb0_function_set_pid_nak(USB_FUNCTION_PIPE0); - - g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size; - g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0], - (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; - - status = usb0_function_write_buffer_c(USB_FUNCTION_PIPE0); - - /* Peripheral Control sequence */ - switch (status) - { - case DEVDRV_USBF_WRITESHRT: /* End of data write */ - case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */ - case DEVDRV_USBF_WRITING: /* Continue of data write */ - usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */ - break; - - case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ - break; - - default: - break; - } - - return status; /* End or Err or Continue */ -} - -/******************************************************************************* -* Function Name: usb0_api_function_CtrlWriteStart -* Description : Executes the USB control write transfer. -* : USB host controller -> USB device -* Arguments : uint16_t size ; Data Size -* : uint8_t *data ; Data Address -* Return Value : none -*******************************************************************************/ -void usb0_api_function_CtrlWriteStart (uint32_t size, uint8_t * data) -{ - uint16_t mbw; - - usb0_function_set_pid_nak(USB_FUNCTION_PIPE0); - - g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size; - g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data; - - mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0], - (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]); - usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; - - usb0_function_enable_brdy_int(USB_FUNCTION_PIPE0); - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_global.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_global.c deleted file mode 100644 index 5f1ff018f2..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_global.c +++ /dev/null @@ -1,144 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_global.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -const uint16_t g_usb0_function_bit_set[16] = -{ - 0x0001, 0x0002, 0x0004, 0x0008, - 0x0010, 0x0020, 0x0040, 0x0080, - 0x0100, 0x0200, 0x0400, 0x0800, - 0x1000, 0x2000, 0x4000, 0x8000 -}; - -uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint8_t * g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; - -uint16_t g_usb0_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint16_t g_usb0_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint16_t g_usb0_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint32_t g_usb0_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1]; - -USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[2]; -uint16_t g_usb0_function_DmaPipe[2]; -uint16_t g_usb0_function_DmaBval[2]; -uint16_t g_usb0_function_DmaStatus[2]; - -uint16_t g_usb0_function_CtrZeroLengthFlag; - -//uint16_t g_usb0_function_ConfigNum; -//uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO]; -//uint16_t g_usb0_function_RemoteWakeupFlag; -uint16_t g_usb0_function_TestModeFlag; -uint16_t g_usb0_function_TestModeSelectors; - -//uint16_t g_usb0_function_ReqType; -//uint16_t g_usb0_function_ReqTypeType; -//uint16_t g_usb0_function_ReqTypeRecip; -//uint16_t g_usb0_function_ReqRequest; -//uint16_t g_usb0_function_ReqValue; -//uint16_t g_usb0_function_ReqIndex; -//uint16_t g_usb0_function_ReqLength; - -//uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; - -uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; -uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; - - -/******************************************************************************* -* Function Name: usb0_function_init_status -* Description : Initialization USB Sample Driver Variable. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_init_status (void) -{ - uint16_t pipe; - - //g_usb0_function_ConfigNum = 0; - //g_usb0_function_RemoteWakeupFlag = DEVDRV_USBF_OFF; - g_usb0_function_TestModeFlag = DEVDRV_USBF_OFF; - g_usb0_function_CtrZeroLengthFlag = 0; - -#if 0 - usb0_function_clear_alt(); -#endif - - for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) - { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - g_usb0_function_PipeDataSize[pipe] = 0; - g_usb0_function_data_count[pipe] = 0; - - /* pipe configuration in usb0_function_ResetEP() */ - g_usb0_function_pipecfg[pipe] = 0; - g_usb0_function_pipebuf[pipe] = 0; - g_usb0_function_pipemaxp[pipe] = 0; - g_usb0_function_pipeperi[pipe] = 0; - } -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sig.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sig.c deleted file mode 100644 index 66949dee63..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sig.c +++ /dev/null @@ -1,330 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_sig.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_function_EnableINTModule(void); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_function_InitModule -* Description : Initializes the USB module in the USB function mode. -* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode -* : ; other ; Full-speed Mode -* Return Value : none -*******************************************************************************/ -void usb0_function_InitModule (uint16_t mode) -{ - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_DCFM_SHIFT, - USB_SYSCFG_DCFM); /* USB function */ - - /* USB module operation enabled */ - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_USBE_SHIFT, - USB_SYSCFG_USBE); - - if (mode == USB_FUNCTION_HIGH_SPEED) - { - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE); /* Hi-Speed Mode */ - } - else - { - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_HSE_SHIFT, - USB_SYSCFG_HSE); - } - - /* for power-on */ - if (usb0_function_CheckVBUStaus() == DEVDRV_USBF_ON) - { - usb0_function_EnableINTModule(); /* Interrupt Enable */ - usb0_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */ - } - else - { - usb0_function_USB_FUNCTION_Detach(); /* USB Detach */ - /* with Interrupt Enable */ - } -} - -/******************************************************************************* -* Function Name: usb0_function_CheckVBUStaus -* Description : Checks the USB-VBUS state to returns the connection state to -* : the USB host. -* Arguments : none -* Return Value : DEVDRV_USBF_ON : VBUS ON -* : DEVDRV_USBF_OFF : VBUS OFF -*******************************************************************************/ -uint16_t usb0_function_CheckVBUStaus (void) -{ - uint16_t buf1; - uint16_t buf2; - uint16_t buf3; - - /* monitor VBUS pins */ - do - { - buf1 = RZA_IO_RegRead_16(&USB200.INTSTS0, - USB_INTSTS0_VBSTS_SHIFT, - USB_INTSTS0_VBSTS); - Userdef_USB_usb0_function_delay_10us(1); - buf2 = RZA_IO_RegRead_16(&USB200.INTSTS0, - USB_INTSTS0_VBSTS_SHIFT, - USB_INTSTS0_VBSTS); - Userdef_USB_usb0_function_delay_10us(1); - buf3 = RZA_IO_RegRead_16(&USB200.INTSTS0, - USB_INTSTS0_VBSTS_SHIFT, - USB_INTSTS0_VBSTS); - } while ((buf1 != buf2) || (buf2 != buf3)); - - if (buf1 == DEVDRV_USBF_OFF) - { - return DEVDRV_USBF_OFF; /* detach */ - } - - return DEVDRV_USBF_ON; /* attach */ -} - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_Attach -* Description : Connects to the USB host controller. -* : This function pulls up D+. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_USB_FUNCTION_Attach (void) -{ - Userdef_USB_usb0_function_attach(); - - Userdef_USB_usb0_function_delay_xms(10); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_DPRPU_SHIFT, - USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */ -} - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_Detach -* Description : Disconnects from the USB host controller. -* : This function opens D+/D-. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_USB_FUNCTION_Detach (void) -{ - uint16_t pipe; - - Userdef_USB_usb0_function_detach(); - - for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) - { - if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE) - { - usb0_function_stop_transfer(pipe); - } - } - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_DPRPU_SHIFT, - USB_SYSCFG_DPRPU); /* open D+ and D- */ - - /* Detach Recovery */ - Userdef_USB_usb0_function_delay_500ns(); /* need 1us=500ns * 2 wait */ - Userdef_USB_usb0_function_delay_500ns(); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_DCFM_SHIFT, - USB_SYSCFG_DCFM); - Userdef_USB_usb0_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */ - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_DCFM_SHIFT, - USB_SYSCFG_DCFM); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 0, - USB_SYSCFG_USBE_SHIFT, - USB_SYSCFG_USBE); /* soft reset module */ - Userdef_USB_usb0_function_delay_500ns(); - - RZA_IO_RegWrite_16(&USB200.SYSCFG0, - 1, - USB_SYSCFG_USBE_SHIFT, - USB_SYSCFG_USBE); - - usb0_function_EnableINTModule(); /* Interrupt Enable */ -} - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_BusReset -* Description : This function is executed when the USB device is transitioned -* : to POWERD_STATE. Sets the device descriptor according to the -* : connection speed determined by the USB reset hand shake. -* Arguments : none -* Return Value : none -*******************************************************************************/ -#if 0 /*The USBHAL in mbed does not need this function*/ -void usb0_function_USB_FUNCTION_BusReset (void) -{ - usb0_function_init_status(); /* memory clear */ - - if (usb0_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) - { - usb0_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */ - } - else - { - usb0_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */ - } - - usb0_function_ResetDCP(); /* Default Control PIPE reset */ -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_Resume -* Description : This function is executed when the USB device detects a resume -* : signal. -* : The USB sample driver does not operate for this function. -* Arguments : none -* Return Value : none -*******************************************************************************/ -#if 0 /*The USBHAL in mbed does not need this function*/ -void usb0_function_USB_FUNCTION_Resume (void) -{ - /* NOP */ -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_Suspend -* Description : This function is executed when the USB device detects a suspend -* : signal. -* : The USB sample driver does not operate for this function. -* Arguments : none -* Return Value : none -*******************************************************************************/ -#if 0 /*The USBHAL in mbed does not need this function*/ -void usb0_function_USB_FUNCTION_Suspend (void) -{ - /* NOP */ -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_USB_FUNCTION_TestMode -* Description : This function is executed when the USB device is transitioned U -* : to TEST_MODE by the USB standard request. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_USB_FUNCTION_TestMode (void) -{ - switch (g_usb0_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT) - { - case USB_FUNCTION_FUNCTION_TEST_J: - case USB_FUNCTION_FUNCTION_TEST_K: - case USB_FUNCTION_FUNCTION_TEST_SE0_NAK: - case USB_FUNCTION_FUNCTION_TEST_PACKET: - RZA_IO_RegWrite_16(&USB200.TESTMODE, - (g_usb0_function_TestModeSelectors >> 8), - USB_TESTMODE_UTST_SHIFT, - USB_TESTMODE_UTST); - break; - - case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE: - default: - break; - } -} - -/******************************************************************************* -* Function Name: usb0_function_EnableINTModule -* Description : Enables USB interrupt. -* Arguments : none -* Return Value : none -*******************************************************************************/ -static void usb0_function_EnableINTModule (void) -{ - uint16_t buf; - - buf = USB200.INTENB0; - buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE | - USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE); - USB200.INTENB0 = buf; - - usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sub.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sub.c deleted file mode 100644 index df7fbf5bbb..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/function/usb0_function_sub.c +++ /dev/null @@ -1,453 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_sub.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include "usb0_function.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -#if 0 -extern const uint16_t *g_usb0_function_EndPntPtr[]; -extern uint8_t g_usb0_function_DeviceDescriptor[]; -extern uint8_t *g_usb0_function_ConfigurationPtr[]; -#endif - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: usb0_function_ResetDCP -* Description : Initializes the default control pipe(DCP). -* Outline : Reset default control pipe -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_ResetDCP (void) -{ - USB200.DCPCFG = 0; -#if 0 - USB200.DCPMAXP = g_usb0_function_DeviceDescriptor[7]; -#else - USB200.DCPMAXP = 64; -#endif - - USB200.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); - USB200.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); - USB200.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); -} - -/******************************************************************************* -* Function Name: usb0_function_ResetEP -* Description : Initializes the end point. -* Arguments : uint16_t num ; Configuration Number -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_ResetEP (uint16_t num) -{ - uint16_t pipe; - uint16_t ep; - uint16_t index; - uint16_t buf; - uint16_t * tbl; - - tbl = (uint16_t *)(g_usb0_function_EndPntPtr[num - 1]); - - for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) - { - if (g_usb0_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR) - { - index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb0_function_EPTableIndex[ep]); - pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE); - - g_usb0_function_PipeTbl[pipe] = (uint16_t)( ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) | - ep | - (tbl[index + 0] & USB_FUNCTION_FIFO_USE) ); - - if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT) - { - tbl[index + 1] |= USB_FUNCTION_SHTNAKON; -#ifdef __USB_DMA_BFRE_ENABLE__ - /* this routine cannnot be perfomred if read operation is executed in buffer size */ - if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) || - ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)) - { - tbl[index + 1] |= USB_FUNCTION_BFREON; - } -#endif - } - - /* Interrupt Disable */ - buf = USB200.BRDYENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.BRDYENB = buf; - buf = USB200.NRDYENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.NRDYENB = buf; - buf = USB200.BEMPENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.BEMPENB = buf; - - usb0_function_set_pid_nak(pipe); - - /* CurrentPIPE Clear */ - if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, - USB_CFIFOSEL_CURPIPE_SHIFT, - USB_CFIFOSEL_CURPIPE) == pipe) - { - RZA_IO_RegWrite_16(&USB200.CFIFOSEL, - 0, - USB_CFIFOSEL_CURPIPE_SHIFT, - USB_CFIFOSEL_CURPIPE); - } - - if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE) == pipe) - { - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, - 0, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE); - } - - if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE) == pipe) - { - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, - 0, - USB_DnFIFOSEL_CURPIPE_SHIFT, - USB_DnFIFOSEL_CURPIPE); - } - - /* PIPE Configuration */ - USB200.PIPESEL = pipe; - USB200.PIPECFG = tbl[index + 1]; - USB200.PIPEBUF = tbl[index + 2]; - USB200.PIPEMAXP = tbl[index + 3]; - USB200.PIPEPERI = tbl[index + 4]; - - g_usb0_function_pipecfg[pipe] = tbl[index + 1]; - g_usb0_function_pipebuf[pipe] = tbl[index + 2]; - g_usb0_function_pipemaxp[pipe] = tbl[index + 3]; - g_usb0_function_pipeperi[pipe] = tbl[index + 4]; - - /* Buffer Clear */ - usb0_function_set_sqclr(pipe); - usb0_function_aclrm(pipe); - - /* init Global */ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - g_usb0_function_PipeDataSize[pipe] = 0; - } - } -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_EpToPipe -* Description : Returns the pipe which end point specified by the argument is -* : allocated to. -* Arguments : uint16_t ep ; Direction + Endpoint Number -* Return Value : USB_FUNCTION_EP_ERROR : Error -* : Others : Pipe Number -*******************************************************************************/ -uint16_t usb0_function_EpToPipe (uint16_t ep) -{ - uint16_t pipe; - - for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) - { - if ((g_usb0_function_PipeTbl[pipe] & 0x00ff) == ep) - { - return pipe; - } - } - - return USB_FUNCTION_EP_ERROR; -} - -/******************************************************************************* -* Function Name: usb0_function_InitEPTable -* Description : Sets the end point by the Alternate setting value of the -* : configuration number and the interface number specified by the -* : argument. -* Arguments : uint16_t Con_Num ; Configuration Number -* : uint16_t Int_Num ; Interface Number -* : uint16_t Alt_Num ; Alternate Setting -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num) -{ - uint8_t * ptr; - uint16_t point_interface; - uint16_t point_endpoint; - uint16_t length; - uint16_t start; - uint16_t numbers; - uint16_t endpoint; - - ptr = (uint8_t *)g_usb0_function_ConfigurationPtr[Con_Num - 1]; - point_interface = *ptr; - length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2)); - ptr += *ptr; - start = 0; - numbers = 0; - point_endpoint = 0; - - for (; point_interface < length;) - { - switch (*(ptr + 1)) /* Descriptor Type ? */ - { - case USB_FUNCTION_DT_INTERFACE: /* Interface */ - if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num)) - { - numbers = *(ptr + 4); - } - else - { - start += *(ptr + 4); - } - point_interface += *ptr; - ptr += *ptr; - break; - - case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ - if (point_endpoint < numbers) - { - endpoint = (uint16_t)(*(ptr + 2) & 0x0f); - g_usb0_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint); - ++point_endpoint; - } - point_interface += *ptr; - ptr += *ptr; - break; - - case USB_FUNCTION_DT_DEVICE: /* Device */ - case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ - case USB_FUNCTION_DT_STRING: /* String */ - default: /* Class, Vendor, else */ - point_interface += *ptr; - ptr += *ptr; - break; - } - } -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_GetConfigNum -* Description : Returns the number of configuration referring to the number of -* : configuration described in the device descriptor. -* Arguments : none -* Return Value : Number of possible configurations (bNumConfigurations). -*******************************************************************************/ -#if 0 -uint16_t usb0_function_GetConfigNum (void) -{ - return (uint16_t)g_usb0_function_DeviceDescriptor[17]; -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_GetInterfaceNum -* Description : Returns the number of interface referring to the number of -* : interface described in the configuration descriptor. -* Arguments : uint16_t num ; Configuration Number -* Return Value : Number of this interface (bNumInterfaces). -*******************************************************************************/ -#if 0 -uint16_t usb0_function_GetInterfaceNum (uint16_t num) -{ - return (uint16_t)(*(g_usb0_function_ConfigurationPtr[num - 1] + 4)); -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_GetAltNum -* Description : Returns the Alternate setting value of the configuration number -* : and the interface number specified by the argument. -* Arguments : uint16_t Con_Num ; Configuration Number -* : uint16_t Int_Num ; Interface Number -* Return Value : Value used to select this alternate setting(bAlternateSetting). -*******************************************************************************/ -#if 0 -uint16_t usb0_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num) -{ - uint8_t * ptr; - uint16_t point; - uint16_t alt_num = 0; - uint16_t length; - - ptr = (uint8_t *)(g_usb0_function_ConfigurationPtr[Con_Num - 1]); - point = ptr[0]; - ptr += ptr[0]; /* InterfaceDescriptor[0] */ - length = (uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 2)); - length |= (uint16_t)((uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8); - - for (; point < length;) /* Search Descriptor Table size */ - { - switch (ptr[1]) /* Descriptor Type ? */ - { - case USB_FUNCTION_DT_INTERFACE: /* Interface */ - if (Int_Num == ptr[2]) - { - alt_num = (uint16_t)ptr[3]; /* Alternate Number count */ - } - point += ptr[0]; - ptr += ptr[0]; - break; - - case USB_FUNCTION_DT_DEVICE: /* Device */ - case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ - case USB_FUNCTION_DT_STRING: /* String */ - case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ - default: /* Class, Vendor, else */ - point += ptr[0]; - ptr += ptr[0]; - break; - } - } - return alt_num; -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_CheckRemoteWakeup -* Description : Returns the result of the remote wake up function is supported -* : or not referring to the configuration descriptor. -* Arguments : none -* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup -* : DEVDRV_USBF_OFF : not Support Remote Wakeup -*******************************************************************************/ -#if 0 -uint16_t usb0_function_CheckRemoteWakeup (void) -{ - uint8_t atr; - - if (g_usb0_function_ConfigNum == 0) - { - return DEVDRV_USBF_OFF; - } - - atr = *(g_usb0_function_ConfigurationPtr[g_usb0_function_ConfigNum - 1] + 7); - - if (atr & USB_FUNCTION_CF_RWUP) - { - return DEVDRV_USBF_ON; - } - - return DEVDRV_USBF_OFF; -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_clear_alt -* Description : Initializes the Alternate setting area. -* Arguments : none -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_clear_alt (void) -{ - int i; - - for (i = 0; i < USB_FUNCTION_ALT_NO; ++i) - { - g_usb0_function_Alternate[i] = 0; /* Alternate */ - } -} -#endif - -/******************************************************************************* -* Function Name: usb0_function_clear_pipe_tbl -* Description : Initializes pipe definition table. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void usb0_function_clear_pipe_tbl (void) -{ - int pipe; - - for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) - { - g_usb0_function_PipeTbl[pipe] = 0; - } -} - -/******************************************************************************* -* Function Name: usb0_function_clear_ep_table_index -* Description : Initializes the end point table index. -* Arguments : none -* Return Value : none -*******************************************************************************/ -#if 0 -void usb0_function_clear_ep_table_index (void) -{ - int ep; - - for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) - { - g_usb0_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR; - } -} -#endif - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_dmacdrv.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_dmacdrv.c deleted file mode 100644 index 5b46b68ee9..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_dmacdrv.c +++ /dev/null @@ -1,698 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_dmacdrv.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include "r_typedefs.h" -#include "iodefine.h" -#include "rza_io_regrw.h" -#include "usb0_function_dmacdrv.h" - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ - -/* ==== Request setting information for on-chip peripheral module ==== */ -typedef enum dmac_peri_req_reg_type -{ - DMAC_REQ_MID, - DMAC_REQ_RID, - DMAC_REQ_AM, - DMAC_REQ_LVL, - DMAC_REQ_REQD -} dmac_peri_req_reg_type_t; - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ -/* ==== Prototype declaration ==== */ - -/* ==== Global variable ==== */ -/* On-chip peripheral module request setting table */ -static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] = -{ - /* MID,RID,AM,LVL,REQD */ - {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ - {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ - {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ - {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ - {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ - {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ - {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ - {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ -}; - - -/******************************************************************************* -* Function Name: usb0_function_DMAC1_PeriReqInit -* Description : Sets the register mode for DMA mode and the on-chip peripheral -* : module request for transfer request for DMAC channel 1. -* : Executes DMAC initial setting using the DMA information -* : specified by the argument *trans_info and the enabled/disabled -* : continuous transfer specified by the argument continuation. -* : Registers DMAC channel 1 interrupt handler function and sets -* : the interrupt priority level. Then enables transfer completion -* : interrupt. -* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register -* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) -* : uint32_t continuation : Set continuous transfer to be valid -* : after DMA transfer has been completed -* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer -* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer -* : uint32_t request_factor : Factor for on-chip peripheral module request -* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match -* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match -* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match -* : : -* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit -* Return Value : none -*******************************************************************************/ -void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, - uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction) -{ - /* ==== Register mode ==== */ - if (DMAC_MODE_REGISTER == dmamode) - { - /* ==== Next0 register set ==== */ - DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ - DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ - DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */ - - /* DAD : Transfer destination address counting direction */ - /* SAD : Transfer source address counting direction */ - /* DDS : Transfer destination transfer size */ - /* SDS : Transfer source transfer size */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->daddr_dir, - DMAC1_CHCFG_n_DAD_SHIFT, - DMAC1_CHCFG_n_DAD); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->saddr_dir, - DMAC1_CHCFG_n_SAD_SHIFT, - DMAC1_CHCFG_n_SAD); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->dst_size, - DMAC1_CHCFG_n_DDS_SHIFT, - DMAC1_CHCFG_n_DDS); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - trans_info->src_size, - DMAC1_CHCFG_n_SDS_SHIFT, - DMAC1_CHCFG_n_SDS); - - /* DMS : Register mode */ - /* RSEL : Select Next0 register set */ - /* SBE : No discharge of buffer data when aborted */ - /* DEM : No DMA interrupt mask */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_DMS_SHIFT, - DMAC1_CHCFG_n_DMS); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_RSEL_SHIFT, - DMAC1_CHCFG_n_RSEL); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_SBE_SHIFT, - DMAC1_CHCFG_n_SBE); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_DEM_SHIFT, - DMAC1_CHCFG_n_DEM); - - /* ---- Continuous transfer ---- */ - if (DMAC_SAMPLE_CONTINUATION == continuation) - { - /* REN : Execute continuous transfer */ - /* RSW : Change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_REN_SHIFT, - DMAC1_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_RSW_SHIFT, - DMAC1_CHCFG_n_RSW); - } - /* ---- Single transfer ---- */ - else - { - /* REN : Do not execute continuous transfer */ - /* RSW : Do not change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_REN_SHIFT, - DMAC1_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_RSW_SHIFT, - DMAC1_CHCFG_n_RSW); - } - - /* TM : Single transfer */ - /* SEL : Channel setting */ - /* HIEN, LOEN : On-chip peripheral module request */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_TM_SHIFT, - DMAC1_CHCFG_n_TM); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_SEL_SHIFT, - DMAC1_CHCFG_n_SEL); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 1, - DMAC1_CHCFG_n_HIEN_SHIFT, - DMAC1_CHCFG_n_HIEN); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - 0, - DMAC1_CHCFG_n_LOEN_SHIFT, - DMAC1_CHCFG_n_LOEN); - - /* ---- Set factor by specified on-chip peripheral module request ---- */ - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], - DMAC1_CHCFG_n_AM_SHIFT, - DMAC1_CHCFG_n_AM); - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], - DMAC1_CHCFG_n_LVL_SHIFT, - DMAC1_CHCFG_n_LVL); - - if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) - { - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], - DMAC1_CHCFG_n_REQD_SHIFT, - DMAC1_CHCFG_n_REQD); - } - else - { - RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, - req_direction, - DMAC1_CHCFG_n_REQD_SHIFT, - DMAC1_CHCFG_n_REQD); - } - - RZA_IO_RegWrite_32(&DMAC01.DMARS, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], - DMAC01_DMARS_CH1_RID_SHIFT, - DMAC01_DMARS_CH1_RID); - RZA_IO_RegWrite_32(&DMAC01.DMARS, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], - DMAC01_DMARS_CH1_MID_SHIFT, - DMAC01_DMARS_CH1_MID); - - /* PR : Round robin mode */ - RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, - 1, - DMAC07_DCTRL_0_7_PR_SHIFT, - DMAC07_DCTRL_0_7_PR); - } -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC1_Open -* Description : Enables DMAC channel 1 transfer. -* Arguments : uint32_t req : DMAC request mode -* Return Value : 0 : Succeeded in enabling DMA transfer -* : -1 : Failed to enable DMA transfer (due to DMA operation) -*******************************************************************************/ -int32_t usb0_function_DMAC1_Open (uint32_t req) -{ - int32_t ret; - volatile uint8_t dummy; - - /* Transferable? */ - if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_EN_SHIFT, - DMAC1_CHSTAT_n_EN)) && - (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_TACT_SHIFT, - DMAC1_CHSTAT_n_TACT))) - { - /* Clear Channel Status Register */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_SWRST_SHIFT, - DMAC1_CHCTRL_n_SWRST); - dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n, - DMAC1_CHCTRL_n_SWRST_SHIFT, - DMAC1_CHCTRL_n_SWRST); - /* Enable DMA transfer */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_SETEN_SHIFT, - DMAC1_CHCTRL_n_SETEN); - - /* ---- Request by software ---- */ - if (DMAC_REQ_MODE_SOFT == req) - { - /* DMA transfer Request by software */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_STG_SHIFT, - DMAC1_CHCTRL_n_STG); - } - - ret = 0; - } - else - { - ret = -1; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC1_Close -* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer -* : byte count at the time of DMA transfer abort to the argument -* : *remain. -* Arguments : uint32_t * remain : Remaining transfer byte count when -* : : DMA transfer is aborted -* Return Value : none -*******************************************************************************/ -void usb0_function_DMAC1_Close (uint32_t * remain) -{ - - /* ==== Abort transfer ==== */ - RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, - 1, - DMAC1_CHCTRL_n_CLREN_SHIFT, - DMAC1_CHCTRL_n_CLREN); - - while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_TACT_SHIFT, - DMAC1_CHSTAT_n_TACT)) - { - /* Loop until transfer is aborted */ - } - - while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_EN_SHIFT, - DMAC1_CHSTAT_n_EN)) - { - /* Loop until 0 is set in EN before checking the remaining transfer byte count */ - } - /* ==== Obtain remaining transfer byte count ==== */ - *remain = DMAC1.CRTB_n; -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC1_Load_Set -* Description : Sets the transfer source address, transfer destination -* : address, and total transfer byte count respectively -* : specified by the argument src_addr, dst_addr, and count to -* : DMAC channel 1 as DMA transfer information. -* : Sets the register set selected by the CHCFG_n register -* : RSEL bit from the Next0 or Next1 register set. -* : This function should be called when DMA transfer of DMAC -* : channel 1 is aboted. -* Arguments : uint32_t src_addr : Transfer source address -* : uint32_t dst_addr : Transfer destination address -* : uint32_t count : Total transfer byte count -* Return Value : none -*******************************************************************************/ -void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) -{ - uint8_t reg_set; - - /* Obtain register set in use */ - reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, - DMAC1_CHSTAT_n_SR_SHIFT, - DMAC1_CHSTAT_n_SR); - - /* ==== Load ==== */ - if (0 == reg_set) - { - /* ---- Next0 Register Set ---- */ - DMAC1.N0SA_n = src_addr; /* Start address of transfer source */ - DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */ - DMAC1.N0TB_n = count; /* Total transfer byte count */ - } - else - { - /* ---- Next1 Register Set ---- */ - DMAC1.N1SA_n = src_addr; /* Start address of transfer source */ - DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */ - DMAC1.N1TB_n = count; /* Total transfer byte count */ - } -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC2_PeriReqInit -* Description : Sets the register mode for DMA mode and the on-chip peripheral -* : module request for transfer request for DMAC channel 2. -* : Executes DMAC initial setting using the DMA information -* : specified by the argument *trans_info and the enabled/disabled -* : continuous transfer specified by the argument continuation. -* : Registers DMAC channel 2 interrupt handler function and sets -* : the interrupt priority level. Then enables transfer completion -* : interrupt. -* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC -* : : register -* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) -* : uint32_t continuation : Set continuous transfer to be valid -* : : after DMA transfer has been completed -* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer -* : DMAC_SAMPLE_SINGLE : Do not execute continuous -* : : transfer -* : uint32_t request_factor : Factor for on-chip peripheral module -* : : request -* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match -* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match -* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match -* : : -* : uint32_t req_direction : Setting value of CHCFG_n register -* : : REQD bit -*******************************************************************************/ -void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, - uint32_t dmamode, uint32_t continuation, - uint32_t request_factor, uint32_t req_direction) -{ - /* ==== Register mode ==== */ - if (DMAC_MODE_REGISTER == dmamode) - { - /* ==== Next0 register set ==== */ - DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ - DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ - DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */ - - /* DAD : Transfer destination address counting direction */ - /* SAD : Transfer source address counting direction */ - /* DDS : Transfer destination transfer size */ - /* SDS : Transfer source transfer size */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->daddr_dir, - DMAC2_CHCFG_n_DAD_SHIFT, - DMAC2_CHCFG_n_DAD); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->saddr_dir, - DMAC2_CHCFG_n_SAD_SHIFT, - DMAC2_CHCFG_n_SAD); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->dst_size, - DMAC2_CHCFG_n_DDS_SHIFT, - DMAC2_CHCFG_n_DDS); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - trans_info->src_size, - DMAC2_CHCFG_n_SDS_SHIFT, - DMAC2_CHCFG_n_SDS); - - /* DMS : Register mode */ - /* RSEL : Select Next0 register set */ - /* SBE : No discharge of buffer data when aborted */ - /* DEM : No DMA interrupt mask */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_DMS_SHIFT, - DMAC2_CHCFG_n_DMS); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_RSEL_SHIFT, - DMAC2_CHCFG_n_RSEL); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_SBE_SHIFT, - DMAC2_CHCFG_n_SBE); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_DEM_SHIFT, - DMAC2_CHCFG_n_DEM); - - /* ---- Continuous transfer ---- */ - if (DMAC_SAMPLE_CONTINUATION == continuation) - { - /* REN : Execute continuous transfer */ - /* RSW : Change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_REN_SHIFT, - DMAC2_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_RSW_SHIFT, - DMAC2_CHCFG_n_RSW); - } - /* ---- Single transfer ---- */ - else - { - /* REN : Do not execute continuous transfer */ - /* RSW : Do not change register set when DMA transfer is completed. */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_REN_SHIFT, - DMAC2_CHCFG_n_REN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_RSW_SHIFT, - DMAC2_CHCFG_n_RSW); - } - - /* TM : Single transfer */ - /* SEL : Channel setting */ - /* HIEN, LOEN : On-chip peripheral module request */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_TM_SHIFT, - DMAC2_CHCFG_n_TM); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 2, - DMAC2_CHCFG_n_SEL_SHIFT, - DMAC2_CHCFG_n_SEL); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 1, - DMAC2_CHCFG_n_HIEN_SHIFT, - DMAC2_CHCFG_n_HIEN); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - 0, - DMAC2_CHCFG_n_LOEN_SHIFT, - DMAC2_CHCFG_n_LOEN); - - /* ---- Set factor by specified on-chip peripheral module request ---- */ - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], - DMAC2_CHCFG_n_AM_SHIFT, - DMAC2_CHCFG_n_AM); - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], - DMAC2_CHCFG_n_LVL_SHIFT, - DMAC2_CHCFG_n_LVL); - if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) - { - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], - DMAC2_CHCFG_n_REQD_SHIFT, - DMAC2_CHCFG_n_REQD); - } - else - { - RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, - req_direction, - DMAC2_CHCFG_n_REQD_SHIFT, - DMAC2_CHCFG_n_REQD); - } - RZA_IO_RegWrite_32(&DMAC23.DMARS, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], - DMAC23_DMARS_CH2_RID_SHIFT, - DMAC23_DMARS_CH2_RID); - RZA_IO_RegWrite_32(&DMAC23.DMARS, - usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], - DMAC23_DMARS_CH2_MID_SHIFT, - DMAC23_DMARS_CH2_MID); - - /* PR : Round robin mode */ - RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, - 1, - DMAC07_DCTRL_0_7_PR_SHIFT, - DMAC07_DCTRL_0_7_PR); - } -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC2_Open -* Description : Enables DMAC channel 2 transfer. -* Arguments : uint32_t req : DMAC request mode -* Return Value : 0 : Succeeded in enabling DMA transfer -* : -1 : Failed to enable DMA transfer (due to DMA operation) -*******************************************************************************/ -int32_t usb0_function_DMAC2_Open (uint32_t req) -{ - int32_t ret; - volatile uint8_t dummy; - - /* Transferable? */ - if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2, - DMAC2_CHSTAT_n_EN_SHIFT, - DMAC2_CHSTAT_n_EN)) && - (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2, - DMAC2_CHSTAT_n_TACT_SHIFT, - DMAC2_CHSTAT_n_TACT))) - { - /* Clear Channel Status Register */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_SWRST_SHIFT, - DMAC2_CHCTRL_n_SWRST); - dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n, - DMAC2_CHCTRL_n_SWRST_SHIFT, - DMAC2_CHCTRL_n_SWRST); - /* Enable DMA transfer */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_SETEN_SHIFT, - DMAC2_CHCTRL_n_SETEN); - - /* ---- Request by software ---- */ - if (DMAC_REQ_MODE_SOFT == req) - { - /* DMA transfer Request by software */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_STG_SHIFT, - DMAC2_CHCTRL_n_STG); - } - - ret = 0; - } - else - { - ret = -1; - } - - return ret; -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC2_Close -* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer -* : byte count at the time of DMA transfer abort to the argument -* : *remain. -* Arguments : uint32_t * remain : Remaining transfer byte count when -* : : DMA transfer is aborted -* Return Value : none -*******************************************************************************/ -void usb0_function_DMAC2_Close (uint32_t * remain) -{ - - /* ==== Abort transfer ==== */ - RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, - 1, - DMAC2_CHCTRL_n_CLREN_SHIFT, - DMAC2_CHCTRL_n_CLREN); - - while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_TACT_SHIFT, - DMAC2_CHSTAT_n_TACT)) - { - /* Loop until transfer is aborted */ - } - - while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_EN_SHIFT, - DMAC2_CHSTAT_n_EN)) - { - /* Loop until 0 is set in EN before checking the remaining transfer byte count */ - } - /* ==== Obtain remaining transfer byte count ==== */ - *remain = DMAC2.CRTB_n; -} - -/******************************************************************************* -* Function Name: usb0_function_DMAC2_Load_Set -* Description : Sets the transfer source address, transfer destination -* : address, and total transfer byte count respectively -* : specified by the argument src_addr, dst_addr, and count to -* : DMAC channel 2 as DMA transfer information. -* : Sets the register set selected by the CHCFG_n register -* : RSEL bit from the Next0 or Next1 register set. -* : This function should be called when DMA transfer of DMAC -* : channel 2 is aboted. -* Arguments : uint32_t src_addr : Transfer source address -* : uint32_t dst_addr : Transfer destination address -* : uint32_t count : Total transfer byte count -* Return Value : none -*******************************************************************************/ -void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) -{ - uint8_t reg_set; - - /* Obtain register set in use */ - reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, - DMAC2_CHSTAT_n_SR_SHIFT, - DMAC2_CHSTAT_n_SR); - - /* ==== Load ==== */ - if (0 == reg_set) - { - /* ---- Next0 Register Set ---- */ - DMAC2.N0SA_n = src_addr; /* Start address of transfer source */ - DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */ - DMAC2.N0TB_n = count; /* Total transfer byte count */ - } - else - { - /* ---- Next1 Register Set ---- */ - DMAC2.N1SA_n = src_addr; /* Start address of transfer source */ - DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */ - DMAC2.N1TB_n = count; /* Total transfer byte count */ - } -} - -/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_userdef.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_userdef.c deleted file mode 100644 index 5449f60c70..0000000000 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_userdef.c +++ /dev/null @@ -1,762 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb0_function_userdef.c -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Device(s) : RZ/A1H -* Tool-Chain : -* OS : None -* H/W Platform : -* Description : RZ/A1H R7S72100 USB Sample Program -* Operation : -* Limitations : -*******************************************************************************/ - - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include "r_typedefs.h" -#include "iodefine.h" -#include "devdrv_usb_function_api.h" -#include "usb0_function_dmacdrv.h" /* common DMAC driver for USB */ - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define DUMMY_ACCESS OSTM0CNT - -/* #define CACHE_WRITEBACK */ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -extern int32_t io_cwb(unsigned long start, unsigned long end); - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -static void usb0_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); -static void usb0_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); -static void Userdef_USB_usb0_function_delay_10us_2(void); - - -/******************************************************************************* -Private global variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_d0fifo_dmaintid -* Description : get D0FIFO DMA Interrupt ID -* Arguments : none -* Return Value : D0FIFO DMA Interrupt ID -*******************************************************************************/ -IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid (void) -{ -#if 0 - return DMAINT1_IRQn; -#else - return 0xFFFF; -#endif -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_d1fifo_dmaintid -* Description : get D1FIFO DMA Interrupt ID -* Arguments : none -* Return Value : D1FIFO DMA Interrupt ID -*******************************************************************************/ -IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid (void) -{ -#if 0 - return DMAINT1_IRQn; -#else - return 0xFFFF; -#endif -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_attach -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_attach (void) -{ - printf("\n"); - printf("channel 0 attach device\n"); - printf("\n"); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_detach -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_detach (void) -{ - printf("\n"); - printf("channel 0 detach device\n"); - printf("\n"); -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_delay_1ms -* Description : Wait for the software of 1ms. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_delay_1ms (void) -{ - volatile int i; - volatile unsigned long tmp; - - /* - * Wait 1ms (Please change for your MCU). - */ - for (i = 0; i < 1440; ++i) - { - tmp = DUMMY_ACCESS; - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_delay_xms -* Description : Wait for the software in the period of time specified by the -* : argument. -* : Alter this function according to the user's system. -* Arguments : uint32_t msec ; Wait Time (msec) -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_delay_xms (uint32_t msec) -{ - volatile unsigned short i; - - for (i = 0; i < msec; ++i) - { - Userdef_USB_usb0_function_delay_1ms(); - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_delay_10us -* Description : Waits for software for the period specified by the argument. -* : Alter this function according to the user's system. -* Arguments : uint32_t usec ; Wait Time(x 10usec) -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_delay_10us (uint32_t usec) -{ - volatile int i; - - /* Wait 10us (Please change for your MCU) */ - for (i = 0; i < usec; ++i) - { - Userdef_USB_usb0_function_delay_10us_2(); - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_delay_10us_2 -* Description : Waits for software for the period specified by the argument. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -static void Userdef_USB_usb0_function_delay_10us_2 (void) -{ - volatile int i; - volatile unsigned long tmp; - - /* Wait 1us (Please change for your MCU) */ - for (i = 0; i < 14; ++i) - { - tmp = DUMMY_ACCESS; - } -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_delay_500ns -* Description : Wait for software for 500ns. -* : Alter this function according to the user's system. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_delay_500ns (void) -{ - volatile int i; - volatile unsigned long tmp; - - /* Wait 500ns (Please change for your MCU) */ - /* Wait 500ns I clock 266MHz */ - tmp = DUMMY_ACCESS; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_start_dma -* Description : Enables DMA transfer on the information specified by the argument. -* : Set DMAC register by this function to enable DMA transfer. -* : After executing this function, USB module is set to start DMA -* : transfer. DMA transfer should not wait for DMA transfer complete. -* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter -* : typedef struct{ -* : uint32_t fifo; FIFO for using -* : uint32_t buffer; Start address of transfer source/destination -* : uint32_t bytes; Transfer size(Byte) -* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) -* : uint32_t size; DMA transfer size -* : } USB_FUNCTION_DMA_t; -* : uint16_t dfacc ; 0 : cycle steal mode -* : 1 : 16byte continuous mode -* : 2 : 32byte continuous mode -* Return Value : none -*******************************************************************************/ -void Userdef_USB_usb0_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc) -{ - uint32_t trncount; - uint32_t src; - uint32_t dst; - uint32_t size; - uint32_t dir; -#ifdef CACHE_WRITEBACK - uint32_t ptr; -#endif - - trncount = dma->bytes; - dir = dma->dir; - - if (dir == USB_FUNCTION_FIFO2BUF) - { - /* DxFIFO determination */ - dst = dma->buffer; -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - size = dma->size; - - if (size == 0) - { - src += 3; /* byte access */ - } - else if (size == 1) - { - src += 2; /* short access */ - } - else - { - /* Do Nothing */ - } -#else - size = dma->size; - - if (size == 2) - { - /* 32bit access */ - if (dfacc == 2) - { - /* 32byte access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - src = (uint32_t)(&USB200.D1FIFOB0); - } - } - else if (dfacc == 1) - { - /* 16byte access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - src = (uint32_t)(&USB200.D1FIFOB0); - } - } - else - { - /* normal access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - } - } - else if (size == 1) - { - /* 16bit access */ - dfacc = 0; /* force normal access */ - - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - src += 2; /* short access */ - } - else - { - /* 8bit access */ - dfacc = 0; /* force normal access */ - - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - src = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - src = (uint32_t)(&USB200.D1FIFO.UINT32); - } - src += 3; /* byte access */ - } -#endif - } - else - { - /* DxFIFO determination */ - src = dma->buffer; -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - size = dma->size; - - if (size == 0) - { - dst += 3; /* byte access */ - } - else if (size == 1) - { - dst += 2; /* short access */ - } - else - { - /* Do Nothing */ - } -#else - size = dma->size; - - if (size == 2) - { - /* 32bit access */ - if (dfacc == 2) - { - /* 32byte access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - dst = (uint32_t)(&USB200.D1FIFOB0); - } - } - else if (dfacc == 1) - { - /* 16byte access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFOB0); - } - else - { - dst = (uint32_t)(&USB200.D1FIFOB0); - } - } - else - { - /* normal access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - } - } - else if (size == 1) - { - /* 16bit access */ - dfacc = 0; /* force normal access */ - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - dst += 2; /* short access */ - } - else - { - /* 8bit access */ - dfacc = 0; /* force normal access */ - - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - dst = (uint32_t)(&USB200.D0FIFO.UINT32); - } - else - { - dst = (uint32_t)(&USB200.D1FIFO.UINT32); - } - dst += 3; /* byte access */ - } -#endif - } - -#ifdef CACHE_WRITEBACK - ptr = (uint32_t)dma->buffer; - - if ((ptr & 0x20000000ul) == 0) - { - io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount); - } -#endif - - if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) - { - usb0_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); - } - else - { - usb0_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); - } -} - -/******************************************************************************* -* Function Name: usb0_function_enable_dmac0 -* Description : Enables DMA transfer on the information specified by the argument. -* Arguments : uint32_t src : src address -* : uint32_t dst : dst address -* : uint32_t count : transfer byte -* : uint32_t size : transfer size -* : uint32_t dir : direction -* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) -* : uint16_t dfacc : 0 : normal access -* : : 1 : 16byte access -* : : 2 : 32byte access -* Return Value : none -*******************************************************************************/ -static void usb0_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) -{ - dmac_transinfo_t trans_info; - uint32_t request_factor = 0; - int32_t ret; - - /* ==== Variable setting for DMAC initialization ==== */ - trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ - trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ - trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { - printf("size error!!\n"); - } -#else - if (dfacc == 2) - { - /* 32byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ - } - else if (dfacc == 1) - { - /* 16byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ - } - else - { - /* normal access */ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { - printf("size error!!\n"); - } - } -#endif - - if (dir == USB_FUNCTION_FIFO2BUF) - { - request_factor =DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ - trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ - } - else if (dir == USB_FUNCTION_BUF2FIFO) - { - request_factor =DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ - trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ - } - else - { - /* Do Nothing */ - } - - /* ==== DMAC initialization ==== */ - usb0_function_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info, - DMAC_MODE_REGISTER, - DMAC_SAMPLE_SINGLE, - request_factor, - 0); /* Don't care DMAC_REQ_REQD is setting in - usb0_function_DMAC1_PeriReqInit() */ - - /* ==== DMAC startup ==== */ - ret = usb0_function_DMAC1_Open(DMAC_REQ_MODE_PERI); - if (ret != 0) - { - printf("DMAC1 Open error!!\n"); - } - - return; -} - -/******************************************************************************* -* Function Name: usb0_function_enable_dmac1 -* Description : Enables DMA transfer on the information specified by the argument. -* Arguments : uint32_t src : src address -* : uint32_t dst : dst address -* : uint32_t count : transfer byte -* : uint32_t size : transfer size -* : uint32_t dir : direction -* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) -* : uint16_t dfacc : 0 : normal access -* : : 1 : 16byte access -* : : 2 : 32byte access -* Return Value : none -*******************************************************************************/ -static void usb0_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, - uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) -{ - dmac_transinfo_t trans_info; - uint32_t request_factor = 0; - int32_t ret; - - /* ==== Variable setting for DMAC initialization ==== */ - trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ - trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ - trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ -#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { - printf("size error!!\n"); - } -#else - if (dfacc == 2) - { - /* 32byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ - } - else if (dfacc == 1) - { - /* 16byte access */ - trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ - } - else - { - /* normal access */ - if (size == 0) - { - trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ - } - else if (size == 1) - { - trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ - } - else if (size == 2) - { - trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ - trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ - } - else - { - printf("size error!!\n"); - } - } -#endif - - if (dir == USB_FUNCTION_FIFO2BUF) - { - request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ - trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ - } - else if (dir == USB_FUNCTION_BUF2FIFO) - { - request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ - trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ - trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ - } - else - { - /* Do Nothing */ - } - - /* ==== DMAC initialization ==== */ - usb0_function_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info, - DMAC_MODE_REGISTER, - DMAC_SAMPLE_SINGLE, - request_factor, - 0); /* Don't care DMAC_REQ_REQD is setting in - usb0_function_DMAC1_PeriReqInit() */ - - /* ==== DMAC startup ==== */ - ret = usb0_function_DMAC2_Open(DMAC_REQ_MODE_PERI); - if (ret != 0) - { - printf("DMAC2 Open error!!\n"); - } - - return; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_stop_dma0 -* Description : Disables DMA transfer. -* : This function should be executed to DMAC executed at the time -* : of specification of D0_FIF0_DMA in dma->fifo. -* Arguments : none -* Return Value : uint32_t return Transfer Counter register(DMATCRn) value -* : regarding to the bus width. -*******************************************************************************/ -uint32_t Userdef_USB_usb0_function_stop_dma0 (void) -{ - uint32_t remain; - - /* ==== DMAC release ==== */ - usb0_function_DMAC1_Close(&remain); - - return remain; -} - -/******************************************************************************* -* Function Name: Userdef_USB_usb0_function_stop_dma1 -* Description : Disables DMA transfer. -* : This function should be executed to DMAC executed at the time -* : of specification of D1_FIF0_DMA in dma->fifo. -* Arguments : none -* Return Value : uint32_t return Transfer Counter register(DMATCRn) value -* : regarding to the bus width. -*******************************************************************************/ -uint32_t Userdef_USB_usb0_function_stop_dma1 (void) -{ - uint32_t remain; - - /* ==== DMAC release ==== */ - usb0_function_DMAC2_Close(&remain); - - return remain; -} - -/* End of File */ From 6e7d45db00c519ea6f98c9a3975445d494a06af2 Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:11:46 +0900 Subject: [PATCH 029/143] Add 2Port function to USBHost(usb0). --- .../TARGET_RZ_A1H/inc/devdrv_usb_host_api.h | 3 - .../TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c | 713 ++++- .../TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h | 46 +- .../TARGET_RZ_A1H/ohci_wrapp_pipe.c | 190 ++ .../TARGET_RZ_A1H/usb0/inc/usb0_host.h | 156 + .../TARGET_RZ_A1H/usb0/inc/usb0_host_api.h | 112 + .../usb0/inc/usb0_host_dmacdrv.h | 139 + .../usb0/src/common/usb0_host_dataio.c | 2835 +++++++++++++++++ .../usb0/src/common/usb0_host_dma.c | 355 +++ .../usb0/src/common/usb0_host_intrn.c | 285 ++ .../usb0/src/common/usb0_host_lib.c | 1580 +++++++++ .../usb0/src/host/usb0_host_controlrw.c | 434 +++ .../usb0/src/host/usb0_host_drv_api.c | 889 ++++++ .../usb0/src/host/usb0_host_global.c | 137 + .../usb0/src/host/usb0_host_usbint.c | 496 +++ .../usb0/src/host/usb0_host_usbsig.c | 637 ++++ .../usb0/src/userdef/usb0_host_dmacdrv.c | 698 ++++ .../usb0/src/userdef/usb0_host_userdef.c | 778 +++++ .../TARGET_RZ_A1H/usb_host_setting.h | 100 + .../USBHost/USBHost/USBHALHost_RZ_A1.cpp | 5 +- 20 files changed, 10419 insertions(+), 169 deletions(-) create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h index eb08292c99..fbbf066e3f 100644 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h @@ -286,10 +286,7 @@ void R_USB_api_host_elt_get_desc(uint16_t root); Includes , "Project Includes" *******************************************************************************/ #include "usb0_host_api.h" -#if(1) /* ohci_wrapp */ -#else #include "usb1_host_api.h" -#endif /******************************************************************************* diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c index e1a96e60fe..0b1b7da656 100644 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c @@ -21,12 +21,12 @@ #include "cmsis_os.h" #include "ohci_wrapp_RZ_A1.h" #include "ohci_wrapp_RZ_A1_local.h" - #include "rza_io_regrw.h" -#include "usb0_host.h" +#include "usb_host_setting.h" /* ------------------ HcControl Register --------------------- */ #define OR_CONTROL_PLE (0x00000004) +#define OR_CONTROL_IE (0x00000008) #define OR_CONTROL_CLE (0x00000010) #define OR_CONTROL_BLE (0x00000020) /* ----------------- HcCommandStatus Register ----------------- */ @@ -47,6 +47,7 @@ #define OR_RH_PORT_POCI (0x00000008) #define OR_RH_PORT_CCS (0x00000001) +#define ED_FORMAT (0x00008000) /* Format */ #define ED_SKIP (0x00004000) /* Skip this ep in queue */ #define ED_TOGLE_CARRY (0x00000002) #define ED_HALTED (0x00000001) @@ -70,11 +71,16 @@ #define TD_CTL_SHFT_T (24) #define ED_SHFT_TOGLE_CARRY (1) #define SIG_GEN_LIST_REQ (1) +#if (ISO_TRANS_MAX_NUM > 0) +#define TD_PSW_MSK_CC (0xF000) +#define TD_PSW_SHFT_CC (12) +#define TD_CTL_MSK_FC (0x07000000) +#define TD_CTL_SHFT_FC (24) +#endif #define CTL_TRANS_TIMEOUT (1000) #define BLK_TRANS_TIMEOUT (5) -#define INT_TRANS_MAX_NUM (4) /* min:1 max:4 */ -#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM)) +#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM)) #define PORT_LOW_SPEED (0x00000200) #define PORT_HIGH_SPEED (0x00000400) @@ -87,10 +93,21 @@ typedef struct tag_hctd { uint8_t *bufEnd; /* Physical address of end of buffer */ } hctd_t; +#if (ISO_TRANS_MAX_NUM > 0) +#define PSW_NUM (8) +typedef struct tag_hcisotd { + uint32_t control; /* Transfer descriptor control */ + uint8_t *bufferPage0; /* Buffer Page 0 */ + struct tag_hcisotd *nextTD; /* Physical pointer to next Transfer Descriptor */ + uint8_t *bufEnd; /* Physical address of end of buffer */ + uint16_t offsetPSW[PSW_NUM]; /* Offset/PSW */ +} hcisotd_t; +#endif + typedef struct tag_hced { uint32_t control; /* Endpoint descriptor control */ - hctd_t *tailTD; /* Physical address of tail in Transfer descriptor list */ - hctd_t *headTD; /* Physcial address of head in Transfer descriptor list */ + uint32_t tailTD; /* Physical address of tail in Transfer descriptor list */ + uint32_t headTD; /* Physcial address of head in Transfer descriptor list */ struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */ } hced_t; @@ -131,12 +148,15 @@ typedef struct tag_genelal_ed { osThreadId tskid; osSemaphoreId semid_wait; osSemaphoreId semid_list; - hctd_t *p_curr_td; + void *p_curr_td; /* pointer of hctd_t or hcisotd_t */ hced_t *p_curr_ed; uint32_t pipe_no; uint32_t trans_wait; uint32_t cycle_time; uint8_t *p_start_buf; +#if (ISO_TRANS_MAX_NUM > 0) + uint32_t psw_idx; +#endif } genelal_ed_t; typedef struct tag_tdinfo { @@ -163,7 +183,7 @@ static void bulk_ed_task(void const * argument); static void int_ed_task(void const * argument); static int32_t int_trans_doing(hced_t *p_ed, uint32_t index); static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed); -static void chk_td_done(genelal_ed_t *p_g_ed); +static void chk_genelal_td_done(genelal_ed_t *p_g_ed); static void chk_split_trans_setting(genelal_ed_t *p_g_ed); static void set_split_trans_setting(void); static void control_trans(genelal_ed_t *p_g_ed); @@ -173,10 +193,22 @@ static uint32_t chk_cycle(hced_t *p_ed); static void int_trans(genelal_ed_t *p_g_ed); static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info); static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed); +#if (ISO_TRANS_MAX_NUM > 0) +static void iso_ed_task(void const * argument); +static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index); +static void chk_iso_td_done(genelal_ed_t *p_g_ed); +static int32_t chk_iso_ed(genelal_ed_t *p_g_ed); +static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index); +static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed); +static void iso_trans(genelal_ed_t *p_g_ed); +#endif static void connect_check(void); -extern USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[]; -extern USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[]; +extern USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[]; +extern USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[]; +#if (ISO_TRANS_MAX_NUM > 0) +extern USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[]; +#endif static usb_ohci_reg_t usb_reg; static usb_ohci_reg_t *p_usb_reg = &usb_reg; @@ -189,6 +221,10 @@ static genelal_ed_t blk_ed; static genelal_ed_t int_ed[INT_TRANS_MAX_NUM]; static split_trans_t split_ctl; +#if (ISO_TRANS_MAX_NUM > 0) +static genelal_ed_t iso_ed[ISO_TRANS_MAX_NUM]; +#endif + osSemaphoreDef(ohciwrapp_sem_01); osSemaphoreDef(ohciwrapp_sem_02); osSemaphoreDef(ohciwrapp_sem_03); @@ -208,13 +244,55 @@ osSemaphoreDef(ohciwrapp_sem_11); osSemaphoreDef(ohciwrapp_sem_12); osSemaphoreDef(ohciwrapp_sem_13); #endif +#if (ISO_TRANS_MAX_NUM >= 1) +osSemaphoreDef(ohciwrapp_sem_14); +osSemaphoreDef(ohciwrapp_sem_15); +#endif +#if (ISO_TRANS_MAX_NUM >= 2) +osSemaphoreDef(ohciwrapp_sem_16); +osSemaphoreDef(ohciwrapp_sem_17); +#endif osThreadDef(callback_task, osPriorityHigh, 512); osThreadDef(control_ed_task, osPriorityNormal, 512); osThreadDef(bulk_ed_task, osPriorityNormal, 512); -osThreadDef(int_ed_task, osPriorityAboveNormal, 512); +static void int_ed_task_1(void const * argument) { + int_ed_task(argument); +} +osThreadDef(int_ed_task_1, osPriorityNormal, 512); +#if (INT_TRANS_MAX_NUM >= 2) +static void int_ed_task_2(void const * argument) { + int_ed_task(argument); +} +osThreadDef(int_ed_task_2, osPriorityNormal, 512); +#endif +#if (INT_TRANS_MAX_NUM >= 3) +static void int_ed_task_3(void const * argument) { + int_ed_task(argument); +} +osThreadDef(int_ed_task_3, osPriorityNormal, 512); +#endif +#if (INT_TRANS_MAX_NUM >= 4) +static void int_ed_task_4(void const * argument) { + int_ed_task(argument); +} +osThreadDef(int_ed_task_4, osPriorityNormal, 512); +#endif -void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) { +#if (ISO_TRANS_MAX_NUM >= 1) +static void iso_ed_task_1(void const * argument) { + iso_ed_task(argument); +} +osThreadDef(iso_ed_task_1, osPriorityNormal, 512); +#endif +#if (ISO_TRANS_MAX_NUM >= 2) +static void iso_ed_task_2(void const * argument) { + iso_ed_task(argument); +} +osThreadDef(iso_ed_task_2, osPriorityNormal, 512); +#endif + +void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) { static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = { osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03) , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06) @@ -227,25 +305,54 @@ void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) { #endif #if (INT_TRANS_MAX_NUM >= 4) , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13) +#endif +#if (ISO_TRANS_MAX_NUM >= 1) + , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15) +#endif +#if (ISO_TRANS_MAX_NUM >= 2) + , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17) #endif }; + static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = { + osThread(int_ed_task_1) +#if (INT_TRANS_MAX_NUM >= 2) + , osThread(int_ed_task_2) +#endif +#if (INT_TRANS_MAX_NUM >= 3) + , osThread(int_ed_task_3) +#endif +#if (INT_TRANS_MAX_NUM >= 4) + , osThread(int_ed_task_4) +#endif + }; +#if (ISO_TRANS_MAX_NUM > 0) + static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = { + osThread(iso_ed_task_1) +#if (ISO_TRANS_MAX_NUM >= 2) + , osThread(iso_ed_task_2) +#endif + }; +#endif + uint32_t cnt; uint32_t index = 0; /* Disables interrupt for usb */ - GIC_DisableIRQ(USBI0_IRQn); + GIC_DisableIRQ(USBIXUSBIX); +#if (USB_HOST_CH == 0) /* P4_1(USB0_EN) */ GPIOP4 &= ~0x0002; /* Outputs low level */ GPIOPMC4 &= ~0x0002; /* Port mode */ GPIOPM4 &= ~0x0002; /* Output mode */ +#endif p_usbisr_cb = p_usbisr_fnc; - if (hi_speed == 0) { - g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED; - } else { - g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED; - } +#if (USB_HOST_HISPEED == 0) + g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED; +#else + g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED; +#endif p_usb_reg->HcRevision = 0x00000010; p_usb_reg->HcControl = 0x00000000; p_usb_reg->HcCommandStatus = 0x00000000; @@ -269,15 +376,22 @@ void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) { p_usb_reg->HcRhStatus = 0x00000000; p_usb_reg->HcRhPortStatus1 = 0x00000000; +#if (USB_HOST_CH == 0) GPIOP4 |= 0x0002; /* P4_1 Outputs high level */ osDelay(5); GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */ osDelay(10); +#else + osDelay(15); +#endif if (init_end == 0) { (void)memset(&ctl_ed, 0, sizeof(ctl_ed)); (void)memset(&blk_ed, 0, sizeof(blk_ed)); (void)memset(&int_ed[0], 0, sizeof(int_ed)); +#if (ISO_TRANS_MAX_NUM > 0) + (void)memset(&iso_ed[0], 0, sizeof(iso_ed)); +#endif /* callback */ semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0); @@ -304,8 +418,19 @@ void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) { index++; int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0); index++; - int_ed[cnt].tskid = osThreadCreate(osThread(int_ed_task), (void *)cnt); + int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt); } + +#if (ISO_TRANS_MAX_NUM > 0) + /* isochronous transfer */ + for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) { + iso_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + iso_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0); + index++; + iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt); + } +#endif init_end = 1; } } @@ -355,6 +480,22 @@ void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) { (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever); } } +#if (ISO_TRANS_MAX_NUM > 0) + if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) { + /* change IE */ + for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) { + if ((set_data & OR_CONTROL_IE) != 0) { + (void)osSemaphoreRelease(iso_ed[cnt].semid_list); + } else { + if (iso_ed[cnt].trans_wait == 1) { + iso_ed[cnt].trans_wait = 0; + (void)osSemaphoreRelease(iso_ed[cnt].semid_wait); + } + (void)osSemaphoreWait(iso_ed[cnt].semid_list, osWaitForever); + } + } + } +#endif if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) { /* change PLE */ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) { @@ -373,7 +514,7 @@ void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) { case OHCI_REG_COMMANDSTATUS: if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR; - if (usb0_api_host_init(16, g_usb0_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) { + if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) { ohciwrapp_loc_Connect(1); } p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR; @@ -429,7 +570,7 @@ void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) { p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000); if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */ p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS; - usb0_host_UsbBusReset(); + usbx_host_UsbBusReset(); p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS; } break; @@ -474,9 +615,7 @@ static void control_ed_task(void const * argument) { ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED; if (chk_genelal_ed(&ctl_ed) != 0) { control_trans(&ctl_ed); - chk_split_trans_setting(&ctl_ed); p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF; - chk_td_done(&ctl_ed); } p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED; } else { @@ -505,7 +644,6 @@ static void bulk_ed_task(void const * argument) { if (chk_genelal_ed(&blk_ed) != 0) { bulk_trans(&blk_ed); p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF; - chk_td_done(&blk_ed); } p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED; } else { @@ -551,7 +689,8 @@ static void int_ed_task(void const * argument) { while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) { if (chk_genelal_ed(p_int_ed) != 0) { int_trans(p_int_ed); - chk_td_done(p_int_ed); + (void)osSemaphoreWait(p_int_ed->semid_wait, osWaitForever); + usbx_host_stop_transfer(p_int_ed->pipe_no); wait_cnt = p_int_ed->cycle_time; } else { if (wait_cnt > 0) { @@ -590,17 +729,20 @@ static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){ hced_t *p_ed = p_g_ed->p_curr_ed; if (((p_ed->control & ED_SKIP) != 0) - || (((uint32_t)p_ed->headTD & ED_HALTED) != 0) - || (((uint32_t)p_ed->tailTD & 0xFFFFFFF0) == ((uint32_t)p_ed->headTD & 0xFFFFFFF0))) { + || ((p_ed->control & ED_FORMAT) != 0) + || ((p_ed->headTD & ED_HALTED) != 0) + || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) { /* Do Nothing */ } else if ((p_ed->control & 0x0000007F) > 10) { - p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED); + p_ed->headTD |= ED_HALTED; } else { - p_g_ed->p_curr_td = (hctd_t *)((uint32_t)p_ed->headTD & 0xFFFFFFF0); + p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0); if (p_g_ed->p_curr_td == NULL) { - p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED); + p_ed->headTD |= ED_HALTED; } else { - p_g_ed->p_start_buf = p_g_ed->p_curr_td->currBufPtr; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; + + p_g_ed->p_start_buf = p_td->currBufPtr; ret = 1; } } @@ -608,14 +750,15 @@ static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){ return ret; } -static void chk_td_done(genelal_ed_t *p_g_ed) { +static void chk_genelal_td_done(genelal_ed_t *p_g_ed) { hcca_t *p_hcca; - uint32_t ConditionCode = RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; + uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) { - p_g_ed->p_curr_ed->headTD = (hctd_t *)(((uint32_t)p_g_ed->p_curr_td->nextTD & 0xFFFFFFF0) - | ((uint32_t)p_g_ed->p_curr_ed->headTD & 0x0000000F)); - p_g_ed->p_curr_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead; + p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0) + | (p_g_ed->p_curr_ed->headTD & 0x0000000F); + p_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead; p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td; if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) { p_hcca = (hcca_t *)p_usb_reg->HcHCCA; @@ -630,13 +773,14 @@ static void chk_td_done(genelal_ed_t *p_g_ed) { static void chk_split_trans_setting(genelal_ed_t *p_g_ed) { uint8_t *p_buf; tdinfo_t td_info; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; /* Hi-Speed mode only */ - if (g_usb0_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) { + if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) { return; } - if (RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) { + if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) { return; } @@ -651,8 +795,8 @@ static void chk_split_trans_setting(genelal_ed_t *p_g_ed) { if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) { /* SET_ADDRESS */ - usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); - usb0_host_set_devadd(wValue, &devadd); + usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + usbx_host_set_devadd(wValue, &devadd); if (split_ctl.root_devadr == 0) { split_ctl.root_devadr = wValue; /* New Address */ } @@ -684,7 +828,7 @@ static void set_split_trans_setting(void) { uint16_t devadd; if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) { - usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd); RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB); RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT); if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) { @@ -695,42 +839,42 @@ static void set_split_trans_setting(void) { port_speed = USB_HOST_FULL_SPEED; } RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); - usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd); + usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd); split_ctl.reset_port = 0; } } static void control_trans(genelal_ed_t *p_g_ed) { - hctd_t *p_td = p_g_ed->p_curr_td; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; tdinfo_t td_info; uint16_t devadd; get_td_info(p_g_ed, &td_info); - if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { + if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { if (td_info.devadr == 0) { set_split_trans_setting(); } } else { /* When a non-Hi-Speed, the communication speed is determined from the TD. */ - usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd); + usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd); if (td_info.speed == 1) { RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); } else { RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); } - usb0_host_set_devadd(td_info.devadr, &devadd); + usbx_host_set_devadd(td_info.devadr, &devadd); } - USB200.DCPMAXP = (td_info.devadr << 12) + td_info.msp; + USB20X.DCPMAXP = (td_info.devadr << 12) + td_info.msp; if (td_info.direction == 0) { - g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); + g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); } else if (td_info.count != 0) { - g_usb0_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE); + g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE); } else { - g_usb0_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE); + g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE); } - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; + g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; p_g_ed->pipe_no = USB_HOST_PIPE0; p_g_ed->trans_wait = 1; @@ -741,12 +885,12 @@ static void control_trans(genelal_ed_t *p_g_ed) { uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4]; uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6]; - g_usb0_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd; - usb0_host_SetupStage(Req, Val, Indx, Len); + g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd; + usbx_host_SetupStage(Req, Val, Indx, Len); } else if (td_info.direction == 1) { - usb0_host_CtrlWriteStart(td_info.count, p_td->currBufPtr); + usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr); } else { - usb0_host_CtrlReadStart(td_info.count, p_td->currBufPtr); + usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr); } (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT); @@ -755,16 +899,16 @@ static void control_trans(genelal_ed_t *p_g_ed) { RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); } - g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); - g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; - g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; + g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE; + g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; } static void bulk_trans(genelal_ed_t *p_g_ed) { - hctd_t *p_td = p_g_ed->p_curr_td; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; hced_t *p_ed = p_g_ed->p_curr_ed; tdinfo_t td_info; - USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_blk_ep_tbl1[0]; + USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0]; uint8_t wk_table[6]; get_td_info(p_g_ed, &td_info); @@ -779,26 +923,26 @@ static void bulk_trans(genelal_ed_t *p_g_ed) { wk_table[4] = (uint8_t)td_info.msp; wk_table[5] = (uint8_t)(td_info.msp >> 8); p_g_ed->pipe_no = user_table->pipe_number; - usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); + usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); set_togle(p_g_ed->pipe_no, p_td, p_ed); p_g_ed->trans_wait = 1; if (td_info.direction == 1) { - usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); } else { - usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); } (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT); - usb0_host_stop_transfer(p_g_ed->pipe_no); + usbx_host_stop_transfer(p_g_ed->pipe_no); } static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { - hctd_t *p_td = p_g_ed->p_curr_td; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; hced_t *p_ed = p_g_ed->p_curr_ed; tdinfo_t td_info; - USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_int_ep_tbl1[index]; + USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index]; uint8_t wk_table[6]; uint32_t cycle_time; uint16_t devadd; @@ -821,8 +965,8 @@ static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { cycle_time >>= 1; user_table->pipe_cycle++; } - if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { - usb0_host_get_devadd(td_info.devadr, &devadd); + if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { + usbx_host_get_devadd(td_info.devadr, &devadd); if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) { user_table->pipe_cycle += 3; if (user_table->pipe_cycle > 7) { @@ -832,7 +976,7 @@ static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { } p_g_ed->pipe_no = user_table->pipe_number; - usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); + usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); set_togle(p_g_ed->pipe_no, p_td, p_ed); } @@ -874,22 +1018,19 @@ static uint32_t chk_cycle(hced_t *p_ed) { } static void int_trans(genelal_ed_t *p_g_ed) { - hctd_t *p_td = p_g_ed->p_curr_td; + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; tdinfo_t td_info; get_td_info(p_g_ed, &td_info); p_g_ed->trans_wait = 1; if (td_info.direction == 1) { - usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); } else { - usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); } - (void)osSemaphoreWait(p_g_ed->semid_wait, osWaitForever); - usb0_host_stop_transfer(p_g_ed->pipe_no); } static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) { - hctd_t *p_td = p_g_ed->p_curr_td; hced_t *p_ed = p_g_ed->p_curr_ed; p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F); @@ -897,42 +1038,251 @@ static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) { p_td_info->devadr = p_ed->control & 0x0000000F; p_td_info->speed = (p_ed->control >> 13) & 0x00000001; p_td_info->direction = (p_ed->control >> 11) & 0x00000003; - if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) { - if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) { - p_td_info->direction = 0; - } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) { - p_td_info->direction = 1; - } else { - p_td_info->direction = 2; + + if ((p_ed->control & ED_FORMAT) == 0) { + hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td; + + if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) { + if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) { + p_td_info->direction = 0; + } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) { + p_td_info->direction = 1; + } else { + p_td_info->direction = 2; + } + } + if (p_td->currBufPtr != NULL) { + p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1; + } else { + p_td_info->count = 0; } - } - if (p_td->currBufPtr != NULL) { - p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1; } else { - p_td_info->count = 0; +#if (ISO_TRANS_MAX_NUM > 0) + hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; + + if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) { + if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) { + p_td_info->direction = 0; + } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) { + p_td_info->direction = 1; + } else { + p_td_info->direction = 2; + } + } +#endif } } static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) { if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) { - usb0_host_set_sqclr(pipe); + usbx_host_set_sqclr(pipe); } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) { - usb0_host_set_sqset(pipe); - } else if (((uint32_t)p_ed->headTD & ED_TOGLE_CARRY) == 0) { - usb0_host_set_sqclr(pipe); + usbx_host_set_sqset(pipe); + } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) { + usbx_host_set_sqclr(pipe); } else { - usb0_host_set_sqset(pipe); + usbx_host_set_sqset(pipe); } } -static void connect_check(void) { +#if (ISO_TRANS_MAX_NUM > 0) +static void iso_ed_task(void const * argument) { + genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument]; + uint32_t wait_cnt = 0; + uint32_t wait_time = 0; + hcca_t *p_hcca; + hced_t *p_ed; + + while (1) { + (void)osSemaphoreWait(p_iso_ed->semid_list, osWaitForever); + if (p_iso_ed->p_curr_ed == NULL) { + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + p_ed = (hced_t *)p_hcca->IntTable[0]; + while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) + && (p_iso_ed->p_curr_ed == NULL)) { + if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) { + p_iso_ed->p_curr_ed = p_ed; + if (chk_iso_ed(p_iso_ed) != 0) { + iso_trans_setting(p_iso_ed, (uint32_t)argument); + } else { + p_iso_ed->p_curr_ed = NULL; + } + } + p_ed = p_ed->nextED; + } + p_iso_ed->psw_idx = 0; + } + if (p_iso_ed->p_curr_ed != NULL) { + while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) { + if (chk_iso_ed(p_iso_ed) != 0) { + wait_time = iso_chk_starting_frame(p_iso_ed); + if (wait_time != 0) { + osDelay(wait_time); + p_usb_reg->HcFmNumber += wait_time; + p_usb_reg->HcFmNumber &= 0x0000FFFF; + } + p_iso_ed->psw_idx = 0; + iso_trans(p_iso_ed); + (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever); + usbx_host_stop_transfer(p_iso_ed->pipe_no); + wait_cnt = 1; + } else { + if (wait_cnt > 0) { + wait_cnt--; + } else { + p_iso_ed->p_curr_ed = NULL; + } + break; + } + } + } + (void)osSemaphoreRelease(p_iso_ed->semid_list); + if (p_iso_ed->p_curr_ed == NULL) { + osDelay(10); + } else { + osDelay(1); + } + } +} + +static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) { uint32_t cnt; + int32_t ret = 0; + + for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) { + if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) { + ret = 1; + } + } + + return ret; +} + +static void chk_iso_td_done(genelal_ed_t *p_g_ed) { + hcca_t *p_hcca; + hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; + uint32_t ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + + if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) { + p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0) + | (p_g_ed->p_curr_ed->headTD & 0x0000000F); + p_isotd->nextTD = (hcisotd_t *)p_usb_reg->HcDoneHead; + p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td; + if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) { + p_hcca = (hcca_t *)p_usb_reg->HcHCCA; + p_hcca->DoneHead = p_usb_reg->HcDoneHead; + p_usb_reg->HcDoneHead = 0x00000000; + p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH; + (void)osSemaphoreRelease(semid_cb); + } + } +} + +static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){ + int32_t ret = 0; + hced_t *p_ed = p_g_ed->p_curr_ed; + + if (((p_ed->control & ED_SKIP) != 0) + || ((p_ed->control & ED_FORMAT) == 0) + || ((p_ed->headTD & ED_HALTED) != 0) + || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) { + /* Do Nothing */ + } else if ((p_ed->control & 0x0000007F) > 10) { + p_ed->headTD |= ED_HALTED; + } else { + p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0); + if (p_g_ed->p_curr_td == NULL) { + p_ed->headTD |= ED_HALTED; + } else { + hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; + + p_g_ed->p_start_buf = p_isotd->bufferPage0; + ret = 1; + } + } + + return ret; +} + +static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { + tdinfo_t td_info; + USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index]; + uint8_t wk_table[6]; + uint16_t devadd; + + get_td_info(p_g_ed, &td_info); + + wk_table[0] = 0; + wk_table[1] = USB_HOST_ENDPOINT_DESC; + wk_table[2] = td_info.endpoint_no; + if (td_info.direction == 2) { + wk_table[2] |= USB_HOST_EP_IN; + } + wk_table[3] = USB_HOST_EP_ISO; + wk_table[4] = (uint8_t)td_info.msp; + wk_table[5] = (uint8_t)(td_info.msp >> 8); + p_g_ed->cycle_time = 1; + user_table->pipe_cycle = 0; + if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) { + usbx_host_get_devadd(td_info.devadr, &devadd); + if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) { + user_table->pipe_cycle += 3; + } + } + + p_g_ed->pipe_no = user_table->pipe_number; + usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); +} + +static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) { + hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; + uint32_t starting_frame = p_isotd->control & 0x0000FFFF; + uint32_t wait_time = 0; + + if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) { + wait_time = starting_frame - p_usb_reg->HcFmNumber; + } + + return wait_time; +} + +static void iso_trans(genelal_ed_t *p_g_ed) { + hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; + tdinfo_t td_info; + uint32_t buff_addr; + uint32_t data_size; + + if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) { + buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000; + } else { + buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000; + } + buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF; + + if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) { + data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx]; + } else { + data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1; + } + p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size; + + get_td_info(p_g_ed, &td_info); + p_g_ed->trans_wait = 1; + if (td_info.direction == 1) { + usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + } else { + usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + } +} +#endif + +static void connect_check(void) { uint32_t type = 0; uint16_t stat; uint16_t devadd = 0; uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1; - if (usb0_host_CheckAttach() == USB_HOST_ATTACH) { + if (usbx_host_CheckAttach() == USB_HOST_ATTACH) { type = 1; } @@ -942,36 +1292,41 @@ static void connect_check(void) { } if (type == 0) { - usb0_host_UsbDetach(); + usbx_host_UsbDetach(); wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS; } else { - usb0_host_UsbAttach(); - stat = usb0_host_UsbBusReset(); + usbx_host_UsbAttach(); + stat = usbx_host_UsbBusReset(); RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB); RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT); if (stat == USB_HOST_HSMODE) { wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA; - RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); - g_usb0_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED; + RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED; } else if (stat == USB_HOST_FSMODE) { wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA; - RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); - g_usb0_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED; + RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED; } else { wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA; - RZA_IO_RegWrite_16(&USB200.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); - g_usb0_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED; + RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL); + g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED; } - RZA_IO_RegWrite_16(&devadd, g_usb0_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); - usb0_host_init_pipe_status(); - usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd); + RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD); + usbx_host_init_pipe_status(); + usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd); wk_HcRhPortStatus1 |= OR_RH_PORT_CCS; } wk_HcRhPortStatus1 |= OR_RH_PORT_CSC; p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1; p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC; (void)memset(&split_ctl, 0, sizeof(split_ctl)); +} +void ohciwrapp_loc_Connect(uint32_t type) { + uint32_t cnt; + + connect_change = type; if (type == 0) { if (ctl_ed.trans_wait == 1) { ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING); @@ -984,18 +1339,24 @@ static void connect_check(void) { ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING); } } - } -} +#if (ISO_TRANS_MAX_NUM > 0) + for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) { + if (iso_ed[cnt].trans_wait == 1) { + hced_t *p_ed = iso_ed[cnt].p_curr_ed; -void ohciwrapp_loc_Connect(uint32_t type) { - connect_change = type; + p_ed->headTD |= ED_HALTED; + ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING); + } + } +#endif + } (void)osSemaphoreRelease(semid_cb); } void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) { + uint32_t periodic = 0; uint32_t cnt; uint32_t sqmon; - hctd_t *p_td; hced_t *p_ed; genelal_ed_t *p_wait_ed = NULL; @@ -1004,48 +1365,122 @@ void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) { } else if (blk_ed.pipe_no == pipe) { p_wait_ed = &blk_ed; } else { - for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) { - if (int_ed[cnt].pipe_no == pipe) { - p_wait_ed = &int_ed[cnt]; - break; +#if (ISO_TRANS_MAX_NUM > 0) + if (p_wait_ed == NULL) { + for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) { + if (iso_ed[cnt].pipe_no == pipe) { + p_wait_ed = &iso_ed[cnt]; + break; + } + } + } +#endif + if (p_wait_ed == NULL) { + for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) { + if (int_ed[cnt].pipe_no == pipe) { + p_wait_ed = &int_ed[cnt]; + periodic = 1; + break; + } } } } + if (p_wait_ed == NULL) { return; } - - p_td = p_wait_ed->p_curr_td; p_ed = p_wait_ed->p_curr_ed; - if ((p_td == NULL) || (p_ed == NULL)) { + if (p_ed == NULL) { return; } - if (ConditionCode == TD_CC_NOERROR) { - /* ErrorCount */ - RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); + if ((p_ed->control & ED_FORMAT) == 0) { + hctd_t *p_td = (hctd_t *)p_wait_ed->p_curr_td; - /* CurrentBufferPointer */ - p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usb0_host_data_count[pipe]; + if (p_td != NULL) { + if (ConditionCode == TD_CC_NOERROR) { + /* ErrorCount */ + RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); + + /* CurrentBufferPointer */ + p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe]; + } else { + /* ErrorCount */ + RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); + } + + /* DataToggle */ + sqmon = usbx_host_get_sqmon(pipe); + RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T); + if (sqmon == 0) { + p_ed->headTD &= ~ED_TOGLE_CARRY; + } else { + p_ed->headTD |= ED_TOGLE_CARRY; + } + + /* ConditionCode */ + RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + + if (p_wait_ed == &ctl_ed) { + chk_split_trans_setting(&ctl_ed); + } + chk_genelal_td_done(p_wait_ed); + + if (periodic != 0) { + if (chk_genelal_ed(p_wait_ed) != 0) { + int_trans(p_wait_ed); + } else { + p_wait_ed->trans_wait = 0; + (void)osSemaphoreRelease(p_wait_ed->semid_wait); + } + } else { + p_wait_ed->trans_wait = 0; + (void)osSemaphoreRelease(p_wait_ed->semid_wait); + } + } } else { - /* ErrorCount */ - RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC); +#if (ISO_TRANS_MAX_NUM > 0) + hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td; + uint32_t next_trans = 0; + + if (p_isotd != NULL) { + usbx_host_stop_transfer(pipe); + if (p_usb_reg->HcFmNumber < 0x0000FFFF) { + p_usb_reg->HcFmNumber++; + } else { + p_usb_reg->HcFmNumber = 0; + } + + /* Size of packet */ + p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe]; + + /* ConditionCode */ + RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx], + (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC); + + if (usbx_host_CheckAttach() != USB_HOST_ATTACH) { + p_ed->headTD |= ED_HALTED; + } + if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) { + p_wait_ed->psw_idx = 0; + chk_iso_td_done(p_wait_ed); + } else { + p_wait_ed->psw_idx++; + } + if (chk_iso_ed(p_wait_ed) != 0) { + if (iso_chk_starting_frame(p_wait_ed) == 0) { + iso_trans(p_wait_ed); + next_trans = 1; + } + } + if (next_trans == 0) { + p_wait_ed->trans_wait = 0; + (void)osSemaphoreRelease(p_wait_ed->semid_wait); + } + } +#endif } - /* DataToggle */ - sqmon = usb0_host_get_sqmon(pipe); - RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T); - if (sqmon == 0) { - p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD & ~ED_TOGLE_CARRY); - } else { - p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_TOGLE_CARRY); - } - - /* ConditionCode */ - RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); - - p_wait_ed->trans_wait = 0; - - (void)osSemaphoreRelease(p_wait_ed->semid_wait); } diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h index 33f3281595..0b1a9ef810 100644 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h @@ -23,32 +23,32 @@ extern "C" { #endif -#define OHCI_REG_REVISION (0x00) -#define OHCI_REG_CONTROL (0x04) -#define OHCI_REG_COMMANDSTATUS (0x08) -#define OHCI_REG_INTERRUPTSTATUS (0x0C) -#define OHCI_REG_INTERRUPTENABLE (0x10) -#define OHCI_REG_INTERRUPTDISABLE (0x14) -#define OHCI_REG_HCCA (0x18) -#define OHCI_REG_PERIODCURRENTED (0x1C) -#define OHCI_REG_CONTROLHEADED (0x20) -#define OHCI_REG_CONTROLCURRENTED (0x24) -#define OHCI_REG_BULKHEADED (0x28) -#define OHCI_REG_BULKCURRENTED (0x2C) -#define OHCI_REG_DONEHEADED (0x30) -#define OHCI_REG_FMINTERVAL (0x34) -#define OHCI_REG_FMREMAINING (0x38) -#define OHCI_REG_FMNUMBER (0x3C) -#define OHCI_REG_PERIODICSTART (0x40) -#define OHCI_REG_LSTHRESHOLD (0x44) -#define OHCI_REG_RHDESCRIPTORA (0x48) -#define OHCI_REG_RHDESCRIPTORB (0x4C) -#define OHCI_REG_RHSTATUS (0x50) -#define OHCI_REG_RHPORTSTATUS1 (0x54) +#define OHCI_REG_REVISION (0x00) /* HcRevision */ +#define OHCI_REG_CONTROL (0x04) /* HcControl */ +#define OHCI_REG_COMMANDSTATUS (0x08) /* HcCommandStatus */ +#define OHCI_REG_INTERRUPTSTATUS (0x0C) /* HcInterruptStatus */ +#define OHCI_REG_INTERRUPTENABLE (0x10) /* HcInterruptEnable */ +#define OHCI_REG_INTERRUPTDISABLE (0x14) /* HcInterruptDisable */ +#define OHCI_REG_HCCA (0x18) /* HcHCCA */ +#define OHCI_REG_PERIODCURRENTED (0x1C) /* HcPeriodCurrentED */ +#define OHCI_REG_CONTROLHEADED (0x20) /* HcControlHeadED */ +#define OHCI_REG_CONTROLCURRENTED (0x24) /* HcControlCurrentED */ +#define OHCI_REG_BULKHEADED (0x28) /* HcBulkHeadED */ +#define OHCI_REG_BULKCURRENTED (0x2C) /* HcBulkCurrentED */ +#define OHCI_REG_DONEHEADED (0x30) /* HcDoneHead */ +#define OHCI_REG_FMINTERVAL (0x34) /* HcFmInterval */ +#define OHCI_REG_FMREMAINING (0x38) /* HcFmRemaining */ +#define OHCI_REG_FMNUMBER (0x3C) /* HcFmNumber */ +#define OHCI_REG_PERIODICSTART (0x40) /* HcPeriodicStart */ +#define OHCI_REG_LSTHRESHOLD (0x44) /* HcLSThreshold */ +#define OHCI_REG_RHDESCRIPTORA (0x48) /* HcRhDescriptorA */ +#define OHCI_REG_RHDESCRIPTORB (0x4C) /* HcRhDescriptorB */ +#define OHCI_REG_RHSTATUS (0x50) /* HcRhStatus */ +#define OHCI_REG_RHPORTSTATUS1 (0x54) /* HcRhPortStatus1 */ typedef void (usbisr_fnc_t)(void); -extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed); +extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc); extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs); extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data); extern void ohciwrapp_interrupt(uint32_t int_sense); diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c new file mode 100644 index 0000000000..2a6d126ddc --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c @@ -0,0 +1,190 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/********************************************************************************************************/ +/* Endpoint Configuration Data Format */ +/********************************************************************************************************/ +/* LINE1: Pipe Window Select Register */ +/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */ +/* LINE2: Pipe Configuration Register */ +/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ +/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ +/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE3: Pipe Buffer Configuration Register */ +/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */ +/* [ ### SET ### ] */ +/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */ +/* LINE4: Pipe Maxpacket Size Register */ +/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE5: Pipe Cycle Configuration Register (0x6C) */ +/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */ +/* LINE6: use FIFO port */ +/* : USB_HOST_CUSE [ ### SET ### ] */ +/* : USB_HOST_D0USE / USB_HOST_D1USE */ +/* : USB_HOST_D0DMA / USB_HOST_D0DMA */ +/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */ +/********************************************************************************************************/ + +/* Device Address 1 */ +USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[ ] = +{ + { + USB_HOST_PIPE3, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D0USE + }, + + { + /* Pipe end */ + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF + } +}; + +USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] = +{ + { + USB_HOST_PIPE6, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE7, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE8, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE9, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + /* Pipe end */ + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF + } +}; + +USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] = +{ + { + USB_HOST_PIPE1, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + USB_HOST_PIPE2, + /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60), + USB_HOST_NONE, + USB_HOST_NONE, + USB_HOST_D1USE + }, + + { + /* Pipe end */ + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF, + 0xFFFF + } +}; + + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h new file mode 100644 index 0000000000..70e5c21151 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h @@ -0,0 +1,156 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_H +#define USB0_HOST_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" +#include "usb_host.h" + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb0_host_bit_set[]; +extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb0_host_PipeIgnore[]; +extern uint16_t g_usb0_host_PipeTbl[]; +extern uint16_t g_usb0_host_pipe_status[]; +extern uint32_t g_usb0_host_PipeDataSize[]; + +extern USB_HOST_DMA_t g_usb0_host_DmaInfo[]; +extern uint16_t g_usb0_host_DmaPipe[]; +extern uint16_t g_usb0_host_DmaBval[]; +extern uint16_t g_usb0_host_DmaStatus[]; + +extern uint16_t g_usb0_host_driver_state; +extern uint16_t g_usb0_host_ConfigNum; +extern uint16_t g_usb0_host_CmdStage; +extern uint16_t g_usb0_host_bchg_flag; +extern uint16_t g_usb0_host_detach_flag; +extern uint16_t g_usb0_host_attach_flag; + +extern uint16_t g_usb0_host_UsbAddress; +extern uint16_t g_usb0_host_setUsbAddress; +extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +extern uint16_t g_usb0_host_UsbDeviceSpeed; +extern uint16_t g_usb0_host_SupportUsbDeviceSpeed; + +extern uint16_t g_usb0_host_SavReq; +extern uint16_t g_usb0_host_SavVal; +extern uint16_t g_usb0_host_SavIndx; +extern uint16_t g_usb0_host_SavLen; + +extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +/* ==== common ==== */ +void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb0_host_is_hispeed(void); +uint16_t usb0_host_is_hispeed_enable(void); +uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_write_buffer(uint16_t pipe); +uint16_t usb0_host_write_buffer_c(uint16_t pipe); +uint16_t usb0_host_write_buffer_d0(uint16_t pipe); +uint16_t usb0_host_write_buffer_d1(uint16_t pipe); +void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_read_buffer(uint16_t pipe); +uint16_t usb0_host_read_buffer_c(uint16_t pipe); +uint16_t usb0_host_read_buffer_d0(uint16_t pipe); +uint16_t usb0_host_read_buffer_d1(uint16_t pipe); +uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb0_host_read_dma(uint16_t pipe); +void usb0_host_stop_transfer(uint16_t pipe); +void usb0_host_brdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_bemp_int(uint16_t status, uint16_t int_enb); +void usb0_host_setting_interrupt(uint8_t level); +void usb0_host_reset_module(uint16_t clockmode); +uint16_t usb0_host_get_buf_size(uint16_t pipe); +uint16_t usb0_host_get_mxps(uint16_t pipe); +void usb0_host_enable_brdy_int(uint16_t pipe); +void usb0_host_disable_brdy_int(uint16_t pipe); +void usb0_host_clear_brdy_sts(uint16_t pipe); +void usb0_host_enable_bemp_int(uint16_t pipe); +void usb0_host_disable_bemp_int(uint16_t pipe); +void usb0_host_clear_bemp_sts(uint16_t pipe); +void usb0_host_enable_nrdy_int(uint16_t pipe); +void usb0_host_disable_nrdy_int(uint16_t pipe); +void usb0_host_clear_nrdy_sts(uint16_t pipe); +void usb0_host_set_pid_buf(uint16_t pipe); +void usb0_host_set_pid_nak(uint16_t pipe); +void usb0_host_set_pid_stall(uint16_t pipe); +void usb0_host_clear_pid_stall(uint16_t pipe); +uint16_t usb0_host_get_pid(uint16_t pipe); +void usb0_host_set_sqclr(uint16_t pipe); +void usb0_host_set_sqset(uint16_t pipe); +void usb0_host_set_csclr(uint16_t pipe); +void usb0_host_aclrm(uint16_t pipe); +void usb0_host_set_aclrm(uint16_t pipe); +void usb0_host_clr_aclrm(uint16_t pipe); +uint16_t usb0_host_get_sqmon(uint16_t pipe); +uint16_t usb0_host_get_inbuf(uint16_t pipe); + +/* ==== host ==== */ +void usb0_host_init_pipe_status(void); +int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table); +void usb0_host_StatusStage(void); +void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_InitModule(void); +uint16_t usb0_host_CheckAttach(void); +void usb0_host_UsbDetach(void); +void usb0_host_UsbDetach2(void); +void usb0_host_UsbAttach(void); +uint16_t usb0_host_UsbBusReset(void); +int32_t usb0_host_UsbResume(void); +int32_t usb0_host_UsbSuspend(void); +void usb0_host_Enable_DetachINT(void); +void usb0_host_Disable_DetachINT(void); +void usb0_host_UsbStateManager(void); + + +#endif /* USB0_HOST_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h new file mode 100644 index 0000000000..dbdd64d6d9 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h @@ -0,0 +1,112 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_API_H +#define USB0_HOST_API_H + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb0_host_interrupt(uint32_t int_sense); +void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense); +void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense); + +uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +int32_t usb0_api_host_enumeration(uint16_t devadr); +int32_t usb0_api_host_detach(void); +int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); +int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table); +int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); +uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table); +int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count); + +int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum); +int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); +int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir); +uint16_t usb0_api_host_GetUsbDeviceState(void); + +void usb0_api_host_elt_4_4(void); +void usb0_api_host_elt_4_5(void); +void usb0_api_host_elt_4_6(void); +void usb0_api_host_elt_4_7(void); +void usb0_api_host_elt_4_8(void); +void usb0_api_host_elt_4_9(void); +void usb0_api_host_elt_get_desc(void); + +void usb0_host_EL_ModeInit(void); +void usb0_host_EL_SetUACT(void); +void usb0_host_EL_ClearUACT(void); +void usb0_host_EL_SetTESTMODE(uint16_t mode); +void usb0_host_EL_ClearNRDYSTS(uint16_t pipe); +uint16_t usb0_host_EL_GetINTSTS1(void); +void usb0_host_EL_UsbBusReset(void); +void usb0_host_EL_UsbAttach(void); +void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_EL_StatusStage(void); +void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +int32_t usb0_host_EL_UsbSuspend(void); +int32_t usb0_host_EL_UsbResume(void); + +#if 0 /* prototype in devdrv_usb_host_api.h */ +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void); +void Userdef_USB_usb0_host_attach(void); +void Userdef_USB_usb0_host_detach(void); +void Userdef_USB_usb0_host_delay_1ms(void); +void Userdef_USB_usb0_host_delay_xms(uint32_t msec); +void Userdef_USB_usb0_host_delay_10us(uint32_t usec); +void Userdef_USB_usb0_host_delay_500ns(void); +void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc); +uint32_t Userdef_USB_usb0_host_stop_dma0(void); +uint32_t Userdef_USB_usb0_host_stop_dma1(void); +#endif + +#endif /* USB0_HOST_API_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h new file mode 100644 index 0000000000..3e5e40c3bb --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dmacdrv.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_DMACDRV_H +#define USB0_HOST_DMACDRV_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef struct dmac_transinfo +{ + uint32_t src_addr; /* Transfer source address */ + uint32_t dst_addr; /* Transfer destination address */ + uint32_t count; /* Transfer byte count */ + uint32_t src_size; /* Transfer source data size */ + uint32_t dst_size; /* Transfer destination data size */ + uint32_t saddr_dir; /* Transfer source address direction */ + uint32_t daddr_dir; /* Transfer destination address direction */ +} dmac_transinfo_t; + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* ==== Transfer specification of the sample program ==== */ +#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ +#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ + +/* ==== DMA modes ==== */ +#define DMAC_MODE_REGISTER (0) /* Register mode */ +#define DMAC_MODE_LINK (1) /* Link mode */ + +/* ==== Transfer requests ==== */ +#define DMAC_REQ_MODE_EXT (0) /* External request */ +#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ +#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ + +/* ==== DMAC transfer sizes ==== */ +#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ +#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ +#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ +#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ +#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ +#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ +#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ +#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ + +/* ==== Address increment for transferring ==== */ +#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ +#define DMAC_TRANS_ADR_INC (0) /* Increment */ + +/* ==== Method for detecting DMA request ==== */ +#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ +#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ +#define DMAC_REQ_DET_LOW (2) /* Low level detection */ +#define DMAC_REQ_DET_HIGH (3) /* High level detection */ + +/* ==== Request Direction ==== */ +#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ +#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ + +/* ==== Descriptors ==== */ +#define DMAC_DESC_HEADER (0) /* Header */ +#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ +#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ +#define DMAC_DESC_COUNT (3) /* Transaction Byte */ +#define DMAC_DESC_CHCFG (4) /* Channel Confg */ +#define DMAC_DESC_CHITVL (5) /* Channel Interval */ +#define DMAC_DESC_CHEXT (6) /* Channel Extension */ +#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ + +/* ==== On-chip peripheral module requests ===== */ +typedef enum dmac_request_factor +{ + DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ + DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ + DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ + DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ + DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ + DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ + DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ + DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ +} dmac_request_factor_t; + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_host_DMAC1_Open(uint32_t req); +void usb0_host_DMAC1_Close(uint32_t * remain); +void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_host_DMAC2_Open(uint32_t req); +void usb0_host_DMAC2_Close(uint32_t * remain); +void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +#endif /* USB0_HOST_DMACDRV_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c new file mode 100644 index 0000000000..bb7b68f2bf --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c @@ -0,0 +1,2835 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dataio.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)]; + +static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static uint16_t usb0_host_read_dma_d0(uint16_t pipe); +static uint16_t usb0_host_read_dma_d1(uint16_t pipe); +static uint16_t usb0_host_write_dma_d0(uint16_t pipe); +static uint16_t usb0_host_write_dma_d1(uint16_t pipe); + +static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count); +static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count); +static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count); + +static void usb0_host_clear_transaction_counter(uint16_t pipe); +static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count); + +static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr); + +static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count); +static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count); + + +/******************************************************************************* +* Function Name: usb0_host_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t usefifo; + uint16_t mbw; + + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + usb0_host_clear_bemp_sts(pipe); + usb0_host_clear_brdy_sts(pipe); + usb0_host_clear_nrdy_sts(pipe); + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + case USB_HOST_D0FIFO_DMA: + usefifo = USB_HOST_D0USE; + break; + + case USB_HOST_D1FIFO_USE: + case USB_HOST_D1FIFO_DMA: + usefifo = USB_HOST_D1USE; + break; + + default: + usefifo = USB_HOST_CUSE; + break; + }; + + usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw); + + usb0_host_clear_transaction_counter(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + status = usb0_host_write_buffer(pipe); + + if (status != USB_HOST_FIFOERROR) + { + usb0_host_set_pid_buf(pipe); + } + + return status; +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer +* Description : Writes data in the buffer allocated in the pipe specified by +* : the argument. The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer (uint16_t pipe) +{ + uint16_t status; + uint16_t usefifo; + + g_usb0_host_PipeIgnore[pipe] = 0; + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + status = usb0_host_write_buffer_d0(pipe); + break; + + case USB_HOST_D1FIFO_USE: + status = usb0_host_write_buffer_d1(pipe); + break; + + case USB_HOST_D0FIFO_DMA: + status = usb0_host_write_dma_d0(pipe); + break; + + case USB_HOST_D1FIFO_DMA: + status = usb0_host_write_dma_d1(pipe); + break; + + default: + status = usb0_host_write_buffer_c(pipe); + break; + }; + + switch (status) + { + case USB_HOST_WRITING: /* Continue of data write */ + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write */ + case USB_HOST_WRITESHRT: /* End of data write */ + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + usb0_host_clear_nrdy_sts(pipe); + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + + /* for last transfer */ + usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEDMA: /* DMA write */ + usb0_host_clear_nrdy_sts(pipe); + usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_c +* Description : Writes data in the buffer allocated in the pipe specified in +* : the argument. Writes data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (pipe == USB_HOST_PIPE0) + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw); + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + } + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_c_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, + USB_CFIFOCTR_BVAL_SHIFT, + USB_CFIFOCTR_BVAL) == 0) + { + USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_d0_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_buffer_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_write_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb0_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_host_write_d1_fifo(pipe, (uint16_t)count); + + if (g_usb0_host_data_count[pipe] < (uint32_t)size) + { + g_usb0_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D0FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_host_write_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_host_data_count[pipe]; + + if (count != 0) + { + g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1; + } + else + { + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; + } + + dfacc = usb0_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb0_host_data_count[pipe] = 0; + g_usb0_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_write_dma_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D1FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_host_write_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_host_data_count[pipe]; + + if (count != 0) + { + g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1; + } + else + { + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; + } + + dfacc = usb0_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb0_host_data_count[pipe] = 0; + g_usb0_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t usefifo; + + usb0_host_clear_bemp_sts(pipe); + usb0_host_clear_brdy_sts(pipe); + usb0_host_clear_nrdy_sts(pipe); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb0_host_start_receive_trns_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_USE: + usb0_host_start_receive_trns_d1(pipe, size, data); + break; + + case USB_HOST_D0FIFO_DMA: + usb0_host_start_receive_dma_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_DMA: + usb0_host_start_receive_dma_d1(pipe, size, data); + break; + + default: + usb0_host_start_receive_trns_c(pipe, size, data); + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* : When storing data in the buffer allocated in the pipe specified in the +* : argument, BRDY interrupt is generated to read data +* : in the interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data in the +* : interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_trns_d1 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D1FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = size; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_dma_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = 0; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_host_read_dma(pipe); + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + else + { + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_start_receive_dma_d1 +* Description : Read data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_host_set_pid_nak(pipe); + g_usb0_host_data_count[pipe] = size; + g_usb0_host_data_pointer[pipe] = (uint8_t *)data; + g_usb0_host_PipeIgnore[pipe] = 0; + + g_usb0_host_PipeDataSize[pipe] = 0; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb0_host_get_mbw(size, (uint32_t)data); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb0_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_host_read_dma(pipe); + + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + else + { + usb0_host_enable_nrdy_int(pipe); + usb0_host_enable_brdy_int(pipe); + } + + usb0_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Uses FIF0 set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer (uint16_t pipe) +{ + uint16_t status; + + g_usb0_host_PipeIgnore[pipe] = 0; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + status = usb0_host_read_buffer_d0(pipe); + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + status = usb0_host_read_buffer_d1(pipe); + } + else + { + status = usb0_host_read_buffer_c(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_c_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_d0 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_d0_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_buffer_d1 +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb0_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) !=0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb0_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_host_read_d1_fifo(pipe, (uint16_t)count); + } + + g_usb0_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO or D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_host_read_dma (uint16_t pipe) +{ + uint16_t status; + + g_usb0_host_PipeIgnore[pipe] = 0; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + status = usb0_host_read_dma_d0(pipe); + } + else + { + status = usb0_host_read_dma_d1(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READZERO: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(pipe); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + } + break; + + case USB_HOST_READOVER: /* buffer over */ + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe]; + } +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_host_read_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */ + g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */ + + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_host_data_count[pipe] -= count; + g_usb0_host_data_pointer[pipe] += count; + g_usb0_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_read_dma_d1 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by DMA transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_host_read_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb0_host_data_count[pipe]; + } + else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */ + g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */ + + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe]; + g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_host_data_count[pipe] -= count; + g_usb0_host_data_pointer[pipe] += count; + g_usb0_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_change_fifo_port +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. After allocating FIF0, waits in the software +* : till the corresponding pipe becomes ready. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : USB_HOST_FIFOERROR ; Error +* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value +*******************************************************************************/ +uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + usb0_host_set_curpipe(pipe, fifosel, isel, mbw); + + for (loop = 0; loop < 4; loop++) + { + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOCTR; + break; + + case USB_HOST_D0USE: + case USB_HOST_D0DMA: + buffer = USB200.D0FIFOCTR; + break; + + case USB_HOST_D1USE: + case USB_HOST_D1DMA: + buffer = USB200.D1FIFOCTR; + break; + + default: + buffer = 0; + break; + } + + if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY) + { + return buffer; + } + + loop2 = 25; + + while (loop2-- > 0) + { + /* wait */ + } + } + + return USB_HOST_FIFOERROR; +} + +/******************************************************************************* +* Function Name: usb0_host_set_curpipe +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + g_usb0_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB200.D0FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB200.D1FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_curpipe2 +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument.(DFACC) +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* : uint16_t dfacc ; DFACC Access mode +* Return Value : none +*******************************************************************************/ +void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) +{ + uint16_t buffer; + uint32_t loop; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + uint32_t dummy; +#endif + volatile uint32_t loop2; + + g_usb0_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB200.D0FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D0FIFO.UINT32; + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB200.D1FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D1FIFO.UINT32; + loop = dummy; // avoid warning. + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_c_fifo +* Description : Writes data in CFIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_c_fifo +* Description : Reads data from CFIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_d0_fifo +* Description : Writes data in D0FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_d0_fifo +* Description : Reads data from D0FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating DOFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t Pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_write_d1_fifo +* Description : Writes data in D1FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]); + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_read_d1_fifo +* Description : Reads data from D1FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH]; + g_usb0_host_data_pointer[pipe] += 1; + } + } + else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H]; + g_usb0_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32; + g_usb0_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_com_get_dmasize +* Description : Calculates access width of DMA transfer by the argument to + return as the Return Value. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : DMA transfer size : 0 8bit +* : : 1 16bit +* : : 2 32bit +*******************************************************************************/ +static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + + if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) + { + /* When transfer byte count is odd */ + /* or transfer data area is 8-bit alignment */ + size = 0; /* 8bit */ + } + else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) + { + /* When the transfer byte count is multiples of 2 */ + /* or the transfer data area is 16-bit alignment */ + size = 1; /* 16bit */ + } + else + { + /* When the transfer byte count is multiples of 4 */ + /* or the transfer data area is 32-bit alignment */ + size = 2; /* 32bit */ + } + + return size; +} + +/******************************************************************************* +* Function Name: usb0_host_get_mbw +* Description : Calculates access width of DMA to return the value set in MBW. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit +* : : USB_HOST_BITMBW_16 16bit +* : : USB_HOST_BITMBW_32 32bit +*******************************************************************************/ +uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + uint16_t mbw; + + size = usb0_host_com_get_dmasize(trncount, dtptr); + + if (size == 0) + { + /* 8bit */ + mbw = USB_HOST_BITMBW_8; + } + else if (size == 1) + { + /* 16bit */ + mbw = USB_HOST_BITMBW_16; + } + else + { + /* 32bit */ + mbw = USB_HOST_BITMBW_32; + } + + return mbw; +} + +/******************************************************************************* +* Function Name: usb0_host_set_transaction_counter +* Description : Sets transaction counter by the argument(PIPEnTRN). +* : Clears transaction before setting to enable transaction counter setting. +* Arguments : uint16_t pipe ; Pipe number +* : uint32_t bsize : Data transfer size +* Return Value : none +*******************************************************************************/ +static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize) +{ + uint16_t mxps; + uint16_t cnt; + + if (bsize == 0) + { + return; + } + + mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */ + + if ((bsize % mxps) == 0) + { + cnt = (uint16_t)(bsize / mxps); + } + else + { + cnt = (uint16_t)((bsize / mxps) + 1); + } + + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE1TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE2TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE3TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE4TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE5TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE9TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_clear_transaction_counter +* Description : Clears the transaction counter by the argument. +* : After executing this function, the transaction counter is invalid. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_transaction_counter (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_stop_transfer +* Description : Stops the USB transfer in the pipe specified by the argument. +* : After stopping the USB transfer, clears the buffer allocated in +* : the pipe. +* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0; +* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt +* : in the corresponding pipe becomes invalid. Sequence bit is also +* : cleared. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_stop_transfer (uint16_t pipe) +{ + uint16_t usefifo; + uint32_t remain; + + usb0_host_set_pid_nak(pipe); + + usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb0_host_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_USE: + usb0_host_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D0FIFO_DMA: + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + usb0_host_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_DMA: + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + usb0_host_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + default: + usb0_host_clear_transaction_counter(pipe); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + } + + /* Interrupt of pipe set is disabled */ + usb0_host_disable_brdy_int(pipe); + usb0_host_disable_nrdy_int(pipe); + usb0_host_disable_bemp_int(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb0_host_aclrm(pipe); +#endif + usb0_host_set_csclr(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_set_dfacc_d0 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/******************************************************************************* +* Function Name: usb0_host_set_dfacc_d1 +* Description : Sets the DFACC setting value in D1FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c new file mode 100644 index 0000000000..57e6e5a084 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c @@ -0,0 +1,355 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dma.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +/* #include "usb0_host_dmacdrv.h" */ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static void usb0_host_dmaint(uint16_t fifo); +static void usb0_host_dmaint_buf2fifo(uint16_t pipe); +static void usb0_host_dmaint_fifo2buf(uint16_t pipe); + + +/******************************************************************************* +* Function Name: usb0_host_dma_stop_d0 +* Description : D0FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB200.D0FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); + g_usb0_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_host_dma_stop_d1 +* Description : D1FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB200.D1FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain); + g_usb0_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_host_dma_interrupt_d0fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense) +{ + usb0_host_dmaint(USB_HOST_D0FIFO); + g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_host_dma_interrupt_d1fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense) +{ + usb0_host_dmaint(USB_HOST_D1FIFO); + g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint +* Description : This function is DMA transfer end interrupt +* Arguments : uint16_t fifo ; fifo number +* : ; USB_HOST_D0FIFO +* : ; USB_HOST_D1FIFO +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint (uint16_t fifo) +{ + uint16_t pipe; + + pipe = g_usb0_host_DmaPipe[fifo]; + + if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO) + { + usb0_host_dmaint_buf2fifo(pipe); + } + else + { + usb0_host_dmaint_fifo2buf(pipe); + } +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint_fifo2buf +* Description : Executes read completion from FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint_fifo2buf (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND) + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb0_host_enable_brdy_int(pipe); + } + } + } + else + { + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND) + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb0_host_enable_brdy_int(pipe); + } + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_dmaint_buf2fifo +* Description : Executes write completion in FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_host_dmaint_buf2fifo (uint16_t pipe) +{ + uint16_t useport; + uint32_t remain; + + useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_host_stop_dma0(); + usb0_host_dma_stop_d0(pipe, remain); + + if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + else + { + remain = Userdef_USB_usb0_host_stop_dma1(); + usb0_host_dma_stop_d1(pipe, remain); + + if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + + usb0_host_enable_bemp_int(pipe); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c new file mode 100644 index 0000000000..0dbce8e916 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c @@ -0,0 +1,285 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_intrn.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_brdy_int +* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9). +* : According to the pipe that interrupt is generated in, +* : reads/writes buffer allocated in the pipe. +* : This function is executed in the BRDY interrupt handler. +* : This function clears BRDY interrupt status and BEMP interrupt +* : status. +* Arguments : uint16_t status ; BRDYSTS Register Value +* : uint16_t int_enb ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_brdy_int (uint16_t status, uint16_t int_enb) +{ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + pipebit = g_usb0_host_bit_set[pipe]; + + if ((status & pipebit) && (int_enb & pipebit)) + { + USB200.BRDYSTS = (uint16_t)~pipebit; + USB200.BEMPSTS = (uint16_t)~pipebit; + + if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY) + { + usb0_host_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_host_read_dma(pipe); + usb0_host_disable_brdy_int(pipe); + } + else + { + USB200.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA) + { + if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY) + { + usb0_host_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_host_read_dma(pipe); + usb0_host_disable_brdy_int(pipe); + } + else + { + USB200.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + usb0_host_read_buffer(pipe); + } + else + { + usb0_host_write_buffer(pipe); + } + } +#if(1) /* ohci_wrapp */ + switch (g_usb0_host_pipe_status[pipe]) + { + case USB_HOST_PIPE_DONE: + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); + break; + case USB_HOST_PIPE_NORES: + case USB_HOST_PIPE_STALL: + case USB_HOST_PIPE_ERROR: + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); + break; + default: + /* Do Nothing */ + break; + } +#endif + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_nrdy_int +* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9). +* : Checks NRDY interrupt cause by PID. When the cause if STALL, +* : regards the pipe state as STALL and ends the processing. +* : Then the cause is not STALL, increments the error count to +* : communicate again. When the error count is 3, determines +* : the pipe state as USB_HOST_PIPE_NORES and ends the processing. +* : This function is executed in the NRDY interrupt handler. +* : This function clears NRDY interrupt status. +* Arguments : uint16_t status ; NRDYSTS Register Value +* : uint16_t int_enb ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.NRDYSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) + { + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM) == 1) + { + if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT) + { + pid = usb0_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING); +#else + g_usb0_host_PipeIgnore[pipe]++; + + if (g_usb0_host_PipeIgnore[pipe] == 3) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + } + else + { + usb0_host_set_pid_buf(pipe); + } +#endif + } + } + } + else + { + /* USB Function */ + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_bemp_int +* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9). +* Arguments : uint16_t status ; BEMPSTS Register Value +* : uint16_t int_enb ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_bemp_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe]) + { + pid = usb0_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { + inbuf = usb0_host_get_inbuf(pipe); + + if (inbuf == 0) + { + usb0_host_disable_bemp_int(pipe); + usb0_host_set_pid_nak(pipe); + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); +#endif + } + } + } + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c new file mode 100644 index 0000000000..eb3359e286 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c @@ -0,0 +1,1580 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_lib.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "MBRZA1H.h" /* INTC Driver Header */ +#else +#include "devdrv_intc.h" /* INTC Driver Header */ +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_enable_brdy_int +* Description : Enables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_brdy_int (uint16_t pipe) +{ + /* enable brdy interrupt */ + USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_brdy_int +* Description : Disables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_brdy_int (uint16_t pipe) +{ + /* disable brdy interrupt */ + USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_brdy_sts (uint16_t pipe) +{ + /* clear brdy status */ + USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_enable_bemp_int +* Description : Enables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_bemp_int (uint16_t pipe) +{ + /* enable bemp interrupt */ + USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_bemp_int +* Description : Disables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_bemp_int (uint16_t pipe) +{ + /* disable bemp interrupt */ + USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_bemp_sts (uint16_t pipe) +{ + /* clear bemp status */ + USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_enable_nrdy_int +* Description : Enables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : NRDY. Enables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_enable_nrdy_int (uint16_t pipe) +{ + /* enable nrdy interrupt */ + USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_host_disable_nrdy_int +* Description : Disables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : NRDY. Disables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_disable_nrdy_int (uint16_t pipe) +{ + /* disable nrdy interrupt */ + USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_nrdy_sts (uint16_t pipe) +{ + /* clear nrdy status */ + USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_host_is_hispeed +* Description : Returns the result of USB reset hand shake (RHST) as +* : return value. +* Arguments : none +* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed +* : USB_HOST_FULL_SPEED ; Full-Speed +* : USB_HOST_LOW_SPEED ; Low-Speed +* : USB_HOST_NON_SPEED ; error +*******************************************************************************/ +uint16_t usb0_host_is_hispeed (void) +{ + uint16_t rhst; + uint16_t speed; + + rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_HSMODE) + { + speed = USB_HOST_HIGH_SPEED; + } + else if (rhst == USB_HOST_FSMODE) + { + speed = USB_HOST_FULL_SPEED; + } + else if (rhst == USB_HOST_LSMODE) + { + speed = USB_HOST_LOW_SPEED; + } + else + { + speed = USB_HOST_NON_SPEED; + } + + return speed; +} + +/******************************************************************************* +* Function Name: usb0_host_is_hispeed_enable +* Description : Returns the USB High-Speed connection enabled status as +* : return value. +* Arguments : none +* Return Value : USB_HOST_YES : Hi-Speed Enable +* : USB_HOST_NO : Hi-Speed Disable +*******************************************************************************/ +uint16_t usb0_host_is_hispeed_enable (void) +{ + uint16_t ret; + + ret = USB_HOST_NO; + + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE) == 1) + { + ret = USB_HOST_YES; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_buf (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb0_host_set_pid_nak(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_BUF, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_nak (uint16_t pipe) +{ + uint16_t pid; + uint16_t pbusy; + uint32_t loop; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb0_host_set_pid_stall(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_NAK, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + + if (pid == USB_HOST_PID_BUF) + { + for (loop = 0; loop < 200; loop++) + { + switch (pipe) + { + case USB_HOST_PIPE0: + pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PBUSY_SHIFT, + USB_DCPCTR_PBUSY); + break; + + case USB_HOST_PIPE1: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE2: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE3: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE4: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE5: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE6: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE7: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE8: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE9: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PBUSY_SHIFT, + USB_PIPEnCTR_9_PBUSY); + break; + + default: + pbusy = 1; + break; + } + + if (pbusy == 0) + { + break; + } + + Userdef_USB_usb0_host_delay_500ns(); + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_pid_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_host_get_pid(pipe); + + if (pid == USB_HOST_PID_BUF) + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_STALL2, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } + else + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + USB_HOST_PID_STALL, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name: usb0_host_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_clear_pid_stall (uint16_t pipe) +{ + usb0_host_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb0_host_get_pid (uint16_t pipe) +{ + uint16_t pid; + + switch (pipe) + { + case USB_HOST_PIPE0: + pid = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + pid = 0; + break; + } + + return pid; +} + +/******************************************************************************* +* Function Name: usb0_host_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_csclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_CSCLR_SHIFT, + USB_DCPCTR_CSCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_CSCLR_SHIFT, + USB_PIPEnCTR_9_CSCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_sqclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQCLR_SHIFT, + USB_DCPCTR_SQCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQCLR_SHIFT, + USB_PIPEnCTR_9_SQCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_host_set_sqset (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQSET_SHIFT, + USB_DCPCTR_SQSET); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQSET_SHIFT, + USB_PIPEnCTR_9_SQSET); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_sqmon +* Description : Toggle bit of specified pipe is obtained +* Arguments : uint16_t pipe ; Pipe number +* Return Value : sqmon +*******************************************************************************/ +uint16_t usb0_host_get_sqmon (uint16_t pipe) +{ + uint16_t sqmon; + + switch (pipe) + { + case USB_HOST_PIPE0: + sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_SQMON_SHIFT, + USB_DCPCTR_SQMON); + break; + + case USB_HOST_PIPE1: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE2: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE3: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE4: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE5: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE6: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE7: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE8: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE9: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_SQMON_SHIFT, + USB_PIPEnCTR_9_SQMON); + break; + + default: + sqmon = 0; + break; + } + + return sqmon; +} + +/******************************************************************************* +* Function Name: usb0_host_aclrm +* Description : The buffer of specified pipe is initialized +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_aclrm (uint16_t pipe) +{ + usb0_host_set_aclrm(pipe); + usb0_host_clr_aclrm(pipe); +} + +/******************************************************************************* +* Function Name: usb0_host_set_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_set_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_clr_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_host_clr_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 0, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_inbuf +* Description : Returns INBUFM of the pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : inbuf +*******************************************************************************/ +uint16_t usb0_host_get_inbuf (uint16_t pipe) +{ + uint16_t inbuf; + + switch (pipe) + { + case USB_HOST_PIPE0: + inbuf = 0; + break; + + case USB_HOST_PIPE1: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE2: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE3: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE4: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE5: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE6: + inbuf = 0; + break; + + case USB_HOST_PIPE7: + inbuf = 0; + break; + + case USB_HOST_PIPE8: + inbuf = 0; + break; + + case USB_HOST_PIPE9: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_INBUFM_SHIFT, + USB_PIPEnCTR_9_INBUFM); + break; + + default: + inbuf = 0; + break; + } + + return inbuf; +} + +/******************************************************************************* +* Function Name: usb0_host_setting_interrupt +* Description : Sets the USB module interrupt level. +* Arguments : uint8_t level ; interrupt level +* Return Value : none +*******************************************************************************/ +void usb0_host_setting_interrupt (uint8_t level) +{ +#if(1) /* ohci_wrapp */ + IRQn_Type d0fifo_dmaintid; + IRQn_Type d1fifo_dmaintid; + + InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt); + GIC_SetPriority(USBI0_IRQn, level); + GIC_EnableIRQ(USBI0_IRQn); + + d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); + GIC_SetPriority(d0fifo_dmaintid, level); + GIC_EnableIRQ(d0fifo_dmaintid); + } + + d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); + GIC_SetPriority(d1fifo_dmaintid, level); + GIC_EnableIRQ(d1fifo_dmaintid); + } +#else + uint16_t d0fifo_dmaintid; + uint16_t d1fifo_dmaintid; + + R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt); + R_INTC_SetPriority(INTC_ID_USBI0, level); + R_INTC_Enable(INTC_ID_USBI0); + + d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo); + R_INTC_SetPriority(d0fifo_dmaintid, level); + R_INTC_Enable(d0fifo_dmaintid); + } + + d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo); + R_INTC_SetPriority(d1fifo_dmaintid, level); + R_INTC_Enable(d1fifo_dmaintid); + } +#endif +} + +/******************************************************************************* +* Function Name: usb0_host_reset_module +* Description : Initializes the USB module. +* : Enables providing clock to the USB module. +* : Sets USB bus wait register. +* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ +* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +void usb0_host_reset_module (uint16_t clockmode) +{ + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_UPLLE_SHIFT, + USB_SYSCFG_UPLLE) == 1) + { + if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode) + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb0_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + + USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT); +} + +/******************************************************************************* +* Function Name: usb0_host_get_buf_size +* Description : Obtains pipe buffer size specified by the argument and +* : maximum packet size of the USB device in use. +* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum +* : packet size of the USB device using the corresponding pipe. +* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the +* : corresponding pipe is in continuous transfer mode, +* : obtains the buffer size allocated in the corresponcing pipe, +* : when incontinuous transfer, obtains maximum packet size. +* Arguments : uint16_t ; pipe Number +* Return Value : Maximum packet size or buffer size +*******************************************************************************/ +uint16_t usb0_host_get_buf_size (uint16_t pipe) +{ + uint16_t size; + uint16_t bufsize; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) + { + bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); + size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + } + return size; +} + +/******************************************************************************* +* Function Name: usb0_host_get_mxps +* Description : Obtains maximum packet size of the USB device using the pipe +* : specified by the argument. +* Arguments : uint16_t ; Pipe Number +* Return Value : Max Packet Size +*******************************************************************************/ +uint16_t usb0_host_get_mxps (uint16_t pipe) +{ + uint16_t size; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + + return size; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c new file mode 100644 index 0000000000..2f8ef12a38 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c @@ -0,0 +1,434 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_controlrw.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_CtrlTransStart +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *Buf ; Data buffer +* Return Value : DEVDRV_SUCCESS ; SUCCESS +* : DEVDRV_ERROR ; ERROR +*******************************************************************************/ +int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val, + uint16_t Indx, uint16_t Len, uint8_t * Buf) +{ + if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED) + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 1, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + else + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]); + + if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); + + if (Len == 0) + { + g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */ + } + else + { + if ((Req & 0x0080) != 0) + { + g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */ + } + else + { + g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */ + } + } + + g_usb0_host_SavReq = Req; /* save request */ + g_usb0_host_SavVal = Val; + g_usb0_host_SavIndx = Indx; + g_usb0_host_SavLen = Len; + } + else + { + if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val) + || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len)) + { + return DEVDRV_ERROR; + } + } + + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + /* --------------- SETUP STAGE --------------- */ + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE): + usb0_host_SetupStage(Req, Val, Indx, Len); + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_READ: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_NO_DATA: + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + default: + break; + } + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + } + break; + + /* --------------- DATA STAGE --------------- */ + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE): + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + usb0_host_CtrlWriteStart((uint32_t)Len, Buf); + break; + + case USB_HOST_MODE_READ: + usb0_host_CtrlReadStart((uint32_t)Len, Buf); + break; + + default: + break; + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL): + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + /* --------------- STATUS STAGE --------------- */ + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE): + usb0_host_StatusStage(); + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */ + usb0_host_set_pid_nak(USB_HOST_PIPE0); + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES): + if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL): + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + default: + break; + } + + if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT) + { + RZA_IO_RegWrite_16(&USB200.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_SetupStage +* Description : Executes USB control transfer/set up stage. +* Arguments : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* Return Value : none +*******************************************************************************/ +void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len) +{ + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */ + USB200.USBREQ = Req; + USB200.USBVAL = Val; + USB200.USBINDX = Indx; + USB200.USBLENG = Len; + USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */ +} + +/******************************************************************************* +* Function Name: usb0_host_StatusStage +* Description : Executes USB control transfer/status stage. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_StatusStage (void) +{ + uint8_t Buf1[16]; + + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_READ: + usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + case USB_HOST_MODE_WRITE: + usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + case USB_HOST_MODE_NO_DATA: + usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_host_CtrlWriteStart +* Description : Executes USB control transfer/data stage(write). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : USB_HOST_WRITESHRT ; End of data write +* : USB_HOST_WRITEEND ; End of data write (not null) +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_FIFOERROR ; FIFO access error +*******************************************************************************/ +uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t EndFlag_K; + uint16_t mbw; + + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb0_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB200.DCPCFG, + 1, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0); + /* Host Control sequence */ + switch (EndFlag_K) + { + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write (not null) */ + case USB_HOST_WRITING: /* Continue of data write */ + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + break; + + default: + break; + } + usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ + return (EndFlag_K); /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_host_CtrlReadStart +* Description : Executes USB control transfer/data stage(read). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : none +*******************************************************************************/ +void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t mbw; + + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DOING; + + usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb0_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB200.DCPCFG, + 0, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]); + usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw); + USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */ + usb0_host_clear_pid_stall(USB_HOST_PIPE0); + usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c new file mode 100644 index 0000000000..baa39adaac --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c @@ -0,0 +1,889 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_drv_api.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_api_host_init +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint8_t int_level : USB Module interrupt level +* : USBU16 mode : USB_HOST_HIGH_SPEED +* : USB_HOST_FULL_SPEED +* : uint16_t clockmode : USB Clock mode +* Return Value : USB detach or attach +* : USB_HOST_ATTACH +* : USB_HOST_DETACH +*******************************************************************************/ +uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) +{ + uint16_t connect; + volatile uint8_t dummy_buf; + + CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */ + dummy_buf = CPG.STBCR7; /* (Dummy read) */ + + g_usb0_host_SupportUsbDeviceSpeed = mode; + + usb0_host_setting_interrupt(int_level); + usb0_host_reset_module(clockmode); + + g_usb0_host_bchg_flag = USB_HOST_NO; + g_usb0_host_detach_flag = USB_HOST_NO; + g_usb0_host_attach_flag = USB_HOST_NO; + + g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; + g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb0_host_InitModule(); + + connect = usb0_host_CheckAttach(); + + if (connect == USB_HOST_ATTACH) + { + g_usb0_host_attach_flag = USB_HOST_YES; + } + else + { + usb0_host_UsbDetach2(); + } + + return connect; +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb0_api_host_enumeration +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint16_t devadr : device address +* Return Value : DEVDRV_USBH_DETACH_ERR : device detach +* : DEVDRV_SUCCESS : device enumeration success +* : DEVDRV_ERROR : device enumeration error +*******************************************************************************/ +int32_t usb0_api_host_enumeration (uint16_t devadr) +{ + int32_t ret; + uint16_t driver_sts; + + g_usb0_host_setUsbAddress = devadr; + + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = DEVDRV_USBH_DETACH_ERR; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = DEVDRV_SUCCESS; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_detach +* Description : USB detach routine +* Arguments : none +* Return Value : USB_HOST_DETACH : USB detach +* : USB_HOST_ATTACH : USB attach +* : DEVDRV_ERROR : error +*******************************************************************************/ +int32_t usb0_api_host_detach (void) +{ + int32_t ret; + uint16_t driver_sts; + + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = USB_HOST_DETACH; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = USB_HOST_ATTACH; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb0_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_data_in +* Description : Executes USB transfer as data-in in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1) + { + return DEVDRV_ERROR; + } + + if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb0_host_start_receive_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb0_host_stop_transfer(Pipe); + + g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_data_out +* Description : Executes USB transfer as data-out in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + return DEVDRV_ERROR; + } + + if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb0_host_start_send_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb0_host_stop_transfer(Pipe); + + g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_control_transfer +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *buf ; Buffer +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_USBH_DETACH_ERR ; device detach +* : DEVDRV_USBH_CTRL_COM_ERR ; device no response +* : DEVDRV_USBH_STALL ; STALL +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, + uint16_t Len, uint8_t * Buf) +{ + int32_t ret; + + do + { + ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf); + + if (ret == DEVDRV_SUCCESS) + { + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE) + && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)) + { + break; + } + } + else + { + return DEVDRV_ERROR; + } + } while (1); + + if (g_usb0_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb0_host_pipe_status[USB_HOST_PIPE0]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_CTRL_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_api_host_set_endpoint +* Description : Sets end point on the information specified in the argument. +* Arguments : uint16_t devadr ; device address +* : uint8_t *configdescriptor ; device configration descriptor +* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor) +{ + uint16_t ret; + uint32_t end_point; + uint32_t offset; + uint32_t totalLength; + USB_HOST_CFG_PIPETBL_t * pipe_table; + + /* End Point Search */ + end_point = 0; + offset = configdescriptor[0]; + totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8)); + + do + { + if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC) + { + pipe_table = &user_table[end_point]; + + if (pipe_table->pipe_number == 0xffff) + { + break; + } + + ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]); + + if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT)) + { + return DEVDRV_ERROR; + } + + ++end_point; + } + + /* Next End Point Search */ + offset += configdescriptor[offset]; + + } while (offset < totalLength); + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_api_host_clear_endpoint +* Description : Clears the pipe definition table specified in the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + + user_table++; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_api_host_clear_endpoint_pipe +* Description : Clears the pipe definition table specified in the argument. +* Arguments : uint16_t pipe_sel : Pipe Number +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + + if (user_table->pipe_number == pipe_sel) + { + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + break; + } + + user_table++; + } + + return DEVDRV_SUCCESS; +} +#endif + +/******************************************************************************* +* Function Name: usb0_api_host_SetEndpointTable +* Description : Sets the end point on the information specified by the argument. +* Arguments : uint16_t devadr : device address +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* : uint8_t *Table : Endpoint descriptor +* Return Value : USB_HOST_DIR_H_IN ; IN endpoint +* : USB_HOST_DIR_H_OUT ; OUT endpoint +* : USB_END_POINT_ERROR ; error +*******************************************************************************/ +uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table) +{ + uint16_t PipeCfg; + uint16_t PipeMaxp; + uint16_t pipe_number; + uint16_t ret; + uint16_t ret_flag = 0; // avoid warning. + + pipe_number = user_table->pipe_number; + + if (Table[1] != USB_HOST_ENDPOINT_DESC) + { + return USB_END_POINT_ERROR; + } + + switch (Table[3] & USB_HOST_EP_TYPE) + { + case USB_HOST_EP_CNTRL: + ret_flag = USB_END_POINT_ERROR; + break; + + case USB_HOST_EP_ISO: + if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_ISO; + break; + + case USB_HOST_EP_BULK: + if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_BULK; + break; + + case USB_HOST_EP_INT: + if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_INTERRUPT; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Set pipe configuration table */ + if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= USB_HOST_DIR_H_IN; + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */ + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + break; + + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); +#ifdef __USB_DMA_BFRE_ENABLE__ + /* this routine cannnot be perfomred if read operation is executed in buffer size */ + PipeCfg |= USB_HOST_BFREON; +#endif + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + ret = USB_HOST_PIPE_IN; + } + else /* OUT(send) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + } + PipeCfg |= USB_HOST_DIR_H_OUT; + ret = USB_HOST_PIPE_OUT; + } + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE; + break; + + case USB_HOST_D0USE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE; + break; + + case USB_HOST_D1USE: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE; + break; + + case USB_HOST_D0DMA: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA; + break; + + case USB_HOST_D1DMA: + g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Endpoint number set */ + PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + + /* Max packet size set */ + PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8)); + + if (PipeMaxp == 0u) + { + return USB_END_POINT_ERROR; + } + + /* Set device address */ + PipeMaxp |= (uint16_t)(devadr << 12); + + user_table->pipe_cfg = PipeCfg; + user_table->pipe_max_pktsize = PipeMaxp; + + usb0_host_resetEP(user_table); + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_resetEP +* Description : Sets the end point on the information specified by the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table +* Return Value : none +*******************************************************************************/ +static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl) +{ + + uint16_t pipe; + + /* Host pipe */ + /* The pipe number of pipe definition table is obtained */ + pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */ + + /* FIFO port access pipe is set to initial value */ + /* The connection with FIFO should be cut before setting the pipe */ + if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + /* Interrupt of pipe set is disabled */ + usb0_host_disable_brdy_int(pipe); + usb0_host_disable_nrdy_int(pipe); + usb0_host_disable_bemp_int(pipe); + + /* Pipe to set is set to NAK */ + usb0_host_set_pid_nak(pipe); + + /* Pipe is set */ + USB200.PIPESEL = pipe; + + USB200.PIPECFG = tbl->pipe_cfg; + USB200.PIPEBUF = tbl->pipe_buf; + USB200.PIPEMAXP = tbl->pipe_max_pktsize; + USB200.PIPEPERI = tbl->pipe_cycle; + + g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg; + g_usb0_host_pipebuf[pipe] = tbl->pipe_buf; + g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize; + g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle; + + /* Sequence bit clear */ + usb0_host_set_sqclr(pipe); + + usb0_host_aclrm(pipe); + usb0_host_set_csclr(pipe); + + /* Pipe window selection is set to unused */ + USB200.PIPESEL = USB_HOST_PIPE0; + +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb0_api_host_data_count +* Description : Get g_usb0_host_data_count[pipe] +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t *data_count ; return g_usb0_data_count[pipe] +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count) +{ + if (pipe > USB_HOST_MAX_PIPE_NO) + { + return DEVDRV_ERROR; + } + + *data_count = g_usb0_host_PipeDataSize[pipe]; + + return DEVDRV_SUCCESS; +} +#endif + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c new file mode 100644 index 0000000000..2d1d5f5fc4 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_global.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +const uint16_t g_usb0_host_bit_set[16] = +{ + 0x0001, 0x0002, 0x0004, 0x0008, + 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, + 0x1000, 0x2000, 0x4000, 0x8000 +}; + +uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1]; +uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1]; + +USB_HOST_DMA_t g_usb0_host_DmaInfo[2]; + +uint16_t g_usb0_host_DmaPipe[2]; +uint16_t g_usb0_host_DmaBval[2]; +uint16_t g_usb0_host_DmaStatus[2]; + +uint16_t g_usb0_host_driver_state; +uint16_t g_usb0_host_ConfigNum; +uint16_t g_usb0_host_CmdStage; +uint16_t g_usb0_host_bchg_flag; +uint16_t g_usb0_host_detach_flag; +uint16_t g_usb0_host_attach_flag; + +uint16_t g_usb0_host_UsbAddress; +uint16_t g_usb0_host_setUsbAddress; +uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +uint16_t g_usb0_host_UsbDeviceSpeed; +uint16_t g_usb0_host_SupportUsbDeviceSpeed; + +uint16_t g_usb0_host_SavReq; +uint16_t g_usb0_host_SavVal; +uint16_t g_usb0_host_SavIndx; +uint16_t g_usb0_host_SavLen; + +uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_init_pipe_status +* Description : Initialize pipe status. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_init_pipe_status (void) +{ + uint16_t loop; + + g_usb0_host_ConfigNum = 0; + + for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop) + { + g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE; + g_usb0_host_PipeDataSize[loop] = 0; + + /* pipe configuration in usb0_host_resetEP() */ + g_usb0_host_pipecfg[loop] = 0; + g_usb0_host_pipebuf[loop] = 0; + g_usb0_host_pipemaxp[loop] = 0; + g_usb0_host_pipeperi[loop] = 0; + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c new file mode 100644 index 0000000000..f4e5a27c77 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c @@ -0,0 +1,496 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_usbint.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_interrupt1(void); +static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_interrupt +* Description : Executes USB interrupt. +* : Register this function in the USB interrupt handler. +* : Set CFIF0 in the pipe set before the interrupt after executing +* : this function. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_host_interrupt (uint32_t int_sense) +{ + uint16_t savepipe1; + uint16_t savepipe2; + uint16_t buffer; + + savepipe1 = USB200.CFIFOSEL; + savepipe2 = USB200.PIPESEL; + usb0_host_interrupt1(); + + /* Control transmission changes ISEL within interruption processing. */ + /* For this reason, write return of ISEL cannot be performed. */ + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE); + USB200.CFIFOSEL = buffer; + USB200.PIPESEL = savepipe2; +} + +/******************************************************************************* +* Function Name: usb0_host_interrupt1 +* Description : Execue the USB interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_interrupt1 (void) +{ + uint16_t intsts0; + uint16_t intsts1; + uint16_t intenb0; + uint16_t intenb1; + uint16_t brdysts; + uint16_t nrdysts; + uint16_t bempsts; + uint16_t brdyenb; + uint16_t nrdyenb; + uint16_t bempenb; + volatile uint16_t dumy_sts; + + intsts0 = USB200.INTSTS0; + intsts1 = USB200.INTSTS1; + intenb0 = USB200.INTENB0; + intenb1 = USB200.INTENB1; + + if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + g_usb0_host_bchg_flag = USB_HOST_YES; + } + else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); +#else + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; +#endif + } + else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#else + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; +#endif + } + else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH) + && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); + g_usb0_host_detach_flag = USB_HOST_YES; + + Userdef_USB_usb0_host_detach(); + + usb0_host_UsbDetach2(); + } + else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH) + && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE)) + { + USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH; + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); + g_usb0_host_attach_flag = USB_HOST_YES; + + Userdef_USB_usb0_host_attach(); + + usb0_host_UsbAttach(); + } + else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY))) + { + brdysts = USB200.BRDYSTS; + nrdysts = USB200.NRDYSTS; + bempsts = USB200.BEMPSTS; + brdyenb = USB200.BRDYENB; + nrdyenb = USB200.NRDYENB; + bempenb = USB200.BEMPENB; + + if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb)) + { + usb0_host_BRDYInterrupt(brdysts, brdyenb); + } + else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb)) + { + usb0_host_BEMPInterrupt(bempsts, bempenb); + } + else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb)) + { + usb0_host_NRDYInterrupt(nrdysts, nrdyenb); + } + else + { + /* Do Nothing */ + } + } + else + { + /* Do Nothing */ + } + + /* Three dummy read for clearing interrupt requests */ + dumy_sts = USB200.INTSTS0; + dumy_sts = USB200.INTSTS1; + +} + +/******************************************************************************* +* Function Name: usb0_host_BRDYInterrupt +* Description : Executes USB BRDY interrupt. +* Arguments : uint16_t Status ; BRDYSTS Register Value +* : uint16_t Int_enbl ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + +#if(1) /* ohci_wrapp */ + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_READOVER: /* buffer over */ + USB200.CFIFOCTR = USB_HOST_BITBCLR; + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#else + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0); + + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + USB200.CFIFOCTR = USB_HOST_BITBCLR; + usb0_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#endif + } + else + { + usb0_host_brdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BRDYSTS; +} + +/******************************************************************************* +* Function Name: usb0_host_NRDYInterrupt +* Description : Executes USB NRDY interrupt. +* Arguments : uint16_t Status ; NRDYSTS Register Value +* : uint16_t Int_enbl ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + pid = usb0_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else if (pid == USB_HOST_PID_NAK) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_NORES; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { + /* Do Nothing */ + } + } + else + { + usb0_host_nrdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.NRDYSTS; +} + +/******************************************************************************* +* Function Name: usb0_host_BEMPInterrupt +* Description : Executes USB BEMP interrupt. +* Arguments : uint16_t Status ; BEMPSTS Register Value +* : uint16_t Int_enbl ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0])) + { + USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0]; + pid = usb0_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + /* do nothing */ + break; + } +#else + switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb0_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + default: + /* do nothing */ + break; + } +#endif + } + } + else + { + usb0_host_bemp_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB200.BEMPSTS; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c new file mode 100644 index 0000000000..4c5f810db3 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c @@ -0,0 +1,637 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_usbsig.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_EnableINT_Module(void); +static void usb0_host_Enable_AttachINT(void); +static void usb0_host_Disable_AttachINT(void); +static void usb0_host_Disable_BchgINT(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_host_InitModule +* Description : Initializes the USB module in USB host module. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_InitModule (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + + usb0_host_init_pipe_status(); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); /* HOST mode */ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DRPD_SHIFT, + USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */ + + do + { + buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); +} + +/******************************************************************************* +* Function Name: usb0_host_CheckAttach +* Description : Returns the USB device connection state. +* Arguments : none +* Return Value : uint16_t ; USB_HOST_ATTACH : Attached +* : ; USB_HOST_DETACH : not Attached +*******************************************************************************/ +uint16_t usb0_host_CheckAttach (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + uint16_t rhst; + + do + { + buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb0_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_UNDECID) + { + if (buf1 == USB_HOST_FS_JSTS) + { + if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED) + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + else + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + return USB_HOST_ATTACH; + } + else if (buf1 == USB_HOST_LS_JSTS) + { + /* Low Speed Device */ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + } + else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE)) + { + return USB_HOST_ATTACH; + } + else if (rhst == USB_HOST_LSMODE) + { + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + + return USB_HOST_DETACH; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbAttach +* Description : Connects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbAttach (void) +{ + usb0_host_EnableINT_Module(); + usb0_host_Disable_BchgINT(); + usb0_host_Disable_AttachINT(); + usb0_host_Enable_DetachINT(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbDetach +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbDetach (void) +{ + uint16_t pipe; + uint16_t devadr; + + g_usb0_host_driver_state = USB_HOST_DRV_DETACHED; + + /* Terminate all the pipes in which communications on port */ + /* are currently carried out */ + for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe) + { + if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE) + { + if (pipe == USB_HOST_PIPE0) + { + devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_DEVSEL_SHIFT, + USB_DCPMAXP_DEVSEL); + } + else + { + devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL); + } + + if (devadr == g_usb0_host_UsbAddress) + { + usb0_host_stop_transfer(pipe); + } + + g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE; + } + } + + g_usb0_host_ConfigNum = 0; + g_usb0_host_UsbAddress = 0; + g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb0_host_UsbDetach2(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbDetach2 +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_UsbDetach2 (void) +{ + usb0_host_Disable_DetachINT(); + usb0_host_Disable_BchgINT(); + usb0_host_Enable_AttachINT(); +} + +/******************************************************************************* +* Function Name: usb0_host_UsbBusReset +* Description : Issues the USB bus reset signal. +* Arguments : none +* Return Value : uint16_t ; RHST +*******************************************************************************/ +uint16_t usb0_host_UsbBusReset (void) +{ + uint16_t buffer; + uint16_t loop; + + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 1, + USB_DVSTCTR0_USBRST_SHIFT, + USB_DVSTCTR0_USBRST); + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb0_host_delay_xms(50); + + buffer = USB200.DVSTCTR0; + buffer &= (uint16_t)(~(USB_HOST_BITRST)); + buffer |= USB_HOST_BITUACT; + USB200.DVSTCTR0 = buffer; + + Userdef_USB_usb0_host_delay_xms(20); + + for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop) + { + buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (buffer == USB_HOST_HSPROC) + { + Userdef_USB_usb0_host_delay_xms(10); + } + else + { + break; + } + } + + return buffer; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbResume +* Description : Issues the USB resume signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS +* : ; DEVDRV_ERROR +*******************************************************************************/ +int32_t usb0_host_UsbResume (void) +{ + uint16_t buf; + + if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0) + { + /* not SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 1, + USB_DVSTCTR0_RESUME_SHIFT, + USB_DVSTCTR0_RESUME); + Userdef_USB_usb0_host_delay_xms(20); + + buf = USB200.DVSTCTR0; + buf &= (uint16_t)(~(USB_HOST_BITRESUME)); + buf |= USB_HOST_BITUACT; + USB200.DVSTCTR0 = buf; + + g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND; + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_UsbSuspend +* Description : Issues the USB suspend signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND +* : ; DEVDRV_ERROR :SUSPEND +*******************************************************************************/ +int32_t usb0_host_UsbSuspend (void) +{ + uint16_t buf; + + if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0) + { + /* SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB200.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb0_host_delay_xms(5); + + buf = RZA_IO_RegRead_16(&USB200.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS)) + { + usb0_host_UsbDetach(); + } + else + { + g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_host_Enable_DetachINT +* Description : Enables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Enable_DetachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 1, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_DetachINT +* Description : Disables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_DetachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Enable_AttachINT +* Description : Enables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Enable_AttachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 1, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_AttachINT +* Description : Disables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_AttachINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb0_host_Disable_BchgINT +* Description : Disables the USB bus change detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_Disable_BchgINT (void) +{ + USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG)); + RZA_IO_RegWrite_16(&USB200.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); +} + +/******************************************************************************* +* Function Name: usb0_host_set_devadd +* Description : DEVADDn register is set by specified value +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : Set value +* Return Value : none +*******************************************************************************/ +void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB200.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB200.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB200.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB200.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB200.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB200.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB200.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB200.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB200.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB200.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB200.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK); + } +} + +/******************************************************************************* +* Function Name: usb0_host_get_devadd +* Description : DEVADDn register is obtained +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : USB_HOST_DEVADD register value +* Return Value : none +*******************************************************************************/ +void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB200.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB200.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB200.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB200.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB200.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB200.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB200.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB200.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB200.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB200.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB200.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *devadd = *ptr; + } +} + +/******************************************************************************* +* Function Name: usb0_host_EnableINT_Module +* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt. +* : Enables NRDY/BEMP interrupt in the pipe0. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_host_EnableINT_Module (void) +{ + uint16_t buf; + + buf = USB200.INTENB0; + buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE); + USB200.INTENB0 = buf; + + buf = USB200.INTENB1; + buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE); + USB200.INTENB1 = buf; + + usb0_host_enable_nrdy_int(USB_HOST_PIPE0); + usb0_host_enable_bemp_int(USB_HOST_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c new file mode 100644 index 0000000000..8f081a618f --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c @@ -0,0 +1,698 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_dmacdrv.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" +#include "usb0_host_dmacdrv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ + +/* ==== Request setting information for on-chip peripheral module ==== */ +typedef enum dmac_peri_req_reg_type +{ + DMAC_REQ_MID, + DMAC_REQ_RID, + DMAC_REQ_AM, + DMAC_REQ_LVL, + DMAC_REQ_REQD +} dmac_peri_req_reg_type_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +/* ==== Prototype declaration ==== */ + +/* ==== Global variable ==== */ +/* On-chip peripheral module request setting table */ +static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] = +{ + /* MID,RID, AM,LVL,REQD */ + { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ + { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ + { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ + { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ + { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ + { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ + { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ + { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ +}; + + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 1. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 1 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->daddr_dir, + DMAC1_CHCFG_n_DAD_SHIFT, + DMAC1_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->saddr_dir, + DMAC1_CHCFG_n_SAD_SHIFT, + DMAC1_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->dst_size, + DMAC1_CHCFG_n_DDS_SHIFT, + DMAC1_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->src_size, + DMAC1_CHCFG_n_SDS_SHIFT, + DMAC1_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DMS_SHIFT, + DMAC1_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSEL_SHIFT, + DMAC1_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_SBE_SHIFT, + DMAC1_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DEM_SHIFT, + DMAC1_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_TM_SHIFT, + DMAC1_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_SEL_SHIFT, + DMAC1_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_HIEN_SHIFT, + DMAC1_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_LOEN_SHIFT, + DMAC1_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC1_CHCFG_n_AM_SHIFT, + DMAC1_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC1_CHCFG_n_LVL_SHIFT, + DMAC1_CHCFG_n_LVL); + if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + req_direction, + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC01_DMARS_CH1_RID_SHIFT, + DMAC01_DMARS_CH1_RID); + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC01_DMARS_CH1_MID_SHIFT, + DMAC01_DMARS_CH1_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Open +* Description : Enables DMAC channel 1 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_host_DMAC1_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SETEN_SHIFT, + DMAC1_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_STG_SHIFT, + DMAC1_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Close +* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_CLREN_SHIFT, + DMAC1_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC1.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC1_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 1 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 1 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_SR_SHIFT, + DMAC1_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC1.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC1.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N1TB_n = count; /* Total transfer byte count */ + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 2. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 2 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->daddr_dir, + DMAC2_CHCFG_n_DAD_SHIFT, + DMAC2_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->saddr_dir, + DMAC2_CHCFG_n_SAD_SHIFT, + DMAC2_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->dst_size, + DMAC2_CHCFG_n_DDS_SHIFT, + DMAC2_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->src_size, + DMAC2_CHCFG_n_SDS_SHIFT, + DMAC2_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DMS_SHIFT, + DMAC2_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSEL_SHIFT, + DMAC2_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_SBE_SHIFT, + DMAC2_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DEM_SHIFT, + DMAC2_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_TM_SHIFT, + DMAC2_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 2, + DMAC2_CHCFG_n_SEL_SHIFT, + DMAC2_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_HIEN_SHIFT, + DMAC2_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_LOEN_SHIFT, + DMAC2_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC2_CHCFG_n_AM_SHIFT, + DMAC2_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC2_CHCFG_n_LVL_SHIFT, + DMAC2_CHCFG_n_LVL); + if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + req_direction, + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC23_DMARS_CH2_RID_SHIFT, + DMAC23_DMARS_CH2_RID); + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC23_DMARS_CH2_MID_SHIFT, + DMAC23_DMARS_CH2_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Open +* Description : Enables DMAC channel 2 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_host_DMAC2_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SETEN_SHIFT, + DMAC2_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_STG_SHIFT, + DMAC2_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Close +* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_CLREN_SHIFT, + DMAC2_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC2.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_host_DMAC2_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 2 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 2 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_SR_SHIFT, + DMAC2_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC2.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC2.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N1TB_n = count; /* Total transfer byte count */ + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c new file mode 100644 index 0000000000..db0b4cfd1d --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c @@ -0,0 +1,778 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_userdef.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "cmsis_os.h" +#include "r_typedefs.h" +#include "iodefine.h" +#include "devdrv_usb_host_api.h" +#include "usb0_host.h" +#include "MBRZA1H.h" /* INTC Driver Header */ +#include "usb0_host_dmacdrv.h" +#include "ohci_wrapp_RZ_A1_local.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DUMMY_ACCESS OSTM0CNT + +/* #define CACHE_WRITEBACK */ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int32_t io_cwb(unsigned long start, unsigned long end); + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void Userdef_USB_usb0_host_delay_10us_2(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid +* Description : get D0FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D0FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void) +{ +#if(1) /* ohci_wrapp */ + return 0xFFFF; +#else + return DMAINT1_IRQn; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid +* Description : get D1FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D1FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void) +{ +#if(1) /* ohci_wrapp */ + return 0xFFFF; +#else + return DMAINT2_IRQn; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_attach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_attach (void) +{ +// printf("\n"); +// printf("channel 0 attach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_detach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_detach (void) +{ +// printf("\n"); +// printf("channel 0 detach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(0); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_1ms +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_1ms (void) +{ + osDelay(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_xms +* Description : Wait for the software in the period of time specified by the +* : argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t msec ; Wait Time (msec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_xms (uint32_t msec) +{ + osDelay(msec); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_10us +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t usec ; Wait Time(x 10usec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_10us (uint32_t usec) +{ + volatile int i; + + /* Wait 10us (Please change for your MCU) */ + for (i = 0; i < usec; ++i) + { + Userdef_USB_usb0_host_delay_10us_2(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_10us_2 +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void Userdef_USB_usb0_host_delay_10us_2 (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 1us (Please change for your MCU) */ + for (i = 0; i < 14; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_delay_500ns +* Description : Wait for software for 500ns. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_delay_500ns (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 500ns (Please change for your MCU) */ + /* Wait 500ns I clock 266MHz */ + tmp = DUMMY_ACCESS; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_start_dma +* Description : Enables DMA transfer on the information specified by the argument. +* : Set DMAC register by this function to enable DMA transfer. +* : After executing this function, USB module is set to start DMA +* : transfer. DMA transfer should not wait for DMA transfer complete. +* Arguments : USB_HOST_DMA_t *dma : DMA parameter +* : typedef struct{ +* : uint32_t fifo; FIFO for using +* : uint32_t buffer; Start address of transfer source/destination +* : uint32_t bytes; Transfer size(Byte) +* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) +* : uint32_t size; DMA transfer size +* : } USB_HOST_DMA_t; +* : uint16_t dfacc ; 0 : cycle steal mode +* : 1 : 16byte continuous mode +* : 2 : 32byte continuous mode +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc) +{ + uint32_t trncount; + uint32_t src; + uint32_t dst; + uint32_t size; + uint32_t dir; +#ifdef CACHE_WRITEBACK + uint32_t ptr; +#endif + + trncount = dma->bytes; + dir = dma->dir; + + if (dir == USB_HOST_FIFO2BUF) + { + /* DxFIFO determination */ + dst = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + src += 3; /* byte access */ + } + else if (size == 1) + { + src += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 3; /* byte access */ + } +#endif + } + else + { + /* DxFIFO determination */ + src = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + dst += 3; /* byte access */ + } + else if (size == 1) + { + dst += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 3; /* byte access */ + } +#endif + } + +#ifdef CACHE_WRITEBACK + ptr = (uint32_t)dma->buffer; + if ((ptr & 0x20000000ul) == 0) + { + io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount); + } +#endif + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); + } + else + { + usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); + } +} + +/******************************************************************************* +* Function Name: usb0_host_enable_dmac0 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC1 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: usb0_host_enable_dmac1 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC2 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_stop_dma0 +* Description : Disables DMA transfer. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +* Notice : This function should be executed to DMAC executed at the time +* : of specification of D0_FIF0_DMA in dma->fifo. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_host_stop_dma0 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_host_DMAC1_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_stop_dma1 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D1_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_host_stop_dma1 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_host_DMAC2_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_notice +* Description : Notice of USER +* Arguments : const char *format +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_notice (const char * format) +{ +// printf(format); + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_host_user_rdy +* Description : This function notify a user and wait for trigger +* Arguments : const char *format +* : uint16_t data +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data) +{ +// printf(format, data); + getchar(); + + return; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h new file mode 100644 index 0000000000..b1c450cd1e --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +#ifndef USB_HOST_SETTING_H +#define USB_HOST_SETTING_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_HOST_CH 0 +#define USB_HOST_HISPEED 1 + +#define INT_TRANS_MAX_NUM 4 /* min:1 max:4 */ +#define ISO_TRANS_MAX_NUM 0 /* min:0 max:2 */ + +#if (USB_HOST_CH == 0) +#include "usb0_host.h" +#define USB20X USB200 +#define USBIXUSBIX USBI0_IRQn +#define g_usbx_host_SupportUsbDeviceSpeed g_usb0_host_SupportUsbDeviceSpeed +#define g_usbx_host_UsbDeviceSpeed g_usb0_host_UsbDeviceSpeed +#define g_usbx_host_CmdStage g_usb0_host_CmdStage +#define g_usbx_host_pipe_status g_usb0_host_pipe_status +#define g_usbx_host_data_pointer g_usb0_host_data_pointer +#define g_usbx_host_data_count g_usb0_host_data_count +#define usbx_api_host_init usb0_api_host_init +#define usbx_host_UsbBusReset usb0_host_UsbBusReset +#define usbx_host_get_devadd usb0_host_get_devadd +#define usbx_host_set_devadd usb0_host_set_devadd +#define usbx_host_SetupStage usb0_host_SetupStage +#define usbx_host_CtrlWriteStart usb0_host_CtrlWriteStart +#define usbx_host_CtrlReadStart usb0_host_CtrlReadStart +#define usbx_api_host_SetEndpointTable usb0_api_host_SetEndpointTable +#define usbx_host_start_send_transfer usb0_host_start_send_transfer +#define usbx_host_start_receive_transfer usb0_host_start_receive_transfer +#define usbx_host_stop_transfer usb0_host_stop_transfer +#define usbx_host_set_sqclr usb0_host_set_sqclr +#define usbx_host_set_sqset usb0_host_set_sqset +#define usbx_host_CheckAttach usb0_host_CheckAttach +#define usbx_host_UsbDetach usb0_host_UsbDetach +#define usbx_host_UsbAttach usb0_host_UsbAttach +#define usbx_host_init_pipe_status usb0_host_init_pipe_status +#define usbx_host_get_sqmon usb0_host_get_sqmon +#else +#include "usb1_host.h" +#define USB20X USB201 +#define USBIXUSBIX USBI1_IRQn +#define g_usbx_host_SupportUsbDeviceSpeed g_usb1_host_SupportUsbDeviceSpeed +#define g_usbx_host_UsbDeviceSpeed g_usb1_host_UsbDeviceSpeed +#define g_usbx_host_CmdStage g_usb1_host_CmdStage +#define g_usbx_host_pipe_status g_usb1_host_pipe_status +#define g_usbx_host_data_pointer g_usb1_host_data_pointer +#define g_usbx_host_data_count g_usb1_host_data_count +#define usbx_api_host_init usb1_api_host_init +#define usbx_host_UsbBusReset usb1_host_UsbBusReset +#define usbx_host_get_devadd usb1_host_get_devadd +#define usbx_host_set_devadd usb1_host_set_devadd +#define usbx_host_SetupStage usb1_host_SetupStage +#define usbx_host_CtrlWriteStart usb1_host_CtrlWriteStart +#define usbx_host_CtrlReadStart usb1_host_CtrlReadStart +#define usbx_api_host_SetEndpointTable usb1_api_host_SetEndpointTable +#define usbx_host_start_send_transfer usb1_host_start_send_transfer +#define usbx_host_start_receive_transfer usb1_host_start_receive_transfer +#define usbx_host_stop_transfer usb1_host_stop_transfer +#define usbx_host_set_sqclr usb1_host_set_sqclr +#define usbx_host_set_sqset usb1_host_set_sqset +#define usbx_host_CheckAttach usb1_host_CheckAttach +#define usbx_host_UsbDetach usb1_host_UsbDetach +#define usbx_host_UsbAttach usb1_host_UsbAttach +#define usbx_host_init_pipe_status usb1_host_init_pipe_status +#define usbx_host_get_sqmon usb1_host_get_sqmon +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* USB_HOST_SETTING_H */ diff --git a/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp index 833f7ad5ed..38213c76a2 100644 --- a/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp +++ b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp @@ -47,7 +47,7 @@ USBHALHost::USBHALHost() { } void USBHALHost::init() { - ohciwrapp_init(&_usbisr, 1); + ohciwrapp_init(&_usbisr); ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero @@ -266,9 +266,6 @@ void USBHALHost::UsbIrqhandler() { usb_hcca->DoneHead = 0; } - // wait 200ms to avoid bounce - wait_ms(200); - deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE); if (int_status & OR_INTR_STATUS_WDH) { From 070e5e484732a8da13755c7c873e9c5e01c8962a Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:13:41 +0900 Subject: [PATCH 030/143] Add 2Port function to USBHost(usb1). --- .../TARGET_RZ_A1H/usb1/inc/usb1_host.h | 156 + .../TARGET_RZ_A1H/usb1/inc/usb1_host_api.h | 112 + .../usb1/inc/usb1_host_dmacdrv.h | 139 + .../usb1/src/common/usb1_host_dataio.c | 2835 +++++++++++++++++ .../usb1/src/common/usb1_host_dma.c | 355 +++ .../usb1/src/common/usb1_host_intrn.c | 285 ++ .../usb1/src/common/usb1_host_lib.c | 1598 ++++++++++ .../usb1/src/host/usb1_host_controlrw.c | 434 +++ .../usb1/src/host/usb1_host_drv_api.c | 889 ++++++ .../usb1/src/host/usb1_host_global.c | 137 + .../usb1/src/host/usb1_host_usbint.c | 497 +++ .../usb1/src/host/usb1_host_usbsig.c | 637 ++++ .../usb1/src/userdef/usb1_host_dmacdrv.c | 698 ++++ .../usb1/src/userdef/usb1_host_userdef.c | 778 +++++ 14 files changed, 9550 insertions(+) create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c create mode 100644 libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h new file mode 100644 index 0000000000..1759e70383 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h @@ -0,0 +1,156 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_HOST_H +#define USB1_HOST_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" +#include "usb_host.h" + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb1_host_bit_set[]; +extern uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb1_host_PipeIgnore[]; +extern uint16_t g_usb1_host_PipeTbl[]; +extern uint16_t g_usb1_host_pipe_status[]; +extern uint32_t g_usb1_host_PipeDataSize[]; + +extern USB_HOST_DMA_t g_usb1_host_DmaInfo[]; +extern uint16_t g_usb1_host_DmaPipe[]; +extern uint16_t g_usb1_host_DmaBval[]; +extern uint16_t g_usb1_host_DmaStatus[]; + +extern uint16_t g_usb1_host_driver_state; +extern uint16_t g_usb1_host_ConfigNum; +extern uint16_t g_usb1_host_CmdStage; +extern uint16_t g_usb1_host_bchg_flag; +extern uint16_t g_usb1_host_detach_flag; +extern uint16_t g_usb1_host_attach_flag; + +extern uint16_t g_usb1_host_UsbAddress; +extern uint16_t g_usb1_host_setUsbAddress; +extern uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +extern uint16_t g_usb1_host_UsbDeviceSpeed; +extern uint16_t g_usb1_host_SupportUsbDeviceSpeed; + +extern uint16_t g_usb1_host_SavReq; +extern uint16_t g_usb1_host_SavVal; +extern uint16_t g_usb1_host_SavIndx; +extern uint16_t g_usb1_host_SavLen; + +extern uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +/* ==== common ==== */ +void usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb1_host_is_hispeed(void); +uint16_t usb1_host_is_hispeed_enable(void); +uint16_t usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb1_host_write_buffer(uint16_t pipe); +uint16_t usb1_host_write_buffer_c(uint16_t pipe); +uint16_t usb1_host_write_buffer_d0(uint16_t pipe); +uint16_t usb1_host_write_buffer_d1(uint16_t pipe); +void usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb1_host_read_buffer(uint16_t pipe); +uint16_t usb1_host_read_buffer_c(uint16_t pipe); +uint16_t usb1_host_read_buffer_d0(uint16_t pipe); +uint16_t usb1_host_read_buffer_d1(uint16_t pipe); +uint16_t usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb1_host_read_dma(uint16_t pipe); +void usb1_host_stop_transfer(uint16_t pipe); +void usb1_host_brdy_int(uint16_t status, uint16_t int_enb); +void usb1_host_nrdy_int(uint16_t status, uint16_t int_enb); +void usb1_host_bemp_int(uint16_t status, uint16_t int_enb); +void usb1_host_setting_interrupt(uint8_t level); +void usb1_host_reset_module(uint16_t clockmode); +uint16_t usb1_host_get_buf_size(uint16_t pipe); +uint16_t usb1_host_get_mxps(uint16_t pipe); +void usb1_host_enable_brdy_int(uint16_t pipe); +void usb1_host_disable_brdy_int(uint16_t pipe); +void usb1_host_clear_brdy_sts(uint16_t pipe); +void usb1_host_enable_bemp_int(uint16_t pipe); +void usb1_host_disable_bemp_int(uint16_t pipe); +void usb1_host_clear_bemp_sts(uint16_t pipe); +void usb1_host_enable_nrdy_int(uint16_t pipe); +void usb1_host_disable_nrdy_int(uint16_t pipe); +void usb1_host_clear_nrdy_sts(uint16_t pipe); +void usb1_host_set_pid_buf(uint16_t pipe); +void usb1_host_set_pid_nak(uint16_t pipe); +void usb1_host_set_pid_stall(uint16_t pipe); +void usb1_host_clear_pid_stall(uint16_t pipe); +uint16_t usb1_host_get_pid(uint16_t pipe); +void usb1_host_set_sqclr(uint16_t pipe); +void usb1_host_set_sqset(uint16_t pipe); +void usb1_host_set_csclr(uint16_t pipe); +void usb1_host_aclrm(uint16_t pipe); +void usb1_host_set_aclrm(uint16_t pipe); +void usb1_host_clr_aclrm(uint16_t pipe); +uint16_t usb1_host_get_sqmon(uint16_t pipe); +uint16_t usb1_host_get_inbuf(uint16_t pipe); + +/* ==== host ==== */ +void usb1_host_init_pipe_status(void); +int32_t usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +void usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +uint16_t usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table); +void usb1_host_StatusStage(void); +void usb1_host_get_devadd(uint16_t addr, uint16_t *devadd); +void usb1_host_set_devadd(uint16_t addr, uint16_t *devadd); +void usb1_host_InitModule(void); +uint16_t usb1_host_CheckAttach(void); +void usb1_host_UsbDetach(void); +void usb1_host_UsbDetach2(void); +void usb1_host_UsbAttach(void); +uint16_t usb1_host_UsbBusReset(void); +int32_t usb1_host_UsbResume(void); +int32_t usb1_host_UsbSuspend(void); +void usb1_host_Enable_DetachINT(void); +void usb1_host_Disable_DetachINT(void); +void usb1_host_UsbStateManager(void); + + +#endif /* USB1_HOST_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h new file mode 100644 index 0000000000..63ae6d6508 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h @@ -0,0 +1,112 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_HOST_API_H +#define USB1_HOST_API_H + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb1_host_interrupt(uint32_t int_sense); +void usb1_host_dma_interrupt_d0fifo(uint32_t int_sense); +void usb1_host_dma_interrupt_d1fifo(uint32_t int_sense); + +uint16_t usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +int32_t usb1_api_host_enumeration(uint16_t devadr); +int32_t usb1_api_host_detach(void); +int32_t usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +int32_t usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); +int32_t usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table); +int32_t usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); +uint16_t usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table); +int32_t usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count); + +int32_t usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum); +int32_t usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); +int32_t usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir); +uint16_t usb1_api_host_GetUsbDeviceState(void); + +void usb1_api_host_elt_4_4(void); +void usb1_api_host_elt_4_5(void); +void usb1_api_host_elt_4_6(void); +void usb1_api_host_elt_4_7(void); +void usb1_api_host_elt_4_8(void); +void usb1_api_host_elt_4_9(void); +void usb1_api_host_elt_get_desc(void); + +void usb1_host_EL_ModeInit(void); +void usb1_host_EL_SetUACT(void); +void usb1_host_EL_ClearUACT(void); +void usb1_host_EL_SetTESTMODE(uint16_t mode); +void usb1_host_EL_ClearNRDYSTS(uint16_t pipe); +uint16_t usb1_host_EL_GetINTSTS1(void); +void usb1_host_EL_UsbBusReset(void); +void usb1_host_EL_UsbAttach(void); +void usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb1_host_EL_StatusStage(void); +void usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +int32_t usb1_host_EL_UsbSuspend(void); +int32_t usb1_host_EL_UsbResume(void); + +#if 0 /* prototype in devdrv_usb_host_api.h */ +uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void); +void Userdef_USB_usb1_host_attach(void); +void Userdef_USB_usb1_host_detach(void); +void Userdef_USB_usb1_host_delay_1ms(void); +void Userdef_USB_usb1_host_delay_xms(uint32_t msec); +void Userdef_USB_usb1_host_delay_10us(uint32_t usec); +void Userdef_USB_usb1_host_delay_500ns(void); +void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc); +uint32_t Userdef_USB_usb1_host_stop_dma0(void); +uint32_t Userdef_USB_usb1_host_stop_dma1(void); +#endif + +#endif /* USB1_HOST_API_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h new file mode 100644 index 0000000000..a4c3943d7a --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_dmacdrv.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_HOST_DMACDRV_H +#define USB1_HOST_DMACDRV_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef struct dmac_transinfo +{ + uint32_t src_addr; /* Transfer source address */ + uint32_t dst_addr; /* Transfer destination address */ + uint32_t count; /* Transfer byte count */ + uint32_t src_size; /* Transfer source data size */ + uint32_t dst_size; /* Transfer destination data size */ + uint32_t saddr_dir; /* Transfer source address direction */ + uint32_t daddr_dir; /* Transfer destination address direction */ +} dmac_transinfo_t; + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* ==== Transfer specification of the sample program ==== */ +#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ +#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ + +/* ==== DMA modes ==== */ +#define DMAC_MODE_REGISTER (0) /* Register mode */ +#define DMAC_MODE_LINK (1) /* Link mode */ + +/* ==== Transfer requests ==== */ +#define DMAC_REQ_MODE_EXT (0) /* External request */ +#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ +#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ + +/* ==== DMAC transfer sizes ==== */ +#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ +#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ +#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ +#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ +#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ +#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ +#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ +#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ + +/* ==== Address increment for transferring ==== */ +#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ +#define DMAC_TRANS_ADR_INC (0) /* Increment */ + +/* ==== Method for detecting DMA request ==== */ +#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ +#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ +#define DMAC_REQ_DET_LOW (2) /* Low level detection */ +#define DMAC_REQ_DET_HIGH (3) /* High level detection */ + +/* ==== Request Direction ==== */ +#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ +#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ + +/* ==== Descriptors ==== */ +#define DMAC_DESC_HEADER (0) /* Header */ +#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ +#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ +#define DMAC_DESC_COUNT (3) /* Transaction Byte */ +#define DMAC_DESC_CHCFG (4) /* Channel Confg */ +#define DMAC_DESC_CHITVL (5) /* Channel Interval */ +#define DMAC_DESC_CHEXT (6) /* Channel Extension */ +#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ + +/* ==== On-chip peripheral module requests ===== */ +typedef enum dmac_request_factor +{ + DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ + DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ + DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ + DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ + DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ + DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ + DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ + DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ +} dmac_request_factor_t; + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb1_host_DMAC3_Open(uint32_t req); +void usb1_host_DMAC3_Close(uint32_t *remain); +void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb1_host_DMAC4_Open(uint32_t req); +void usb1_host_DMAC4_Close(uint32_t *remain); +void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +#endif /* USB1_HOST_DMACDRV_H */ + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c new file mode 100644 index 0000000000..aa76d6143f --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c @@ -0,0 +1,2835 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_dataio.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static uint16_t g_usb1_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)]; + +static void usb1_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static uint16_t usb1_host_read_dma_d0(uint16_t pipe); +static uint16_t usb1_host_read_dma_d1(uint16_t pipe); +static uint16_t usb1_host_write_dma_d0(uint16_t pipe); +static uint16_t usb1_host_write_dma_d1(uint16_t pipe); + +static void usb1_host_read_c_fifo(uint16_t pipe, uint16_t count); +static void usb1_host_write_c_fifo(uint16_t Pipe, uint16_t count); +static void usb1_host_read_d0_fifo(uint16_t pipe, uint16_t count); +static void usb1_host_write_d0_fifo(uint16_t pipe, uint16_t count); +static void usb1_host_read_d1_fifo(uint16_t pipe, uint16_t count); +static void usb1_host_write_d1_fifo(uint16_t pipe, uint16_t count); + +static void usb1_host_clear_transaction_counter(uint16_t pipe); +static void usb1_host_set_transaction_counter(uint16_t pipe, uint32_t count); + +static uint32_t usb1_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr); + +static uint16_t usb1_host_set_dfacc_d0(uint16_t mbw, uint32_t count); +static uint16_t usb1_host_set_dfacc_d1(uint16_t mbw, uint32_t count); + + +/******************************************************************************* +* Function Name: usb1_host_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t usefifo; + uint16_t mbw; + + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + usb1_host_clear_bemp_sts(pipe); + usb1_host_clear_brdy_sts(pipe); + usb1_host_clear_nrdy_sts(pipe); + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + + usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + case USB_HOST_D0FIFO_DMA: + usefifo = USB_HOST_D0USE; + break; + + case USB_HOST_D1FIFO_USE: + case USB_HOST_D1FIFO_DMA: + usefifo = USB_HOST_D1USE; + break; + + default: + usefifo = USB_HOST_CUSE; + break; + }; + + usb1_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw); + + usb1_host_clear_transaction_counter(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + status = usb1_host_write_buffer(pipe); + + if (status != USB_HOST_FIFOERROR) + { + usb1_host_set_pid_buf(pipe); + } + + return status; +} + +/******************************************************************************* +* Function Name: usb1_host_write_buffer +* Description : Writes data in the buffer allocated in the pipe specified by +* : the argument. The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_write_buffer (uint16_t pipe) +{ + uint16_t status; + uint16_t usefifo; + + g_usb1_host_PipeIgnore[pipe] = 0; + usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + status = usb1_host_write_buffer_d0(pipe); + break; + + case USB_HOST_D1FIFO_USE: + status = usb1_host_write_buffer_d1(pipe); + break; + + case USB_HOST_D0FIFO_DMA: + status = usb1_host_write_dma_d0(pipe); + break; + + case USB_HOST_D1FIFO_DMA: + status = usb1_host_write_dma_d1(pipe); + break; + + default: + status = usb1_host_write_buffer_c(pipe); + break; + }; + + switch (status) + { + case USB_HOST_WRITING: /* Continue of data write */ + usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + usb1_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write */ + case USB_HOST_WRITESHRT: /* End of data write */ + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + usb1_host_clear_nrdy_sts(pipe); + usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + + /* for last transfer */ + usb1_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEDMA: /* DMA write */ + usb1_host_clear_nrdy_sts(pipe); + usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb1_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_write_buffer_c +* Description : Writes data in the buffer allocated in the pipe specified in +* : the argument. Writes data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_write_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + + if (pipe == USB_HOST_PIPE0) + { + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw); + } + else + { + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + } + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb1_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_host_write_c_fifo(pipe, (uint16_t)count); + + if (g_usb1_host_data_count[pipe] < (uint32_t)size) + { + g_usb1_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB201.CFIFOCTR, + USB_CFIFOCTR_BVAL_SHIFT, + USB_CFIFOCTR_BVAL) == 0) + { + USB201.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb1_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_write_buffer_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_write_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb1_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_host_write_d0_fifo(pipe, (uint16_t)count); + + if (g_usb1_host_data_count[pipe] < (uint32_t)size) + { + g_usb1_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB201.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb1_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_write_buffer_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND ; Write end +* : USB_HOST_WRITESHRT ; short data +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_WRITEDMA ; Write DMA +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_write_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] <= (uint32_t)size) + { + status = USB_HOST_WRITEEND; /* write continues */ + count = g_usb1_host_data_count[pipe]; + + if (count == 0) + { + status = USB_HOST_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = USB_HOST_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_host_write_d1_fifo(pipe, (uint16_t)count); + + if (g_usb1_host_data_count[pipe] < (uint32_t)size) + { + g_usb1_host_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + USB201.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb1_host_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_write_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D0FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb1_host_write_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb1_host_data_count[pipe]; + + if (count != 0) + { + g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 1; + } + else + { + g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0; + } + + dfacc = usb1_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe]; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb1_host_data_count[pipe] = 0; + g_usb1_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_write_dma_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D1FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_WRITEEND : Write end +* : USB_HOST_WRITESHRT : short data +* : USB_HOST_WRITING : Continue of data write +* : USB_HOST_WRITEDMA : Write DMA +* : USB_HOST_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb1_host_write_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + count = g_usb1_host_data_count[pipe]; + + if (count != 0) + { + g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 1; + } + else + { + g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0; + } + + dfacc = usb1_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe]; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc); + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + + g_usb1_host_data_count[pipe] = 0; + g_usb1_host_data_pointer[pipe] += count; + + status = USB_HOST_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = USB_HOST_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb1_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t usefifo; + + usb1_host_clear_bemp_sts(pipe); + usb1_host_clear_brdy_sts(pipe); + usb1_host_clear_nrdy_sts(pipe); + + usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb1_host_start_receive_trns_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_USE: + usb1_host_start_receive_trns_d1(pipe, size, data); + break; + + case USB_HOST_D0FIFO_DMA: + usb1_host_start_receive_dma_d0(pipe, size, data); + break; + + case USB_HOST_D1FIFO_DMA: + usb1_host_start_receive_dma_d1(pipe, size, data); + break; + + default: + usb1_host_start_receive_trns_c(pipe, size, data); + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_trns_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* : When storing data in the buffer allocated in the pipe specified in the +* : argument, BRDY interrupt is generated to read data +* : in the interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_host_set_pid_nak(pipe); + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_PipeIgnore[pipe] = 0; + + g_usb1_host_PipeDataSize[pipe] = size; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw); + USB201.CFIFOCTR = USB_HOST_BITBCLR; + + usb1_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + + usb1_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_trns_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data in the +* : interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_host_set_pid_nak(pipe); + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_PipeIgnore[pipe] = 0; + + g_usb1_host_PipeDataSize[pipe] = size; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb1_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + + usb1_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_trns_d1 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D1FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_host_set_pid_nak(pipe); + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_PipeIgnore[pipe] = 0; + + g_usb1_host_PipeDataSize[pipe] = size; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb1_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + + usb1_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_dma_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_host_set_pid_nak(pipe); + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_PipeIgnore[pipe] = 0; + + g_usb1_host_PipeDataSize[pipe] = 0; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw); + + usb1_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb1_host_read_dma(pipe); + + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + } + else + { + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + } + + usb1_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_start_receive_dma_d1 +* Description : Read data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_host_set_pid_nak(pipe); + g_usb1_host_data_count[pipe] = size; + g_usb1_host_data_pointer[pipe] = (uint8_t *)data; + g_usb1_host_PipeIgnore[pipe] = 0; + + g_usb1_host_PipeDataSize[pipe] = 0; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT; + + mbw = usb1_host_get_mbw(size, (uint32_t)data); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw); + + usb1_host_set_transaction_counter(pipe, size); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb1_host_read_dma(pipe); + + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + } + else + { + usb1_host_enable_nrdy_int(pipe); + usb1_host_enable_brdy_int(pipe); + } + + usb1_host_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_read_buffer +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Uses FIF0 set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_read_buffer (uint16_t pipe) +{ + uint16_t status; + + g_usb1_host_PipeIgnore[pipe] = 0; + + if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + status = usb1_host_read_buffer_d0(pipe); + } + else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + status = usb1_host_read_buffer_d1(pipe); + } + else + { + status = usb1_host_read_buffer_c(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb1_host_disable_brdy_int(pipe); + g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe]; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE) + { + USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE) + { + USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe]; + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_buffer_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_read_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_host_data_count[pipe]; + } + else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_host_read_c_fifo(pipe, (uint16_t)count); + } + + g_usb1_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_buffer_d0 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_read_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_host_data_count[pipe]; + } + else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_host_read_d0_fifo(pipe, (uint16_t)count); + } + + g_usb1_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_buffer_d1 +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_read_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_host_data_count[pipe]; + } + else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + usb1_host_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) !=0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + usb1_host_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_host_read_d1_fifo(pipe, (uint16_t)count); + } + + g_usb1_host_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_dma +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO or D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_host_read_dma (uint16_t pipe) +{ + uint16_t status; + + g_usb1_host_PipeIgnore[pipe] = 0; + + if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + status = usb1_host_read_dma_d0(pipe); + } + else + { + status = usb1_host_read_dma_d1(pipe); + } + + switch (status) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READZERO: /* End of data read */ + usb1_host_disable_brdy_int(pipe); + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb1_host_disable_brdy_int(pipe); + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe]; + } + break; + + case USB_HOST_READOVER: /* buffer over */ + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe]; + } +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#else + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; +#endif + break; + + case USB_HOST_FIFOERROR: /* FIFO access status */ + default: + usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb1_host_read_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb1_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb1_host_data_count[pipe]; + } + else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb1_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb1_host_set_dfacc_d0(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */ + g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */ + + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe]; + g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc); + + usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw , dfacc); + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb1_host_data_count[pipe] -= count; + g_usb1_host_data_pointer[pipe] += count; + g_usb1_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_read_dma_d1 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by DMA transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_HOST_READEND ; Read end +* : USB_HOST_READSHRT ; short data +* : USB_HOST_READZERO ; zero data +* : USB_HOST_READING ; Continue of data read +* : USB_HOST_READOVER ; buffer over +* : USB_HOST_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb1_host_read_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb1_host_data_count[pipe]; + status = USB_HOST_READING; + } + else + { + buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + + if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */ + { + return USB_HOST_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_HOST_BITDTLN); + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_HOST_READOVER; + count = g_usb1_host_data_count[pipe]; + } + else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_HOST_READEND; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_HOST_READING; + count = dtln; + + if (count == 0) + { + status = USB_HOST_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_HOST_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */ + status = USB_HOST_READZERO; /* Null Packet receive */ + } + else + { + usb1_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb1_host_set_dfacc_d1(mbw, count); + + if (mbw == USB_HOST_BITMBW_32) + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_HOST_BITMBW_16) + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */ + g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */ + + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe]; + g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count; + + if (status == USB_HOST_READING) + { + g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY; + } + else + { + g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND; + } + + Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc); + + usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc); + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb1_host_data_count[pipe] -= count; + g_usb1_host_data_pointer[pipe] += count; + g_usb1_host_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_change_fifo_port +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. After allocating FIF0, waits in the software +* : till the corresponding pipe becomes ready. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : USB_HOST_FIFOERROR ; Error +* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value +*******************************************************************************/ +uint16_t usb1_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + usb1_host_set_curpipe(pipe, fifosel, isel, mbw); + + for (loop = 0; loop < 4; loop++) + { + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB201.CFIFOCTR; + break; + + case USB_HOST_D0USE: + case USB_HOST_D0DMA: + buffer = USB201.D0FIFOCTR; + break; + + case USB_HOST_D1USE: + case USB_HOST_D1DMA: + buffer = USB201.D1FIFOCTR; + break; + + default: + buffer = 0; + break; + } + + if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY) + { + return buffer; + } + + loop2 = 25; + + while (loop2-- > 0) + { + /* wait */ + } + } + + return USB_HOST_FIFOERROR; +} + +/******************************************************************************* +* Function Name: usb1_host_set_curpipe +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb1_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + g_usb1_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB201.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB201.D0FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB201.D1FIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb1_host_set_curpipe2 +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument.(DFACC) +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* : uint16_t dfacc ; DFACC Access mode +* Return Value : none +*******************************************************************************/ +void usb1_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) +{ + uint16_t buffer; + uint32_t loop; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + uint32_t dummy; +#endif + volatile uint32_t loop2; + + g_usb1_host_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_HOST_CUSE: + buffer = USB201.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_HOST_BITISEL); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + + buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)) + == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D0DMA: + case USB_HOST_D0USE: + buffer = USB201.D0FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB201.D0FIFO.UINT32; + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_HOST_D1DMA: + case USB_HOST_D1USE: + buffer = USB201.D1FIFOSEL; +#ifdef __USB_HOST_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_HOST_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); +#endif + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_HOST_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB201.D1FIFO.UINT32; + loop = dummy; // avoid warning. + } +#endif + + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb1_host_write_c_fifo +* Description : Writes data in CFIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_write_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.CFIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_read_c_fifo +* Description : Reads data from CFIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_read_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_host_data_pointer[pipe] = USB201.CFIFO.UINT8[HH]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT16[H]; + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT32; + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_write_d0_fifo +* Description : Writes data in D0FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_write_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.D0FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_read_d0_fifo +* Description : Reads data from D0FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating DOFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_host_mbw[]. +* Arguments : uint16_t Pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_read_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_host_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H]; + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT32; + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_write_d1_fifo +* Description : Writes data in D1FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_write_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.D1FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]); + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_read_d1_fifo +* Description : Reads data from D1FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_host_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_host_read_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_host_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH]; + g_usb1_host_data_pointer[pipe] += 1; + } + } + else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H]; + g_usb1_host_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT32; + g_usb1_host_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_com_get_dmasize +* Description : Calculates access width of DMA transfer by the argument to + return as the Return Value. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : DMA transfer size : 0 8bit +* : : 1 16bit +* : : 2 32bit +*******************************************************************************/ +static uint32_t usb1_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + + if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) + { + /* When transfer byte count is odd */ + /* or transfer data area is 8-bit alignment */ + size = 0; /* 8bit */ + } + else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) + { + /* When the transfer byte count is multiples of 2 */ + /* or the transfer data area is 16-bit alignment */ + size = 1; /* 16bit */ + } + else + { + /* When the transfer byte count is multiples of 4 */ + /* or the transfer data area is 32-bit alignment */ + size = 2; /* 32bit */ + } + + return size; +} + +/******************************************************************************* +* Function Name: usb1_host_get_mbw +* Description : Calculates access width of DMA to return the value set in MBW. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit +* : : USB_HOST_BITMBW_16 16bit +* : : USB_HOST_BITMBW_32 32bit +*******************************************************************************/ +uint16_t usb1_host_get_mbw (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + uint16_t mbw; + + size = usb1_host_com_get_dmasize(trncount, dtptr); + + if (size == 0) + { + /* 8bit */ + mbw = USB_HOST_BITMBW_8; + } + else if (size == 1) + { + /* 16bit */ + mbw = USB_HOST_BITMBW_16; + } + else + { + /* 32bit */ + mbw = USB_HOST_BITMBW_32; + } + + return mbw; +} + +/******************************************************************************* +* Function Name: usb1_host_set_transaction_counter +* Description : Sets transaction counter by the argument(PIPEnTRN). +* : Clears transaction before setting to enable transaction counter setting. +* Arguments : uint16_t pipe ; Pipe number +* : uint32_t bsize : Data transfer size +* Return Value : none +*******************************************************************************/ +static void usb1_host_set_transaction_counter (uint16_t pipe, uint32_t bsize) +{ + uint16_t mxps; + uint16_t cnt; + + if (bsize == 0) + { + return; + } + + mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */ + + if ((bsize % mxps) == 0) + { + cnt = (uint16_t)(bsize / mxps); + } + else + { + cnt = (uint16_t)((bsize / mxps) + 1); + } + + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE1TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE2TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE3TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE4TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE5TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE9TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_clear_transaction_counter +* Description : Clears the transaction counter by the argument. +* : After executing this function, the transaction counter is invalid. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_host_clear_transaction_counter (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_stop_transfer +* Description : Stops the USB transfer in the pipe specified by the argument. +* : After stopping the USB transfer, clears the buffer allocated in +* : the pipe. +* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0; +* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt +* : in the corresponding pipe becomes invalid. Sequence bit is also +* : cleared. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_stop_transfer (uint16_t pipe) +{ + uint16_t usefifo; + uint32_t remain; + + usb1_host_set_pid_nak(pipe); + + usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + switch (usefifo) + { + case USB_HOST_D0FIFO_USE: + usb1_host_clear_transaction_counter(pipe); + USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_USE: + usb1_host_clear_transaction_counter(pipe); + USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D0FIFO_DMA: + remain = Userdef_USB_usb1_host_stop_dma0(); + usb1_host_dma_stop_d0(pipe, remain); + usb1_host_clear_transaction_counter(pipe); + USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + case USB_HOST_D1FIFO_DMA: + remain = Userdef_USB_usb1_host_stop_dma1(); + usb1_host_dma_stop_d1(pipe, remain); + usb1_host_clear_transaction_counter(pipe); + USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + + default: + usb1_host_clear_transaction_counter(pipe); + USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + break; + } + + /* Interrupt of pipe set is disabled */ + usb1_host_disable_brdy_int(pipe); + usb1_host_disable_nrdy_int(pipe); + usb1_host_disable_bemp_int(pipe); + +#if(1) /* ohci_wrapp */ +#else + usb1_host_aclrm(pipe); +#endif + usb1_host_set_csclr(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_set_dfacc_d0 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb1_host_set_dfacc_d0 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/******************************************************************************* +* Function Name: usb1_host_set_dfacc_d1 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb1_host_set_dfacc_d1 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_HOST_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_HOST_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_HOST_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c new file mode 100644 index 0000000000..6c8a5f9d79 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c @@ -0,0 +1,355 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_dma.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +/* #include "usb1_host_dmacdrv.h" */ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static void usb1_host_dmaint(uint16_t fifo); +static void usb1_host_dmaint_buf2fifo(uint16_t pipe); +static void usb1_host_dmaint_fifo2buf(uint16_t pipe); + + +/******************************************************************************* +* Function Name: usb1_host_dma_stop_d0 +* Description : D0FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB201.D0FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain); + g_usb1_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb1_host_dma_stop_d1 +* Description : D1FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + buffer = USB201.D1FIFOCTR; + dtln = (buffer & USB_HOST_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain); + g_usb1_host_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, + 0, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb1_host_dma_interrupt_d0fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense) +{ + usb1_host_dmaint(USB_HOST_D0FIFO); + g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb1_host_dma_interrupt_d1fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense) +{ + usb1_host_dmaint(USB_HOST_D1FIFO); + g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb1_host_dmaint +* Description : This function is DMA transfer end interrupt +* Arguments : uint16_t fifo ; fifo number +* : ; USB_HOST_D0FIFO +* : ; USB_HOST_D1FIFO +* Return Value : none +*******************************************************************************/ +static void usb1_host_dmaint (uint16_t fifo) +{ + uint16_t pipe; + + pipe = g_usb1_host_DmaPipe[fifo]; + + if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO) + { + usb1_host_dmaint_buf2fifo(pipe); + } + else + { + usb1_host_dmaint_fifo2buf(pipe); + } +} + +/******************************************************************************* +* Function Name: usb1_host_dmaint_fifo2buf +* Description : Executes read completion from FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb1_host_dmaint_fifo2buf (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE) + { + useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb1_host_stop_dma0(); + usb1_host_dma_stop_d0(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND) + { + USB201.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb1_host_enable_brdy_int(pipe); + } + } + } + else + { + remain = Userdef_USB_usb1_host_stop_dma1(); + usb1_host_dma_stop_d1(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND) + { + USB201.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + else + { + usb1_host_enable_brdy_int(pipe); + } + } + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_dmaint_buf2fifo +* Description : Executes write completion in FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb1_host_dmaint_buf2fifo (uint16_t pipe) +{ + uint16_t useport; + uint32_t remain; + + useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE); + + if (useport == USB_HOST_D0FIFO_DMA) + { + remain = Userdef_USB_usb1_host_stop_dma0(); + usb1_host_dma_stop_d0(pipe, remain); + + if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + else + { + remain = Userdef_USB_usb1_host_stop_dma1(); + usb1_host_dma_stop_d1(pipe, remain); + + if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + + usb1_host_enable_bemp_int(pipe); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c new file mode 100644 index 0000000000..503ec7a13b --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c @@ -0,0 +1,285 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_intrn.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_brdy_int +* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9). +* : According to the pipe that interrupt is generated in, +* : reads/writes buffer allocated in the pipe. +* : This function is executed in the BRDY interrupt handler. +* : This function clears BRDY interrupt status and BEMP interrupt +* : status. +* Arguments : uint16_t status ; BRDYSTS Register Value +* : uint16_t int_enb ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_brdy_int (uint16_t status, uint16_t int_enb) +{ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + pipebit = g_usb1_host_bit_set[pipe]; + + if ((status & pipebit) && (int_enb & pipebit)) + { + USB201.BRDYSTS = (uint16_t)~pipebit; + USB201.BEMPSTS = (uint16_t)~pipebit; + + if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA) + { + if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY) + { + usb1_host_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb1_host_read_dma(pipe); + usb1_host_disable_brdy_int(pipe); + } + else + { + USB201.D0FIFOCTR = USB_HOST_BITBCLR; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA) + { + if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY) + { + usb1_host_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb1_host_read_dma(pipe); + usb1_host_disable_brdy_int(pipe); + } + else + { + USB201.D1FIFOCTR = USB_HOST_BITBCLR; + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; + } + } + else + { + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + usb1_host_read_buffer(pipe); + } + else + { + usb1_host_write_buffer(pipe); + } + } +#if(1) /* ohci_wrapp */ + switch (g_usb1_host_pipe_status[pipe]) + { + case USB_HOST_PIPE_DONE: + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); + break; + case USB_HOST_PIPE_NORES: + case USB_HOST_PIPE_STALL: + case USB_HOST_PIPE_ERROR: + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); + break; + default: + /* Do Nothing */ + break; + } +#endif + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_nrdy_int +* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9). +* : Checks NRDY interrupt cause by PID. When the cause if STALL, +* : regards the pipe state as STALL and ends the processing. +* : Then the cause is not STALL, increments the error count to +* : communicate again. When the error count is 3, determines +* : the pipe state as USB_HOST_PIPE_NORES and ends the processing. +* : This function is executed in the NRDY interrupt handler. +* : This function clears NRDY interrupt status. +* Arguments : uint16_t status ; NRDYSTS Register Value +* : uint16_t int_enb ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + + bitcheck = (uint16_t)(status & int_enb); + + USB201.NRDYSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe]) + { + if (RZA_IO_RegRead_16(&USB201.SYSCFG0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM) == 1) + { + if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT) + { + pid = usb1_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING); +#else + g_usb1_host_PipeIgnore[pipe]++; + + if (g_usb1_host_PipeIgnore[pipe] == 3) + { + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES; + } + else + { + usb1_host_set_pid_buf(pipe); + } +#endif + } + } + } + else + { + /* USB Function */ + } + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_bemp_int +* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9). +* Arguments : uint16_t status ; BEMPSTS Register Value +* : uint16_t int_enb ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_bemp_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + + bitcheck = (uint16_t)(status & int_enb); + + USB201.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe]) + { + pid = usb1_host_get_pid(pipe); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL); +#endif + } + else + { + inbuf = usb1_host_get_inbuf(pipe); + + if (inbuf == 0) + { + usb1_host_disable_bemp_int(pipe); + usb1_host_set_pid_nak(pipe); + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR); +#endif + } + } + } + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c new file mode 100644 index 0000000000..b242794fa3 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c @@ -0,0 +1,1598 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_lib.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#if(1) /* ohci_wrapp */ +#include "MBRZA1H.h" /* INTC Driver Header */ +#else +#include "devdrv_intc.h" /* INTC Driver Header */ +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_enable_brdy_int +* Description : Enables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_enable_brdy_int (uint16_t pipe) +{ + /* enable brdy interrupt */ + USB201.BRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_host_disable_brdy_int +* Description : Disables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_disable_brdy_int (uint16_t pipe) +{ + /* disable brdy interrupt */ + USB201.BRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_clear_brdy_sts (uint16_t pipe) +{ + /* clear brdy status */ + USB201.BRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_enable_bemp_int +* Description : Enables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_enable_bemp_int (uint16_t pipe) +{ + /* enable bemp interrupt */ + USB201.BEMPENB |= (uint16_t)g_usb1_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_host_disable_bemp_int +* Description : Disables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_disable_bemp_int (uint16_t pipe) +{ + /* disable bemp interrupt */ + USB201.BEMPENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_clear_bemp_sts (uint16_t pipe) +{ + /* clear bemp status */ + USB201.BEMPSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_enable_nrdy_int +* Description : Enables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : NRDY. Enables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_enable_nrdy_int (uint16_t pipe) +{ + /* enable nrdy interrupt */ + USB201.NRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_host_disable_nrdy_int +* Description : Disables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : NRDY. Disables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_disable_nrdy_int (uint16_t pipe) +{ + /* disable nrdy interrupt */ + USB201.NRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_clear_nrdy_sts (uint16_t pipe) +{ + /* clear nrdy status */ + USB201.NRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_host_is_hispeed +* Description : Returns the result of USB reset hand shake (RHST) as +* : return value. +* Arguments : none +* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed +* : USB_HOST_FULL_SPEED ; Full-Speed +* : USB_HOST_LOW_SPEED ; Low-Speed +* : USB_HOST_NON_SPEED ; error +*******************************************************************************/ +uint16_t usb1_host_is_hispeed (void) +{ + uint16_t rhst; + uint16_t speed; + + rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_HSMODE) + { + speed = USB_HOST_HIGH_SPEED; + } + else if (rhst == USB_HOST_FSMODE) + { + speed = USB_HOST_FULL_SPEED; + } + else if (rhst == USB_HOST_LSMODE) + { + speed = USB_HOST_LOW_SPEED; + } + else + { + speed = USB_HOST_NON_SPEED; + } + + return speed; +} + +/******************************************************************************* +* Function Name: usb1_host_is_hispeed_enable +* Description : Returns the USB High-Speed connection enabled status as +* : return value. +* Arguments : none +* Return Value : USB_HOST_YES : Hi-Speed Enable +* : USB_HOST_NO : Hi-Speed Disable +*******************************************************************************/ +uint16_t usb1_host_is_hispeed_enable (void) +{ + uint16_t ret; + + ret = USB_HOST_NO; + + if (RZA_IO_RegRead_16(&USB201.SYSCFG0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE) == 1) + { + ret = USB_HOST_YES; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_host_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_pid_buf (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb1_host_set_pid_nak(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + USB_HOST_PID_BUF, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + USB_HOST_PID_BUF, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_pid_nak (uint16_t pipe) +{ + uint16_t pid; + uint16_t pbusy; + uint32_t loop; + + pid = usb1_host_get_pid(pipe); + + if (pid == USB_HOST_PID_STALL2) + { + usb1_host_set_pid_stall(pipe); + } + + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + USB_HOST_PID_NAK, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + USB_HOST_PID_NAK, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + + if (pid == USB_HOST_PID_BUF) + { + for (loop = 0; loop < 200; loop++) + { + switch (pipe) + { + case USB_HOST_PIPE0: + pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_PBUSY_SHIFT, + USB_DCPCTR_PBUSY); + break; + + case USB_HOST_PIPE1: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE2: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE3: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE4: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE5: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_HOST_PIPE6: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE7: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE8: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_HOST_PIPE9: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_PBUSY_SHIFT, + USB_PIPEnCTR_9_PBUSY); + break; + + default: + pbusy = 1; + break; + } + + if (pbusy == 0) + { + break; + } + + Userdef_USB_usb1_host_delay_500ns(); + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_pid_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_host_get_pid(pipe); + + if (pid == USB_HOST_PID_BUF) + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + USB_HOST_PID_STALL2, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + USB_HOST_PID_STALL2, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } + else + { + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + USB_HOST_PID_STALL, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + USB_HOST_PID_STALL, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name: usb1_host_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_clear_pid_stall (uint16_t pipe) +{ + usb1_host_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb1_host_get_pid (uint16_t pipe) +{ + uint16_t pid; + + switch (pipe) + { + case USB_HOST_PIPE0: + pid = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_HOST_PIPE1: + pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE2: + pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE3: + pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE4: + pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE5: + pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_HOST_PIPE6: + pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE7: + pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE8: + pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_HOST_PIPE9: + pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + default: + pid = 0; + break; + } + + return pid; +} + +/******************************************************************************* +* Function Name: usb1_host_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_csclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_CSCLR_SHIFT, + USB_DCPCTR_CSCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_CSCLR_SHIFT, + USB_PIPEnCTR_9_CSCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_sqclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_SQCLR_SHIFT, + USB_DCPCTR_SQCLR); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQCLR_SHIFT, + USB_PIPEnCTR_9_SQCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_host_set_sqset (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_SQSET_SHIFT, + USB_DCPCTR_SQSET); + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQSET_SHIFT, + USB_PIPEnCTR_9_SQSET); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_get_sqmon +* Description : Toggle bit of specified pipe is obtained +* Arguments : uint16_t pipe ; Pipe number +* Return Value : sqmon +*******************************************************************************/ +uint16_t usb1_host_get_sqmon (uint16_t pipe) +{ + uint16_t sqmon; + + switch (pipe) + { + case USB_HOST_PIPE0: + sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_SQMON_SHIFT, + USB_DCPCTR_SQMON); + break; + + case USB_HOST_PIPE1: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE2: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE3: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE4: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE5: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_HOST_PIPE6: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE7: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE8: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_HOST_PIPE9: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_SQMON_SHIFT, + USB_PIPEnCTR_9_SQMON); + break; + + default: + sqmon = 0; + break; + } + + return sqmon; +} + +/******************************************************************************* +* Function Name: usb1_host_aclrm +* Description : The buffer of specified pipe is initialized +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_host_aclrm (uint16_t pipe) +{ + usb1_host_set_aclrm(pipe); + usb1_host_clr_aclrm(pipe); +} + +/******************************************************************************* +* Function Name: usb1_host_set_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_host_set_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_clr_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_host_clr_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_HOST_PIPE0: + break; + + case USB_HOST_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_HOST_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_HOST_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 0, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_get_inbuf +* Description : Returns INBUFM of the pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : inbuf +*******************************************************************************/ +uint16_t usb1_host_get_inbuf (uint16_t pipe) +{ + uint16_t inbuf; + + switch (pipe) + { + case USB_HOST_PIPE0: + inbuf = 0; + break; + + case USB_HOST_PIPE1: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE2: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE3: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE4: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE5: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_HOST_PIPE6: + inbuf = 0; + break; + + case USB_HOST_PIPE7: + inbuf = 0; + break; + + case USB_HOST_PIPE8: + inbuf = 0; + break; + + case USB_HOST_PIPE9: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_INBUFM_SHIFT, + USB_PIPEnCTR_9_INBUFM); + break; + + default: + inbuf = 0; + break; + } + + return inbuf; +} + +/******************************************************************************* +* Function Name: usb1_host_setting_interrupt +* Description : Sets the USB module interrupt level. +* Arguments : uint8_t level ; interrupt level +* Return Value : none +*******************************************************************************/ +void usb1_host_setting_interrupt (uint8_t level) +{ +#if(1) /* ohci_wrapp */ + IRQn_Type d0fifo_dmaintid; + IRQn_Type d1fifo_dmaintid; + + InterruptHandlerRegister(USBI1_IRQn, usb1_host_interrupt); + GIC_SetPriority(USBI1_IRQn, level); + GIC_EnableIRQ(USBI1_IRQn); + + d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo); + GIC_SetPriority(d0fifo_dmaintid, level); + GIC_EnableIRQ(d0fifo_dmaintid); + } + + d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + InterruptHandlerRegister(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo); + GIC_SetPriority(d1fifo_dmaintid, level); + GIC_EnableIRQ(d1fifo_dmaintid); + } +#else + uint16_t d0fifo_dmaintid; + uint16_t d1fifo_dmaintid; + + R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_host_interrupt); + R_INTC_SetPriority(INTC_ID_USBI1, level); + R_INTC_Enable(INTC_ID_USBI1); + + d0fifo_dmaintid = Userdef_USB_usb1_host_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo); + R_INTC_SetPriority(d0fifo_dmaintid, level); + R_INTC_Enable(d0fifo_dmaintid); + } + + d1fifo_dmaintid = Userdef_USB_usb1_host_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo); + R_INTC_SetPriority(d1fifo_dmaintid, level); + R_INTC_Enable(d1fifo_dmaintid); + } +#endif +} + +/******************************************************************************* +* Function Name: usb1_host_reset_module +* Description : Initializes the USB module. +* : Enables providing clock to the USB module. +* : Sets USB bus wait register. +* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ +* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +void usb1_host_reset_module (uint16_t clockmode) +{ + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_UPLLE_SHIFT, + USB_SYSCFG_UPLLE) == 1) + { + if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode) + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB201.SYSCFG0 = 0; + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb1_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + else + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + Userdef_USB_usb1_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + } + else + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB201.SYSCFG0 = 0; + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode); + Userdef_USB_usb1_host_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + + USB201.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT); +} + +/******************************************************************************* +* Function Name: usb1_host_get_buf_size +* Description : Obtains pipe buffer size specified by the argument and +* : maximum packet size of the USB device in use. +* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum +* : packet size of the USB device using the corresponding pipe. +* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the +* : corresponding pipe is in continuous transfer mode, +* : obtains the buffer size allocated in the corresponcing pipe, +* : when incontinuous transfer, obtains maximum packet size. +* Arguments : uint16_t ; pipe Number +* Return Value : Maximum packet size or buffer size +*******************************************************************************/ +uint16_t usb1_host_get_buf_size (uint16_t pipe) +{ + uint16_t size; + uint16_t bufsize; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB201.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) + { + bufsize = RZA_IO_RegRead_16(&g_usb1_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); + size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF); + } + else + { + size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + } + return size; +} + +/******************************************************************************* +* Function Name: usb1_host_get_mxps +* Description : Obtains maximum packet size of the USB device using the pipe +* : specified by the argument. +* Arguments : uint16_t ; Pipe Number +* Return Value : Max Packet Size +*******************************************************************************/ +uint16_t usb1_host_get_mxps (uint16_t pipe) +{ + uint16_t size; + + if (pipe == USB_HOST_PIPE0) + { + size = RZA_IO_RegRead_16(&USB201.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + + return size; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c new file mode 100644 index 0000000000..913e5ad9c8 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c @@ -0,0 +1,434 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_controlrw.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_CtrlTransStart +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *Buf ; Data buffer +* Return Value : DEVDRV_SUCCESS ; SUCCESS +* : DEVDRV_ERROR ; ERROR +*******************************************************************************/ +int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val, + uint16_t Indx, uint16_t Len, uint8_t * Buf) +{ + if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED) + { + RZA_IO_RegWrite_16(&USB201.SOFCFG, + 1, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + else + { + RZA_IO_RegWrite_16(&USB201.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]); + + if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE) + { + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT; + g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE); + + if (Len == 0) + { + g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */ + } + else + { + if ((Req & 0x0080) != 0) + { + g_usb1_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */ + } + else + { + g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */ + } + } + + g_usb1_host_SavReq = Req; /* save request */ + g_usb1_host_SavVal = Val; + g_usb1_host_SavIndx = Indx; + g_usb1_host_SavLen = Len; + } + else + { + if ((g_usb1_host_SavReq != Req) || (g_usb1_host_SavVal != Val) + || (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len)) + { + return DEVDRV_ERROR; + } + } + + switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + /* --------------- SETUP STAGE --------------- */ + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE): + usb1_host_SetupStage(Req, Val, Indx, Len); + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_READ: + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA; + break; + + case USB_HOST_MODE_NO_DATA: + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + default: + break; + } + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES): + if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE; + } + break; + + /* --------------- DATA STAGE --------------- */ + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE): + switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_WRITE: + usb1_host_CtrlWriteStart((uint32_t)Len, Buf); + break; + + case USB_HOST_MODE_READ: + usb1_host_CtrlReadStart((uint32_t)Len, Buf); + break; + + default: + break; + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */ + g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */ + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS; + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES): + if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DOING; + usb1_host_clear_pid_stall(USB_HOST_PIPE0); + usb1_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL): + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + /* --------------- STATUS STAGE --------------- */ + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE): + usb1_host_StatusStage(); + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + /* do nothing */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */ + usb1_host_set_pid_nak(USB_HOST_PIPE0); + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */ + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES): + if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3) + { + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + } + else + { + g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */ + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DOING; + usb1_host_clear_pid_stall(USB_HOST_PIPE0); + usb1_host_set_pid_buf(USB_HOST_PIPE0); + } + break; + + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL): + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + break; + + default: + break; + } + + if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT) + { + RZA_IO_RegWrite_16(&USB201.SOFCFG, + 0, + USB_SOFCFG_TRNENSEL_SHIFT, + USB_SOFCFG_TRNENSEL); + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_host_SetupStage +* Description : Executes USB control transfer/set up stage. +* Arguments : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* Return Value : none +*******************************************************************************/ +void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len) +{ + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DOING; + + USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */ + USB201.USBREQ = Req; + USB201.USBVAL = Val; + USB201.USBINDX = Indx; + USB201.USBLENG = Len; + USB201.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */ +} + +/******************************************************************************* +* Function Name: usb1_host_StatusStage +* Description : Executes USB control transfer/status stage. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_StatusStage (void) +{ + uint8_t Buf1[16]; + + switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD))) + { + case USB_HOST_MODE_READ: + usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1); + break; + + case USB_HOST_MODE_WRITE: + usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1); + break; + + case USB_HOST_MODE_NO_DATA: + usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_host_CtrlWriteStart +* Description : Executes USB control transfer/data stage(write). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : USB_HOST_WRITESHRT ; End of data write +* : USB_HOST_WRITEEND ; End of data write (not null) +* : USB_HOST_WRITING ; Continue of data write +* : USB_HOST_FIFOERROR ; FIFO access error +*******************************************************************************/ +uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t EndFlag_K; + uint16_t mbw; + + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DOING; + + usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb1_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB201.DCPCFG, + 1, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw); + USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb1_host_clear_pid_stall(USB_HOST_PIPE0); + EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0); + /* Host Control sequence */ + switch (EndFlag_K) + { + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS; + usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_WRITEEND: /* End of data write (not null) */ + case USB_HOST_WRITING: /* Continue of data write */ + usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */ + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + break; + + default: + break; + } + usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ + return (EndFlag_K); /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_host_CtrlReadStart +* Description : Executes USB control transfer/data stage(read). +* Arguments : uint32_t Bsize ; Data Size +* : uint8_t *Table ; Data Table Address +* Return Value : none +*******************************************************************************/ +void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table) +{ + uint16_t mbw; + + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DOING; + + usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */ + g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */ + g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */ + + USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */ +#if(1) /* ohci_wrapp */ + Userdef_USB_usb1_host_delay_10us(3); +#endif + RZA_IO_RegWrite_16(&USB201.DCPCFG, + 0, + USB_DCPCFG_DIR_SHIFT, + USB_DCPCFG_DIR); + + mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]); + usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw); + USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */ + + usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */ + usb1_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */ + usb1_host_clear_pid_stall(USB_HOST_PIPE0); + usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */ +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c new file mode 100644 index 0000000000..260328e04a --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c @@ -0,0 +1,889 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_drv_api.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_api_host_init +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint8_t int_level : USB Module interrupt level +* : USBU16 mode : USB_HOST_HIGH_SPEED +* : USB_HOST_FULL_SPEED +* : uint16_t clockmode : USB Clock mode +* Return Value : USB detach or attach +* : USB_HOST_ATTACH +* : USB_HOST_DETACH +*******************************************************************************/ +uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) +{ + uint16_t connect; + volatile uint8_t dummy_buf; + + CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */ + dummy_buf = CPG.STBCR7; /* (Dummy read) */ + + g_usb1_host_SupportUsbDeviceSpeed = mode; + + usb1_host_setting_interrupt(int_level); + usb1_host_reset_module(clockmode); + + g_usb1_host_bchg_flag = USB_HOST_NO; + g_usb1_host_detach_flag = USB_HOST_NO; + g_usb1_host_attach_flag = USB_HOST_NO; + + g_usb1_host_driver_state = USB_HOST_DRV_DETACHED; + g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb1_host_InitModule(); + + connect = usb1_host_CheckAttach(); + + if (connect == USB_HOST_ATTACH) + { + g_usb1_host_attach_flag = USB_HOST_YES; + } + else + { + usb1_host_UsbDetach2(); + } + + return connect; +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb1_api_host_enumeration +* Description : Initializes USB module in the USB host mode. +* : USB connection is executed when executing this function in +* : the states that USB device isconnected to the USB port. +* Arguments : uint16_t devadr : device address +* Return Value : DEVDRV_USBH_DETACH_ERR : device detach +* : DEVDRV_SUCCESS : device enumeration success +* : DEVDRV_ERROR : device enumeration error +*******************************************************************************/ +int32_t usb1_api_host_enumeration (uint16_t devadr) +{ + int32_t ret; + uint16_t driver_sts; + + g_usb1_host_setUsbAddress = devadr; + + while (1) + { + driver_sts = usb1_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = DEVDRV_USBH_DETACH_ERR; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = DEVDRV_SUCCESS; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb1_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_api_host_detach +* Description : USB detach routine +* Arguments : none +* Return Value : USB_HOST_DETACH : USB detach +* : USB_HOST_ATTACH : USB attach +* : DEVDRV_ERROR : error +*******************************************************************************/ +int32_t usb1_api_host_detach (void) +{ + int32_t ret; + uint16_t driver_sts; + + while (1) + { + driver_sts = usb1_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + ret = USB_HOST_DETACH; + break; + } + else if (driver_sts == USB_HOST_DRV_CONFIGURED) + { + ret = USB_HOST_ATTACH; + break; + } + else if (driver_sts == USB_HOST_DRV_STALL) + { + ret = DEVDRV_ERROR; + break; + } + else if (driver_sts == USB_HOST_DRV_NORES) + { + ret = DEVDRV_ERROR; + break; + } + else + { + /* Do Nothing */ + } + } + + if (driver_sts == USB_HOST_DRV_NORES) + { + while (1) + { + driver_sts = usb1_api_host_GetUsbDeviceState(); + + if (driver_sts == USB_HOST_DRV_DETACHED) + { + break; + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_api_host_data_in +* Description : Executes USB transfer as data-in in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1) + { + return DEVDRV_ERROR; + } + + if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb1_host_start_receive_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb1_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb1_host_stop_transfer(Pipe); + + g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_api_host_data_out +* Description : Executes USB transfer as data-out in the argument specified pipe. +* Arguments : uint16_t devadr ; device address +* : uint16_t Pipe ; Pipe Number +* : uint32_t Size ; Data Size +* : uint8_t *data_buf ; Data data_buf Address +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf) +{ + int32_t ret; + + if (Pipe == USB_HOST_PIPE0) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr) + { + return DEVDRV_ERROR; + } + + if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + return DEVDRV_ERROR; + } + + if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE) + { + usb1_host_start_send_transfer(Pipe, Size, data_buf); + } + else + { + return DEVDRV_ERROR; /* Now pipe is busy */ + } + + /* waiting for completing routine */ + do + { + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT)) + { + break; + } + + } while (1); + + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb1_host_pipe_status[Pipe]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + usb1_host_stop_transfer(Pipe); + + g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_api_host_control_transfer +* Description : Executes USB control transfer. +* Arguments : uint16_t devadr ; device address +* : uint16_t Req ; bmRequestType & bRequest +* : uint16_t Val ; wValue +* : uint16_t Indx ; wIndex +* : uint16_t Len ; wLength +* : uint8_t *buf ; Buffer +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_USBH_DETACH_ERR ; device detach +* : DEVDRV_USBH_CTRL_COM_ERR ; device no response +* : DEVDRV_USBH_STALL ; STALL +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, + uint16_t Len, uint8_t * Buf) +{ + int32_t ret; + + do + { + ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf); + + if (ret == DEVDRV_SUCCESS) + { + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + break; + } + + if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE) + && (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)) + { + break; + } + } + else + { + return DEVDRV_ERROR; + } + } while (1); + + if (g_usb1_host_detach_flag == USB_HOST_YES) + { + return DEVDRV_USBH_DETACH_ERR; + } + + switch (g_usb1_host_pipe_status[USB_HOST_PIPE0]) + { + case USB_HOST_PIPE_DONE: + ret = DEVDRV_SUCCESS; + break; + + case USB_HOST_PIPE_STALL: + ret = DEVDRV_USBH_STALL; + break; + + case USB_HOST_PIPE_NORES: + ret = DEVDRV_USBH_CTRL_COM_ERR; + break; + + default: + ret = DEVDRV_ERROR; + break; + } + + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE; + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_api_host_set_endpoint +* Description : Sets end point on the information specified in the argument. +* Arguments : uint16_t devadr ; device address +* : uint8_t *configdescriptor ; device configration descriptor +* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor) +{ + uint16_t ret; + uint32_t end_point; + uint32_t offset; + uint32_t totalLength; + USB_HOST_CFG_PIPETBL_t * pipe_table; + + /* End Point Search */ + end_point = 0; + offset = configdescriptor[0]; + totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8)); + + do + { + if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC) + { + pipe_table = &user_table[end_point]; + + if (pipe_table->pipe_number == 0xffff) + { + break; + } + + ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]); + + if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT)) + { + return DEVDRV_ERROR; + } + + ++end_point; + } + + /* Next End Point Search */ + offset += configdescriptor[offset]; + + } while (offset < totalLength); + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_api_host_clear_endpoint +* Description : Clears the pipe definition table specified in the argument. +* Arguments : uint16_t pipe_sel : Pipe Number +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + + user_table++; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_api_host_clear_endpoint_pipe +* Description : Clears the pipe definition table specified in the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table) +{ + uint16_t pipe; + + for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe) + { + if (user_table->pipe_number == 0xffff) + { + break; + } + + if (user_table->pipe_number == pipe_sel) + { + user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD); + user_table->pipe_max_pktsize = 0; + user_table->pipe_cycle = 0; + break; + } + + user_table++; + } + + return DEVDRV_SUCCESS; +} +#endif + +/******************************************************************************* +* Function Name: usb1_api_host_SetEndpointTable +* Description : Sets the end point on the information specified by the argument. +* Arguments : uint16_t devadr : device address +* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table +* : uint8_t *Table : Endpoint descriptor +* Return Value : USB_HOST_DIR_H_IN ; IN endpoint +* : USB_HOST_DIR_H_OUT ; OUT endpoint +* : USB_END_POINT_ERROR ; error +*******************************************************************************/ +uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table) +{ + uint16_t PipeCfg; + uint16_t PipeMaxp; + uint16_t pipe_number; + uint16_t ret; + uint16_t ret_flag = 0; // avoid warning. + + pipe_number = user_table->pipe_number; + + if (Table[1] != USB_HOST_ENDPOINT_DESC) + { + return USB_END_POINT_ERROR; + } + + switch (Table[3] & USB_HOST_EP_TYPE) + { + case USB_HOST_EP_CNTRL: + ret_flag = USB_END_POINT_ERROR; + break; + + case USB_HOST_EP_ISO: + if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_ISO; + break; + + case USB_HOST_EP_BULK: + if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_BULK; + break; + + case USB_HOST_EP_INT: + if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9)) + { + return USB_END_POINT_ERROR; + } + + PipeCfg = USB_HOST_INTERRUPT; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Set pipe configuration table */ + if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= USB_HOST_DIR_H_IN; + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */ + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + case USB_HOST_D0USE: + case USB_HOST_D1USE: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + break; + + case USB_HOST_D0DMA: + case USB_HOST_D1DMA: + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); +#ifdef __USB_DMA_BFRE_ENABLE__ + /* this routine cannnot be perfomred if read operation is executed in buffer size */ + PipeCfg |= USB_HOST_BFREON; +#endif + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + } + ret = USB_HOST_PIPE_IN; + } + else /* OUT(send) */ + { + if (PipeCfg == USB_HOST_ISO) + { + /* Transfer Type is ISO*/ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD); + } + else + { + /* Transfer Type is BULK or INT */ + PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD)); + } + PipeCfg |= USB_HOST_DIR_H_OUT; + ret = USB_HOST_PIPE_OUT; + } + + switch (user_table->fifo_port) + { + case USB_HOST_CUSE: + g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE; + break; + + case USB_HOST_D0USE: + g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE; + break; + + case USB_HOST_D1USE: + g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE; + break; + + case USB_HOST_D0DMA: + g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA; + break; + + case USB_HOST_D1DMA: + g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA; + break; + + default: + ret_flag = USB_END_POINT_ERROR; + break; + } + + if (ret_flag == USB_END_POINT_ERROR) + { + return ret_flag; + } + + /* Endpoint number set */ + PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK); + + /* Max packet size set */ + PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8)); + + if (PipeMaxp == 0u) + { + return USB_END_POINT_ERROR; + } + + /* Set device address */ + PipeMaxp |= (uint16_t)(devadr << 12); + + user_table->pipe_cfg = PipeCfg; + user_table->pipe_max_pktsize = PipeMaxp; + + usb1_host_resetEP(user_table); + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_host_resetEP +* Description : Sets the end point on the information specified by the argument. +* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table +* Return Value : none +*******************************************************************************/ +static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl) +{ + + uint16_t pipe; + + /* Host pipe */ + /* The pipe number of pipe definition table is obtained */ + pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */ + + /* FIFO port access pipe is set to initial value */ + /* The connection with FIFO should be cut before setting the pipe */ + if (RZA_IO_RegRead_16(&USB201.CFIFOSEL, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE) == pipe) + { + usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16); + } + + /* Interrupt of pipe set is disabled */ + usb1_host_disable_brdy_int(pipe); + usb1_host_disable_nrdy_int(pipe); + usb1_host_disable_bemp_int(pipe); + + /* Pipe to set is set to NAK */ + usb1_host_set_pid_nak(pipe); + + /* Pipe is set */ + USB201.PIPESEL = pipe; + + USB201.PIPECFG = tbl->pipe_cfg; + USB201.PIPEBUF = tbl->pipe_buf; + USB201.PIPEMAXP = tbl->pipe_max_pktsize; + USB201.PIPEPERI = tbl->pipe_cycle; + + g_usb1_host_pipecfg[pipe] = tbl->pipe_cfg; + g_usb1_host_pipebuf[pipe] = tbl->pipe_buf; + g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize; + g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle; + + /* Sequence bit clear */ + usb1_host_set_sqclr(pipe); + + usb1_host_aclrm(pipe); + usb1_host_set_csclr(pipe); + + /* Pipe window selection is set to unused */ + USB201.PIPESEL = USB_HOST_PIPE0; + +} + +#if(1) /* ohci_wrapp */ +#else +/******************************************************************************* +* Function Name: usb1_api_host_data_count +* Description : Get g_usb0_host_data_count[pipe] +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t *data_count ; return g_usb0_data_count[pipe] +* Return Value : DEVDRV_SUCCESS ; success +* : DEVDRV_ERROR ; error +*******************************************************************************/ +int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count) +{ + if (pipe > USB_HOST_MAX_PIPE_NO) + { + return DEVDRV_ERROR; + } + + *data_count = g_usb1_host_PipeDataSize[pipe]; + + return DEVDRV_SUCCESS; +} +#endif + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c new file mode 100644 index 0000000000..245da23af3 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_global.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +const uint16_t g_usb1_host_bit_set[16] = +{ + 0x0001, 0x0002, 0x0004, 0x0008, + 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, + 0x1000, 0x2000, 0x4000, 0x8000 +}; + +uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +uint16_t g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1]; +uint32_t g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1]; + +USB_HOST_DMA_t g_usb1_host_DmaInfo[2]; + +uint16_t g_usb1_host_DmaPipe[2]; +uint16_t g_usb1_host_DmaBval[2]; +uint16_t g_usb1_host_DmaStatus[2]; + +uint16_t g_usb1_host_driver_state; +uint16_t g_usb1_host_ConfigNum; +uint16_t g_usb1_host_CmdStage; +uint16_t g_usb1_host_bchg_flag; +uint16_t g_usb1_host_detach_flag; +uint16_t g_usb1_host_attach_flag; + +uint16_t g_usb1_host_UsbAddress; +uint16_t g_usb1_host_setUsbAddress; +uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +uint16_t g_usb1_host_UsbDeviceSpeed; +uint16_t g_usb1_host_SupportUsbDeviceSpeed; + +uint16_t g_usb1_host_SavReq; +uint16_t g_usb1_host_SavVal; +uint16_t g_usb1_host_SavIndx; +uint16_t g_usb1_host_SavLen; + +uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_init_pipe_status +* Description : Initialize pipe status. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_init_pipe_status (void) +{ + uint16_t loop; + + g_usb1_host_ConfigNum = 0; + + for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop) + { + g_usb1_host_pipe_status[loop] = USB_HOST_PIPE_IDLE; + g_usb1_host_PipeDataSize[loop] = 0; + + /* pipe configuration in usb1_host_resetEP() */ + g_usb1_host_pipecfg[loop] = 0; + g_usb1_host_pipebuf[loop] = 0; + g_usb1_host_pipemaxp[loop] = 0; + g_usb1_host_pipeperi[loop] = 0; + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c new file mode 100644 index 0000000000..d05b19d0e1 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c @@ -0,0 +1,497 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_usbint.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#if(1) /* ohci_wrapp */ +#include "ohci_wrapp_RZ_A1_local.h" +#endif + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_host_interrupt1(void); +static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl); +static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_interrupt +* Description : Executes USB interrupt. +* : Register this function in the USB interrupt handler. +* : Set CFIF0 in the pipe set before the interrupt after executing +* : this function. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb1_host_interrupt (uint32_t int_sense) +{ + uint16_t savepipe1; + uint16_t savepipe2; + uint16_t buffer; + + savepipe1 = USB201.CFIFOSEL; + savepipe2 = USB201.PIPESEL; + usb1_host_interrupt1(); + + /* Control transmission changes ISEL within interruption processing. */ + /* For this reason, write return of ISEL cannot be performed. */ + buffer = USB201.CFIFOSEL; + buffer &= (uint16_t)~(USB_HOST_BITCURPIPE); + buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE); + USB201.CFIFOSEL = buffer; + USB201.PIPESEL = savepipe2; +} + +/******************************************************************************* +* Function Name: usb1_host_interrupt1 +* Description : Execue the USB interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_interrupt1 (void) +{ + uint16_t intsts0; + uint16_t intsts1; + uint16_t intenb0; + uint16_t intenb1; + uint16_t brdysts; + uint16_t nrdysts; + uint16_t bempsts; + uint16_t brdyenb; + uint16_t nrdyenb; + uint16_t bempenb; + volatile uint16_t dumy_sts; + + intsts0 = USB201.INTSTS0; + intsts1 = USB201.INTSTS1; + intenb0 = USB201.INTENB0; + intenb1 = USB201.INTENB1; + + if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE)) + { + USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG; + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + g_usb1_host_bchg_flag = USB_HOST_YES; + } + else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE)) + { + USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK; +#if(1) /* ohci_wrapp */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); +#else + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; +#endif + } + else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE)) + { + USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN; +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#else + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_NORES; +#endif + } + else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH) + && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE)) + { + USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH; + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); + g_usb1_host_detach_flag = USB_HOST_YES; + + Userdef_USB_usb1_host_detach(); + + usb1_host_UsbDetach2(); + } + else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH) + && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE)) + { + USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH; + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); + g_usb1_host_attach_flag = USB_HOST_YES; + + Userdef_USB_usb1_host_attach(); + + usb1_host_UsbAttach(); + } + else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY))) + { + brdysts = USB201.BRDYSTS; + nrdysts = USB201.NRDYSTS; + bempsts = USB201.BEMPSTS; + brdyenb = USB201.BRDYENB; + nrdyenb = USB201.NRDYENB; + bempenb = USB201.BEMPENB; + + if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb)) + { + usb1_host_BRDYInterrupt(brdysts, brdyenb); + } + else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb)) + { + usb1_host_BEMPInterrupt(bempsts, bempenb); + } + else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb)) + { + usb1_host_NRDYInterrupt(nrdysts, nrdyenb); + } + else + { + /* Do Nothing */ + } + } + else + { + /* Do Nothing */ + } + + /* Three dummy read for clearing interrupt requests */ + dumy_sts = USB201.INTSTS0; + dumy_sts = USB201.INTSTS1; + +} + +/******************************************************************************* +* Function Name: usb1_host_BRDYInterrupt +* Description : Executes USB BRDY interrupt. +* Arguments : uint16_t Status ; BRDYSTS Register Value +* : uint16_t Int_enbl ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + volatile uint16_t dumy_sts; + + if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0])) + { + USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0]; + +#if(1) /* ohci_wrapp */ + switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0); + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_READOVER: /* buffer over */ + USB201.CFIFOCTR = USB_HOST_BITBCLR; + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#else + switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0); + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0); + + switch (buffer) + { + case USB_HOST_READING: /* Continue of data read */ + break; + + case USB_HOST_READEND: /* End of data read */ + case USB_HOST_READSHRT: /* End of data read */ + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_READOVER: /* buffer over */ + USB201.CFIFOCTR = USB_HOST_BITBCLR; + usb1_host_disable_brdy_int(USB_HOST_PIPE0); + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + break; + } +#endif + } + else + { + usb1_host_brdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB201.BRDYSTS; +} + +/******************************************************************************* +* Function Name: usb1_host_NRDYInterrupt +* Description : Executes USB NRDY interrupt. +* Arguments : uint16_t Status ; NRDYSTS Register Value +* : uint16_t Int_enbl ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0])) + { + USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0]; + pid = usb1_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + + } + else if (pid == USB_HOST_PID_NAK) + { + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_NORES; +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { + /* Do Nothing */ + } + } + else + { + usb1_host_nrdy_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB201.NRDYSTS; +} + +/******************************************************************************* +* Function Name: usb1_host_BEMPInterrupt +* Description : Executes USB BEMP interrupt. +* Arguments : uint16_t Status ; BEMPSTS Register Value +* : uint16_t Int_enbl ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl) +{ + uint16_t buffer; + uint16_t pid; + volatile uint16_t dumy_sts; + + if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0])) + { + USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0]; + pid = usb1_host_get_pid(USB_HOST_PIPE0); + + if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2)) + { + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_STALL; +#if(1) /* ohci_wrapp */ + g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */ + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL); +#endif + } + else + { +#if(1) /* ohci_wrapp */ + switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb1_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS; + ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR); + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + default: + /* do nothing */ + break; + } +#else + switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD))) + { + case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_DONE; + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING): + buffer = usb1_host_write_buffer(USB_HOST_PIPE0); + switch (buffer) + { + case USB_HOST_WRITING: /* Continue of data write */ + case USB_HOST_WRITEEND: /* End of data write (zero-length) */ + break; + + case USB_HOST_WRITESHRT: /* End of data write */ + g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD); + g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS; + break; + + case USB_HOST_FIFOERROR: /* FIFO access error */ + default: + break; + } + break; + + case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING): + g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD); + g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE; + break; + + default: + /* do nothing */ + break; + } +#endif + } + } + else + { + usb1_host_bemp_int(Status, Int_enbl); + } + + /* Three dummy reads for clearing interrupt requests */ + dumy_sts = USB201.BEMPSTS; +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c new file mode 100644 index 0000000000..ea8abf876a --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c @@ -0,0 +1,637 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_usbsig.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_host.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_host_EnableINT_Module(void); +static void usb1_host_Enable_AttachINT(void); +static void usb1_host_Disable_AttachINT(void); +static void usb1_host_Disable_BchgINT(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_host_InitModule +* Description : Initializes the USB module in USB host module. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_InitModule (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + + usb1_host_init_pipe_status(); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); /* HOST mode */ + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_DRPD_SHIFT, + USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */ + + do + { + buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb1_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb1_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + USB201.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB201.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); + USB201.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE); +} + +/******************************************************************************* +* Function Name: usb1_host_CheckAttach +* Description : Returns the USB device connection state. +* Arguments : none +* Return Value : uint16_t ; USB_HOST_ATTACH : Attached +* : ; USB_HOST_DETACH : not Attached +*******************************************************************************/ +uint16_t usb1_host_CheckAttach (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + uint16_t rhst; + + do + { + buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb1_host_delay_xms(50); + buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + Userdef_USB_usb1_host_delay_xms(50); + buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + + } while ((buf1 != buf2) || (buf1 != buf3)); + + rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (rhst == USB_HOST_UNDECID) + { + if (buf1 == USB_HOST_FS_JSTS) + { + if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED) + { + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + else + { + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + return USB_HOST_ATTACH; + } + else if (buf1 == USB_HOST_LS_JSTS) + { + /* Low Speed Device */ + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + } + else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE)) + { + return USB_HOST_ATTACH; + } + else if (rhst == USB_HOST_LSMODE) + { + return USB_HOST_ATTACH; + } + else + { + /* Do Nothing */ + } + + return USB_HOST_DETACH; +} + +/******************************************************************************* +* Function Name: usb1_host_UsbAttach +* Description : Connects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_UsbAttach (void) +{ + usb1_host_EnableINT_Module(); + usb1_host_Disable_BchgINT(); + usb1_host_Disable_AttachINT(); + usb1_host_Enable_DetachINT(); +} + +/******************************************************************************* +* Function Name: usb1_host_UsbDetach +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_UsbDetach (void) +{ + uint16_t pipe; + uint16_t devadr; + + g_usb1_host_driver_state = USB_HOST_DRV_DETACHED; + + /* Terminate all the pipes in which communications on port */ + /* are currently carried out */ + for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe) + { + if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE) + { + if (pipe == USB_HOST_PIPE0) + { + devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP, + USB_DCPMAXP_DEVSEL_SHIFT, + USB_DCPMAXP_DEVSEL); + } + else + { + devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL); + } + + if (devadr == g_usb1_host_UsbAddress) + { + usb1_host_stop_transfer(pipe); + } + + g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE; + } + } + + g_usb1_host_ConfigNum = 0; + g_usb1_host_UsbAddress = 0; + g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64; + + usb1_host_UsbDetach2(); +} + +/******************************************************************************* +* Function Name: usb1_host_UsbDetach2 +* Description : Disconnects the USB device. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_UsbDetach2 (void) +{ + usb1_host_Disable_DetachINT(); + usb1_host_Disable_BchgINT(); + usb1_host_Enable_AttachINT(); +} + +/******************************************************************************* +* Function Name: usb1_host_UsbBusReset +* Description : Issues the USB bus reset signal. +* Arguments : none +* Return Value : uint16_t ; RHST +*******************************************************************************/ +uint16_t usb1_host_UsbBusReset (void) +{ + uint16_t buffer; + uint16_t loop; + + RZA_IO_RegWrite_16(&USB201.DVSTCTR0, + 1, + USB_DVSTCTR0_USBRST_SHIFT, + USB_DVSTCTR0_USBRST); + RZA_IO_RegWrite_16(&USB201.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb1_host_delay_xms(50); + + buffer = USB201.DVSTCTR0; + buffer &= (uint16_t)(~(USB_HOST_BITRST)); + buffer |= USB_HOST_BITUACT; + USB201.DVSTCTR0 = buffer; + + Userdef_USB_usb1_host_delay_xms(20); + + for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop) + { + buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0, + USB_DVSTCTR0_RHST_SHIFT, + USB_DVSTCTR0_RHST); + if (buffer == USB_HOST_HSPROC) + { + Userdef_USB_usb1_host_delay_xms(10); + } + else + { + break; + } + } + + return buffer; +} + +/******************************************************************************* +* Function Name: usb1_host_UsbResume +* Description : Issues the USB resume signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS +* : ; DEVDRV_ERROR +*******************************************************************************/ +int32_t usb1_host_UsbResume (void) +{ + uint16_t buf; + + if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0) + { + /* not SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); + RZA_IO_RegWrite_16(&USB201.DVSTCTR0, + 1, + USB_DVSTCTR0_RESUME_SHIFT, + USB_DVSTCTR0_RESUME); + Userdef_USB_usb1_host_delay_xms(20); + + buf = USB201.DVSTCTR0; + buf &= (uint16_t)(~(USB_HOST_BITRESUME)); + buf |= USB_HOST_BITUACT; + USB201.DVSTCTR0 = buf; + + g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND; + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_host_UsbSuspend +* Description : Issues the USB suspend signal. +* Arguments : none +* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND +* : ; DEVDRV_ERROR :SUSPEND +*******************************************************************************/ +int32_t usb1_host_UsbSuspend (void) +{ + uint16_t buf; + + if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0) + { + /* SUSPEND */ + return DEVDRV_ERROR; + } + + RZA_IO_RegWrite_16(&USB201.DVSTCTR0, + 0, + USB_DVSTCTR0_UACT_SHIFT, + USB_DVSTCTR0_UACT); + + Userdef_USB_usb1_host_delay_xms(5); + + buf = RZA_IO_RegRead_16(&USB201.SYSSTS0, + USB_SYSSTS0_LNST_SHIFT, + USB_SYSSTS0_LNST); + if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS)) + { + usb1_host_UsbDetach(); + } + else + { + g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_host_Enable_DetachINT +* Description : Enables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_Enable_DetachINT (void) +{ + USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB201.INTENB1, + 1, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb1_host_Disable_DetachINT +* Description : Disables the USB disconnection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_Disable_DetachINT (void) +{ + USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH)); + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_DTCHE_SHIFT, + USB_INTENB1_DTCHE); +} + +/******************************************************************************* +* Function Name: usb1_host_Enable_AttachINT +* Description : Enables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_Enable_AttachINT (void) +{ + USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB201.INTENB1, + 1, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb1_host_Disable_AttachINT +* Description : Disables the USB connection detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_Disable_AttachINT (void) +{ + USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH)); + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_ATTCHE_SHIFT, + USB_INTENB1_ATTCHE); +} + +/******************************************************************************* +* Function Name: usb1_host_Disable_BchgINT +* Description : Disables the USB bus change detection interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_Disable_BchgINT (void) +{ + USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG)); + RZA_IO_RegWrite_16(&USB201.INTENB1, + 0, + USB_INTENB1_BCHGE_SHIFT, + USB_INTENB1_BCHGE); +} + +/******************************************************************************* +* Function Name: usb1_host_set_devadd +* Description : DEVADDn register is set by specified value +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : Set value +* Return Value : none +*******************************************************************************/ +void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB201.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB201.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB201.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB201.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB201.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB201.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB201.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB201.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB201.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB201.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB201.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK); + } +} + +/******************************************************************************* +* Function Name: usb1_host_get_devadd +* Description : DEVADDn register is obtained +* Arguments : uint16_t addr : Device address +* : uint16_t *devadd : USB_HOST_DEVADD register value +* Return Value : none +*******************************************************************************/ +void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd) +{ + uint16_t * ptr; + uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning. + + switch (addr) + { + case USB_HOST_DEVICE_0: + ptr = (uint16_t *)&USB201.DEVADD0; + break; + + case USB_HOST_DEVICE_1: + ptr = (uint16_t *)&USB201.DEVADD1; + break; + + case USB_HOST_DEVICE_2: + ptr = (uint16_t *)&USB201.DEVADD2; + break; + + case USB_HOST_DEVICE_3: + ptr = (uint16_t *)&USB201.DEVADD3; + break; + + case USB_HOST_DEVICE_4: + ptr = (uint16_t *)&USB201.DEVADD4; + break; + + case USB_HOST_DEVICE_5: + ptr = (uint16_t *)&USB201.DEVADD5; + break; + + case USB_HOST_DEVICE_6: + ptr = (uint16_t *)&USB201.DEVADD6; + break; + + case USB_HOST_DEVICE_7: + ptr = (uint16_t *)&USB201.DEVADD7; + break; + + case USB_HOST_DEVICE_8: + ptr = (uint16_t *)&USB201.DEVADD8; + break; + + case USB_HOST_DEVICE_9: + ptr = (uint16_t *)&USB201.DEVADD9; + break; + + case USB_HOST_DEVICE_10: + ptr = (uint16_t *)&USB201.DEVADDA; + break; + + default: + ret_flag = DEVDRV_FLAG_OFF; + break; + } + + if (ret_flag == DEVDRV_FLAG_ON) + { + *devadd = *ptr; + } +} + +/******************************************************************************* +* Function Name: usb1_host_EnableINT_Module +* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt. +* : Enables NRDY/BEMP interrupt in the pipe0. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_host_EnableINT_Module (void) +{ + uint16_t buf; + + buf = USB201.INTENB0; + buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE); + USB201.INTENB0 = buf; + + buf = USB201.INTENB1; + buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE); + USB201.INTENB1 = buf; + + usb1_host_enable_nrdy_int(USB_HOST_PIPE0); + usb1_host_enable_bemp_int(USB_HOST_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c new file mode 100644 index 0000000000..b3cc2e6e0c --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c @@ -0,0 +1,698 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_dmacdrv.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" +#include "usb1_host_dmacdrv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ + +/* ==== Request setting information for on-chip peripheral module ==== */ +typedef enum dmac_peri_req_reg_type +{ + DMAC_REQ_MID, + DMAC_REQ_RID, + DMAC_REQ_AM, + DMAC_REQ_LVL, + DMAC_REQ_REQD +} dmac_peri_req_reg_type_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +/* ==== Prototype declaration ==== */ + +/* ==== Global variable ==== */ +/* On-chip peripheral module request setting table */ +static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] = +{ + /* MID,RID, AM,LVL,REQD */ + { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ + { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ + { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ + { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ + { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ + { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ + { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ + { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ +}; + + +/******************************************************************************* +* Function Name: usb1_host_DMAC3_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 3. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 3 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->daddr_dir, + DMAC3_CHCFG_n_DAD_SHIFT, + DMAC3_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->saddr_dir, + DMAC3_CHCFG_n_SAD_SHIFT, + DMAC3_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->dst_size, + DMAC3_CHCFG_n_DDS_SHIFT, + DMAC3_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->src_size, + DMAC3_CHCFG_n_SDS_SHIFT, + DMAC3_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_DMS_SHIFT, + DMAC3_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_RSEL_SHIFT, + DMAC3_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_SBE_SHIFT, + DMAC3_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_DEM_SHIFT, + DMAC3_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_REN_SHIFT, + DMAC3_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_RSW_SHIFT, + DMAC3_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_REN_SHIFT, + DMAC3_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_RSW_SHIFT, + DMAC3_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_TM_SHIFT, + DMAC3_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 3, + DMAC3_CHCFG_n_SEL_SHIFT, + DMAC3_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_HIEN_SHIFT, + DMAC3_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_LOEN_SHIFT, + DMAC3_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC3_CHCFG_n_AM_SHIFT, + DMAC3_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC3_CHCFG_n_LVL_SHIFT, + DMAC3_CHCFG_n_LVL); + if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC3_CHCFG_n_REQD_SHIFT, + DMAC3_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + req_direction, + DMAC3_CHCFG_n_REQD_SHIFT, + DMAC3_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC23_DMARS_CH3_RID_SHIFT, + DMAC23_DMARS_CH3_RID); + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC23_DMARS_CH3_MID_SHIFT, + DMAC23_DMARS_CH3_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC3_Open +* Description : Enables DMAC channel 3 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb1_host_DMAC3_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_EN_SHIFT, + DMAC3_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_TACT_SHIFT, + DMAC3_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_SWRST_SHIFT, + DMAC3_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n, + DMAC3_CHCTRL_n_SWRST_SHIFT, + DMAC3_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_SETEN_SHIFT, + DMAC3_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_STG_SHIFT, + DMAC3_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC3_Close +* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC3_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_CLREN_SHIFT, + DMAC3_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_TACT_SHIFT, + DMAC3_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_EN_SHIFT, + DMAC3_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC3.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC3_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 3 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 3 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_SR_SHIFT, + DMAC3_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC3.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC3.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC3.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC3.N1TB_n = count; /* Total transfer byte count */ + } +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC4_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 4. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 4 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->daddr_dir, + DMAC4_CHCFG_n_DAD_SHIFT, + DMAC4_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->saddr_dir, + DMAC4_CHCFG_n_SAD_SHIFT, + DMAC4_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->dst_size, + DMAC4_CHCFG_n_DDS_SHIFT, + DMAC4_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->src_size, + DMAC4_CHCFG_n_SDS_SHIFT, + DMAC4_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_DMS_SHIFT, + DMAC4_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_RSEL_SHIFT, + DMAC4_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_SBE_SHIFT, + DMAC4_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_DEM_SHIFT, + DMAC4_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_REN_SHIFT, + DMAC4_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_RSW_SHIFT, + DMAC4_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_REN_SHIFT, + DMAC4_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_RSW_SHIFT, + DMAC4_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_TM_SHIFT, + DMAC4_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 4, + DMAC4_CHCFG_n_SEL_SHIFT, + DMAC4_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_HIEN_SHIFT, + DMAC4_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_LOEN_SHIFT, + DMAC4_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC4_CHCFG_n_AM_SHIFT, + DMAC4_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC4_CHCFG_n_LVL_SHIFT, + DMAC4_CHCFG_n_LVL); + if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC4_CHCFG_n_REQD_SHIFT, + DMAC4_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + req_direction, + DMAC4_CHCFG_n_REQD_SHIFT, + DMAC4_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC45.DMARS, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC45_DMARS_CH4_RID_SHIFT, + DMAC45_DMARS_CH4_RID); + RZA_IO_RegWrite_32(&DMAC45.DMARS, + usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC45_DMARS_CH4_MID_SHIFT, + DMAC45_DMARS_CH4_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC4_Open +* Description : Enables DMAC channel 4 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb1_host_DMAC4_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_EN_SHIFT, + DMAC4_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_TACT_SHIFT, + DMAC4_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_SWRST_SHIFT, + DMAC4_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n, + DMAC4_CHCTRL_n_SWRST_SHIFT, + DMAC4_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_SETEN_SHIFT, + DMAC4_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_STG_SHIFT, + DMAC4_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC4_Close +* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC4_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_CLREN_SHIFT, + DMAC4_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_TACT_SHIFT, + DMAC4_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_EN_SHIFT, + DMAC4_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC4.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb1_host_DMAC4_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 4 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 4 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_SR_SHIFT, + DMAC4_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC4.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC4.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC4.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC4.N1TB_n = count; /* Total transfer byte count */ + } +} + +/* End of File */ diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c new file mode 100644 index 0000000000..f002e54b06 --- /dev/null +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c @@ -0,0 +1,778 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_host_userdef.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "cmsis_os.h" +#include "r_typedefs.h" +#include "iodefine.h" +#include "devdrv_usb_host_api.h" +#include "usb1_host.h" +#include "MBRZA1H.h" /* INTC Driver Header */ +#include "usb1_host_dmacdrv.h" +#include "ohci_wrapp_RZ_A1_local.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DUMMY_ACCESS OSTM0CNT + +/* #define CACHE_WRITEBACK */ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int32_t io_cwb(unsigned long start, unsigned long end); + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void Userdef_USB_usb1_host_delay_10us_2(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid +* Description : get D0FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D0FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void) +{ +#if(1) /* ohci_wrapp */ + return 0xFFFF; +#else + return DMAINT1_IRQn; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid +* Description : get D1FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D1FIFO DMA Interrupt ID +*******************************************************************************/ +uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void) +{ +#if(1) /* ohci_wrapp */ + return 0xFFFF; +#else + return DMAINT2_IRQn; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_attach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_attach (void) +{ +// printf("\n"); +// printf("channel 1 attach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_detach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_detach (void) +{ +// printf("\n"); +// printf("channel 1 detach device\n"); +// printf("\n"); + ohciwrapp_loc_Connect(0); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_delay_1ms +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_delay_1ms (void) +{ + osDelay(1); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_delay_xms +* Description : Wait for the software in the period of time specified by the +* : argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t msec ; Wait Time (msec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_delay_xms (uint32_t msec) +{ + osDelay(msec); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_delay_10us +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t usec ; Wait Time(x 10usec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_delay_10us (uint32_t usec) +{ + volatile int i; + + /* Wait 10us (Please change for your MCU) */ + for (i = 0; i < usec; ++i) + { + Userdef_USB_usb1_host_delay_10us_2(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_delay_10us_2 +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void Userdef_USB_usb1_host_delay_10us_2 (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 1us (Please change for your MCU) */ + for (i = 0; i < 14; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_delay_500ns +* Description : Wait for software for 500ns. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_delay_500ns (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 500ns (Please change for your MCU) */ + /* Wait 500ns I clock 266MHz */ + tmp = DUMMY_ACCESS; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_start_dma +* Description : Enables DMA transfer on the information specified by the argument. +* : Set DMAC register by this function to enable DMA transfer. +* : After executing this function, USB module is set to start DMA +* : transfer. DMA transfer should not wait for DMA transfer complete. +* Arguments : USB_HOST_DMA_t *dma : DMA parameter +* : typedef struct{ +* : uint32_t fifo; FIFO for using +* : uint32_t buffer; Start address of transfer source/destination +* : uint32_t bytes; Transfer size(Byte) +* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) +* : uint32_t size; DMA transfer size +* : } USB_HOST_DMA_t; +* : uint16_t dfacc ; 0 : cycle steal mode +* : 1 : 16byte continuous mode +* : 2 : 32byte continuous mode +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc) +{ + uint32_t trncount; + uint32_t src; + uint32_t dst; + uint32_t size; + uint32_t dir; +#ifdef CACHE_WRITEBACK + uint32_t ptr; +#endif + + trncount = dma->bytes; + dir = dma->dir; + + if (dir == USB_HOST_FIFO2BUF) + { + /* DxFIFO determination */ + dst = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + src += 3; /* byte access */ + } + else if (size == 1) + { + src += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB201.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB201.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + src += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + src += 3; /* byte access */ + } +#endif + } + else + { + /* DxFIFO determination */ + src = dma->buffer; +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + dst += 3; /* byte access */ + } + else if (size == 1) + { + dst += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB201.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB201.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + dst += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + dst += 3; /* byte access */ + } +#endif + } + +#ifdef CACHE_WRITEBACK + ptr = (uint32_t)dma->buffer; + if ((ptr & 0x20000000ul) == 0) + { + io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount); + } +#endif + + if (dma->fifo == USB_HOST_D0FIFO_DMA) + { + usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); + } + else + { + usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); + } +} + +/******************************************************************************* +* Function Name: usb1_host_enable_dmac0 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor = DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor = DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC3 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: usb1_host_enable_dmac1 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_HOST_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { +// printf("size error!!\n"); + } + } +#endif + + if (dir == USB_HOST_FIFO2BUF) + { + request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_HOST_BUF2FIFO) + { + request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI); + + if (ret != 0) + { +// printf("DMAC4 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_stop_dma0 +* Description : Disables DMA transfer. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +* Notice : This function should be executed to DMAC executed at the time +* : of specification of D0_FIF0_DMA in dma->fifo. +*******************************************************************************/ +uint32_t Userdef_USB_usb1_host_stop_dma0 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb1_host_DMAC3_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_stop_dma1 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D1_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb1_host_stop_dma1 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb1_host_DMAC4_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_notice +* Description : Notice of USER +* Arguments : const char *format +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_notice (const char * format) +{ +// printf(format); + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_host_user_rdy +* Description : This function notify a user and wait for trigger +* Arguments : const char *format +* : uint16_t data +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data) +{ +// printf(format, data); + getchar(); + + return; +} + +/* End of File */ From 6c78c36541ecf894822682375108fa739527648a Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:15:42 +0900 Subject: [PATCH 031/143] Add 2Port function to USBDevice(usb0). --- .../inc/devdrv_usb_function_api.h | 2 - .../TARGET_RZ_A1H/usb0/inc/usb0_function.h | 171 + .../usb0/inc/usb0_function_api.h | 104 + .../usb0/inc/usb0_function_dmacdrv.h | 142 + .../usb0/src/common/usb0_function_dataio.c | 2933 +++++++++++++++++ .../usb0/src/common/usb0_function_dma.c | 346 ++ .../usb0/src/common/usb0_function_intrn.c | 249 ++ .../usb0/src/common/usb0_function_lib.c | 2026 ++++++++++++ .../usb0/src/function/usb0_function_api.c | 441 +++ .../src/function/usb0_function_controlrw.c | 142 + .../usb0/src/function/usb0_function_global.c | 144 + .../usb0/src/function/usb0_function_sig.c | 330 ++ .../usb0/src/function/usb0_function_sub.c | 453 +++ .../usb0/src/userdef/usb0_function_dmacdrv.c | 698 ++++ .../usb0/src/userdef/usb0_function_userdef.c | 762 +++++ .../TARGET_RZ_A1H/usb_function_setting.h | 173 + .../USBDevice/USBDevice/USBHAL_RZ_A1H.cpp | 510 +-- 17 files changed, 9371 insertions(+), 255 deletions(-) create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h index cfbc20cab5..d319e60f30 100644 --- a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h @@ -36,9 +36,7 @@ Includes , "Project Includes" #include #include "r_typedefs.h" #include "usb0_function_api.h" -#if 0 #include "usb1_function_api.h" -#endif #ifdef __cplusplus diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h new file mode 100644 index 0000000000..02855eb13e --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h @@ -0,0 +1,171 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_FUNCTION_H +#define USB0_FUNCTION_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_function_api.h" +#include "usb_function.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb0_function_bit_set[]; +extern uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb0_function_PipeIgnore[]; +extern uint16_t g_usb0_function_PipeTbl[]; +extern uint16_t g_usb0_function_pipe_status[]; +extern uint32_t g_usb0_function_PipeDataSize[]; + +extern USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[]; +extern uint16_t g_usb0_function_DmaPipe[]; +extern uint16_t g_usb0_function_DmaBval[]; +extern uint16_t g_usb0_function_DmaStatus[]; + +extern uint16_t g_usb0_function_CtrZeroLengthFlag; + +extern uint16_t g_usb0_function_ConfigNum; +extern uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO]; +extern uint16_t g_usb0_function_RemoteWakeupFlag; +extern uint16_t g_usb0_function_TestModeFlag; +extern uint16_t g_usb0_function_TestModeSelectors; + +extern uint16_t g_usb0_function_ReqType; +extern uint16_t g_usb0_function_ReqTypeType; +extern uint16_t g_usb0_function_ReqTypeRecip; +extern uint16_t g_usb0_function_ReqRequest; +extern uint16_t g_usb0_function_ReqValue; +extern uint16_t g_usb0_function_ReqIndex; +extern uint16_t g_usb0_function_ReqLength; + +extern uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; + +extern uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +/* ==== common ==== */ +void usb0_function_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb0_function_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb0_function_is_hispeed(void); +uint16_t usb0_function_is_hispeed_enable(void); +uint16_t usb0_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_function_write_buffer(uint16_t pipe); +uint16_t usb0_function_write_buffer_c(uint16_t pipe); +uint16_t usb0_function_write_buffer_d0(uint16_t pipe); +uint16_t usb0_function_write_buffer_d1(uint16_t pipe); +void usb0_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_function_read_buffer(uint16_t pipe); +uint16_t usb0_function_read_buffer_c(uint16_t pipe); +uint16_t usb0_function_read_buffer_d0(uint16_t pipe); +uint16_t usb0_function_read_buffer_d1(uint16_t pipe); +uint16_t usb0_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb0_function_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb0_function_read_dma(uint16_t pipe); +void usb0_function_brdy_int(uint16_t status, uint16_t int_enb); +void usb0_function_nrdy_int(uint16_t status, uint16_t int_enb); +void usb0_function_bemp_int(uint16_t status, uint16_t int_enb); +void usb0_function_setting_interrupt(uint8_t level); +void usb0_function_reset_module(uint16_t clockmode); +uint16_t usb0_function_get_buf_size(uint16_t pipe); +uint16_t usb0_function_get_mxps(uint16_t pipe); +void usb0_function_clear_brdy_sts(uint16_t pipe); +void usb0_function_clear_bemp_sts(uint16_t pipe); +void usb0_function_clear_nrdy_sts(uint16_t pipe); +void usb0_function_set_pid_buf(uint16_t pipe); +void usb0_function_set_pid_nak(uint16_t pipe); +void usb0_function_set_pid_stall(uint16_t pipe); +void usb0_function_clear_pid_stall(uint16_t pipe); +uint16_t usb0_function_get_pid(uint16_t pipe); +void usb0_function_set_sqclr(uint16_t pipe); +void usb0_function_set_sqset(uint16_t pipe); +void usb0_function_set_csclr(uint16_t pipe); +void usb0_function_aclrm(uint16_t pipe); +void usb0_function_set_aclrm(uint16_t pipe); +void usb0_function_clr_aclrm(uint16_t pipe); +uint16_t usb0_function_get_sqmon(uint16_t pipe); +uint16_t usb0_function_get_inbuf(uint16_t pipe); + +/* ==== function ==== */ +void usb0_function_init_status(void); +void usb0_function_InitModule(uint16_t mode); +uint16_t usb0_function_CheckVBUStaus(void); +void usb0_function_USB_FUNCTION_Attach(void); +void usb0_function_USB_FUNCTION_Detach(void); +void usb0_function_USB_FUNCTION_BusReset(void); +void usb0_function_USB_FUNCTION_Resume(void); +void usb0_function_USB_FUNCTION_Suspend(void); +void usb0_function_USB_FUNCTION_TestMode(void); +void usb0_function_ResetDCP(void); +void usb0_function_ResetEP(uint16_t num); +uint16_t usb0_function_EpToPipe(uint16_t ep); +void usb0_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num); +uint16_t usb0_function_GetConfigNum(void); +uint16_t usb0_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num); +uint16_t usb0_function_CheckRemoteWakeup(void); +void usb0_function_clear_alt(void); +void usb0_function_clear_pipe_tbl(void); +void usb0_function_clear_ep_table_index(void); +uint16_t usb0_function_GetInterfaceNum(uint16_t num); + +#ifdef __cplusplus +} +#endif + + +#endif /* USB0_FUNCTION_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h new file mode 100644 index 0000000000..c33b3e63ea --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_FUNCTION_API_H +#define USB0_FUNCTION_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void usb0_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +uint16_t usb0_api_function_IsConfigured(void); +uint16_t usb0_function_GetDeviceState(void); +uint16_t usb0_api_function_CtrlReadStart(uint32_t size, uint8_t *data); +void usb0_api_function_CtrlWriteStart(uint32_t size, uint8_t *data); +uint16_t usb0_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_api_function_check_pipe_status(uint16_t pipe, uint32_t *size); +void usb0_api_function_clear_pipe_status(uint16_t pipe); +void usb0_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +void usb0_api_function_set_pid_buf(uint16_t pipe); +void usb0_api_function_set_pid_nak(uint16_t pipe); +void usb0_api_function_set_pid_stall(uint16_t pipe); +void usb0_api_function_clear_pid_stall(uint16_t pipe); +uint16_t usb0_api_function_get_pid(uint16_t pipe); +int32_t usb0_api_function_check_stall(uint16_t pipe); +void usb0_api_function_set_sqclr(uint16_t pipe); +void usb0_api_function_set_sqset(uint16_t pipe); +void usb0_api_function_set_csclr(uint16_t pipe); +void usb0_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_api_function_clear_brdy_sts(uint16_t pipe); +void usb0_api_function_clear_bemp_sts(uint16_t pipe); +void usb0_api_function_clear_nrdy_sts(uint16_t pipe); + +void usb0_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb0_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* USB0_FUNCTION_API_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h new file mode 100644 index 0000000000..d74bac718c --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_dmacdrv.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_FUNCTION_DMACDRV_H +#define USB0_FUNCTION_DMACDRV_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef struct dmac_transinfo +{ + uint32_t src_addr; /* Transfer source address */ + uint32_t dst_addr; /* Transfer destination address */ + uint32_t count; /* Transfer byte count */ + uint32_t src_size; /* Transfer source data size */ + uint32_t dst_size; /* Transfer destination data size */ + uint32_t saddr_dir; /* Transfer source address direction */ + uint32_t daddr_dir; /* Transfer destination address direction */ +} dmac_transinfo_t; + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* ==== Transfer specification of the sample program ==== */ +#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ +#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ + +/* ==== DMA modes ==== */ +#define DMAC_MODE_REGISTER (0) /* Register mode */ +#define DMAC_MODE_LINK (1) /* Link mode */ + +/* ==== Transfer requests ==== */ +#define DMAC_REQ_MODE_EXT (0) /* External request */ +#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ +#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ + +/* ==== DMAC transfer sizes ==== */ +#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ +#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ +#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ +#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ +#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ +#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ +#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ +#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ + +/* ==== Address increment for transferring ==== */ +#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ +#define DMAC_TRANS_ADR_INC (0) /* Increment */ + +/* ==== Method for detecting DMA request ==== */ +#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ +#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ +#define DMAC_REQ_DET_LOW (2) /* Low level detection */ +#define DMAC_REQ_DET_HIGH (3) /* High level detection */ + +/* ==== Request Direction ==== */ +#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ +#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ + +/* ==== Descriptors ==== */ +#define DMAC_DESC_HEADER (0) /* Header */ +#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ +#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ +#define DMAC_DESC_COUNT (3) /* Transaction Byte */ +#define DMAC_DESC_CHCFG (4) /* Channel Confg */ +#define DMAC_DESC_CHITVL (5) /* Channel Interval */ +#define DMAC_DESC_CHEXT (6) /* Channel Extension */ +#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ + +/* ==== On-chip peripheral module requests ===== */ +typedef enum dmac_request_factor +{ + DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ + DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ + DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ + DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ + DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ + DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ + DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ + DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ +} dmac_request_factor_t; + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void usb0_function_DMAC1_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_function_DMAC1_Open(uint32_t req); +void usb0_function_DMAC1_Close(uint32_t *remain); +void usb0_function_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +void usb0_function_DMAC2_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb0_function_DMAC2_Open(uint32_t req); +void usb0_function_DMAC2_Close(uint32_t *remain); +void usb0_function_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +#ifdef __cplusplus +} +#endif + +#endif /* USB0_FUNCTION_DMACDRV_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c new file mode 100644 index 0000000000..2f283c7389 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c @@ -0,0 +1,2933 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_dataio.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static uint16_t g_usb0_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)]; + +static void usb0_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb0_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static uint16_t usb0_function_read_dma_d0(uint16_t pipe); +static uint16_t usb0_function_read_dma_d1(uint16_t pipe); +static uint16_t usb0_function_write_dma_d0(uint16_t pipe); +static uint16_t usb0_function_write_dma_d1(uint16_t pipe); + +static void usb0_function_read_c_fifo(uint16_t pipe, uint16_t count); +static void usb0_function_write_c_fifo(uint16_t Pipe, uint16_t count); +static void usb0_function_read_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_function_write_d0_fifo(uint16_t pipe, uint16_t count); +static void usb0_function_read_d1_fifo(uint16_t pipe, uint16_t count); +static void usb0_function_write_d1_fifo(uint16_t pipe, uint16_t count); + +static void usb0_function_clear_transaction_counter(uint16_t pipe); +static void usb0_function_set_transaction_counter(uint16_t pipe, uint32_t count); + +static uint32_t usb0_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr); + +static uint16_t usb0_function_set_dfacc_d0(uint16_t mbw, uint32_t count); +static uint16_t usb0_function_set_dfacc_d1(uint16_t mbw, uint32_t count); + + +/******************************************************************************* +* Function Name: usb0_function_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t usefifo; + uint16_t mbw; + + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + usb0_function_clear_bemp_sts(pipe); + usb0_function_clear_brdy_sts(pipe); + usb0_function_clear_nrdy_sts(pipe); + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + + usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + case USB_FUNCTION_D0FIFO_DMA: + usefifo = USB_FUNCTION_D0USE; + break; + + case USB_FUNCTION_D1FIFO_USE: + case USB_FUNCTION_D1FIFO_DMA: + usefifo = USB_FUNCTION_D1USE; + break; + + default: + usefifo = USB_FUNCTION_CUSE; + break; + }; + + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw); + + usb0_function_clear_transaction_counter(pipe); + + usb0_function_aclrm(pipe); + + status = usb0_function_write_buffer(pipe); + + if (status != DEVDRV_USBF_FIFOERROR) + { + usb0_function_set_pid_buf(pipe); + } + + return status; +} + +/******************************************************************************* +* Function Name: usb0_function_write_buffer +* Description : Writes data in the buffer allocated in the pipe specified by +* : the argument. The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_write_buffer (uint16_t pipe) +{ + uint16_t status; + uint16_t usefifo; + + g_usb0_function_PipeIgnore[pipe] = 0; + usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + status = usb0_function_write_buffer_d0(pipe); + break; + + case USB_FUNCTION_D1FIFO_USE: + status = usb0_function_write_buffer_d1(pipe); + break; + + case USB_FUNCTION_D0FIFO_DMA: + status = usb0_function_write_dma_d0(pipe); + break; + + case USB_FUNCTION_D1FIFO_DMA: + status = usb0_function_write_dma_d1(pipe); + break; + + default: + status = usb0_function_write_buffer_c(pipe); + break; + }; + + switch (status) + { + case DEVDRV_USBF_WRITING: /* Continue of data write */ + usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + usb0_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */ + break; + + case DEVDRV_USBF_WRITEEND: /* End of data write */ + case DEVDRV_USBF_WRITESHRT: /* End of data write */ + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb0_function_clear_nrdy_sts(pipe); + usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + /* for last transfer */ + usb0_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */ + break; + + case DEVDRV_USBF_WRITEDMA: /* DMA write */ + usb0_function_clear_nrdy_sts(pipe); + usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb0_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */ + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_write_buffer_c +* Description : Writes data in the buffer allocated in the pipe specified in +* : the argument. Writes data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_write_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + if (g_usb0_function_CtrZeroLengthFlag == 1) + { + g_usb0_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */ + return DEVDRV_USBF_WRITEEND; + } + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + if (pipe == USB_FUNCTION_PIPE0) + { + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + } + else + { + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); + } + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb0_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_function_write_c_fifo(pipe, (uint16_t)count); + + if (g_usb0_function_data_count[pipe] < (uint32_t)size) + { + g_usb0_function_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0) + { + USB200.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + g_usb0_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */ + } + } + else + { + g_usb0_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_write_buffer_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_write_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb0_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_function_write_d0_fifo(pipe, (uint16_t)count); + + if (g_usb0_function_data_count[pipe] < (uint32_t)size) + { + g_usb0_function_data_count[pipe] = 0; + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_write_buffer_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_write_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb0_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb0_function_write_d1_fifo(pipe, (uint16_t)count); + + if (g_usb0_function_data_count[pipe] < (uint32_t)size) + { + g_usb0_function_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb0_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_write_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D0FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND : Write end +* : DEVDRV_USBF_WRITESHRT : short data +* : DEVDRV_USBF_WRITING : Continue of data write +* : DEVDRV_USBF_WRITEDMA : Write DMA +* : DEVDRV_USBF_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_function_write_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_function_data_count[pipe]; + + if (count != 0) + { + g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 1; + } + else + { + g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; + } + + dfacc = usb0_function_set_dfacc_d0(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; + + Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); + + usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); + + g_usb0_function_data_count[pipe] = 0; + g_usb0_function_data_pointer[pipe] += count; + status = DEVDRV_USBF_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_write_dma_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D1FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND : Write end +* : DEVDRV_USBF_WRITESHRT : short data +* : DEVDRV_USBF_WRITING : Continue of data write +* : DEVDRV_USBF_WRITEDMA : Write DMA +* : DEVDRV_USBF_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb0_function_write_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc=0; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + count = g_usb0_function_data_count[pipe]; + + if (count != 0) + { + g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; + if ((count % size) != 0) + { + g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 1; + } + else + { + g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; + } + + dfacc = usb0_function_set_dfacc_d1(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; + + Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); + + usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); + + g_usb0_function_data_count[pipe] = 0; + g_usb0_function_data_pointer[pipe] += count; + + status = DEVDRV_USBF_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb0_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t usefifo; + + usb0_function_clear_bemp_sts(pipe); + usb0_function_clear_brdy_sts(pipe); + usb0_function_clear_nrdy_sts(pipe); + + usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + usb0_function_start_receive_trns_d0(pipe, size, data); + break; + + case USB_FUNCTION_D1FIFO_USE: + usb0_function_start_receive_trns_d1(pipe, size, data); + break; + + case USB_FUNCTION_D0FIFO_DMA: + usb0_function_start_receive_dma_d0(pipe, size, data); + break; + + case USB_FUNCTION_D1FIFO_DMA: + usb0_function_start_receive_dma_d1(pipe, size, data); + break; + + default: + usb0_function_start_receive_trns_c(pipe, size, data); + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_trns_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* : When storing data in the buffer allocated in the pipe specified in the +* : argument, BRDY interrupt is generated to read data +* : in the interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(pipe); + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_PipeIgnore[pipe] = 0; + + g_usb0_function_PipeDataSize[pipe] = size; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw); + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + + usb0_function_set_transaction_counter(pipe, size); + + usb0_function_aclrm(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_trns_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data in the +* : interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(pipe); + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_PipeIgnore[pipe] = 0; + + g_usb0_function_PipeDataSize[pipe] = size; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + usb0_function_set_transaction_counter(pipe, size); + + usb0_function_aclrm(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_trns_d1 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D1FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(pipe); + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_PipeIgnore[pipe] = 0; + + g_usb0_function_PipeDataSize[pipe] = size; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + usb0_function_set_transaction_counter(pipe, size); + + usb0_function_aclrm(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_dma_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(pipe); + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_PipeIgnore[pipe] = 0; + + g_usb0_function_PipeDataSize[pipe] = 0; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + usb0_function_set_transaction_counter(pipe, size); + + usb0_function_aclrm(pipe); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_function_read_dma(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + } + else + { + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + } + + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_start_receive_dma_d1 +* Description : Read data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb0_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(pipe); + g_usb0_function_data_count[pipe] = size; + g_usb0_function_data_pointer[pipe] = (uint8_t *)data; + g_usb0_function_PipeIgnore[pipe] = 0; + + g_usb0_function_PipeDataSize[pipe] = 0; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb0_function_get_mbw(size, (uint32_t)data); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + usb0_function_set_transaction_counter(pipe, size); + + usb0_function_aclrm(pipe); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb0_function_read_dma(pipe); + + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + } + else + { + usb0_function_enable_nrdy_int(pipe); + usb0_function_enable_brdy_int(pipe); + } + + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_read_buffer +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Uses FIF0 set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_read_buffer (uint16_t pipe) +{ + uint16_t status; + + g_usb0_function_PipeIgnore[pipe] = 0; + + if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) + { + status = usb0_function_read_buffer_d0(pipe); + } + else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) + { + status = usb0_function_read_buffer_d1(pipe); + } + else + { + status = usb0_function_read_buffer_c(pipe); + } + + switch (status) + { + case USB_FUNCTION_READING: /* Continue of data read */ + break; + + case USB_FUNCTION_READEND: /* End of data read */ + case USB_FUNCTION_READSHRT: /* End of data read */ + usb0_function_disable_brdy_int(pipe); + g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + break; + + case USB_FUNCTION_READOVER: /* buffer over */ + if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_buffer_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_read_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_function_data_count[pipe]; + } + else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_function_read_c_fifo(pipe, (uint16_t)count); + } + + g_usb0_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_buffer_d0 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_read_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_function_data_count[pipe]; + } + else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_function_read_d0_fifo(pipe, (uint16_t)count); + } + + g_usb0_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_buffer_d1 +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_read_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb0_function_data_count[pipe]; + } + else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb0_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb0_function_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb0_function_read_d1_fifo(pipe, (uint16_t)count); + } + + g_usb0_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_dma +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO or D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_function_read_dma (uint16_t pipe) +{ + uint16_t status; + + g_usb0_function_PipeIgnore[pipe] = 0; + if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) + { + status = usb0_function_read_dma_d0(pipe); + } + else + { + status = usb0_function_read_dma_d1(pipe); + } + + switch (status) + { + case USB_FUNCTION_READING: /* Continue of data read */ + break; + + case USB_FUNCTION_READZERO: /* End of data read */ + usb0_function_disable_brdy_int(pipe); + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + break; + + case USB_FUNCTION_READEND: /* End of data read */ + case USB_FUNCTION_READSHRT: /* End of data read */ + usb0_function_disable_brdy_int(pipe); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; + } + break; + + case USB_FUNCTION_READOVER: /* buffer over */ + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe]; + } + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READZERO ; zero data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_function_read_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_function_data_count[pipe]; + status = USB_FUNCTION_READING; + } + else + { + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + count = g_usb0_function_data_count[pipe]; + } + else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + status = USB_FUNCTION_READZERO; /* Null Packet receive */ + } + else + { + usb0_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_function_set_dfacc_d0(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */ + g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */ + + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; + g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; + + if (status == USB_FUNCTION_READING) + { + g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY; + } + else + { + g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND; + } + + Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); + + usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_function_data_count[pipe] -= count; + g_usb0_function_data_pointer[pipe] += count; + g_usb0_function_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_read_dma_d1 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by DMA transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READZERO ; zero data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb0_function_read_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc=0; + uint16_t pipebuf_size; + + g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb0_function_data_count[pipe]; + status = USB_FUNCTION_READING; + } + else + { + buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + count = g_usb0_function_data_count[pipe]; + } + else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + status = USB_FUNCTION_READZERO; /* Null Packet receive */ + } + else + { + usb0_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb0_function_set_dfacc_d1(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */ + g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */ + + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe]; + g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; + + if (status == USB_FUNCTION_READING) + { + g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY; + } + else + { + g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND; + } + + Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); + + usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb0_function_data_count[pipe] -= count; + g_usb0_function_data_pointer[pipe] += count; + g_usb0_function_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_function_change_fifo_port +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. After allocating FIF0, waits in the software +* : till the corresponding pipe becomes ready. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : DEVDRV_USBF_FIFOERROR ; Error +* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value +*******************************************************************************/ +uint16_t usb0_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + usb0_function_set_curpipe(pipe, fifosel, isel, mbw); + + for (loop = 0; loop < 4; loop++) + { + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB200.CFIFOCTR; + break; + + case USB_FUNCTION_D0USE: + case USB_FUNCTION_D0DMA: + buffer = USB200.D0FIFOCTR; + break; + + case USB_FUNCTION_D1USE: + case USB_FUNCTION_D1DMA: + buffer = USB200.D1FIFOCTR; + break; + + default: + buffer = 0; + break; + } + + if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY) + { + return buffer; + } + + loop2 = 25; + while (loop2-- > 0) + { + /* wait */ + } + } + + return DEVDRV_USBF_FIFOERROR; +} + +/******************************************************************************* +* Function Name: usb0_function_set_curpipe +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb0_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + g_usb0_function_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D0DMA: + case USB_FUNCTION_D0USE: + buffer = USB200.D0FIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D1DMA: + case USB_FUNCTION_D1USE: + buffer = USB200.D1FIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_function_set_curpipe2 +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* : uint16_t dfacc ; DFACC Access mode +* Return Value : none +*******************************************************************************/ +void usb0_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) +{ + uint16_t buffer; + uint32_t loop; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + uint32_t dummy; +#endif + volatile uint32_t loop2; + + g_usb0_function_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB200.CFIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB200.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D0DMA: + case USB_FUNCTION_D0USE: + buffer = USB200.D0FIFOSEL; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); +#endif + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D0FIFO.UINT32; + } +#endif + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D1DMA: + case USB_FUNCTION_D1USE: + buffer = USB200.D1FIFOSEL; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); +#endif + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB200.D1FIFO.UINT32; + loop = dummy; // avoid warning. + } +#endif + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB200.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb0_function_write_c_fifo +* Description : Writes data in CFIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_write_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.CFIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_read_c_fifo +* Description : Reads data from CFIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_read_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_function_data_pointer[pipe] = USB200.CFIFO.UINT8[HH]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT16[H]; + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT32; + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_write_d0_fifo +* Description : Writes data in D0FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_write_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D0FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_read_d0_fifo +* Description : Reads data from D0FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating DOFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_read_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_function_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H]; + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT32; + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_write_d1_fifo +* Description : Writes data in D1FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_write_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB200.D1FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]); + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_read_d1_fifo +* Description : Reads data from D1FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb0_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb0_function_read_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb0_function_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH]; + g_usb0_function_data_pointer[pipe] += 1; + } + } + else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H]; + g_usb0_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT32; + g_usb0_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_com_get_dmasize +* Description : Calculates access width of DMA transfer by the argument to +* : return as the Return Value. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : DMA transfer size : 0 8bit +* : : 1 16bit +* : : 2 32bit +*******************************************************************************/ +static uint32_t usb0_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + + if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) + { + /* When transfer byte count is odd */ + /* or transfer data area is 8-bit alignment */ + size = 0; /* 8bit */ + } + else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) + { + /* When the transfer byte count is multiples of 2 */ + /* or the transfer data area is 16-bit alignment */ + size = 1; /* 16bit */ + } + else + { + /* When the transfer byte count is multiples of 4 */ + /* or the transfer data area is 32-bit alignment */ + size = 2; /* 32bit */ + } + + return size; +} + +/******************************************************************************* +* Function Name: usb0_function_get_mbw +* Description : Calculates access width of DMA to return the value set in MBW. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit +* : : USB_FUNCTION_BITMBW_16 16bit +* : : USB_FUNCTION_BITMBW_32 32bit +*******************************************************************************/ +uint16_t usb0_function_get_mbw (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + uint16_t mbw; + + size = usb0_function_com_get_dmasize(trncount, dtptr); + + if (size == 0) + { + /* 8bit */ + mbw = USB_FUNCTION_BITMBW_8; + } + else if (size == 1) + { + /* 16bit */ + mbw = USB_FUNCTION_BITMBW_16; + } + else + { + /* 32bit */ + mbw = USB_FUNCTION_BITMBW_32; + } + + return mbw; +} + +/******************************************************************************* +* Function Name: usb0_function_set_transaction_counter +* Description : Sets transaction counter by the argument(PIPEnTRN). +* : Clears transaction before setting to enable transaction counter setting. +* Arguments : uint16_t pipe ; Pipe number +* : uint32_t bsize : Data transfer size +* Return Value : none +*******************************************************************************/ +static void usb0_function_set_transaction_counter (uint16_t pipe, uint32_t bsize) +{ + uint16_t mxps; + uint16_t cnt; + + if (bsize == 0) + { + return; + } + + mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */ + + if ((bsize % mxps) == 0) + { + cnt = (uint16_t)(bsize / mxps); + } + else + { + cnt = (uint16_t)((bsize / mxps) + 1); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE1TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE2TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE3TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE4TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE5TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPE9TRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEATRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPEATRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPEATRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPEBTRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPEBTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPECTRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPECTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPEDTRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPEDTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEETRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPEETRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPEETRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB200.PIPEFTRN = cnt; + RZA_IO_RegWrite_16(&USB200.PIPEFTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_clear_transaction_counter +* Description : Clears the transaction counter by the argument. +* : After executing this function, the transaction counter is invalid. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_transaction_counter (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEATRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPEATRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPEBTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPECTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPEDTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEETRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPEETRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB200.PIPEFTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_stop_transfer +* Description : Stops the USB transfer in the pipe specified by the argument. +* : After stopping the USB transfer, clears the buffer allocated in +* : the pipe. +* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0; +* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt +* : in the corresponding pipe becomes invalid. Sequence bit is also +* : cleared. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_stop_transfer (uint16_t pipe) +{ + uint16_t usefifo; + uint32_t remain; + uint16_t fifo; + + usb0_function_set_pid_nak(pipe); + + usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + usb0_function_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D0USE; + break; + + case USB_FUNCTION_D1FIFO_USE: + usb0_function_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D1USE; + break; + + case USB_FUNCTION_D0FIFO_DMA: + remain = Userdef_USB_usb0_function_stop_dma0(); + usb0_function_dma_stop_d0(pipe, remain); + usb0_function_clear_transaction_counter(pipe); + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D0DMA; + break; + + case USB_FUNCTION_D1FIFO_DMA: + remain = Userdef_USB_usb0_function_stop_dma1(); + usb0_function_dma_stop_d1(pipe, remain); + usb0_function_clear_transaction_counter(pipe); + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D1DMA; + break; + + default: + usb0_function_clear_transaction_counter(pipe); + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_CUSE; + break; + } + + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16); + + /* Interrupt of pipe set is disabled */ + usb0_function_disable_brdy_int(pipe); + usb0_function_disable_nrdy_int(pipe); + usb0_function_disable_bemp_int(pipe); + + usb0_function_aclrm(pipe); + usb0_function_set_csclr(pipe); + + if ( g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT ) + { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; + } + +} + +/******************************************************************************* +* Function Name: usb0_function_set_dfacc_d0 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_function_set_dfacc_d0 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_FUNCTION_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + return dfacc; +} + +/******************************************************************************* +* Function Name: usb0_function_set_dfacc_d1 +* Description : Set the DFACC setting value in D1FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb0_function_set_dfacc_d1 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_FUNCTION_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB200.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c new file mode 100644 index 0000000000..cfc8d0f492 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c @@ -0,0 +1,346 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_dma.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static void usb0_function_dmaint(uint16_t fifo); +static void usb0_function_dmaint_buf2fifo(uint16_t pipe); +static void usb0_function_dmaint_fifo2buf(uint16_t pipe); + + +/******************************************************************************* +* Function Name: usb0_function_dma_stop_d0 +* Description : D0FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_function_dma_stop_d0 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); + + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + buffer = USB200.D0FIFOCTR; + dtln = (buffer & USB_FUNCTION_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain); + g_usb0_function_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_function_dma_stop_d1 +* Description : D1FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb0_function_dma_stop_d1 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); + + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + buffer = USB200.D1FIFOCTR; + dtln = (buffer & USB_FUNCTION_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain); + g_usb0_function_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb0_function_dma_interrupt_d0fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_function_dma_interrupt_d0fifo (uint32_t int_sense) +{ + usb0_function_dmaint(USB_FUNCTION_D0FIFO); + g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_function_dma_interrupt_d1fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb0_function_dma_interrupt_d1fifo (uint32_t int_sense) +{ + usb0_function_dmaint(USB_FUNCTION_D1FIFO); + g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb0_function_dmaint +* Description : This function is DMA transfer end interrupt +* Arguments : uint16_t fifo ; fifo number +* : ; USB_FUNCTION_D0FIFO +* : ; USB_FUNCTION_D1FIFO +* Return Value : none +*******************************************************************************/ +static void usb0_function_dmaint (uint16_t fifo) +{ + uint16_t pipe; + + pipe = g_usb0_function_DmaPipe[fifo]; + + if (g_usb0_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO) + { + usb0_function_dmaint_buf2fifo(pipe); + } + else + { + usb0_function_dmaint_fifo2buf(pipe); + } +} + +/******************************************************************************* +* Function Name: usb0_function_dmaint_fifo2buf +* Description : Executes read completion from FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_function_dmaint_fifo2buf (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + if (useport == USB_FUNCTION_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_function_stop_dma0(); + usb0_function_dma_stop_d0(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND) + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + else + { + usb0_function_enable_brdy_int(pipe); + } + } + } + else + { + remain = Userdef_USB_usb0_function_stop_dma1(); + usb0_function_dma_stop_d1(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND) + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + else + { + usb0_function_enable_brdy_int(pipe); + } + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_dmaint_buf2fifo +* Description : Executes write completion in FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb0_function_dmaint_buf2fifo (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + if (useport == USB_FUNCTION_D0FIFO_DMA) + { + remain = Userdef_USB_usb0_function_stop_dma0(); + usb0_function_dma_stop_d0(pipe, remain); + + if (g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + else + { + remain = Userdef_USB_usb0_function_stop_dma1(); + usb0_function_dma_stop_d1(pipe, remain); + + if (g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + + usb0_function_enable_bemp_int(pipe); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c new file mode 100644 index 0000000000..827efaed71 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c @@ -0,0 +1,249 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_intrn.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_function_brdy_int +* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). +* : According to the pipe that interrupt is generated in, +* : reads/writes buffer allocated in the pipe. +* : This function is executed in the BRDY interrupt handler. +* : This function clears BRDY interrupt status and BEMP interrupt +* : status. +* Arguments : uint16_t Status ; BRDYSTS Register Value +* : uint16_t Int_enbl ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_brdy_int (uint16_t status, uint16_t int_enb) +{ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + pipebit = g_usb0_function_bit_set[pipe]; + + if ((status & pipebit) && (int_enb & pipebit)) + { + USB200.BRDYSTS = (uint16_t)~pipebit; + USB200.BEMPSTS = (uint16_t)~pipebit; + if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) + { + if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) + { + usb0_function_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_function_read_dma(pipe); + usb0_function_disable_brdy_int(pipe); + } + else + { + USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA) + { + if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) + { + usb0_function_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb0_function_read_dma(pipe); + usb0_function_disable_brdy_int(pipe); + } + else + { + USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + usb0_function_read_buffer(pipe); + } + else + { + usb0_function_write_buffer(pipe); + } + } + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_nrdy_int +* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9). +* : Checks NRDY interrupt cause by PID. When the cause if STALL, +* : regards the pipe state as STALL and ends the processing. +* : Then the cause is not STALL, increments the error count to +* : communicate again. When the error count is 3, determines +* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing. +* : This function is executed in the NRDY interrupt handler. +* : This function clears NRDY interrupt status. +* Arguments : uint16_t status ; NRDYSTS Register Value +* : uint16_t int_enb ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_function_nrdy_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.NRDYSTS = (uint16_t)~status; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe]) + { + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) + { + if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT) + { + pid = usb0_function_get_pid(pipe); + if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) + { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + } + else + { + g_usb0_function_PipeIgnore[pipe]++; + if (g_usb0_function_PipeIgnore[pipe] == 3) + { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; + } + else + { + usb0_function_set_pid_buf(pipe); + } + } + } + } + else + { + /* USB Function */ + } + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_bemp_int +* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9). +* Arguments : uint16_t status ; BEMPSTS Register Value +* : uint16_t int_enb ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb0_function_bemp_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + + bitcheck = (uint16_t)(status & int_enb); + + USB200.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe]) + { + pid = usb0_function_get_pid(pipe); + + if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) + { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + } + else + { + inbuf = usb0_function_get_inbuf(pipe); + + if (inbuf == 0) + { + usb0_function_disable_bemp_int(pipe); + usb0_function_set_pid_nak(pipe); + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + } + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c new file mode 100644 index 0000000000..e3d318b984 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c @@ -0,0 +1,2026 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_lib.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_function_enable_brdy_int +* Description : Enables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_enable_brdy_int (uint16_t pipe) +{ + /* enable brdy interrupt */ + USB200.BRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_function_disable_brdy_int +* Description : Disables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_disable_brdy_int (uint16_t pipe) +{ + /* disable brdy interrupt */ + USB200.BRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_brdy_sts (uint16_t pipe) +{ + /* clear brdy status */ + USB200.BRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_enable_bemp_int +* Description : Enables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_enable_bemp_int (uint16_t pipe) +{ + /* enable bemp interrupt */ + USB200.BEMPENB |= (uint16_t)g_usb0_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_function_disable_bemp_int +* Description : Disables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_disable_bemp_int (uint16_t pipe) +{ + /* disable bemp interrupt */ + USB200.BEMPENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_bemp_sts (uint16_t pipe) +{ + /* clear bemp status */ + USB200.BEMPSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_enable_nrdy_int +* Description : Enables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : NRDY. Enables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_enable_nrdy_int (uint16_t pipe) +{ + /* enable nrdy interrupt */ + USB200.NRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_function_disable_nrdy_int +* Description : Disables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : NRDY. Disables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_disable_nrdy_int (uint16_t pipe) +{ + /* disable nrdy interrupt */ + USB200.NRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_nrdy_sts (uint16_t pipe) +{ + /* clear nrdy status */ + USB200.NRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb0_function_is_hispeed +* Description : Returns the result of USB reset hand shake (RHST) as +* : return value. +* Arguments : none +* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed +* : USB_FUNCTION_FULL_SPEED ; Full-Speed +* : LOW_SPEED ; Low-Speed +* : USB_FUNCTION_NON_SPEED ; error +*******************************************************************************/ +uint16_t usb0_function_is_hispeed (void) +{ + uint16_t rhst; + uint16_t speed; + + rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST); + + if (rhst == USB_FUNCTION_HSMODE) + { + speed = USB_FUNCTION_HIGH_SPEED; + } + else if (rhst == USB_FUNCTION_FSMODE) + { + speed = USB_FUNCTION_FULL_SPEED; + } + else if (rhst == USB_FUNCTION_LSMODE) + { + speed = USB_FUNCTION_LOW_SPEED; + } + else + { + speed = USB_FUNCTION_NON_SPEED; + } + + return speed; +} + +/******************************************************************************* +* Function Name: usb0_function_is_hispeed_enable +* Description : Returns the USB High-Speed connection enabled status as +* : return value. +* Arguments : none +* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable +* : DEVDRV_USBF_NO : Hi-Speed Disable +*******************************************************************************/ +uint16_t usb0_function_is_hispeed_enable (void) +{ + uint16_t ret; + + ret = DEVDRV_USBF_NO; + + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1) + { + ret = DEVDRV_USBF_YES; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_function_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_pid_buf (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_function_get_pid(pipe); + + if (pid == DEVDRV_USBF_PID_STALL2) + { + usb0_function_set_pid_nak(pipe); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + DEVDRV_USBF_PID_BUF, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_pid_nak (uint16_t pipe) +{ + uint16_t pid; + uint16_t pbusy; + uint32_t loop; + + pid = usb0_function_get_pid(pipe); + + if (pid == DEVDRV_USBF_PID_STALL2) + { + usb0_function_set_pid_stall(pipe); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + DEVDRV_USBF_PID_NAK, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + + if (pid == DEVDRV_USBF_PID_BUF) + { + for (loop = 0; loop < 200; loop++) + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PBUSY_SHIFT, + USB_DCPCTR_PBUSY); + break; + + case USB_FUNCTION_PIPE1: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE2: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE3: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE4: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE5: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE6: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE7: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE8: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE9: + pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PBUSY_SHIFT, + USB_PIPEnCTR_9_PBUSY); + break; + + case USB_FUNCTION_PIPEA: + pbusy = RZA_IO_RegRead_16(&USB200.PIPEACTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEB: + pbusy = RZA_IO_RegRead_16(&USB200.PIPEBCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEC: + pbusy = RZA_IO_RegRead_16(&USB200.PIPECCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPED: + pbusy = RZA_IO_RegRead_16(&USB200.PIPEDCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEE: + pbusy = RZA_IO_RegRead_16(&USB200.PIPEECTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEF: + pbusy = RZA_IO_RegRead_16(&USB200.PIPEFCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + default: + pbusy = 1; + break; + } + + if (pbusy == 0) + { + break; + } + Userdef_USB_usb0_function_delay_500ns(); + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_pid_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_function_get_pid(pipe); + if (pid == DEVDRV_USBF_PID_BUF) + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + DEVDRV_USBF_PID_STALL2, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + } + else + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + DEVDRV_USBF_PID_STALL, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name: usb0_function_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_pid_stall (uint16_t pipe) +{ + usb0_function_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb0_function_get_pid (uint16_t pipe) +{ + uint16_t pid; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + pid = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + pid = RZA_IO_RegRead_16(&USB200.PIPEACTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + pid = RZA_IO_RegRead_16(&USB200.PIPEBCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + pid = RZA_IO_RegRead_16(&USB200.PIPECCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + pid = RZA_IO_RegRead_16(&USB200.PIPEDCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + pid = RZA_IO_RegRead_16(&USB200.PIPEECTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + pid = RZA_IO_RegRead_16(&USB200.PIPEFCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + pid = 0; + break; + } + + return pid; +} + +/******************************************************************************* +* Function Name: usb0_function_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_csclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_CSCLR_SHIFT, + USB_DCPCTR_CSCLR); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_CSCLR_SHIFT, + USB_PIPEnCTR_9_CSCLR); + break; + + default: + /* PIPEA-F have not CSCLR */ + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_sqclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQCLR_SHIFT, + USB_DCPCTR_SQCLR); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQCLR_SHIFT, + USB_PIPEnCTR_9_SQCLR); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_function_set_sqset (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB200.DCPCTR, + 1, + USB_DCPCTR_SQSET_SHIFT, + USB_DCPCTR_SQSET); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQSET_SHIFT, + USB_PIPEnCTR_9_SQSET); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_get_sqmon +* Description : Toggle bit of specified pipe is obtained +* Arguments : uint16_t pipe ; Pipe number +* Return Value : sqmon +*******************************************************************************/ +uint16_t usb0_function_get_sqmon (uint16_t pipe) +{ + uint16_t sqmon; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR, + USB_DCPCTR_SQMON_SHIFT, + USB_DCPCTR_SQMON); + break; + + case USB_FUNCTION_PIPE1: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE2: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE3: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE4: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE5: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE6: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE7: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE8: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE9: + sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_SQMON_SHIFT, + USB_PIPEnCTR_9_SQMON); + break; + + case USB_FUNCTION_PIPEA: + sqmon = RZA_IO_RegRead_16(&USB200.PIPEACTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEB: + sqmon = RZA_IO_RegRead_16(&USB200.PIPEBCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEC: + sqmon = RZA_IO_RegRead_16(&USB200.PIPECCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPED: + sqmon = RZA_IO_RegRead_16(&USB200.PIPEDCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEE: + sqmon = RZA_IO_RegRead_16(&USB200.PIPEECTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEF: + sqmon = RZA_IO_RegRead_16(&USB200.PIPEFCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + default: + sqmon = 0; + break; + } + + return sqmon; +} + +/******************************************************************************* +* Function Name: usb0_function_aclrm +* Description : The buffer of specified pipe is initialized +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_function_aclrm (uint16_t pipe) +{ + usb0_function_set_aclrm(pipe); + usb0_function_clr_aclrm(pipe); +} + +/******************************************************************************* +* Function Name: usb0_function_set_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_function_set_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 1, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_clr_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb0_function_clr_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB200.PIPE1CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB200.PIPE2CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB200.PIPE3CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB200.PIPE4CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB200.PIPE5CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB200.PIPE6CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB200.PIPE7CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB200.PIPE8CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB200.PIPE9CTR, + 0, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB200.PIPEACTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB200.PIPEBCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB200.PIPECCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB200.PIPEDCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB200.PIPEECTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB200.PIPEFCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_get_inbuf +* Description : Returns INBUFM of the pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : inbuf +*******************************************************************************/ +uint16_t usb0_function_get_inbuf (uint16_t pipe) +{ + uint16_t inbuf; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE1: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE2: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE3: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE4: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE5: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE6: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE7: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE8: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE9: + inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR, + USB_PIPEnCTR_9_INBUFM_SHIFT, + USB_PIPEnCTR_9_INBUFM); + break; + + case USB_FUNCTION_PIPEA: + inbuf = RZA_IO_RegRead_16(&USB200.PIPEACTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEB: + inbuf = RZA_IO_RegRead_16(&USB200.PIPEBCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEC: + inbuf = RZA_IO_RegRead_16(&USB200.PIPECCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPED: + inbuf = RZA_IO_RegRead_16(&USB200.PIPEDCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEE: + inbuf = RZA_IO_RegRead_16(&USB200.PIPEECTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEF: + inbuf = RZA_IO_RegRead_16(&USB200.PIPEFCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + default: + inbuf = 0; + break; + } + + return inbuf; +} + +/******************************************************************************* +* Function Name: usb0_function_setting_interrupt +* Description : Sets the USB module interrupt level. +* Arguments : uint8_t level ;interrupt level +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_setting_interrupt (uint8_t level) +{ + uint16_t d0fifo_dmaintid; + uint16_t d1fifo_dmaintid; + + R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_function_interrupt); + R_INTC_SetPriority(INTC_ID_USBI0, level); + R_INTC_Enable(INTC_ID_USBI0); + + d0fifo_dmaintid = Userdef_USB_usb0_function_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_function_dma_interrupt_d0fifo); + R_INTC_SetPriority(d0fifo_dmaintid, level); + R_INTC_Enable(d0fifo_dmaintid); + } + + d1fifo_dmaintid = Userdef_USB_usb0_function_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_function_dma_interrupt_d1fifo); + R_INTC_SetPriority(d1fifo_dmaintid, level); + R_INTC_Enable(d1fifo_dmaintid); + } +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_reset_module +* Description : Initializes the USB module. +* : Enables providing clock to the USB module. +* : Sets USB bus wait register. +* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ +* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +void usb0_function_reset_module (uint16_t clockmode) +{ + /* UPLLE bit is only USB0 */ + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_UPLLE_SHIFT, + USB_SYSCFG_UPLLE) == 1) + { + if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode) + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); + Userdef_USB_usb0_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + Userdef_USB_usb0_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + } + else + { + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); + Userdef_USB_usb0_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + + USB200.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT); +} + +/******************************************************************************* +* Function Name: usb0_function_get_buf_size +* Description : Obtains pipe buffer size specified by the argument and +* : maximum packet size of the USB device in use. +* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum +* : packet size of the USB device using the corresponding pipe. +* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the +* : corresponding pipe is in continuous transfer mode, +* : obtains the buffer size allocated in the corresponcing pipe, +* : when incontinuous transfer, obtains maximum packet size. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Maximum packet size or buffer size +*******************************************************************************/ +uint16_t usb0_function_get_buf_size (uint16_t pipe) +{ + uint16_t size; + uint16_t bufsize; + + if (pipe == USB_FUNCTION_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) + { + bufsize = RZA_IO_RegRead_16(&g_usb0_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); + size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + } + return size; +} + +/******************************************************************************* +* Function Name: usb0_function_get_mxps +* Description : Obtains maximum packet size of the USB device using the pipe +* : specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Max Packet Size +*******************************************************************************/ +uint16_t usb0_function_get_mxps (uint16_t pipe) +{ + uint16_t size; + + if (pipe == USB_FUNCTION_PIPE0) + { + size = RZA_IO_RegRead_16(&USB200.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + return size; +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c new file mode 100644 index 0000000000..369b2bea60 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c @@ -0,0 +1,441 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_api.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_api_function_init +* Description : Initializes the USB module in the USB function mode. +* Arguments : uint8_t int_level ; interruput level +* : uint16_t mode : Speed modes +* : : USB_FUCNTION_HIGH_SPEED: High-speed device +* : : USB_FUCNTION_FULL_SPEED: Full-speed device +* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ +* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) +{ + volatile uint8_t dummy_buf; + + CPG.STBCR7 &= 0xfd; /* The clock of USB0 modules is permitted */ + dummy_buf = CPG.STBCR7; /* (Dummy read) */ + + usb0_function_setting_interrupt(int_level); + + usb0_function_reset_module(clockmode); /* reset USB module with setting tranciever */ + /* and HSE=1 */ + + usb0_function_init_status(); /* clear variables */ + + usb0_function_InitModule(mode); /* select USB Function and Interrupt Enable */ + /* Detect USB Device to attach or detach */ +} +#endif + +/******************************************************************************* +* Function Name: usb0_api_function_IsConfigured +* Description : Checks if the USB device is configured to return the result as +* : the return value. +* Arguments : none +* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend +* : DEVDRV_USBF_NO : not Configured +*******************************************************************************/ +uint16_t usb0_api_function_IsConfigured (void) +{ + uint16_t dvst; + + dvst = usb0_function_GetDeviceState(); + + if ((dvst == USB_FUNCTION_DVST_CONFIGURED) || + (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND)) + { + return DEVDRV_USBF_YES; + } + + return DEVDRV_USBF_NO; +} + +/******************************************************************************* +* Function Name: usb0_function_GetDeviceState +* Description : Returns the state of USB device. +* Arguments : none +* Return Value : Device States +*******************************************************************************/ +uint16_t usb0_function_GetDeviceState (void) +{ + uint16_t dvsq; + uint16_t dvst; + + dvsq = USB200.INTSTS0; + switch(dvsq & USB_FUNCTION_BITDVSQ) + { + case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */ + dvst = USB_FUNCTION_DVST_POWERED; + break; + + case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */ + dvst = USB_FUNCTION_DVST_DEFAULT; + break; + + case USB_FUNCTION_DS_ADDS: /* Address state */ + dvst = USB_FUNCTION_DVST_ADDRESS; + break; + + case USB_FUNCTION_DS_CNFG: /* Configured state */ + dvst = USB_FUNCTION_DVST_CONFIGURED; + break; + + case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */ + dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND; + break; + + case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */ + case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */ + case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */ + dvst = USB_FUNCTION_DVST_SUSPEND; + break; + + default: /* error */ + dvst = USB_FUNCTION_DVST_SUSPEND; + break; + } + + return dvst; +} + +/******************************************************************************* +* Function Name: usb0_api_function_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : none +*******************************************************************************/ +void usb0_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + usb0_function_start_receive_transfer(pipe, size, data); +} + +/******************************************************************************* +* Function Name: usb0_api_function_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb0_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + + status = usb0_function_start_send_transfer(pipe, size, data); + + return status; +} + +/******************************************************************************* +* Function Name: usb0_api_function_check_pipe_status +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t *size ; Data Size +* Return Value : Pipe Status +*******************************************************************************/ +uint16_t usb0_api_function_check_pipe_status (uint16_t pipe, uint32_t * size) +{ + if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE) + { + *size = g_usb0_function_PipeDataSize[pipe]; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_DONE; + } + else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES) + { + *size = 0; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_NORES; + } + else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL) + { + *size = 0; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_STALL; + } + else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR) + { + *size = 0; + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_FIFOERROR; + } + else + { + /* Do Nothing */ + } + + return g_usb0_function_pipe_status[pipe]; +} + +/******************************************************************************* +* Function Name: usb0_api_function_clear_pipe_status +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Pipe Status +*******************************************************************************/ +void usb0_api_function_clear_pipe_status (uint16_t pipe) +{ + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb0_function_PipeDataSize[pipe] = 0; +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_pid_buf (uint16_t pipe) +{ + usb0_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_pid_nak (uint16_t pipe) +{ + usb0_function_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_pid_stall (uint16_t pipe) +{ + usb0_function_set_pid_stall(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_clear_pid_stall (uint16_t pipe) +{ + usb0_function_clear_pid_stall(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb0_api_function_get_pid (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_function_get_pid(pipe); + + return pid; +} + +/******************************************************************************* +* Function Name: usb0_api_function_check_stall +* Description : +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +int32_t usb0_api_function_check_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb0_function_get_pid(pipe); + + if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL) + { + return DEVDRV_USBF_STALL; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_sqclr (uint16_t pipe) +{ + usb0_function_set_sqclr(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_sqset (uint16_t pipe) +{ + usb0_function_set_sqset(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_csclr (uint16_t pipe) +{ + usb0_function_set_csclr(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_set_curpipe +* Description : Allocates FIF0 specifed by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb0_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + usb0_function_set_curpipe(pipe, fifosel, isel, mbw); +} + +/******************************************************************************* +* Function Name: usb0_api_function_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_clear_brdy_sts (uint16_t pipe) +{ + usb0_function_clear_brdy_sts(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_clear_bemp_sts (uint16_t pipe) +{ + usb0_function_clear_bemp_sts(pipe); +} + +/******************************************************************************* +* Function Name: usb0_api_function_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb0_api_function_clear_nrdy_sts (uint16_t pipe) +{ + usb0_function_clear_nrdy_sts(pipe); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c new file mode 100644 index 0000000000..0a9121ab8e --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_controlrw.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_api_function_CtrlReadStart +* Description : Executes the USB control read transfer. +* : USB host controller <- USB device +* Arguments : uint16_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : DEVDRV_USBF_WRITEEND ; End of data write +* : DEVDRV_USBF_WRITESHRT ; End of short data write +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_FIFOERROR ; FIFO access error +*******************************************************************************/ +uint16_t usb0_api_function_CtrlReadStart (uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t mbw; + + usb0_function_set_pid_nak(USB_FUNCTION_PIPE0); + + g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size; + g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0], + (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + + status = usb0_function_write_buffer_c(USB_FUNCTION_PIPE0); + + /* Peripheral Control sequence */ + switch (status) + { + case DEVDRV_USBF_WRITESHRT: /* End of data write */ + case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */ + case DEVDRV_USBF_WRITING: /* Continue of data write */ + usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */ + usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */ + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ + break; + + default: + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb0_api_function_CtrlWriteStart +* Description : Executes the USB control write transfer. +* : USB host controller -> USB device +* Arguments : uint16_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb0_api_function_CtrlWriteStart (uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb0_function_set_pid_nak(USB_FUNCTION_PIPE0); + + g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size; + g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data; + + mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0], + (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]); + usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + + usb0_function_enable_brdy_int(USB_FUNCTION_PIPE0); + usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c new file mode 100644 index 0000000000..5f1ff018f2 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c @@ -0,0 +1,144 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_global.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +const uint16_t g_usb0_function_bit_set[16] = +{ + 0x0001, 0x0002, 0x0004, 0x0008, + 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, + 0x1000, 0x2000, 0x4000, 0x8000 +}; + +uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint8_t * g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; + +uint16_t g_usb0_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb0_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb0_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint32_t g_usb0_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1]; + +USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[2]; +uint16_t g_usb0_function_DmaPipe[2]; +uint16_t g_usb0_function_DmaBval[2]; +uint16_t g_usb0_function_DmaStatus[2]; + +uint16_t g_usb0_function_CtrZeroLengthFlag; + +//uint16_t g_usb0_function_ConfigNum; +//uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO]; +//uint16_t g_usb0_function_RemoteWakeupFlag; +uint16_t g_usb0_function_TestModeFlag; +uint16_t g_usb0_function_TestModeSelectors; + +//uint16_t g_usb0_function_ReqType; +//uint16_t g_usb0_function_ReqTypeType; +//uint16_t g_usb0_function_ReqTypeRecip; +//uint16_t g_usb0_function_ReqRequest; +//uint16_t g_usb0_function_ReqValue; +//uint16_t g_usb0_function_ReqIndex; +//uint16_t g_usb0_function_ReqLength; + +//uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; + +uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +* Function Name: usb0_function_init_status +* Description : Initialization USB Sample Driver Variable. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_init_status (void) +{ + uint16_t pipe; + + //g_usb0_function_ConfigNum = 0; + //g_usb0_function_RemoteWakeupFlag = DEVDRV_USBF_OFF; + g_usb0_function_TestModeFlag = DEVDRV_USBF_OFF; + g_usb0_function_CtrZeroLengthFlag = 0; + +#if 0 + usb0_function_clear_alt(); +#endif + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb0_function_PipeDataSize[pipe] = 0; + g_usb0_function_data_count[pipe] = 0; + + /* pipe configuration in usb0_function_ResetEP() */ + g_usb0_function_pipecfg[pipe] = 0; + g_usb0_function_pipebuf[pipe] = 0; + g_usb0_function_pipemaxp[pipe] = 0; + g_usb0_function_pipeperi[pipe] = 0; + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c new file mode 100644 index 0000000000..66949dee63 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c @@ -0,0 +1,330 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_sig.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_function_EnableINTModule(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_function_InitModule +* Description : Initializes the USB module in the USB function mode. +* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode +* : ; other ; Full-speed Mode +* Return Value : none +*******************************************************************************/ +void usb0_function_InitModule (uint16_t mode) +{ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); /* USB function */ + + /* USB module operation enabled */ + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + if (mode == USB_FUNCTION_HIGH_SPEED) + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); /* Hi-Speed Mode */ + } + else + { + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + + /* for power-on */ + if (usb0_function_CheckVBUStaus() == DEVDRV_USBF_ON) + { + usb0_function_EnableINTModule(); /* Interrupt Enable */ + usb0_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */ + } + else + { + usb0_function_USB_FUNCTION_Detach(); /* USB Detach */ + /* with Interrupt Enable */ + } +} + +/******************************************************************************* +* Function Name: usb0_function_CheckVBUStaus +* Description : Checks the USB-VBUS state to returns the connection state to +* : the USB host. +* Arguments : none +* Return Value : DEVDRV_USBF_ON : VBUS ON +* : DEVDRV_USBF_OFF : VBUS OFF +*******************************************************************************/ +uint16_t usb0_function_CheckVBUStaus (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + + /* monitor VBUS pins */ + do + { + buf1 = RZA_IO_RegRead_16(&USB200.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + Userdef_USB_usb0_function_delay_10us(1); + buf2 = RZA_IO_RegRead_16(&USB200.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + Userdef_USB_usb0_function_delay_10us(1); + buf3 = RZA_IO_RegRead_16(&USB200.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + } while ((buf1 != buf2) || (buf2 != buf3)); + + if (buf1 == DEVDRV_USBF_OFF) + { + return DEVDRV_USBF_OFF; /* detach */ + } + + return DEVDRV_USBF_ON; /* attach */ +} + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_Attach +* Description : Connects to the USB host controller. +* : This function pulls up D+. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_USB_FUNCTION_Attach (void) +{ + Userdef_USB_usb0_function_attach(); + + Userdef_USB_usb0_function_delay_xms(10); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DPRPU_SHIFT, + USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */ +} + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_Detach +* Description : Disconnects from the USB host controller. +* : This function opens D+/D-. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_USB_FUNCTION_Detach (void) +{ + uint16_t pipe; + + Userdef_USB_usb0_function_detach(); + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE) + { + usb0_function_stop_transfer(pipe); + } + } + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_DPRPU_SHIFT, + USB_SYSCFG_DPRPU); /* open D+ and D- */ + + /* Detach Recovery */ + Userdef_USB_usb0_function_delay_500ns(); /* need 1us=500ns * 2 wait */ + Userdef_USB_usb0_function_delay_500ns(); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); + Userdef_USB_usb0_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */ + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 0, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); /* soft reset module */ + Userdef_USB_usb0_function_delay_500ns(); + + RZA_IO_RegWrite_16(&USB200.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + usb0_function_EnableINTModule(); /* Interrupt Enable */ +} + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_BusReset +* Description : This function is executed when the USB device is transitioned +* : to POWERD_STATE. Sets the device descriptor according to the +* : connection speed determined by the USB reset hand shake. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb0_function_USB_FUNCTION_BusReset (void) +{ + usb0_function_init_status(); /* memory clear */ + + if (usb0_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) + { + usb0_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */ + } + else + { + usb0_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */ + } + + usb0_function_ResetDCP(); /* Default Control PIPE reset */ +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_Resume +* Description : This function is executed when the USB device detects a resume +* : signal. +* : The USB sample driver does not operate for this function. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb0_function_USB_FUNCTION_Resume (void) +{ + /* NOP */ +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_Suspend +* Description : This function is executed when the USB device detects a suspend +* : signal. +* : The USB sample driver does not operate for this function. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb0_function_USB_FUNCTION_Suspend (void) +{ + /* NOP */ +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_USB_FUNCTION_TestMode +* Description : This function is executed when the USB device is transitioned U +* : to TEST_MODE by the USB standard request. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_USB_FUNCTION_TestMode (void) +{ + switch (g_usb0_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT) + { + case USB_FUNCTION_FUNCTION_TEST_J: + case USB_FUNCTION_FUNCTION_TEST_K: + case USB_FUNCTION_FUNCTION_TEST_SE0_NAK: + case USB_FUNCTION_FUNCTION_TEST_PACKET: + RZA_IO_RegWrite_16(&USB200.TESTMODE, + (g_usb0_function_TestModeSelectors >> 8), + USB_TESTMODE_UTST_SHIFT, + USB_TESTMODE_UTST); + break; + + case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE: + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb0_function_EnableINTModule +* Description : Enables USB interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void usb0_function_EnableINTModule (void) +{ + uint16_t buf; + + buf = USB200.INTENB0; + buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE | + USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE); + USB200.INTENB0 = buf; + + usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c new file mode 100644 index 0000000000..df7fbf5bbb --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c @@ -0,0 +1,453 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_sub.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb0_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +#if 0 +extern const uint16_t *g_usb0_function_EndPntPtr[]; +extern uint8_t g_usb0_function_DeviceDescriptor[]; +extern uint8_t *g_usb0_function_ConfigurationPtr[]; +#endif + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb0_function_ResetDCP +* Description : Initializes the default control pipe(DCP). +* Outline : Reset default control pipe +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_ResetDCP (void) +{ + USB200.DCPCFG = 0; +#if 0 + USB200.DCPMAXP = g_usb0_function_DeviceDescriptor[7]; +#else + USB200.DCPMAXP = 64; +#endif + + USB200.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB200.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB200.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); +} + +/******************************************************************************* +* Function Name: usb0_function_ResetEP +* Description : Initializes the end point. +* Arguments : uint16_t num ; Configuration Number +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_ResetEP (uint16_t num) +{ + uint16_t pipe; + uint16_t ep; + uint16_t index; + uint16_t buf; + uint16_t * tbl; + + tbl = (uint16_t *)(g_usb0_function_EndPntPtr[num - 1]); + + for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) + { + if (g_usb0_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR) + { + index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb0_function_EPTableIndex[ep]); + pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE); + + g_usb0_function_PipeTbl[pipe] = (uint16_t)( ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) | + ep | + (tbl[index + 0] & USB_FUNCTION_FIFO_USE) ); + + if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT) + { + tbl[index + 1] |= USB_FUNCTION_SHTNAKON; +#ifdef __USB_DMA_BFRE_ENABLE__ + /* this routine cannnot be perfomred if read operation is executed in buffer size */ + if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) || + ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)) + { + tbl[index + 1] |= USB_FUNCTION_BFREON; + } +#endif + } + + /* Interrupt Disable */ + buf = USB200.BRDYENB; + buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; + USB200.BRDYENB = buf; + buf = USB200.NRDYENB; + buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; + USB200.NRDYENB = buf; + buf = USB200.BEMPENB; + buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; + USB200.BEMPENB = buf; + + usb0_function_set_pid_nak(pipe); + + /* CurrentPIPE Clear */ + if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB200.CFIFOSEL, + 0, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE); + } + + if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, + 0, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE); + } + + if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, + 0, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE); + } + + /* PIPE Configuration */ + USB200.PIPESEL = pipe; + USB200.PIPECFG = tbl[index + 1]; + USB200.PIPEBUF = tbl[index + 2]; + USB200.PIPEMAXP = tbl[index + 3]; + USB200.PIPEPERI = tbl[index + 4]; + + g_usb0_function_pipecfg[pipe] = tbl[index + 1]; + g_usb0_function_pipebuf[pipe] = tbl[index + 2]; + g_usb0_function_pipemaxp[pipe] = tbl[index + 3]; + g_usb0_function_pipeperi[pipe] = tbl[index + 4]; + + /* Buffer Clear */ + usb0_function_set_sqclr(pipe); + usb0_function_aclrm(pipe); + + /* init Global */ + g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb0_function_PipeDataSize[pipe] = 0; + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_EpToPipe +* Description : Returns the pipe which end point specified by the argument is +* : allocated to. +* Arguments : uint16_t ep ; Direction + Endpoint Number +* Return Value : USB_FUNCTION_EP_ERROR : Error +* : Others : Pipe Number +*******************************************************************************/ +uint16_t usb0_function_EpToPipe (uint16_t ep) +{ + uint16_t pipe; + + for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((g_usb0_function_PipeTbl[pipe] & 0x00ff) == ep) + { + return pipe; + } + } + + return USB_FUNCTION_EP_ERROR; +} + +/******************************************************************************* +* Function Name: usb0_function_InitEPTable +* Description : Sets the end point by the Alternate setting value of the +* : configuration number and the interface number specified by the +* : argument. +* Arguments : uint16_t Con_Num ; Configuration Number +* : uint16_t Int_Num ; Interface Number +* : uint16_t Alt_Num ; Alternate Setting +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num) +{ + uint8_t * ptr; + uint16_t point_interface; + uint16_t point_endpoint; + uint16_t length; + uint16_t start; + uint16_t numbers; + uint16_t endpoint; + + ptr = (uint8_t *)g_usb0_function_ConfigurationPtr[Con_Num - 1]; + point_interface = *ptr; + length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2)); + ptr += *ptr; + start = 0; + numbers = 0; + point_endpoint = 0; + + for (; point_interface < length;) + { + switch (*(ptr + 1)) /* Descriptor Type ? */ + { + case USB_FUNCTION_DT_INTERFACE: /* Interface */ + if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num)) + { + numbers = *(ptr + 4); + } + else + { + start += *(ptr + 4); + } + point_interface += *ptr; + ptr += *ptr; + break; + + case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ + if (point_endpoint < numbers) + { + endpoint = (uint16_t)(*(ptr + 2) & 0x0f); + g_usb0_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint); + ++point_endpoint; + } + point_interface += *ptr; + ptr += *ptr; + break; + + case USB_FUNCTION_DT_DEVICE: /* Device */ + case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ + case USB_FUNCTION_DT_STRING: /* String */ + default: /* Class, Vendor, else */ + point_interface += *ptr; + ptr += *ptr; + break; + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_GetConfigNum +* Description : Returns the number of configuration referring to the number of +* : configuration described in the device descriptor. +* Arguments : none +* Return Value : Number of possible configurations (bNumConfigurations). +*******************************************************************************/ +#if 0 +uint16_t usb0_function_GetConfigNum (void) +{ + return (uint16_t)g_usb0_function_DeviceDescriptor[17]; +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_GetInterfaceNum +* Description : Returns the number of interface referring to the number of +* : interface described in the configuration descriptor. +* Arguments : uint16_t num ; Configuration Number +* Return Value : Number of this interface (bNumInterfaces). +*******************************************************************************/ +#if 0 +uint16_t usb0_function_GetInterfaceNum (uint16_t num) +{ + return (uint16_t)(*(g_usb0_function_ConfigurationPtr[num - 1] + 4)); +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_GetAltNum +* Description : Returns the Alternate setting value of the configuration number +* : and the interface number specified by the argument. +* Arguments : uint16_t Con_Num ; Configuration Number +* : uint16_t Int_Num ; Interface Number +* Return Value : Value used to select this alternate setting(bAlternateSetting). +*******************************************************************************/ +#if 0 +uint16_t usb0_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num) +{ + uint8_t * ptr; + uint16_t point; + uint16_t alt_num = 0; + uint16_t length; + + ptr = (uint8_t *)(g_usb0_function_ConfigurationPtr[Con_Num - 1]); + point = ptr[0]; + ptr += ptr[0]; /* InterfaceDescriptor[0] */ + length = (uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 2)); + length |= (uint16_t)((uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8); + + for (; point < length;) /* Search Descriptor Table size */ + { + switch (ptr[1]) /* Descriptor Type ? */ + { + case USB_FUNCTION_DT_INTERFACE: /* Interface */ + if (Int_Num == ptr[2]) + { + alt_num = (uint16_t)ptr[3]; /* Alternate Number count */ + } + point += ptr[0]; + ptr += ptr[0]; + break; + + case USB_FUNCTION_DT_DEVICE: /* Device */ + case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ + case USB_FUNCTION_DT_STRING: /* String */ + case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ + default: /* Class, Vendor, else */ + point += ptr[0]; + ptr += ptr[0]; + break; + } + } + return alt_num; +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_CheckRemoteWakeup +* Description : Returns the result of the remote wake up function is supported +* : or not referring to the configuration descriptor. +* Arguments : none +* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup +* : DEVDRV_USBF_OFF : not Support Remote Wakeup +*******************************************************************************/ +#if 0 +uint16_t usb0_function_CheckRemoteWakeup (void) +{ + uint8_t atr; + + if (g_usb0_function_ConfigNum == 0) + { + return DEVDRV_USBF_OFF; + } + + atr = *(g_usb0_function_ConfigurationPtr[g_usb0_function_ConfigNum - 1] + 7); + + if (atr & USB_FUNCTION_CF_RWUP) + { + return DEVDRV_USBF_ON; + } + + return DEVDRV_USBF_OFF; +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_clear_alt +* Description : Initializes the Alternate setting area. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_clear_alt (void) +{ + int i; + + for (i = 0; i < USB_FUNCTION_ALT_NO; ++i) + { + g_usb0_function_Alternate[i] = 0; /* Alternate */ + } +} +#endif + +/******************************************************************************* +* Function Name: usb0_function_clear_pipe_tbl +* Description : Initializes pipe definition table. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb0_function_clear_pipe_tbl (void) +{ + int pipe; + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + g_usb0_function_PipeTbl[pipe] = 0; + } +} + +/******************************************************************************* +* Function Name: usb0_function_clear_ep_table_index +* Description : Initializes the end point table index. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 +void usb0_function_clear_ep_table_index (void) +{ + int ep; + + for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) + { + g_usb0_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR; + } +} +#endif + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c new file mode 100644 index 0000000000..5b46b68ee9 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c @@ -0,0 +1,698 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_dmacdrv.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" +#include "usb0_function_dmacdrv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ + +/* ==== Request setting information for on-chip peripheral module ==== */ +typedef enum dmac_peri_req_reg_type +{ + DMAC_REQ_MID, + DMAC_REQ_RID, + DMAC_REQ_AM, + DMAC_REQ_LVL, + DMAC_REQ_REQD +} dmac_peri_req_reg_type_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +/* ==== Prototype declaration ==== */ + +/* ==== Global variable ==== */ +/* On-chip peripheral module request setting table */ +static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] = +{ + /* MID,RID,AM,LVL,REQD */ + {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ + {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ + {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ + {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ + {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ + {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ + {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ + {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ +}; + + +/******************************************************************************* +* Function Name: usb0_function_DMAC1_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 1. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 1 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer +* : uint32_t request_factor : Factor for on-chip peripheral module request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit +* Return Value : none +*******************************************************************************/ +void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, + uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->daddr_dir, + DMAC1_CHCFG_n_DAD_SHIFT, + DMAC1_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->saddr_dir, + DMAC1_CHCFG_n_SAD_SHIFT, + DMAC1_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->dst_size, + DMAC1_CHCFG_n_DDS_SHIFT, + DMAC1_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + trans_info->src_size, + DMAC1_CHCFG_n_SDS_SHIFT, + DMAC1_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DMS_SHIFT, + DMAC1_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSEL_SHIFT, + DMAC1_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_SBE_SHIFT, + DMAC1_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_DEM_SHIFT, + DMAC1_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_REN_SHIFT, + DMAC1_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_RSW_SHIFT, + DMAC1_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_TM_SHIFT, + DMAC1_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_SEL_SHIFT, + DMAC1_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 1, + DMAC1_CHCFG_n_HIEN_SHIFT, + DMAC1_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + 0, + DMAC1_CHCFG_n_LOEN_SHIFT, + DMAC1_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC1_CHCFG_n_AM_SHIFT, + DMAC1_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC1_CHCFG_n_LVL_SHIFT, + DMAC1_CHCFG_n_LVL); + + if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC1.CHCFG_n, + req_direction, + DMAC1_CHCFG_n_REQD_SHIFT, + DMAC1_CHCFG_n_REQD); + } + + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC01_DMARS_CH1_RID_SHIFT, + DMAC01_DMARS_CH1_RID); + RZA_IO_RegWrite_32(&DMAC01.DMARS, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC01_DMARS_CH1_MID_SHIFT, + DMAC01_DMARS_CH1_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC1_Open +* Description : Enables DMAC channel 1 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_function_DMAC1_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n, + DMAC1_CHCTRL_n_SWRST_SHIFT, + DMAC1_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_SETEN_SHIFT, + DMAC1_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_STG_SHIFT, + DMAC1_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC1_Close +* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_function_DMAC1_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n, + 1, + DMAC1_CHCTRL_n_CLREN_SHIFT, + DMAC1_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_TACT_SHIFT, + DMAC1_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_EN_SHIFT, + DMAC1_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC1.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC1_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 1 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 1 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n, + DMAC1_CHSTAT_n_SR_SHIFT, + DMAC1_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC1.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC1.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC1.N1TB_n = count; /* Total transfer byte count */ + } +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC2_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 2. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 2 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +*******************************************************************************/ +void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, + uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->daddr_dir, + DMAC2_CHCFG_n_DAD_SHIFT, + DMAC2_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->saddr_dir, + DMAC2_CHCFG_n_SAD_SHIFT, + DMAC2_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->dst_size, + DMAC2_CHCFG_n_DDS_SHIFT, + DMAC2_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + trans_info->src_size, + DMAC2_CHCFG_n_SDS_SHIFT, + DMAC2_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DMS_SHIFT, + DMAC2_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSEL_SHIFT, + DMAC2_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_SBE_SHIFT, + DMAC2_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_DEM_SHIFT, + DMAC2_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_REN_SHIFT, + DMAC2_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_RSW_SHIFT, + DMAC2_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_TM_SHIFT, + DMAC2_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 2, + DMAC2_CHCFG_n_SEL_SHIFT, + DMAC2_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 1, + DMAC2_CHCFG_n_HIEN_SHIFT, + DMAC2_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + 0, + DMAC2_CHCFG_n_LOEN_SHIFT, + DMAC2_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC2_CHCFG_n_AM_SHIFT, + DMAC2_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC2_CHCFG_n_LVL_SHIFT, + DMAC2_CHCFG_n_LVL); + if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC2.CHCFG_n, + req_direction, + DMAC2_CHCFG_n_REQD_SHIFT, + DMAC2_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC23_DMARS_CH2_RID_SHIFT, + DMAC23_DMARS_CH2_RID); + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC23_DMARS_CH2_MID_SHIFT, + DMAC23_DMARS_CH2_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC2_Open +* Description : Enables DMAC channel 2 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb0_function_DMAC2_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n, + DMAC2_CHCTRL_n_SWRST_SHIFT, + DMAC2_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_SETEN_SHIFT, + DMAC2_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_STG_SHIFT, + DMAC2_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC2_Close +* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb0_function_DMAC2_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n, + 1, + DMAC2_CHCTRL_n_CLREN_SHIFT, + DMAC2_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_TACT_SHIFT, + DMAC2_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_EN_SHIFT, + DMAC2_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC2.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb0_function_DMAC2_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 2 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 2 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n, + DMAC2_CHSTAT_n_SR_SHIFT, + DMAC2_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC2.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC2.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC2.N1TB_n = count; /* Total transfer byte count */ + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c new file mode 100644 index 0000000000..5449f60c70 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c @@ -0,0 +1,762 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_function_userdef.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_typedefs.h" +#include "iodefine.h" +#include "devdrv_usb_function_api.h" +#include "usb0_function_dmacdrv.h" /* common DMAC driver for USB */ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DUMMY_ACCESS OSTM0CNT + +/* #define CACHE_WRITEBACK */ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int32_t io_cwb(unsigned long start, unsigned long end); + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb0_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void usb0_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void Userdef_USB_usb0_function_delay_10us_2(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_d0fifo_dmaintid +* Description : get D0FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D0FIFO DMA Interrupt ID +*******************************************************************************/ +IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid (void) +{ +#if 0 + return DMAINT1_IRQn; +#else + return 0xFFFF; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_d1fifo_dmaintid +* Description : get D1FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D1FIFO DMA Interrupt ID +*******************************************************************************/ +IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid (void) +{ +#if 0 + return DMAINT1_IRQn; +#else + return 0xFFFF; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_attach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_attach (void) +{ + printf("\n"); + printf("channel 0 attach device\n"); + printf("\n"); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_detach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_detach (void) +{ + printf("\n"); + printf("channel 0 detach device\n"); + printf("\n"); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_delay_1ms +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_delay_1ms (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* + * Wait 1ms (Please change for your MCU). + */ + for (i = 0; i < 1440; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_delay_xms +* Description : Wait for the software in the period of time specified by the +* : argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t msec ; Wait Time (msec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_delay_xms (uint32_t msec) +{ + volatile unsigned short i; + + for (i = 0; i < msec; ++i) + { + Userdef_USB_usb0_function_delay_1ms(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_delay_10us +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t usec ; Wait Time(x 10usec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_delay_10us (uint32_t usec) +{ + volatile int i; + + /* Wait 10us (Please change for your MCU) */ + for (i = 0; i < usec; ++i) + { + Userdef_USB_usb0_function_delay_10us_2(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_delay_10us_2 +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void Userdef_USB_usb0_function_delay_10us_2 (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 1us (Please change for your MCU) */ + for (i = 0; i < 14; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_delay_500ns +* Description : Wait for software for 500ns. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_delay_500ns (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 500ns (Please change for your MCU) */ + /* Wait 500ns I clock 266MHz */ + tmp = DUMMY_ACCESS; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_start_dma +* Description : Enables DMA transfer on the information specified by the argument. +* : Set DMAC register by this function to enable DMA transfer. +* : After executing this function, USB module is set to start DMA +* : transfer. DMA transfer should not wait for DMA transfer complete. +* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter +* : typedef struct{ +* : uint32_t fifo; FIFO for using +* : uint32_t buffer; Start address of transfer source/destination +* : uint32_t bytes; Transfer size(Byte) +* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) +* : uint32_t size; DMA transfer size +* : } USB_FUNCTION_DMA_t; +* : uint16_t dfacc ; 0 : cycle steal mode +* : 1 : 16byte continuous mode +* : 2 : 32byte continuous mode +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb0_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc) +{ + uint32_t trncount; + uint32_t src; + uint32_t dst; + uint32_t size; + uint32_t dir; +#ifdef CACHE_WRITEBACK + uint32_t ptr; +#endif + + trncount = dma->bytes; + dir = dma->dir; + + if (dir == USB_FUNCTION_FIFO2BUF) + { + /* DxFIFO determination */ + dst = dma->buffer; +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + src += 3; /* byte access */ + } + else if (size == 1) + { + src += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB200.D1FIFO.UINT32); + } + src += 3; /* byte access */ + } +#endif + } + else + { + /* DxFIFO determination */ + src = dma->buffer; +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + dst += 3; /* byte access */ + } + else if (size == 1) + { + dst += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB200.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB200.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB200.D1FIFO.UINT32); + } + dst += 3; /* byte access */ + } +#endif + } + +#ifdef CACHE_WRITEBACK + ptr = (uint32_t)dma->buffer; + + if ((ptr & 0x20000000ul) == 0) + { + io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount); + } +#endif + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + usb0_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); + } + else + { + usb0_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); + } +} + +/******************************************************************************* +* Function Name: usb0_function_enable_dmac0 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } + } +#endif + + if (dir == USB_FUNCTION_FIFO2BUF) + { + request_factor =DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_FUNCTION_BUF2FIFO) + { + request_factor =DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_function_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in + usb0_function_DMAC1_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_function_DMAC1_Open(DMAC_REQ_MODE_PERI); + if (ret != 0) + { + printf("DMAC1 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: usb0_function_enable_dmac1 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb0_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } + } +#endif + + if (dir == USB_FUNCTION_FIFO2BUF) + { + request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_FUNCTION_BUF2FIFO) + { + request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb0_function_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in + usb0_function_DMAC1_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb0_function_DMAC2_Open(DMAC_REQ_MODE_PERI); + if (ret != 0) + { + printf("DMAC2 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_stop_dma0 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D0_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_function_stop_dma0 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_function_DMAC1_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb0_function_stop_dma1 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D1_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb0_function_stop_dma1 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb0_function_DMAC2_Close(&remain); + + return remain; +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h new file mode 100644 index 0000000000..fc940c4773 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +#ifndef USB_FUNCTION_SETTING_H +#define USB_FUNCTION_SETTING_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_FUNCTION_CH 0 +#define USB_FUNCTION_HISPEED 1 + +#if (USB_FUNCTION_CH == 0) +#include "usb0_function.h" +#define USB20X USB200 +#define USBIX_IRQn USBI0_IRQn +#define g_usbx_function_bit_set g_usb0_function_bit_set +#define g_usbx_function_PipeDataSize g_usb0_function_PipeDataSize +#define g_usbx_function_data_count g_usb0_function_data_count +#define g_usbx_function_PipeTbl g_usb0_function_PipeTbl +#define g_usbx_function_DmaStatus g_usb0_function_DmaStatus +#define g_usbx_function_pipecfg g_usb0_function_pipecfg +#define g_usbx_function_pipe_status g_usb0_function_pipe_status +#define g_usbx_function_data_pointer g_usb0_function_data_pointer +#define g_usbx_function_pipebuf g_usb0_function_pipebuf +#define g_usbx_function_pipemaxp g_usb0_function_pipemaxp +#define g_usbx_function_pipeperi g_usb0_function_pipeperi +#define g_usbx_function_TestModeFlag g_usb0_function_TestModeFlag +#define usbx_function_BRDYInterruptPIPE0 usb0_function_BRDYInterruptPIPE0 +#define usbx_function_BRDYInterrupt usb0_function_BRDYInterrupt +#define usbx_function_NRDYInterruptPIPE0 usb0_function_NRDYInterruptPIPE0 +#define usbx_function_NRDYInterrupt usb0_function_NRDYInterrupt +#define usbx_function_BEMPInterruptPIPE0 usb0_function_BEMPInterruptPIPE0 +#define usbx_function_BEMPInterrupt usb0_function_BEMPInterrupt +#define usbx_function_read_buffer_c usb0_function_read_buffer_c +#define usbx_function_set_pid_buf usb0_function_set_pid_buf +#define usbx_function_disable_brdy_int usb0_function_disable_brdy_int +#define usbx_function_set_pid_stall usb0_function_set_pid_stall +#define usbx_function_dma_interrupt_d0fifo usb0_function_dma_interrupt_d0fifo +#define usbx_function_read_dma usb0_function_read_dma +#define usbx_function_dma_interrupt_d1fifo usb0_function_dma_interrupt_d1fifo +#define usbx_function_write_buffer usb0_function_write_buffer +#define usbx_function_set_pid_nak usb0_function_set_pid_nak +#define usbx_function_get_mbw usb0_function_get_mbw +#define usbx_function_set_curpipe usb0_function_set_curpipe +#define usbx_function_aclrm usb0_function_aclrm +#define usbx_function_enable_nrdy_int usb0_function_enable_nrdy_int +#define usbx_function_enable_brdy_int usb0_function_enable_brdy_int +#define usbx_function_get_pid usb0_function_get_pid +#define usbx_function_get_inbuf usb0_function_get_inbuf +#define usbx_function_disable_bemp_int usb0_function_disable_bemp_int +#define usbx_function_EpToPipe usb0_function_EpToPipe +#define usbx_function_clear_pipe_tbl usb0_function_clear_pipe_tbl +#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb0_function_d0fifo_dmaintid +#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb0_function_d1fifo_dmaintid +#define usbx_function_reset_module usb0_function_reset_module +#define usbx_function_init_status usb0_function_init_status +#define usbx_function_InitModule usb0_function_InitModule +#define usbx_function_clear_alt usb0_function_clear_alt +#define usbx_function_set_sqclr usb0_function_set_sqclr +#define usbx_api_function_CtrlWriteStart usb0_api_function_CtrlWriteStart +#define usbx_api_function_CtrlReadStart usb0_api_function_CtrlReadStart +#define usbx_function_write_buffer_c usb0_function_write_buffer_c +#define usbx_api_function_check_pipe_status usb0_api_function_check_pipe_status +#define usbx_api_function_set_pid_nak usb0_api_function_set_pid_nak +#define usbx_api_function_clear_pipe_status usb0_api_function_clear_pipe_status +#define usbx_api_function_start_receive_transfer usb0_api_function_start_receive_transfer +#define usbx_function_read_buffer usb0_function_read_buffer +#define usbx_api_function_start_send_transfer usb0_api_function_start_send_transfer +#define usbx_function_stop_transfer usb0_function_stop_transfer +#define usbx_function_clear_pid_stall usb0_function_clear_pid_stall +#define usbx_function_CheckVBUStaus usb0_function_CheckVBUStaus +#define usbx_function_USB_FUNCTION_Attach usb0_function_USB_FUNCTION_Attach +#define usbx_function_USB_FUNCTION_Detach usb0_function_USB_FUNCTION_Detach +#define usbx_function_is_hispeed usb0_function_is_hispeed +#define usbx_function_ResetDescriptor usb0_function_ResetDescriptor +#define usbx_function_USB_FUNCTION_Suspend usb0_function_USB_FUNCTION_Suspend +#define usbx_function_USB_FUNCTION_TestMode usb0_function_USB_FUNCTION_TestMode +#else +#include "usb1_function.h" +#define USB20X USB201 +#define USBIX_IRQn USBI1_IRQn +#define g_usbx_function_bit_set g_usb1_function_bit_set +#define g_usbx_function_PipeDataSize g_usb1_function_PipeDataSize +#define g_usbx_function_data_count g_usb1_function_data_count +#define g_usbx_function_PipeTbl g_usb1_function_PipeTbl +#define g_usbx_function_DmaStatus g_usb1_function_DmaStatus +#define g_usbx_function_pipecfg g_usb1_function_pipecfg +#define g_usbx_function_pipe_status g_usb1_function_pipe_status +#define g_usbx_function_data_pointer g_usb1_function_data_pointer +#define g_usbx_function_pipebuf g_usb1_function_pipebuf +#define g_usbx_function_pipemaxp g_usb1_function_pipemaxp +#define g_usbx_function_pipeperi g_usb1_function_pipeperi +#define g_usbx_function_TestModeFlag g_usb1_function_TestModeFlag +#define usbx_function_BRDYInterruptPIPE0 usb1_function_BRDYInterruptPIPE0 +#define usbx_function_BRDYInterrupt usb1_function_BRDYInterrupt +#define usbx_function_NRDYInterruptPIPE0 usb1_function_NRDYInterruptPIPE0 +#define usbx_function_NRDYInterrupt usb1_function_NRDYInterrupt +#define usbx_function_BEMPInterruptPIPE0 usb1_function_BEMPInterruptPIPE0 +#define usbx_function_BEMPInterrupt usb1_function_BEMPInterrupt +#define usbx_function_read_buffer_c usb1_function_read_buffer_c +#define usbx_function_set_pid_buf usb1_function_set_pid_buf +#define usbx_function_disable_brdy_int usb1_function_disable_brdy_int +#define usbx_function_set_pid_stall usb1_function_set_pid_stall +#define usbx_function_dma_interrupt_d0fifo usb1_function_dma_interrupt_d0fifo +#define usbx_function_read_dma usb1_function_read_dma +#define usbx_function_dma_interrupt_d1fifo usb1_function_dma_interrupt_d1fifo +#define usbx_function_write_buffer usb1_function_write_buffer +#define usbx_function_set_pid_nak usb1_function_set_pid_nak +#define usbx_function_get_mbw usb1_function_get_mbw +#define usbx_function_set_curpipe usb1_function_set_curpipe +#define usbx_function_aclrm usb1_function_aclrm +#define usbx_function_enable_nrdy_int usb1_function_enable_nrdy_int +#define usbx_function_enable_brdy_int usb1_function_enable_brdy_int +#define usbx_function_get_pid usb1_function_get_pid +#define usbx_function_get_inbuf usb1_function_get_inbuf +#define usbx_function_disable_bemp_int usb1_function_disable_bemp_int +#define usbx_function_EpToPipe usb1_function_EpToPipe +#define usbx_function_clear_pipe_tbl usb1_function_clear_pipe_tbl +#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb1_function_d0fifo_dmaintid +#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb1_function_d1fifo_dmaintid +#define usbx_function_reset_module usb1_function_reset_module +#define usbx_function_init_status usb1_function_init_status +#define usbx_function_InitModule usb1_function_InitModule +#define usbx_function_clear_alt usb1_function_clear_alt +#define usbx_function_set_sqclr usb1_function_set_sqclr +#define usbx_api_function_CtrlWriteStart usb1_api_function_CtrlWriteStart +#define usbx_api_function_CtrlReadStart usb1_api_function_CtrlReadStart +#define usbx_function_write_buffer_c usb1_function_write_buffer_c +#define usbx_api_function_check_pipe_status usb1_api_function_check_pipe_status +#define usbx_api_function_set_pid_nak usb1_api_function_set_pid_nak +#define usbx_api_function_clear_pipe_status usb1_api_function_clear_pipe_status +#define usbx_api_function_start_receive_transfer usb1_api_function_start_receive_transfer +#define usbx_function_read_buffer usb1_function_read_buffer +#define usbx_api_function_start_send_transfer usb1_api_function_start_send_transfer +#define usbx_function_stop_transfer usb1_function_stop_transfer +#define usbx_function_clear_pid_stall usb1_function_clear_pid_stall +#define usbx_function_CheckVBUStaus usb1_function_CheckVBUStaus +#define usbx_function_USB_FUNCTION_Attach usb1_function_USB_FUNCTION_Attach +#define usbx_function_USB_FUNCTION_Detach usb1_function_USB_FUNCTION_Detach +#define usbx_function_is_hispeed usb1_function_is_hispeed +#define usbx_function_ResetDescriptor usb1_function_ResetDescriptor +#define usbx_function_USB_FUNCTION_Suspend usb1_function_USB_FUNCTION_Suspend +#define usbx_function_USB_FUNCTION_TestMode usb1_function_USB_FUNCTION_TestMode +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* USB_FUNCTION_SETTING_H */ diff --git a/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp b/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp index 328c21daa2..5eee82a644 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp @@ -38,10 +38,10 @@ extern "C" } #include "USBHAL.h" #include "devdrv_usb_function_api.h" -#include "usb0_function.h" #include "usb_iobitmask.h" #include "rza_io_regrw.h" #include "USBDevice_Types.h" +#include "usb_function_setting.h" /*************************************************************************/ @@ -160,7 +160,7 @@ static uint16_t int_level; /* initerrupt level */ static uint16_t clock_mode; /* input clock selector */ static uint16_t mode; /* USB speed (HIGH/FULL) */ -//static DigitalOut *usb0_en; +//static DigitalOut *usbx_en; static uint16_t EP0_read_status; static uint16_t EPx_read_status; @@ -175,22 +175,22 @@ volatile static uint16_t recv_error; /*************************************************************************/ /* prototypes for C */ extern "C" { - void usb0_function_BRDYInterruptPIPE0 (uint16_t status, uint16_t intenb, + void usbx_function_BRDYInterruptPIPE0 (uint16_t status, uint16_t intenb, USBHAL *object, void (USBHAL::*EP0func)(void)); - void usb0_function_BRDYInterrupt (uint16_t status, uint16_t intenb, + void usbx_function_BRDYInterrupt (uint16_t status, uint16_t intenb, USBHAL *object, bool (USBHAL::*epCallback[])(void)); - void usb0_function_NRDYInterruptPIPE0(uint16_t status, uint16_t intenb, + void usbx_function_NRDYInterruptPIPE0(uint16_t status, uint16_t intenb, USBHAL *object, void (USBHAL::*EP0func)(void)); - void usb0_function_NRDYInterrupt (uint16_t status, uint16_t intenb, + void usbx_function_NRDYInterrupt (uint16_t status, uint16_t intenb, USBHAL *object, bool (USBHAL::*epCallback[])(void)); - void usb0_function_BEMPInterruptPIPE0(uint16_t status, uint16_t intenb, + void usbx_function_BEMPInterruptPIPE0(uint16_t status, uint16_t intenb, USBHAL *object, void (USBHAL::*EP0func)(void)); - void usb0_function_BEMPInterrupt (uint16_t status, uint16_t intenb, + void usbx_function_BEMPInterrupt (uint16_t status, uint16_t intenb, USBHAL *object, bool (USBHAL::*epCallback[])(void)); } @@ -199,14 +199,14 @@ extern "C" { /* macros */ /****************************************************************************** - * Function Name: usb0_function_BRDYInterruptPIPE0 + * Function Name: usbx_function_BRDYInterruptPIPE0 * Description : Executes BRDY interrupt for pipe0. * Arguments : uint16_t status ; BRDYSTS Register Value * : uint16_t intenb ; BRDYENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_BRDYInterruptPIPE0 ( + void usbx_function_BRDYInterruptPIPE0 ( uint16_t status, uint16_t intenb, USBHAL *object, @@ -216,34 +216,34 @@ extern "C" { volatile uint16_t dumy_sts; uint16_t read_status; - USB200.BRDYSTS = - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + USB20X.BRDYSTS = + (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0]; RZA_IO_RegWrite_16( - &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, + &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); - g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] = - g_usb0_function_data_count[USB_FUNCTION_PIPE0]; + g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] = + g_usbx_function_data_count[USB_FUNCTION_PIPE0]; - read_status = usb0_function_read_buffer_c(USB_FUNCTION_PIPE0); + read_status = usbx_function_read_buffer_c(USB_FUNCTION_PIPE0); - g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0] -= - g_usb0_function_data_count[USB_FUNCTION_PIPE0]; + g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] -= + g_usbx_function_data_count[USB_FUNCTION_PIPE0]; switch (read_status) { case USB_FUNCTION_READING: /* Continue of data read */ case USB_FUNCTION_READEND: /* End of data read */ /* PID = BUF */ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); + usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); /*callback*/ (object->*EP0func)(); break; case USB_FUNCTION_READSHRT: /* End of data read */ - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0); /* PID = BUF */ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); + usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); /*callback*/ (object->*EP0func)(); @@ -251,10 +251,10 @@ extern "C" { case USB_FUNCTION_READOVER: /* FIFO access error */ /* Buffer Clear */ - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR; + usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0); /* Req Error */ - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); /*callback*/ (object->*EP0func)(); @@ -262,26 +262,26 @@ extern "C" { case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ default: - usb0_function_disable_brdy_int(USB_FUNCTION_PIPE0); + usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0); /* Req Error */ - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); break; } /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BRDYSTS; + dumy_sts = USB20X.BRDYSTS; } } /****************************************************************************** - * Function Name: usb0_function_BRDYInterrupt + * Function Name: usbx_function_BRDYInterrupt * Description : Executes BRDY interrupt uxclude pipe0. * Arguments : uint16_t status ; BRDYSTS Register Value * : uint16_t intenb ; BRDYENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_BRDYInterrupt( + void usbx_function_BRDYInterrupt( uint16_t status, uint16_t intenb, USBHAL *object, @@ -291,7 +291,7 @@ extern "C" { volatile uint16_t dumy_sts; /************************************************************** - * Function Name: usb0_function_brdy_int + * Function Name: usbx_function_brdy_int * Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). * : According to the pipe that interrupt is generated in, * : reads/writes buffer allocated in the pipe. @@ -303,59 +303,59 @@ extern "C" { * : uint16_t Int_enbl ; BRDYENB Register Value * Return Value : none *************************************************************/ - /* copied from usb0_function_intrn.c */ + /* copied from usbx_function_intrn.c */ uint32_t int_sense = 0; uint16_t pipe; uint16_t pipebit; uint16_t ep; for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { - pipebit = g_usb0_function_bit_set[pipe]; + pipebit = g_usbx_function_bit_set[pipe]; if ((status & pipebit) && (intenb & pipebit)) { - USB200.BRDYSTS = (uint16_t)~pipebit; - USB200.BEMPSTS = (uint16_t)~pipebit; + USB20X.BRDYSTS = (uint16_t)~pipebit; + USB20X.BEMPSTS = (uint16_t)~pipebit; - switch (g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { + switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { case USB_FUNCTION_D0FIFO_DMA: - if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) { + if (g_usbx_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) { /*now, DMA is not supported*/ - usb0_function_dma_interrupt_d0fifo(int_sense); + usbx_function_dma_interrupt_d0fifo(int_sense); } if (RZA_IO_RegRead_16( - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { + &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { /*now, DMA is not supported*/ - usb0_function_read_dma(pipe); - usb0_function_disable_brdy_int(pipe); + usbx_function_read_dma(pipe); + usbx_function_disable_brdy_int(pipe); } else { - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; } break; case USB_FUNCTION_D1FIFO_DMA: - if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) { + if (g_usbx_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) { /*now, DMA is not supported*/ - usb0_function_dma_interrupt_d1fifo(int_sense); + usbx_function_dma_interrupt_d1fifo(int_sense); } if (RZA_IO_RegRead_16( - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { + &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) { /*now, DMA is not supported*/ - usb0_function_read_dma(pipe); - usb0_function_disable_brdy_int(pipe); + usbx_function_read_dma(pipe); + usbx_function_disable_brdy_int(pipe); } else { - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; } break; default: - ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; ep <<= 1; if (RZA_IO_RegRead_16( - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { /* read */ EPx_read_status = DEVDRV_USBF_PIPE_WAIT; (object->*(epCallback[ep - 2])) (); @@ -365,26 +365,26 @@ extern "C" { EPx_read_status = DEVDRV_USBF_PIPE_WAIT; (object->*(epCallback[ep - 2 + 1])) (); EPx_read_status = DEVDRV_USBF_PIPE_DONE; - usb0_function_write_buffer(pipe); + usbx_function_write_buffer(pipe); } } } } /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BRDYSTS; + dumy_sts = USB20X.BRDYSTS; } } /****************************************************************************** - * Function Name: usb0_function_NRDYInterruptPIPE0 + * Function Name: usbx_function_NRDYInterruptPIPE0 * Description : Executes NRDY interrupt for pipe0. * Arguments : uint16_t status ; NRDYSTS Register Value * : uint16_t intenb ; NRDYENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_NRDYInterruptPIPE0( + void usbx_function_NRDYInterruptPIPE0( uint16_t status, uint16_t intenb, USBHAL *object, @@ -393,24 +393,24 @@ extern "C" { { volatile uint16_t dumy_sts; - USB200.NRDYSTS = - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + USB20X.NRDYSTS = + (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0]; /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.NRDYSTS; + dumy_sts = USB20X.NRDYSTS; } } /****************************************************************************** - * Function Name: usb0_function_NRDYInterrupt + * Function Name: usbx_function_NRDYInterrupt * Description : Executes NRDY interrupt exclude pipe0. * Arguments : uint16_t status ; NRDYSTS Register Value * : uint16_t intenb ; NRDYENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_NRDYInterrupt( + void usbx_function_NRDYInterrupt( uint16_t status, uint16_t intenb, USBHAL *object, @@ -420,7 +420,7 @@ extern "C" { volatile uint16_t dumy_sts; /************************************************************** - * Function Name: usb0_function_nrdy_int + * Function Name: usbx_function_nrdy_int * Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9). * : Checks NRDY interrupt cause by PID. When the cause if STALL, * : regards the pipe state as STALL and ends the processing. @@ -433,7 +433,7 @@ extern "C" { * : uint16_t int_enb ; NRDYENB Register Value * Return Value : none *************************************************************/ - /* copied from usb0_function_intrn.c */ + /* copied from usbx_function_intrn.c */ #if 0 uint16_t usefifo; #endif @@ -448,72 +448,72 @@ extern "C" { bitcheck = (uint16_t)(status & intenb); - USB200.NRDYSTS = (uint16_t)~status; + USB20X.NRDYSTS = (uint16_t)~status; - if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) { + if (RZA_IO_RegRead_16(&USB20X.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) { /* USB HOST */ /* not support */ } else { /* USB Function */ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { - if ((bitcheck&g_usb0_function_bit_set[pipe]) != g_usb0_function_bit_set[pipe]) { + if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) { continue; } - if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_WAIT) { + if (g_usbx_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_WAIT) { continue; } #if 0 - usb0_function_set_pid_nak(pipe); + usbx_function_set_pid_nak(pipe); - size = (uint32_t)g_usb0_function_data_count[pipe]; - mbw = usb0_function_get_mbw( - size, (uint32_t)g_usb0_function_data_pointer[pipe]); + size = (uint32_t)g_usbx_function_data_count[pipe]; + mbw = usbx_function_get_mbw( + size, (uint32_t)g_usbx_function_data_pointer[pipe]); - usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + usefifo = (uint16_t)(g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); switch (usefifo) { case USB_FUNCTION_D0FIFO_USE: - usb0_function_set_curpipe( + usbx_function_set_curpipe( pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); - USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; + USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR; break; case USB_FUNCTION_D1FIFO_USE: - usb0_function_set_curpipe( + usbx_function_set_curpipe( pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); - USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; + USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR; break; default: - usb0_function_set_curpipe( + usbx_function_set_curpipe( pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw); - USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; + USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR; break; } - usb0_function_aclrm(pipe); + usbx_function_aclrm(pipe); - usb0_function_enable_nrdy_int(pipe); - usb0_function_enable_brdy_int(pipe); + usbx_function_enable_nrdy_int(pipe); + usbx_function_enable_brdy_int(pipe); - usb0_function_set_pid_buf(pipe); + usbx_function_set_pid_buf(pipe); #endif - pid = usb0_function_get_pid(pipe); + pid = usbx_function_get_pid(pipe); if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; } else { - usb0_function_set_pid_buf(pipe); + usbx_function_set_pid_buf(pipe); } - ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; ep <<= 1; if (RZA_IO_RegRead_16( - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { /* read */ __NOP(); } else { @@ -524,19 +524,19 @@ extern "C" { } /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.NRDYSTS; + dumy_sts = USB20X.NRDYSTS; } } /****************************************************************************** - * Function Name: usb0_function_BEMPInterruptPIPE0 + * Function Name: usbx_function_BEMPInterruptPIPE0 * Description : Executes BEMP interrupt for pipe0. * Arguments : uint16_t status ; BEMPSTS Register Value * : uint16_t intenb ; BEMPENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_BEMPInterruptPIPE0( + void usbx_function_BEMPInterruptPIPE0( uint16_t status, uint16_t intenb, USBHAL *object, @@ -545,30 +545,30 @@ extern "C" { { volatile uint16_t dumy_sts; - USB200.BEMPSTS = - (uint16_t)~g_usb0_function_bit_set[USB_FUNCTION_PIPE0]; + USB20X.BEMPSTS = + (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0]; RZA_IO_RegWrite_16( - &USB200.CFIFOSEL, USB_FUNCTION_PIPE0, + &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); - /*usb0_function_write_buffer_c(USB_FUNCTION_PIPE0);*/ + /*usbx_function_write_buffer_c(USB_FUNCTION_PIPE0);*/ (object->*EP0func)(); /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BEMPSTS; + dumy_sts = USB20X.BEMPSTS; } } /****************************************************************************** - * Function Name: usb0_function_BEMPInterrupt + * Function Name: usbx_function_BEMPInterrupt * Description : Executes BEMP interrupt exclude pipe0. * Arguments : uint16_t status ; BEMPSTS Register Value * : uint16_t intenb ; BEMPENB Register Value * Return Value : none *****************************************************************************/ extern "C" { - void usb0_function_BEMPInterrupt( + void usbx_function_BEMPInterrupt( uint16_t status, uint16_t intenb, USBHAL *object, @@ -578,13 +578,13 @@ extern "C" { volatile uint16_t dumy_sts; /************************************************************** - * Function Name: usb0_function_bemp_int + * Function Name: usbx_function_bemp_int * Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9). * Arguments : uint16_t status ; BEMPSTS Register Value * : uint16_t intenb ; BEMPENB Register Value * Return Value : none *************************************************************/ - /* copied from usb0_function_intrn.c */ + /* copied from usbx_function_intrn.c */ uint16_t pid; uint16_t pipe; uint16_t bitcheck; @@ -593,28 +593,28 @@ extern "C" { bitcheck = (uint16_t)(status & intenb); - USB200.BEMPSTS = (uint16_t)~status; + USB20X.BEMPSTS = (uint16_t)~status; for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) { - if ((bitcheck&g_usb0_function_bit_set[pipe]) != g_usb0_function_bit_set[pipe]) { + if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) { continue; } - pid = usb0_function_get_pid(pipe); + pid = usbx_function_get_pid(pipe); if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) { - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; } else { - inbuf = usb0_function_get_inbuf(pipe); + inbuf = usbx_function_get_inbuf(pipe); if (inbuf == 0) { - usb0_function_disable_bemp_int(pipe); - usb0_function_set_pid_nak(pipe); - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + usbx_function_disable_bemp_int(pipe); + usbx_function_set_pid_nak(pipe); + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; - switch (g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { + switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) { case USB_FUNCTION_D0FIFO_DMA: /*now, DMA is not supported*/ break; @@ -624,10 +624,10 @@ extern "C" { break; default: - ep = (g_usb0_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; + ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT; ep <<= 1; if (RZA_IO_RegRead_16( - &g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { + &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) { /* read */ __NOP(); } else { @@ -642,7 +642,7 @@ extern "C" { } /* Three dummy reads for clearing interrupt requests */ - dumy_sts = USB200.BEMPSTS; + dumy_sts = USB20X.BEMPSTS; } } @@ -653,28 +653,28 @@ extern "C" { * Return Value : number of pipe *****************************************************************************/ /*EP2PIPE converter is for pipe1, pipe3 and pipe6 only.*/ -#define EP2PIPE(endpoint) ((uint32_t)usb0_function_EpToPipe(endpoint)) +#define EP2PIPE(endpoint) ((uint32_t)usbx_function_EpToPipe(endpoint)) /****************************************************************************** - * Function Name: usb0_function_save_request + * Function Name: usbx_function_save_request * Description : Retains the USB request information in variables. * Arguments : none * Return Value : none *****************************************************************************/ -#define usb0_function_save_request() \ +#define usbx_function_save_request() \ { \ uint16_t *bufO = &setup_buffer[0]; \ \ - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVALID; \ + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVALID; \ /*data[0] <= bmRequest, data[1] <= bmRequestType */ \ - *bufO++ = USB200.USBREQ; \ + *bufO++ = USB20X.USBREQ; \ /*data[2] data[3] <= wValue*/ \ - *bufO++ = USB200.USBVAL; \ + *bufO++ = USB20X.USBVAL; \ /*data[4] data[5] <= wIndex*/ \ - *bufO++ = USB200.USBINDX; \ + *bufO++ = USB20X.USBINDX; \ /*data[6] data[6] <= wIndex*/ \ - *bufO++ = USB200.USBLENG; \ + *bufO++ = USB20X.USBLENG; \ } @@ -687,16 +687,16 @@ extern "C" { USBHAL::USBHAL(void) { /* ---- P4_1 : P4_1 (USB0_EN for GR-PEACH) ---- */ - //usb0_en = new DigitalOut(P4_1, 1); + //usbx_en = new DigitalOut(P4_1, 1); /* some constants */ - int_id = USBI0_IRQn; + int_id = USBIX_IRQn; int_level = ( 2 << 3 ); clock_mode = USBFCLOCK_X1_48MHZ; -#if 1 - mode = USB_FUNCTION_HIGH_SPEED; -#else +#if (USB_FUNCTION_HISPEED == 0) mode = USB_FUNCTION_FULL_SPEED; +#else + mode = USB_FUNCTION_HIGH_SPEED; #endif EP0_read_status = DEVDRV_USBF_WRITEEND; EPx_read_status = DEVDRV_USBF_PIPE_DONE; @@ -740,20 +740,24 @@ USBHAL::USBHAL(void) instance = this; /* Clear pipe table */ - usb0_function_clear_pipe_tbl(); + usbx_function_clear_pipe_tbl(); /****************************************************************************** - * Function Name: usb0_api_function_init + * Function Name: usbx_api_function_init * Description : Initializes the USB module in the USB function mode. *****************************************************************************/ /* The clock of USB0 modules is permitted */ +#if (USB_FUNCTION_CH == 0) CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71); +#else + CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71 | CPG_STBCR7_MSTP70); +#endif volatile uint8_t dummy8; dummy8 = CPG.STBCR7; { /****************************************************************************** - * Function Name: usb0_function_setting_interrupt + * Function Name: usbx_function_setting_interrupt * Description : Sets the USB module interrupt level. *****************************************************************************/ #if 0 /*DMA is not supported*/ @@ -766,18 +770,18 @@ USBHAL::USBHAL(void) GIC_EnableIRQ(int_id); #if 0 /*DMA is not supported*/ - d0fifo_dmaintid = Userdef_USB_usb0_function_d0fifo_dmaintid(); + d0fifo_dmaintid = Userdef_USB_usbx_function_d0fifo_dmaintid(); if (d0fifo_dmaintid != 0xFFFF) { - InterruptHandlerRegister(d0fifo_dmaintid, usb0_function_dma_interrupt_d0fifo); + InterruptHandlerRegister(d0fifo_dmaintid, usbx_function_dma_interrupt_d0fifo); GIC_SetPriority(d0fifo_dmaintid, int_level); GIC_EnableIRQ(d0fifo_dmaintid); } #endif #if 0 /*DMA is not supported*/ - d1fifo_dmaintid = Userdef_USB_usb0_function_d1fifo_dmaintid(); + d1fifo_dmaintid = Userdef_USB_usbx_function_d1fifo_dmaintid(); if (d1fifo_dmaintid != 0xFFFF) { - InterruptHandlerRegister(d1fifo_dmaintid, usb0_function_dma_interrupt_d1fifo); + InterruptHandlerRegister(d1fifo_dmaintid, usbx_function_dma_interrupt_d1fifo); GIC_SetPriority(d1fifo_dmaintid, int_level); GIC_EnableIRQ(d1fifo_dmaintid); } @@ -786,20 +790,20 @@ USBHAL::USBHAL(void) } /* reset USB module with setting tranciever and HSE=1 */ - usb0_function_reset_module(clock_mode); + usbx_function_reset_module(clock_mode); /* clear variables */ - usb0_function_init_status(); + usbx_function_init_status(); /* select USB Function and Interrupt Enable */ /* Detect USB Device to attach or detach */ - usb0_function_InitModule(mode); + usbx_function_InitModule(mode); { uint16_t buf; - buf = USB200.INTENB0; + buf = USB20X.INTENB0; buf |= USB_INTENB0_SOFE; - USB200.INTENB0 = buf; + USB20X.INTENB0 = buf; } } @@ -811,7 +815,7 @@ USBHAL::~USBHAL(void) /* Unregisters interrupt function and priority */ InterruptHandlerRegister( int_id, (uint32_t)NULL ); - //usb0_en = NULL; + //usbx_en = NULL; instance = NULL; } @@ -819,7 +823,7 @@ USBHAL::~USBHAL(void) void USBHAL::connect(void) { /* Activates USB0_EN */ - //(*usb0_en) = 0; + //(*usbx_en) = 0; } @@ -827,7 +831,7 @@ void USBHAL::connect(void) void USBHAL::disconnect(void) { /* Deactivates USB0_EN */ - //(*usb0_en) = 1; + //(*usbx_en) = 1; } @@ -835,8 +839,8 @@ void USBHAL::disconnect(void) void USBHAL::configureDevice(void) { /*The pipes set up in USBHAL::realiseEndpoint*/ - /*usb0_function_clear_alt();*/ /* Alternate setting clear */ - /*usb0_function_set_pid_buf(USB_FUNCTION_PIPE0);*/ + /*usbx_function_clear_alt();*/ /* Alternate setting clear */ + /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/ } @@ -844,8 +848,8 @@ void USBHAL::configureDevice(void) void USBHAL::unconfigureDevice(void) { /* The Interface would be managed by USBDevice */ - /*usb0_function_clear_alt();*/ /* Alternate setting clear */ - /*usb0_function_set_pid_buf(USB_FUNCTION_PIPE0);*/ + /*usbx_function_clear_alt();*/ /* Alternate setting clear */ + /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/ } @@ -853,9 +857,9 @@ void USBHAL::unconfigureDevice(void) void USBHAL::setAddress(uint8_t address) { if (address <= 127) { - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); /* OK */ + usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); /* OK */ } else { - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); /* Not Spec */ + usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); /* Not Spec */ } } @@ -882,7 +886,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag pipe = ((cfg->pipesel & USB_PIPESEL_PIPESEL) >> USB_PIPESEL_PIPESEL_SHIFT); - g_usb0_function_PipeTbl[ pipe ] = (uint16_t)(endpoint | ((cfg->pipesel & USB_FUNCTION_FIFO_USE) << 0)); + g_usbx_function_PipeTbl[ pipe ] = (uint16_t)(endpoint | ((cfg->pipesel & USB_FUNCTION_FIFO_USE) << 0)); /* There are maintenance routine of SHTNAK and BFRE bits * in original sample program. This sample is not @@ -890,50 +894,50 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag * you want it. */ /* Interrupt Disable */ - buf = USB200.BRDYENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.BRDYENB = buf; - buf = USB200.NRDYENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.NRDYENB = buf; - buf = USB200.BEMPENB; - buf &= (uint16_t)~g_usb0_function_bit_set[pipe]; - USB200.BEMPENB = buf; + buf = USB20X.BRDYENB; + buf &= (uint16_t)~g_usbx_function_bit_set[pipe]; + USB20X.BRDYENB = buf; + buf = USB20X.NRDYENB; + buf &= (uint16_t)~g_usbx_function_bit_set[pipe]; + USB20X.NRDYENB = buf; + buf = USB20X.BEMPENB; + buf &= (uint16_t)~g_usbx_function_bit_set[pipe]; + USB20X.BEMPENB = buf; - usb0_function_set_pid_nak(pipe); + usbx_function_set_pid_nak(pipe); /* CurrentPIPE Clear */ - if (RZA_IO_RegRead_16(&USB200.CFIFOSEL, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE) == pipe) { - RZA_IO_RegWrite_16(&USB200.CFIFOSEL, 0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); + if (RZA_IO_RegRead_16(&USB20X.CFIFOSEL, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE) == pipe) { + RZA_IO_RegWrite_16(&USB20X.CFIFOSEL, 0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE); } - if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) { - RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE); + if (RZA_IO_RegRead_16(&USB20X.D0FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) { + RZA_IO_RegWrite_16(&USB20X.D0FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE); } - if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) { - RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE); + if (RZA_IO_RegRead_16(&USB20X.D1FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) { + RZA_IO_RegWrite_16(&USB20X.D1FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE); } /* PIPE Configuration */ - USB200.PIPESEL = pipe; - USB200.PIPECFG = cfg->pipecfg; - USB200.PIPEBUF = cfg->pipebuf; - USB200.PIPEMAXP = cfg->pipemaxp; - USB200.PIPEPERI = cfg->pipeperi; + USB20X.PIPESEL = pipe; + USB20X.PIPECFG = cfg->pipecfg; + USB20X.PIPEBUF = cfg->pipebuf; + USB20X.PIPEMAXP = cfg->pipemaxp; + USB20X.PIPEPERI = cfg->pipeperi; - g_usb0_function_pipecfg[pipe] = cfg->pipecfg; - g_usb0_function_pipebuf[pipe] = cfg->pipebuf; - g_usb0_function_pipemaxp[pipe] = cfg->pipemaxp; - g_usb0_function_pipeperi[pipe] = cfg->pipeperi; + g_usbx_function_pipecfg[pipe] = cfg->pipecfg; + g_usbx_function_pipebuf[pipe] = cfg->pipebuf; + g_usbx_function_pipemaxp[pipe] = cfg->pipemaxp; + g_usbx_function_pipeperi[pipe] = cfg->pipeperi; /* Buffer Clear */ - usb0_function_set_sqclr(pipe); - usb0_function_aclrm(pipe); + usbx_function_set_sqclr(pipe); + usbx_function_aclrm(pipe); /* init Global */ - g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; - g_usb0_function_PipeDataSize[pipe] = 0; + g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usbx_function_PipeDataSize[pipe] = 0; return true; } @@ -968,16 +972,16 @@ void USBHAL::EP0read(void) buffer = (uint8_t*)(&setup_buffer[4]); size = (MAX_PACKET_SIZE_EP0 / 2) - 8; - usb0_api_function_CtrlWriteStart(size, buffer); + usbx_api_function_CtrlWriteStart(size, buffer); } /*************************************************************************/ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { - memcpy(buffer, (uint8_t*)(&setup_buffer[4]), g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0]); + memcpy(buffer, (uint8_t*)(&setup_buffer[4]), g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0]); - return g_usb0_function_PipeDataSize[USB_FUNCTION_PIPE0]; + return g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0]; } @@ -991,13 +995,13 @@ void USBHAL::EP0write(uint8_t *buffer, uint32_t size) if (EP0_read_status == DEVDRV_USBF_WRITEEND) { /*1st block*/ - EP0_read_status = usb0_api_function_CtrlReadStart(size, buffer); + EP0_read_status = usbx_api_function_CtrlReadStart(size, buffer); } else { /* waits the last transmission */ /*other blocks*/ - g_usb0_function_data_count[ USB_FUNCTION_PIPE0 ] = size; - g_usb0_function_data_pointer [ USB_FUNCTION_PIPE0 ] = buffer; - EP0_read_status = usb0_function_write_buffer_c(USB_FUNCTION_PIPE0); + g_usbx_function_data_count[ USB_FUNCTION_PIPE0 ] = size; + g_usbx_function_data_pointer [ USB_FUNCTION_PIPE0 ] = buffer; + EP0_read_status = usbx_function_write_buffer_c(USB_FUNCTION_PIPE0); } /*max size may be deblocking outside*/ if (size == MAX_PACKET_SIZE_EP0) { @@ -1028,15 +1032,15 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t max_size) uint16_t pipe_status; EP_STATUS status = EP_COMPLETED; - pipe_status = usb0_api_function_check_pipe_status(pipe, &pipe_size); + pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size); switch (pipe_status) { case DEVDRV_USBF_PIPE_IDLE: case DEVDRV_USBF_PIPE_WAIT: - usb0_api_function_set_pid_nak(pipe); - usb0_api_function_clear_pipe_status(pipe); + usbx_api_function_set_pid_nak(pipe); + usbx_api_function_clear_pipe_status(pipe); - usb0_api_function_start_receive_transfer(pipe, max_size, recv_buffer); + usbx_api_function_start_receive_transfer(pipe, max_size, recv_buffer); break; default: @@ -1061,7 +1065,7 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t return status; } - pipe_status = usb0_api_function_check_pipe_status(pipe, bytes_read); + pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read); switch (pipe_status) { case DEVDRV_USBF_PIPE_IDLE: return EP_COMPLETED; @@ -1077,16 +1081,16 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t } /* sets the output buffer and size */ - g_usb0_function_data_pointer[pipe] = buffer; + g_usbx_function_data_pointer[pipe] = buffer; /* receives data from pipe */ - err = usb0_function_read_buffer(pipe); + err = usbx_function_read_buffer(pipe); recv_error = err; switch (err) { case USB_FUNCTION_READEND: case USB_FUNCTION_READSHRT: case USB_FUNCTION_READOVER: - *bytes_read = g_usb0_function_PipeDataSize[pipe]; + *bytes_read = g_usbx_function_PipeDataSize[pipe]; break; case USB_FUNCTION_READING: @@ -1094,7 +1098,7 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t break; } - pipe_status = usb0_api_function_check_pipe_status(pipe, bytes_read); + pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read); switch (pipe_status) { case DEVDRV_USBF_PIPE_DONE: status = EP_COMPLETED; @@ -1122,12 +1126,12 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) uint16_t count; EP_STATUS status = EP_PENDING; - pipe_status = usb0_api_function_check_pipe_status(pipe, &pipe_size); + pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size); /* waits the last transmission */ count = 30000; while ((pipe_status == DEVDRV_USBF_PIPE_WAIT) || (pipe_status == DEVDRV_USBF_PIPE_DONE)) { - pipe_status = usb0_api_function_check_pipe_status(pipe, &pipe_size); + pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size); if( --count == 0 ) { pipe_status = DEVDRV_USBF_PIPE_STALL; break; @@ -1136,7 +1140,7 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) switch (pipe_status) { case DEVDRV_USBF_PIPE_IDLE: - err = usb0_api_function_start_send_transfer(pipe, size, data); + err = usbx_api_function_start_send_transfer(pipe, size, data); switch (err) { /* finish to write */ @@ -1178,7 +1182,7 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) uint16_t pipe_status; EP_STATUS status = EP_PENDING; - pipe_status = usb0_api_function_check_pipe_status(pipe, &pipe_size); + pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size); switch (pipe_status) { case DEVDRV_USBF_PIPE_IDLE: @@ -1190,7 +1194,7 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) break; case DEVDRV_USBF_PIPE_DONE: - usb0_function_stop_transfer(pipe); + usbx_function_stop_transfer(pipe); status = EP_COMPLETED; break; @@ -1215,7 +1219,7 @@ void USBHAL::stallEndpoint(uint8_t endpoint) { uint32_t pipe = EP2PIPE(endpoint); - usb0_function_clear_pid_stall(pipe); + usbx_function_clear_pid_stall(pipe); } @@ -1224,7 +1228,7 @@ void USBHAL::unstallEndpoint(uint8_t endpoint) { uint32_t pipe = EP2PIPE(endpoint); - usb0_function_set_pid_stall( pipe ); + usbx_function_set_pid_stall( pipe ); } @@ -1264,7 +1268,7 @@ void USBHAL::usbisr(void) volatile uint16_t dumy_sts; - int_sts0 = USB200.INTSTS0; + int_sts0 = USB20X.INTSTS0; if (!(int_sts0 & ( USB_FUNCTION_BITVBINT | @@ -1278,81 +1282,81 @@ void USBHAL::usbisr(void) return; } - int_sts1 = USB200.BRDYSTS; - int_sts2 = USB200.NRDYSTS; - int_sts3 = USB200.BEMPSTS; - int_enb0 = USB200.INTENB0; - int_enb2 = USB200.BRDYENB; - int_enb3 = USB200.NRDYENB; - int_enb4 = USB200.BEMPENB; + int_sts1 = USB20X.BRDYSTS; + int_sts2 = USB20X.NRDYSTS; + int_sts3 = USB20X.BEMPSTS; + int_enb0 = USB20X.INTENB0; + int_enb2 = USB20X.BRDYENB; + int_enb3 = USB20X.NRDYENB; + int_enb4 = USB20X.BEMPENB; if ((int_sts0 & USB_FUNCTION_BITRESM) && (int_enb0 & USB_FUNCTION_BITRSME)) { - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITRESM; - RZA_IO_RegWrite_16(&USB200.INTENB0, 0, USB_INTENB0_RSME_SHIFT, USB_INTENB0_RSME); - /*usb0_function_USB_FUNCTION_Resume();*/ + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITRESM; + RZA_IO_RegWrite_16(&USB20X.INTENB0, 0, USB_INTENB0_RSME_SHIFT, USB_INTENB0_RSME); + /*usbx_function_USB_FUNCTION_Resume();*/ suspendStateChanged(1); } else if ( (int_sts0 & USB_FUNCTION_BITVBINT) && (int_enb0 & USB_FUNCTION_BITVBSE)) { - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVBINT; + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVBINT; - if (usb0_function_CheckVBUStaus() == DEVDRV_USBF_ON) { - usb0_function_USB_FUNCTION_Attach(); + if (usbx_function_CheckVBUStaus() == DEVDRV_USBF_ON) { + usbx_function_USB_FUNCTION_Attach(); } else { - usb0_function_USB_FUNCTION_Detach(); + usbx_function_USB_FUNCTION_Detach(); } } else if ( (int_sts0 & USB_FUNCTION_BITSOFR) && (int_enb0 & USB_FUNCTION_BITSOFE)) { - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITSOFR; - SOF((USB200.FRMNUM & USB_FRMNUM_FRNM) >> USB_FRMNUM_FRNM_SHIFT); + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITSOFR; + SOF((USB20X.FRMNUM & USB_FRMNUM_FRNM) >> USB_FRMNUM_FRNM_SHIFT); } else if ( (int_sts0 & USB_FUNCTION_BITDVST) && (int_enb0 & USB_FUNCTION_BITDVSE)) { - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITDVST; + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITDVST; switch (int_sts0 & USB_FUNCTION_BITDVSQ) { case USB_FUNCTION_DS_POWR: break; case USB_FUNCTION_DS_DFLT: /***************************************************************************** - * Function Name: usb0_function_USB_FUNCTION_BusReset + * Function Name: usbx_function_USB_FUNCTION_BusReset * Description : This function is executed when the USB device is transitioned * : to POWERD_STATE. Sets the device descriptor according to the * : connection speed determined by the USB reset hand shake. * Arguments : none * Return Value : none *****************************************************************************/ - usb0_function_init_status(); /* memory clear */ + usbx_function_init_status(); /* memory clear */ #if 0 /* You would program those steps in USBCallback_busReset * if the system need the comment out steps. */ - if (usb0_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) { + if (usbx_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) { /* Device Descriptor reset */ - usb0_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); + usbx_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); } else { /* Device Descriptor reset */ - usb0_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); + usbx_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); } #endif /* Default Control PIPE reset */ /***************************************************************************** - * Function Name: usb0_function_ResetDCP + * Function Name: usbx_function_ResetDCP * Description : Initializes the default control pipe(DCP). * Outline : Reset default control pipe * Arguments : none * Return Value : none *****************************************************************************/ - USB200.DCPCFG = 0; - USB200.DCPMAXP = 64; /*TODO: This value is copied from sample*/ + USB20X.DCPCFG = 0; + USB20X.DCPMAXP = 64; /*TODO: This value is copied from sample*/ - USB200.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); - USB200.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); - USB200.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB20X.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB20X.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB20X.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); busReset(); break; @@ -1368,7 +1372,7 @@ void USBHAL::usbisr(void) case USB_FUNCTION_DS_SPD_ADDR: case USB_FUNCTION_DS_SPD_CNFG: suspendStateChanged(0); - /*usb0_function_USB_FUNCTION_Suspend();*/ + /*usbx_function_USB_FUNCTION_Suspend();*/ break; default: @@ -1377,50 +1381,50 @@ void USBHAL::usbisr(void) } else if ( (int_sts0 & USB_FUNCTION_BITBEMP) && (int_enb0 & USB_FUNCTION_BITBEMP) && - ((int_sts3 & int_enb4) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { + ((int_sts3 & int_enb4) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== BEMP PIPE0 ==== */ - usb0_function_BEMPInterruptPIPE0(int_sts3, int_enb4, this, &USBHAL::EP0in); + usbx_function_BEMPInterruptPIPE0(int_sts3, int_enb4, this, &USBHAL::EP0in); } else if ( (int_sts0 & USB_FUNCTION_BITBRDY) && (int_enb0 & USB_FUNCTION_BITBRDY) && - ((int_sts1 & int_enb2) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { + ((int_sts1 & int_enb2) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== BRDY PIPE0 ==== */ - usb0_function_BRDYInterruptPIPE0(int_sts1, int_enb2, this, &USBHAL::EP0out); + usbx_function_BRDYInterruptPIPE0(int_sts1, int_enb2, this, &USBHAL::EP0out); } else if ( (int_sts0 & USB_FUNCTION_BITNRDY) && (int_enb0 & USB_FUNCTION_BITNRDY) && - ((int_sts2 & int_enb3) & g_usb0_function_bit_set[USB_FUNCTION_PIPE0])) { + ((int_sts2 & int_enb3) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) { /* ==== NRDY PIPE0 ==== */ - usb0_function_NRDYInterruptPIPE0(int_sts2, int_enb3, this, NULL); + usbx_function_NRDYInterruptPIPE0(int_sts2, int_enb3, this, NULL); } else if ( (int_sts0 & USB_FUNCTION_BITCTRT) && (int_enb0 & USB_FUNCTION_BITCTRE)) { - int_sts0 = USB200.INTSTS0; - USB200.INTSTS0 = (uint16_t)~USB_FUNCTION_BITCTRT; + int_sts0 = USB20X.INTSTS0; + USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITCTRT; if (((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) || ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) || ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND)) { /* remake EP0 into buffer */ - usb0_function_save_request(); - if ((USB200.INTSTS0 & USB_FUNCTION_BITVALID) && ( + usbx_function_save_request(); + if ((USB20X.INTSTS0 & USB_FUNCTION_BITVALID) && ( ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) || ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) || ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND))) { /* New SETUP token received */ /* Three dummy reads for cleearing interrupt requests */ - dumy_sts = USB200.INTSTS0; - dumy_sts = USB200.INTSTS0; - dumy_sts = USB200.INTSTS0; + dumy_sts = USB20X.INTSTS0; + dumy_sts = USB20X.INTSTS0; + dumy_sts = USB20X.INTSTS0; return; } } switch (int_sts0 & USB_FUNCTION_BITCTSQ) { case USB_FUNCTION_CS_IDST: - if (g_usb0_function_TestModeFlag == DEVDRV_USBF_YES) { + if (g_usbx_function_TestModeFlag == DEVDRV_USBF_YES) { /* ==== Test Mode ==== */ - usb0_function_USB_FUNCTION_TestMode(); + usbx_function_USB_FUNCTION_TestMode(); } /* Needs not procedure in this state */ break; @@ -1439,25 +1443,25 @@ void USBHAL::usbisr(void) EP0setupCallback(); /*The EP0setupCallback should finish in successful */ - usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); + usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); - RZA_IO_RegWrite_16(&USB200.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); + RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); break; case USB_FUNCTION_CS_RDSS: - RZA_IO_RegWrite_16(&USB200.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); + RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); break; case USB_FUNCTION_CS_WRSS: - RZA_IO_RegWrite_16(&USB200.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); + RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL); break; case USB_FUNCTION_CS_SQER: - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); break; default: - usb0_function_set_pid_stall(USB_FUNCTION_PIPE0); + usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); break; } } else if ( @@ -1465,26 +1469,26 @@ void USBHAL::usbisr(void) (int_enb0 & USB_FUNCTION_BITBEMP) && (int_sts3 & int_enb4) ) { /* ==== BEMP PIPEx ==== */ - usb0_function_BEMPInterrupt(int_sts3, int_enb4, this, epCallback); + usbx_function_BEMPInterrupt(int_sts3, int_enb4, this, epCallback); } else if ( (int_sts0 & USB_FUNCTION_BITBRDY) && (int_enb0 & USB_FUNCTION_BITBRDY) && (int_sts1 & int_enb2) ) { /* ==== BRDY PIPEx ==== */ - usb0_function_BRDYInterrupt(int_sts1, int_enb2, this, epCallback); + usbx_function_BRDYInterrupt(int_sts1, int_enb2, this, epCallback); } else if ( (int_sts0 & USB_FUNCTION_BITNRDY) && (int_enb0 & USB_FUNCTION_BITNRDY) && (int_sts2 & int_enb3)) { /* ==== NRDY PIPEx ==== */ - usb0_function_NRDYInterrupt(int_sts2, int_enb3, this, epCallback); + usbx_function_NRDYInterrupt(int_sts2, int_enb3, this, epCallback); } else { /* Do Nothing */ } /* Three dummy reads for cleearing interrupt requests */ - dumy_sts = USB200.INTSTS0; - dumy_sts = USB200.INTSTS1; + dumy_sts = USB20X.INTSTS0; + dumy_sts = USB20X.INTSTS1; } /*************************************************************************/ From 281ba3862445c290001c67faf9a4d090892a583b Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Mon, 23 Mar 2015 20:16:41 +0900 Subject: [PATCH 032/143] Add 2Port function to USBDevice(usb1). --- .../TARGET_RZ_A1H/usb1/inc/usb1_function.h | 171 + .../usb1/inc/usb1_function_api.h | 104 + .../usb1/inc/usb1_function_dmacdrv.h | 142 + .../usb1/src/common/usb1_function_dataio.c | 2932 +++++++++++++++++ .../usb1/src/common/usb1_function_dma.c | 346 ++ .../usb1/src/common/usb1_function_intrn.c | 249 ++ .../usb1/src/common/usb1_function_lib.c | 2044 ++++++++++++ .../usb1/src/function/usb1_function_api.c | 441 +++ .../src/function/usb1_function_controlrw.c | 142 + .../usb1/src/function/usb1_function_global.c | 144 + .../usb1/src/function/usb1_function_sig.c | 330 ++ .../usb1/src/function/usb1_function_sub.c | 453 +++ .../usb1/src/userdef/usb1_function_dmacdrv.c | 698 ++++ .../usb1/src/userdef/usb1_function_userdef.c | 762 +++++ 14 files changed, 8958 insertions(+) create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c create mode 100644 libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h new file mode 100644 index 0000000000..de51053c0b --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h @@ -0,0 +1,171 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_FUNCTION_H +#define USB1_FUNCTION_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_function_api.h" +#include "usb_function.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb1_function_bit_set[]; +extern uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb1_function_PipeIgnore[]; +extern uint16_t g_usb1_function_PipeTbl[]; +extern uint16_t g_usb1_function_pipe_status[]; +extern uint32_t g_usb1_function_PipeDataSize[]; + +extern USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[]; +extern uint16_t g_usb1_function_DmaPipe[]; +extern uint16_t g_usb1_function_DmaBval[]; +extern uint16_t g_usb1_function_DmaStatus[]; + +extern uint16_t g_usb1_function_CtrZeroLengthFlag; + +extern uint16_t g_usb1_function_ConfigNum; +extern uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO]; +extern uint16_t g_usb1_function_RemoteWakeupFlag; +extern uint16_t g_usb1_function_TestModeFlag; +extern uint16_t g_usb1_function_TestModeSelectors; + +extern uint16_t g_usb1_function_ReqType; +extern uint16_t g_usb1_function_ReqTypeType; +extern uint16_t g_usb1_function_ReqTypeRecip; +extern uint16_t g_usb1_function_ReqRequest; +extern uint16_t g_usb1_function_ReqValue; +extern uint16_t g_usb1_function_ReqIndex; +extern uint16_t g_usb1_function_ReqLength; + +extern uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; + +extern uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; +extern uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +/* ==== common ==== */ +void usb1_function_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb1_function_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb1_function_is_hispeed(void); +uint16_t usb1_function_is_hispeed_enable(void); +uint16_t usb1_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb1_function_write_buffer(uint16_t pipe); +uint16_t usb1_function_write_buffer_c(uint16_t pipe); +uint16_t usb1_function_write_buffer_d0(uint16_t pipe); +uint16_t usb1_function_write_buffer_d1(uint16_t pipe); +void usb1_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb1_function_read_buffer(uint16_t pipe); +uint16_t usb1_function_read_buffer_c(uint16_t pipe); +uint16_t usb1_function_read_buffer_d0(uint16_t pipe); +uint16_t usb1_function_read_buffer_d1(uint16_t pipe); +uint16_t usb1_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb1_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb1_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb1_function_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb1_function_read_dma(uint16_t pipe); +void usb1_function_brdy_int(uint16_t status, uint16_t int_enb); +void usb1_function_nrdy_int(uint16_t status, uint16_t int_enb); +void usb1_function_bemp_int(uint16_t status, uint16_t int_enb); +void usb1_function_setting_interrupt(uint8_t level); +void usb1_function_reset_module(uint16_t clockmode); +uint16_t usb1_function_get_buf_size(uint16_t pipe); +uint16_t usb1_function_get_mxps(uint16_t pipe); +void usb1_function_clear_brdy_sts(uint16_t pipe); +void usb1_function_clear_bemp_sts(uint16_t pipe); +void usb1_function_clear_nrdy_sts(uint16_t pipe); +void usb1_function_set_pid_buf(uint16_t pipe); +void usb1_function_set_pid_nak(uint16_t pipe); +void usb1_function_set_pid_stall(uint16_t pipe); +void usb1_function_clear_pid_stall(uint16_t pipe); +uint16_t usb1_function_get_pid(uint16_t pipe); +void usb1_function_set_sqclr(uint16_t pipe); +void usb1_function_set_sqset(uint16_t pipe); +void usb1_function_set_csclr(uint16_t pipe); +void usb1_function_aclrm(uint16_t pipe); +void usb1_function_set_aclrm(uint16_t pipe); +void usb1_function_clr_aclrm(uint16_t pipe); +uint16_t usb1_function_get_sqmon(uint16_t pipe); +uint16_t usb1_function_get_inbuf(uint16_t pipe); + +/* ==== function ==== */ +void usb1_function_init_status(void); +void usb1_function_InitModule(uint16_t mode); +uint16_t usb1_function_CheckVBUStaus(void); +void usb1_function_USB_FUNCTION_Attach(void); +void usb1_function_USB_FUNCTION_Detach(void); +void usb1_function_USB_FUNCTION_BusReset(void); +void usb1_function_USB_FUNCTION_Resume(void); +void usb1_function_USB_FUNCTION_Suspend(void); +void usb1_function_USB_FUNCTION_TestMode(void); +void usb1_function_ResetDCP(void); +void usb1_function_ResetEP(uint16_t num); +uint16_t usb1_function_EpToPipe(uint16_t ep); +void usb1_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num); +uint16_t usb1_function_GetConfigNum(void); +uint16_t usb1_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num); +uint16_t usb1_function_CheckRemoteWakeup(void); +void usb1_function_clear_alt(void); +void usb1_function_clear_pipe_tbl(void); +void usb1_function_clear_ep_table_index(void); +uint16_t usb1_function_GetInterfaceNum(uint16_t num); + +#ifdef __cplusplus +} +#endif + + +#endif /* USB1_FUNCTION_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h new file mode 100644 index 0000000000..7e78076d9a --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_FUNCTION_API_H +#define USB1_FUNCTION_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void usb1_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +uint16_t usb1_api_function_IsConfigured(void); +uint16_t usb1_function_GetDeviceState(void); +uint16_t usb1_api_function_CtrlReadStart(uint32_t size, uint8_t *data); +void usb1_api_function_CtrlWriteStart(uint32_t size, uint8_t *data); +uint16_t usb1_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb1_api_function_check_pipe_status(uint16_t pipe, uint32_t *size); +void usb1_api_function_clear_pipe_status(uint16_t pipe); +void usb1_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +void usb1_api_function_set_pid_buf(uint16_t pipe); +void usb1_api_function_set_pid_nak(uint16_t pipe); +void usb1_api_function_set_pid_stall(uint16_t pipe); +void usb1_api_function_clear_pid_stall(uint16_t pipe); +uint16_t usb1_api_function_get_pid(uint16_t pipe); +int32_t usb1_api_function_check_stall(uint16_t pipe); +void usb1_api_function_set_sqclr(uint16_t pipe); +void usb1_api_function_set_sqset(uint16_t pipe); +void usb1_api_function_set_csclr(uint16_t pipe); +void usb1_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb1_api_function_clear_brdy_sts(uint16_t pipe); +void usb1_api_function_clear_bemp_sts(uint16_t pipe); +void usb1_api_function_clear_nrdy_sts(uint16_t pipe); + +void usb1_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length); +void usb1_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* USB1_FUNCTION_API_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h new file mode 100644 index 0000000000..a4882f8fad --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_dmacdrv.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB1_FUNCTION_DMACDRV_H +#define USB1_FUNCTION_DMACDRV_H + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef struct dmac_transinfo +{ + uint32_t src_addr; /* Transfer source address */ + uint32_t dst_addr; /* Transfer destination address */ + uint32_t count; /* Transfer byte count */ + uint32_t src_size; /* Transfer source data size */ + uint32_t dst_size; /* Transfer destination data size */ + uint32_t saddr_dir; /* Transfer source address direction */ + uint32_t daddr_dir; /* Transfer destination address direction */ +} dmac_transinfo_t; + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* ==== Transfer specification of the sample program ==== */ +#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */ +#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */ + +/* ==== DMA modes ==== */ +#define DMAC_MODE_REGISTER (0) /* Register mode */ +#define DMAC_MODE_LINK (1) /* Link mode */ + +/* ==== Transfer requests ==== */ +#define DMAC_REQ_MODE_EXT (0) /* External request */ +#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */ +#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */ + +/* ==== DMAC transfer sizes ==== */ +#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */ +#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */ +#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */ +#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */ +#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */ +#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */ +#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */ +#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */ + +/* ==== Address increment for transferring ==== */ +#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */ +#define DMAC_TRANS_ADR_INC (0) /* Increment */ + +/* ==== Method for detecting DMA request ==== */ +#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */ +#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */ +#define DMAC_REQ_DET_LOW (2) /* Low level detection */ +#define DMAC_REQ_DET_HIGH (3) /* High level detection */ + +/* ==== Request Direction ==== */ +#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */ +#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */ + +/* ==== Descriptors ==== */ +#define DMAC_DESC_HEADER (0) /* Header */ +#define DMAC_DESC_SRC_ADDR (1) /* Source Address */ +#define DMAC_DESC_DST_ADDR (2) /* Destination Address */ +#define DMAC_DESC_COUNT (3) /* Transaction Byte */ +#define DMAC_DESC_CHCFG (4) /* Channel Confg */ +#define DMAC_DESC_CHITVL (5) /* Channel Interval */ +#define DMAC_DESC_CHEXT (6) /* Channel Extension */ +#define DMAC_DESC_LINK_ADDR (7) /* Link Address */ + +/* ==== On-chip peripheral module requests ===== */ +typedef enum dmac_request_factor +{ + DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */ + DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */ + DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */ + DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */ + DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */ + DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */ + DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */ + DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */ +} dmac_request_factor_t; + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void usb1_function_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb1_function_DMAC3_Open(uint32_t req); +void usb1_function_DMAC3_Close(uint32_t *remain); +void usb1_function_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +void usb1_function_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction); +int32_t usb1_function_DMAC4_Open(uint32_t req); +void usb1_function_DMAC4_Close(uint32_t *remain); +void usb1_function_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count); + +#ifdef __cplusplus +} +#endif + +#endif /* USB1_FUNCTION_DMACDRV_H */ + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c new file mode 100644 index 0000000000..cf088b60fc --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c @@ -0,0 +1,2932 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_dataio.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static uint16_t g_usb1_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)]; + +static void usb1_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data); +static void usb1_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data); +static uint16_t usb1_function_read_dma_d0(uint16_t pipe); +static uint16_t usb1_function_read_dma_d1(uint16_t pipe); +static uint16_t usb1_function_write_dma_d0(uint16_t pipe); +static uint16_t usb1_function_write_dma_d1(uint16_t pipe); + +static void usb1_function_read_c_fifo(uint16_t pipe, uint16_t count); +static void usb1_function_write_c_fifo(uint16_t Pipe, uint16_t count); +static void usb1_function_read_d0_fifo(uint16_t pipe, uint16_t count); +static void usb1_function_write_d0_fifo(uint16_t pipe, uint16_t count); +static void usb1_function_read_d1_fifo(uint16_t pipe, uint16_t count); +static void usb1_function_write_d1_fifo(uint16_t pipe, uint16_t count); + +static void usb1_function_clear_transaction_counter(uint16_t pipe); +static void usb1_function_set_transaction_counter(uint16_t pipe, uint32_t count); + +static uint32_t usb1_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr); + +static uint16_t usb1_function_set_dfacc_d0(uint16_t mbw, uint32_t count); +static uint16_t usb1_function_set_dfacc_d1(uint16_t mbw, uint32_t count); + + +/******************************************************************************* +* Function Name: usb1_function_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t usefifo; + uint16_t mbw; + + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + usb1_function_clear_bemp_sts(pipe); + usb1_function_clear_brdy_sts(pipe); + usb1_function_clear_nrdy_sts(pipe); + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + + usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + case USB_FUNCTION_D0FIFO_DMA: + usefifo = USB_FUNCTION_D0USE; + break; + + case USB_FUNCTION_D1FIFO_USE: + case USB_FUNCTION_D1FIFO_DMA: + usefifo = USB_FUNCTION_D1USE; + break; + + default: + usefifo = USB_FUNCTION_CUSE; + break; + }; + + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw); + + usb1_function_clear_transaction_counter(pipe); + + usb1_function_aclrm(pipe); + + status = usb1_function_write_buffer(pipe); + + if (status != DEVDRV_USBF_FIFOERROR) + { + usb1_function_set_pid_buf(pipe); + } + + return status; +} + +/******************************************************************************* +* Function Name: usb1_function_write_buffer +* Description : Writes data in the buffer allocated in the pipe specified by +* : the argument. The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_write_buffer (uint16_t pipe) +{ + uint16_t status; + uint16_t usefifo; + + g_usb1_function_PipeIgnore[pipe] = 0; + usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + status = usb1_function_write_buffer_d0(pipe); + break; + + case USB_FUNCTION_D1FIFO_USE: + status = usb1_function_write_buffer_d1(pipe); + break; + + case USB_FUNCTION_D0FIFO_DMA: + status = usb1_function_write_dma_d0(pipe); + break; + + case USB_FUNCTION_D1FIFO_DMA: + status = usb1_function_write_dma_d1(pipe); + break; + + default: + status = usb1_function_write_buffer_c(pipe); + break; + }; + + switch (status) + { + case DEVDRV_USBF_WRITING: /* Continue of data write */ + usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + usb1_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */ + break; + + case DEVDRV_USBF_WRITEEND: /* End of data write */ + case DEVDRV_USBF_WRITESHRT: /* End of data write */ + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb1_function_clear_nrdy_sts(pipe); + usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + /* for last transfer */ + usb1_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */ + break; + + case DEVDRV_USBF_WRITEDMA: /* DMA write */ + usb1_function_clear_nrdy_sts(pipe); + usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */ + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + usb1_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */ + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_write_buffer_c +* Description : Writes data in the buffer allocated in the pipe specified in +* : the argument. Writes data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_write_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + if (g_usb1_function_CtrZeroLengthFlag == 1) + { + g_usb1_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */ + return DEVDRV_USBF_WRITEEND; + } + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + if (pipe == USB_FUNCTION_PIPE0) + { + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + } + else + { + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); + } + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb1_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_function_write_c_fifo(pipe, (uint16_t)count); + + if (g_usb1_function_data_count[pipe] < (uint32_t)size) + { + g_usb1_function_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB201.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0) + { + USB201.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + g_usb1_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */ + } + } + else + { + g_usb1_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_write_buffer_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_write_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb1_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_function_write_d0_fifo(pipe, (uint16_t)count); + + if (g_usb1_function_data_count[pipe] < (uint32_t)size) + { + g_usb1_function_data_count[pipe] = 0; + if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb1_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_write_buffer_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_write_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] <= (uint32_t)size) + { + status = DEVDRV_USBF_WRITEEND; /* write continues */ + count = g_usb1_function_data_count[pipe]; + + if (count == 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */ + } + + if ((count % mxps) != 0) + { + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + } + else + { + status = DEVDRV_USBF_WRITING; /* write continues */ + count = (uint32_t)size; + } + + usb1_function_write_d1_fifo(pipe, (uint16_t)count); + + if (g_usb1_function_data_count[pipe] < (uint32_t)size) + { + g_usb1_function_data_count[pipe] = 0; + + if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */ + } + } + else + { + g_usb1_function_data_count[pipe] -= count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_write_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D0FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND : Write end +* : DEVDRV_USBF_WRITESHRT : short data +* : DEVDRV_USBF_WRITING : Continue of data write +* : DEVDRV_USBF_WRITEDMA : Write DMA +* : DEVDRV_USBF_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb1_function_write_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + count = g_usb1_function_data_count[pipe]; + + if (count != 0) + { + g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; + + if ((count % size) != 0) + { + g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 1; + } + else + { + g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; + } + + dfacc = usb1_function_set_dfacc_d0(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe]; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; + + Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); + + usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); + + g_usb1_function_data_count[pipe] = 0; + g_usb1_function_data_pointer[pipe] += count; + status = DEVDRV_USBF_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_write_dma_d1 +* Description : Writes data in the buffer allocated in the pipe specified in the argument. +* : Writes data by DMA transfer using D1FIFO. +* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma(). +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : DEVDRV_USBF_WRITEEND : Write end +* : DEVDRV_USBF_WRITESHRT : short data +* : DEVDRV_USBF_WRITING : Continue of data write +* : DEVDRV_USBF_WRITEDMA : Write DMA +* : DEVDRV_USBF_FIFOERROR : FIFO status +*******************************************************************************/ +static uint16_t usb1_function_write_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint16_t size; + uint16_t buffer; + uint16_t status; + uint16_t mbw; + uint16_t dfacc=0; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + count = g_usb1_function_data_count[pipe]; + + if (count != 0) + { + g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; + if ((count % size) != 0) + { + g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 1; + } + else + { + g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; + } + + dfacc = usb1_function_set_dfacc_d1(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe]; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; + + Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); + + usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); + + g_usb1_function_data_count[pipe] = 0; + g_usb1_function_data_pointer[pipe] += count; + + status = DEVDRV_USBF_WRITEDMA; /* DMA write */ + } + else + { + if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0) + { + RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */ + } + status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */ + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb1_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t usefifo; + + usb1_function_clear_bemp_sts(pipe); + usb1_function_clear_brdy_sts(pipe); + usb1_function_clear_nrdy_sts(pipe); + + usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + usb1_function_start_receive_trns_d0(pipe, size, data); + break; + + case USB_FUNCTION_D1FIFO_USE: + usb1_function_start_receive_trns_d1(pipe, size, data); + break; + + case USB_FUNCTION_D0FIFO_DMA: + usb1_function_start_receive_dma_d0(pipe, size, data); + break; + + case USB_FUNCTION_D1FIFO_DMA: + usb1_function_start_receive_dma_d1(pipe, size, data); + break; + + default: + usb1_function_start_receive_trns_c(pipe, size, data); + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_trns_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* : When storing data in the buffer allocated in the pipe specified in the +* : argument, BRDY interrupt is generated to read data +* : in the interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(pipe); + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_PipeIgnore[pipe] = 0; + + g_usb1_function_PipeDataSize[pipe] = size; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw); + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; + + usb1_function_set_transaction_counter(pipe, size); + + usb1_function_aclrm(pipe); + + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_trns_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data in the +* : interrupt. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(pipe); + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_PipeIgnore[pipe] = 0; + + g_usb1_function_PipeDataSize[pipe] = size; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + usb1_function_set_transaction_counter(pipe, size); + + usb1_function_aclrm(pipe); + + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_trns_d1 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using D1FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, BRDY interrupt is generated to read data. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(pipe); + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_PipeIgnore[pipe] = 0; + + g_usb1_function_PipeDataSize[pipe] = size; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + usb1_function_set_transaction_counter(pipe, size); + + usb1_function_aclrm(pipe); + + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_dma_d0 +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(pipe); + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_PipeIgnore[pipe] = 0; + + g_usb1_function_PipeDataSize[pipe] = 0; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + usb1_function_set_transaction_counter(pipe, size); + + usb1_function_aclrm(pipe); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb1_function_read_dma(pipe); + + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + } + else + { + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + } + + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_start_receive_dma_d1 +* Description : Read data from the buffer allocated in the pipe specified in the argument. +* : Reads data by DMA transfer using D0FIFO. +* : This function does not read data from the buffer. +* : When storing data in the buffer allocated in the pipe specified +* : in the argument, delivered read request to DMAC to read data from +* : the buffer by DMAC. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +static void usb1_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(pipe); + g_usb1_function_data_count[pipe] = size; + g_usb1_function_data_pointer[pipe] = (uint8_t *)data; + g_usb1_function_PipeIgnore[pipe] = 0; + + g_usb1_function_PipeDataSize[pipe] = 0; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT; + + mbw = usb1_function_get_mbw(size, (uint32_t)data); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + usb1_function_set_transaction_counter(pipe, size); + + usb1_function_aclrm(pipe); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + usb1_function_read_dma(pipe); + + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + } + else + { + usb1_function_enable_nrdy_int(pipe); + usb1_function_enable_brdy_int(pipe); + } + + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_read_buffer +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Uses FIF0 set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_read_buffer (uint16_t pipe) +{ + uint16_t status; + + g_usb1_function_PipeIgnore[pipe] = 0; + + if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) + { + status = usb1_function_read_buffer_d0(pipe); + } + else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) + { + status = usb1_function_read_buffer_d1(pipe); + } + else + { + status = usb1_function_read_buffer_c(pipe); + } + + switch (status) + { + case USB_FUNCTION_READING: /* Continue of data read */ + break; + + case USB_FUNCTION_READEND: /* End of data read */ + case USB_FUNCTION_READSHRT: /* End of data read */ + usb1_function_disable_brdy_int(pipe); + g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe]; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + break; + + case USB_FUNCTION_READOVER: /* buffer over */ + if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE) + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE) + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe]; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_buffer_c +* Description : Reads data from the buffer allocated in the pipe specified in the argument. +* : Reads data by CPU transfer using CFIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_read_buffer_c (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_function_data_count[pipe]; + } + else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_function_read_c_fifo(pipe, (uint16_t)count); + } + + g_usb1_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_buffer_d0 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by CPU transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_read_buffer_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_function_data_count[pipe]; + } + else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_function_read_d0_fifo(pipe, (uint16_t)count); + } + + g_usb1_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_buffer_d1 +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by CPU transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_read_buffer_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t pipebuf_size; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = g_usb1_function_data_count[pipe]; + } + else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + usb1_function_set_pid_nak(pipe); /* Set NAK */ + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + else + { + pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + usb1_function_set_pid_nak(pipe); /* Set NAK */ + } + } + } + + if (count == 0) /* 0 length packet */ + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + } + else + { + usb1_function_read_d1_fifo(pipe, (uint16_t)count); + } + + g_usb1_function_data_count[pipe] -= count; + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_dma +* Description : Reads data from the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO or D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_function_read_dma (uint16_t pipe) +{ + uint16_t status; + + g_usb1_function_PipeIgnore[pipe] = 0; + if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) + { + status = usb1_function_read_dma_d0(pipe); + } + else + { + status = usb1_function_read_dma_d1(pipe); + } + + switch (status) + { + case USB_FUNCTION_READING: /* Continue of data read */ + break; + + case USB_FUNCTION_READZERO: /* End of data read */ + usb1_function_disable_brdy_int(pipe); + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + break; + + case USB_FUNCTION_READEND: /* End of data read */ + case USB_FUNCTION_READSHRT: /* End of data read */ + usb1_function_disable_brdy_int(pipe); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe]; + } + break; + + case USB_FUNCTION_READOVER: /* buffer over */ + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe]; + } + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access status */ + default: + usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */ + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR; + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_dma_d0 +* Description : Writes data in the buffer allocated in the pipe specified +* : in the argument. +* : Reads data by DMA transfer using D0FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READZERO ; zero data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb1_function_read_dma_d0 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb1_function_data_count[pipe]; + status = USB_FUNCTION_READING; + } + else + { + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + count = g_usb1_function_data_count[pipe]; + } + else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + status = USB_FUNCTION_READZERO; /* Null Packet receive */ + } + else + { + usb1_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb1_function_set_dfacc_d0(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */ + g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */ + + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe]; + g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count; + + if (status == USB_FUNCTION_READING) + { + g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY; + } + else + { + g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND; + } + + Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc); + + usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb1_function_data_count[pipe] -= count; + g_usb1_function_data_pointer[pipe] += count; + g_usb1_function_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_read_dma_d1 +* Description : Reads data from the buffer allocated in the pipe specified in +* : the argument. +* : Reads data by DMA transfer using D1FIFO. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : USB_FUNCTION_READEND ; Read end +* : USB_FUNCTION_READSHRT ; short data +* : USB_FUNCTION_READZERO ; zero data +* : USB_FUNCTION_READING ; Continue of data read +* : USB_FUNCTION_READOVER ; buffer over +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +static uint16_t usb1_function_read_dma_d1 (uint16_t pipe) +{ + uint32_t count; + uint32_t dtln; + uint16_t buffer; + uint16_t mxps; + uint16_t status; + uint16_t mbw; + uint16_t dfacc = 0; + uint16_t pipebuf_size; + + g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + count = g_usb1_function_data_count[pipe]; + status = USB_FUNCTION_READING; + } + else + { + buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */ + { + return DEVDRV_USBF_FIFOERROR; + } + + dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN); + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */ + { + status = USB_FUNCTION_READOVER; + count = g_usb1_function_data_count[pipe]; + } + else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */ + { + status = USB_FUNCTION_READEND; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + else /* continue Receive data */ + { + status = USB_FUNCTION_READING; + count = dtln; + if (count == 0) + { + status = USB_FUNCTION_READSHRT; /* Null Packet receive */ + } + + if ((count % mxps) != 0) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + else + { + pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */ + if (count != pipebuf_size) + { + status = USB_FUNCTION_READSHRT; /* Short Packet receive */ + } + } + } + } + + if (count == 0) /* 0 length packet */ + { + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */ + status = USB_FUNCTION_READZERO; /* Null Packet receive */ + } + else + { + usb1_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw); + /* transaction counter No set */ + /* FRDY = 1, DTLN = 0 -> BRDY */ + } + } + else + { + dfacc = usb1_function_set_dfacc_d1(mbw, count); + + if (mbw == USB_FUNCTION_BITMBW_32) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */ + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */ + } + else + { + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */ + } + + g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */ + g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */ + + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe]; + g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count; + + if (status == USB_FUNCTION_READING) + { + g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY; + } + else + { + g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND; + } + + Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc); + + usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc); + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, + 1, + USB_DnFIFOSEL_DREQE_SHIFT, + USB_DnFIFOSEL_DREQE); + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + g_usb1_function_data_count[pipe] -= count; + g_usb1_function_data_pointer[pipe] += count; + g_usb1_function_PipeDataSize[pipe] += count; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_function_change_fifo_port +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. After allocating FIF0, waits in the software +* : till the corresponding pipe becomes ready. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : DEVDRV_USBF_FIFOERROR ; Error +* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value +*******************************************************************************/ +uint16_t usb1_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + usb1_function_set_curpipe(pipe, fifosel, isel, mbw); + + for (loop = 0; loop < 4; loop++) + { + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB201.CFIFOCTR; + break; + + case USB_FUNCTION_D0USE: + case USB_FUNCTION_D0DMA: + buffer = USB201.D0FIFOCTR; + break; + + case USB_FUNCTION_D1USE: + case USB_FUNCTION_D1DMA: + buffer = USB201.D1FIFOCTR; + break; + + default: + buffer = 0; + break; + } + + if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY) + { + return buffer; + } + + loop2 = 25; + while (loop2-- > 0) + { + /* wait */ + } + } + + return DEVDRV_USBF_FIFOERROR; +} + +/******************************************************************************* +* Function Name: usb1_function_set_curpipe +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb1_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + uint16_t buffer; + uint32_t loop; + volatile uint32_t loop2; + + g_usb1_function_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB201.CFIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D0DMA: + case USB_FUNCTION_D0USE: + buffer = USB201.D0FIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D1DMA: + case USB_FUNCTION_D1USE: + buffer = USB201.D1FIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == + (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_curpipe2 +* Description : Allocates FIF0 specified by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* : uint16_t dfacc ; DFACC Access mode +* Return Value : none +*******************************************************************************/ +void usb1_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc) +{ + uint16_t buffer; + uint32_t loop; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + uint32_t dummy; +#endif + volatile uint32_t loop2; + + g_usb1_function_mbw[pipe] = mbw; + + switch (fifosel) + { + case USB_FUNCTION_CUSE: + buffer = USB201.CFIFOSEL; + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE); + buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + while (loop2-- > 0) + { + /* wait */ + } + } + buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(isel | pipe | mbw); + USB201.CFIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) == + (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE))) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D0DMA: + case USB_FUNCTION_D0USE: + buffer = USB201.D0FIFOSEL; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); +#endif + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB201.D0FIFO.UINT32; + } +#endif + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D0FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + case USB_FUNCTION_D1DMA: + case USB_FUNCTION_D1USE: + buffer = USB201.D1FIFOSEL; +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + + if (dfacc != 0) + { + buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32); + } +#else + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE); +#endif + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } +#ifdef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dfacc != 0) + { + dummy = USB201.D1FIFO.UINT32; + loop = dummy; // avoid warning. + } +#endif + buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW); + buffer |= (uint16_t)(pipe | mbw); + USB201.D1FIFOSEL = buffer; + + for (loop = 0; loop < 4; loop++) + { + if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE)) + { + break; + } + + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } + } + break; + + default: + break; + } + + /* Cautions !!! + * Depending on the external bus speed of CPU, you may need to wait for 450ns here. + * For details, please look at the data sheet. */ + loop2 = 100; + + while (loop2-- > 0) + { + /* wait */ + } +} + +/******************************************************************************* +* Function Name: usb1_function_write_c_fifo +* Description : Writes data in CFIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_write_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.CFIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_read_c_fifo +* Description : Reads data from CFIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_read_c_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_function_data_pointer[pipe] = USB201.CFIFO.UINT8[HH]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT16[H]; + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT32; + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_write_d0_fifo +* Description : Writes data in D0FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating CFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_write_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.D0FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_read_d0_fifo +* Description : Reads data from D0FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating DOFIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_read_d0_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_function_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H]; + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT32; + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_write_d1_fifo +* Description : Writes data in D1FIFO. +* : Writes data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_write_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + USB201.D1FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)(count / 2); even; --even) + { + USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)(count / 4); even; --even) + { + USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]); + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_read_d1_fifo +* Description : Reads data from D1FIFO. +* : Reads data by BYTE/WORD/LONG according to access size +* : to the pipe specified by the arguments. +* : Before executing this function, allocating D1FIF0 in the specified pipe +* : should be completed. +* : Before executing this function, access size to the specified pipe +* : should be fixed and set in g_usb1_function_mbw[]. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t count ; Data Size(Byte) +* Return Value : none +*******************************************************************************/ +static void usb1_function_read_d1_fifo (uint16_t pipe, uint16_t count) +{ + uint16_t even; + + if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8) + { + for (even = count; even; --even) + { + *g_usb1_function_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH]; + g_usb1_function_data_pointer[pipe] += 1; + } + } + else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16) + { + for (even = (uint16_t)((count + 1) / 2); even; --even) + { + *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H]; + g_usb1_function_data_pointer[pipe] += 2; + } + } + else + { + for (even = (uint16_t)((count + 3) / 4); even; --even) + { + *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT32; + g_usb1_function_data_pointer[pipe] += 4; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_com_get_dmasize +* Description : Calculates access width of DMA transfer by the argument to +* : return as the Return Value. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : DMA transfer size : 0 8bit +* : : 1 16bit +* : : 2 32bit +*******************************************************************************/ +static uint32_t usb1_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + + if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0)) + { + /* When transfer byte count is odd */ + /* or transfer data area is 8-bit alignment */ + size = 0; /* 8bit */ + } + else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0)) + { + /* When the transfer byte count is multiples of 2 */ + /* or the transfer data area is 16-bit alignment */ + size = 1; /* 16bit */ + } + else + { + /* When the transfer byte count is multiples of 4 */ + /* or the transfer data area is 32-bit alignment */ + size = 2; /* 32bit */ + } + + return size; +} + +/******************************************************************************* +* Function Name: usb1_function_get_mbw +* Description : Calculates access width of DMA to return the value set in MBW. +* Arguments : uint32_t trncount : transfer byte +* : uint32_t dtptr : transfer data pointer +* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit +* : : USB_FUNCTION_BITMBW_16 16bit +* : : USB_FUNCTION_BITMBW_32 32bit +*******************************************************************************/ +uint16_t usb1_function_get_mbw (uint32_t trncount, uint32_t dtptr) +{ + uint32_t size; + uint16_t mbw; + + size = usb1_function_com_get_dmasize(trncount, dtptr); + + if (size == 0) + { + /* 8bit */ + mbw = USB_FUNCTION_BITMBW_8; + } + else if (size == 1) + { + /* 16bit */ + mbw = USB_FUNCTION_BITMBW_16; + } + else + { + /* 32bit */ + mbw = USB_FUNCTION_BITMBW_32; + } + + return mbw; +} + +/******************************************************************************* +* Function Name: usb1_function_set_transaction_counter +* Description : Sets transaction counter by the argument(PIPEnTRN). +* : Clears transaction before setting to enable transaction counter setting. +* Arguments : uint16_t pipe ; Pipe number +* : uint32_t bsize : Data transfer size +* Return Value : none +*******************************************************************************/ +static void usb1_function_set_transaction_counter (uint16_t pipe, uint32_t bsize) +{ + uint16_t mxps; + uint16_t cnt; + + if (bsize == 0) + { + return; + } + + mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */ + + if ((bsize % mxps) == 0) + { + cnt = (uint16_t)(bsize / mxps); + } + else + { + cnt = (uint16_t)((bsize / mxps) + 1); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE1TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE2TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE3TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE4TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE5TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPE9TRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEATRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPEATRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPEATRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPEBTRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPEBTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPECTRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPECTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPEDTRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPEDTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEETRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPEETRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPEETRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + USB201.PIPEFTRN = cnt; + RZA_IO_RegWrite_16(&USB201.PIPEFTRE, + 1, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_clear_transaction_counter +* Description : Clears the transaction counter by the argument. +* : After executing this function, the transaction counter is invalid. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_transaction_counter (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE1TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE2TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE3TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE4TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE5TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPE9TRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEATRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPEATRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPEBTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPECTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPEDTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEETRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPEETRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFTRE, + 0, + USB_PIPEnTRE_TRENB_SHIFT, + USB_PIPEnTRE_TRENB); + RZA_IO_RegWrite_16(&USB201.PIPEFTRE, + 1, + USB_PIPEnTRE_TRCLR_SHIFT, + USB_PIPEnTRE_TRCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_stop_transfer +* Description : Stops the USB transfer in the pipe specified by the argument. +* : After stopping the USB transfer, clears the buffer allocated in +* : the pipe. +* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0; +* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt +* : in the corresponding pipe becomes invalid. Sequence bit is also +* : cleared. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_stop_transfer (uint16_t pipe) +{ + uint16_t usefifo; + uint32_t remain; + uint16_t fifo; + + usb1_function_set_pid_nak(pipe); + + usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + switch (usefifo) + { + case USB_FUNCTION_D0FIFO_USE: + usb1_function_clear_transaction_counter(pipe); + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D0USE; + break; + + case USB_FUNCTION_D1FIFO_USE: + usb1_function_clear_transaction_counter(pipe); + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D1USE; + break; + + case USB_FUNCTION_D0FIFO_DMA: + remain = Userdef_USB_usb1_function_stop_dma0(); + usb1_function_dma_stop_d0(pipe, remain); + usb1_function_clear_transaction_counter(pipe); + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D0DMA; + break; + + case USB_FUNCTION_D1FIFO_DMA: + remain = Userdef_USB_usb1_function_stop_dma1(); + usb1_function_dma_stop_d1(pipe, remain); + usb1_function_clear_transaction_counter(pipe); + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_D1DMA; + break; + + default: + usb1_function_clear_transaction_counter(pipe); + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */ + fifo = USB_FUNCTION_CUSE; + break; + } + + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16); + + /* Interrupt of pipe set is disabled */ + usb1_function_disable_brdy_int(pipe); + usb1_function_disable_nrdy_int(pipe); + usb1_function_disable_bemp_int(pipe); + + usb1_function_aclrm(pipe); + usb1_function_set_csclr(pipe); + + if ( g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT ) + { + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_dfacc_d0 +* Description : Sets the DFACC setting value in D0FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb1_function_set_dfacc_d0 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_FUNCTION_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D0FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + return dfacc; +} + +/******************************************************************************* +* Function Name: usb1_function_set_dfacc_d1 +* Description : Set the DFACC setting value in D1FIFO using the transfer size. +* Arguments : uint16_t mbw ; MBW +* : uint16_t count ; data count +* Return Value : DFACC Access mode +*******************************************************************************/ +static uint16_t usb1_function_set_dfacc_d1 (uint16_t mbw, uint32_t count) +{ + uint16_t dfacc = 0; + +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; +#else + if (mbw == USB_FUNCTION_BITMBW_32) + { + if ((count % 32) == 0) + { + /* 32byte transfer */ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 2, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 2; + } + else if ((count % 16) == 0) + { + /* 16byte transfer */ + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 1, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 1; + } + else + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + } + else if (mbw == USB_FUNCTION_BITMBW_16) + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } + else + { + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_DFACC_SHIFT, + USB_DnFBCFG_DFACC); + RZA_IO_RegWrite_16(&USB201.D1FBCFG, + 0, + USB_DnFBCFG_TENDE_SHIFT, + USB_DnFBCFG_TENDE); + dfacc = 0; + } +#endif + + return dfacc; +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c new file mode 100644 index 0000000000..c6f3f14722 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c @@ -0,0 +1,346 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_dma.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static void usb1_function_dmaint(uint16_t fifo); +static void usb1_function_dmaint_buf2fifo(uint16_t pipe); +static void usb1_function_dmaint_fifo2buf(uint16_t pipe); + + +/******************************************************************************* +* Function Name: usb1_function_dma_stop_d0 +* Description : D0FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb1_function_dma_stop_d0 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); + + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + buffer = USB201.D0FIFOCTR; + dtln = (buffer & USB_FUNCTION_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain); + g_usb1_function_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb1_function_dma_stop_d1 +* Description : D1FIFO DMA stop +* Arguments : uint16_t pipe : pipe number +* : uint32_t remain : transfer byte +* Return Value : none +*******************************************************************************/ +void usb1_function_dma_stop_d1 (uint16_t pipe, uint32_t remain) +{ + uint16_t dtln; + uint16_t dfacc; + uint16_t buffer; + uint16_t sds_b = 1; + + dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC); + + if (dfacc == 2) + { + sds_b = 32; + } + else if (dfacc == 1) + { + sds_b = 16; + } + else + { + if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2) + { + sds_b = 4; + } + else if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1) + { + sds_b = 2; + } + else + { + sds_b = 1; + } + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1) + { + if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + buffer = USB201.D1FIFOCTR; + dtln = (buffer & USB_FUNCTION_BITDTLN); + + if ((dtln % sds_b) != 0) + { + remain += (sds_b - (dtln % sds_b)); + } + g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain); + g_usb1_function_data_count[pipe] = remain; + } + } + + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE); +} + +/******************************************************************************* +* Function Name: usb1_function_dma_interrupt_d0fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb1_function_dma_interrupt_d0fifo (uint32_t int_sense) +{ + usb1_function_dmaint(USB_FUNCTION_D0FIFO); + g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb1_function_dma_interrupt_d1fifo +* Description : This function is DMA interrupt handler entry. +* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function. +* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is +* : specified by dma->fifo. +* : Register this function as DMA complete interrupt. +* Arguments : uint32_t int_sense ; Interrupts detection mode +* : ; INTC_LEVEL_SENSITIVE : Level sense +* : ; INTC_EDGE_TRIGGER : Edge trigger +* Return Value : none +*******************************************************************************/ +void usb1_function_dma_interrupt_d1fifo (uint32_t int_sense) +{ + usb1_function_dmaint(USB_FUNCTION_D1FIFO); + g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY; +} + +/******************************************************************************* +* Function Name: usb1_function_dmaint +* Description : This function is DMA transfer end interrupt +* Arguments : uint16_t fifo ; fifo number +* : ; USB_FUNCTION_D0FIFO +* : ; USB_FUNCTION_D1FIFO +* Return Value : none +*******************************************************************************/ +static void usb1_function_dmaint (uint16_t fifo) +{ + uint16_t pipe; + + pipe = g_usb1_function_DmaPipe[fifo]; + + if (g_usb1_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO) + { + usb1_function_dmaint_buf2fifo(pipe); + } + else + { + usb1_function_dmaint_fifo2buf(pipe); + } +} + +/******************************************************************************* +* Function Name: usb1_function_dmaint_fifo2buf +* Description : Executes read completion from FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb1_function_dmaint_fifo2buf (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE) + { + useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + if (useport == USB_FUNCTION_D0FIFO_DMA) + { + remain = Userdef_USB_usb1_function_stop_dma0(); + usb1_function_dma_stop_d0(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND) + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + else + { + usb1_function_enable_brdy_int(pipe); + } + } + } + else + { + remain = Userdef_USB_usb1_function_stop_dma1(); + usb1_function_dma_stop_d1(pipe, remain); + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND) + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + else + { + usb1_function_enable_brdy_int(pipe); + } + } + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_dmaint_buf2fifo +* Description : Executes write completion in FIFO by DMAC. +* Arguments : uint16_t pipe : pipe number +* Return Value : none +*******************************************************************************/ +static void usb1_function_dmaint_buf2fifo (uint16_t pipe) +{ + uint32_t remain; + uint16_t useport; + + useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE); + + if (useport == USB_FUNCTION_D0FIFO_DMA) + { + remain = Userdef_USB_usb1_function_stop_dma0(); + usb1_function_dma_stop_d0(pipe, remain); + + if (g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + else + { + remain = Userdef_USB_usb1_function_stop_dma1(); + usb1_function_dma_stop_d1(pipe, remain); + + if (g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] != 0) + { + RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, + 1, + USB_DnFIFOCTR_BVAL_SHIFT, + USB_DnFIFOCTR_BVAL); + } + } + + usb1_function_enable_bemp_int(pipe); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c new file mode 100644 index 0000000000..bdcc9a8f78 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c @@ -0,0 +1,249 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_intrn.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_function_brdy_int +* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9). +* : According to the pipe that interrupt is generated in, +* : reads/writes buffer allocated in the pipe. +* : This function is executed in the BRDY interrupt handler. +* : This function clears BRDY interrupt status and BEMP interrupt +* : status. +* Arguments : uint16_t Status ; BRDYSTS Register Value +* : uint16_t Int_enbl ; BRDYENB Register Value +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_brdy_int (uint16_t status, uint16_t int_enb) +{ + uint32_t int_sense = 0; + uint16_t pipe; + uint16_t pipebit; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + pipebit = g_usb1_function_bit_set[pipe]; + + if ((status & pipebit) && (int_enb & pipebit)) + { + USB201.BRDYSTS = (uint16_t)~pipebit; + USB201.BEMPSTS = (uint16_t)~pipebit; + if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) + { + if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) + { + usb1_function_dma_interrupt_d0fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb1_function_read_dma(pipe); + usb1_function_disable_brdy_int(pipe); + } + else + { + USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA) + { + if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) + { + usb1_function_dma_interrupt_d1fifo(int_sense); + } + + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) + { + usb1_function_read_dma(pipe); + usb1_function_disable_brdy_int(pipe); + } + else + { + USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + else + { + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) + { + usb1_function_read_buffer(pipe); + } + else + { + usb1_function_write_buffer(pipe); + } + } + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_nrdy_int +* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9). +* : Checks NRDY interrupt cause by PID. When the cause if STALL, +* : regards the pipe state as STALL and ends the processing. +* : Then the cause is not STALL, increments the error count to +* : communicate again. When the error count is 3, determines +* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing. +* : This function is executed in the NRDY interrupt handler. +* : This function clears NRDY interrupt status. +* Arguments : uint16_t status ; NRDYSTS Register Value +* : uint16_t int_enb ; NRDYENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_function_nrdy_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + + bitcheck = (uint16_t)(status & int_enb); + + USB201.NRDYSTS = (uint16_t)~status; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe]) + { + if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) + { + if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT) + { + pid = usb1_function_get_pid(pipe); + if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) + { + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + } + else + { + g_usb1_function_PipeIgnore[pipe]++; + if (g_usb1_function_PipeIgnore[pipe] == 3) + { + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES; + } + else + { + usb1_function_set_pid_buf(pipe); + } + } + } + } + else + { + /* USB Function */ + } + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_bemp_int +* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9). +* Arguments : uint16_t status ; BEMPSTS Register Value +* : uint16_t int_enb ; BEMPENB Register Value +* Return Value : none +*******************************************************************************/ +void usb1_function_bemp_int (uint16_t status, uint16_t int_enb) +{ + uint16_t pid; + uint16_t pipe; + uint16_t bitcheck; + uint16_t inbuf; + + bitcheck = (uint16_t)(status & int_enb); + + USB201.BEMPSTS = (uint16_t)~status; + + for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe]) + { + pid = usb1_function_get_pid(pipe); + + if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) + { + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL; + } + else + { + inbuf = usb1_function_get_inbuf(pipe); + + if (inbuf == 0) + { + usb1_function_disable_bemp_int(pipe); + usb1_function_set_pid_nak(pipe); + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE; + } + } + } + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c new file mode 100644 index 0000000000..d448dc5992 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c @@ -0,0 +1,2044 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_lib.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_function_enable_brdy_int +* Description : Enables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_enable_brdy_int (uint16_t pipe) +{ + /* enable brdy interrupt */ + USB201.BRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_function_disable_brdy_int +* Description : Disables BRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BRDY. Enables BRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling BRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_disable_brdy_int (uint16_t pipe) +{ + /* disable brdy interrupt */ + USB201.BRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_brdy_sts (uint16_t pipe) +{ + /* clear brdy status */ + USB201.BRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_enable_bemp_int +* Description : Enables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_enable_bemp_int (uint16_t pipe) +{ + /* enable bemp interrupt */ + USB201.BEMPENB |= (uint16_t)g_usb1_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_function_disable_bemp_int +* Description : Disables BEMP interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : BEMP. Enables BEMP interrupt in the pipe specified by the argument +* : in the disabled status. After enabling BEMP, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_disable_bemp_int (uint16_t pipe) +{ + /* disable bemp interrupt */ + USB201.BEMPENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_bemp_sts (uint16_t pipe) +{ + /* clear bemp status */ + USB201.BEMPSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_enable_nrdy_int +* Description : Enables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling +* : NRDY. Enables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After enabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_enable_nrdy_int (uint16_t pipe) +{ + /* enable nrdy interrupt */ + USB201.NRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_function_disable_nrdy_int +* Description : Disables NRDY interrupt in the pipe spceified by the argument. +* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling +* : NRDY. Disables NRDY interrupt in the pipe specified by the argument +* : in the disabled status. After disabling NRDY, recover all +* : BEMP/NRDY/BRDY disabled/enabled status. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_disable_nrdy_int (uint16_t pipe) +{ + /* disable nrdy interrupt */ + USB201.NRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_nrdy_sts (uint16_t pipe) +{ + /* clear nrdy status */ + USB201.NRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]); +} + +/******************************************************************************* +* Function Name: usb1_function_is_hispeed +* Description : Returns the result of USB reset hand shake (RHST) as +* : return value. +* Arguments : none +* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed +* : USB_FUNCTION_FULL_SPEED ; Full-Speed +* : LOW_SPEED ; Low-Speed +* : USB_FUNCTION_NON_SPEED ; error +*******************************************************************************/ +uint16_t usb1_function_is_hispeed (void) +{ + uint16_t rhst; + uint16_t speed; + + rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST); + + if (rhst == USB_FUNCTION_HSMODE) + { + speed = USB_FUNCTION_HIGH_SPEED; + } + else if (rhst == USB_FUNCTION_FSMODE) + { + speed = USB_FUNCTION_FULL_SPEED; + } + else if (rhst == USB_FUNCTION_LSMODE) + { + speed = USB_FUNCTION_LOW_SPEED; + } + else + { + speed = USB_FUNCTION_NON_SPEED; + } + + return speed; +} + +/******************************************************************************* +* Function Name: usb1_function_is_hispeed_enable +* Description : Returns the USB High-Speed connection enabled status as +* : return value. +* Arguments : none +* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable +* : DEVDRV_USBF_NO : Hi-Speed Disable +*******************************************************************************/ +uint16_t usb1_function_is_hispeed_enable (void) +{ + uint16_t ret; + + ret = DEVDRV_USBF_NO; + + if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1) + { + ret = DEVDRV_USBF_YES; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_function_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_pid_buf (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_function_get_pid(pipe); + + if (pid == DEVDRV_USBF_PID_STALL2) + { + usb1_function_set_pid_nak(pipe); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + DEVDRV_USBF_PID_BUF, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + DEVDRV_USBF_PID_BUF, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_pid_nak (uint16_t pipe) +{ + uint16_t pid; + uint16_t pbusy; + uint32_t loop; + + pid = usb1_function_get_pid(pipe); + + if (pid == DEVDRV_USBF_PID_STALL2) + { + usb1_function_set_pid_stall(pipe); + } + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + DEVDRV_USBF_PID_NAK, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + DEVDRV_USBF_PID_NAK, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + + if (pid == DEVDRV_USBF_PID_BUF) + { + for (loop = 0; loop < 200; loop++) + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_PBUSY_SHIFT, + USB_DCPCTR_PBUSY); + break; + + case USB_FUNCTION_PIPE1: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE2: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE3: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE4: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE5: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_PBUSY_SHIFT, + USB_PIPEnCTR_1_5_PBUSY); + break; + + case USB_FUNCTION_PIPE6: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE7: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE8: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_PBUSY_SHIFT, + USB_PIPEnCTR_6_8_PBUSY); + break; + + case USB_FUNCTION_PIPE9: + pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_PBUSY_SHIFT, + USB_PIPEnCTR_9_PBUSY); + break; + + case USB_FUNCTION_PIPEA: + pbusy = RZA_IO_RegRead_16(&USB201.PIPEACTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEB: + pbusy = RZA_IO_RegRead_16(&USB201.PIPEBCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEC: + pbusy = RZA_IO_RegRead_16(&USB201.PIPECCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPED: + pbusy = RZA_IO_RegRead_16(&USB201.PIPEDCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEE: + pbusy = RZA_IO_RegRead_16(&USB201.PIPEECTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + case USB_FUNCTION_PIPEF: + pbusy = RZA_IO_RegRead_16(&USB201.PIPEFCTR, + USB_PIPEnCTR_A_F_PBUSY_SHIFT, + USB_PIPEnCTR_A_F_PBUSY); + break; + + default: + pbusy = 1; + break; + } + + if (pbusy == 0) + { + break; + } + Userdef_USB_usb1_function_delay_500ns(); + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_pid_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_function_get_pid(pipe); + if (pid == DEVDRV_USBF_PID_BUF) + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + DEVDRV_USBF_PID_STALL2, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + DEVDRV_USBF_PID_STALL2, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + } + else + { + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + DEVDRV_USBF_PID_STALL, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + DEVDRV_USBF_PID_STALL, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name: usb1_function_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_pid_stall (uint16_t pipe) +{ + usb1_function_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb1_function_get_pid (uint16_t pipe) +{ + uint16_t pid; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + pid = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_PID_SHIFT, + USB_DCPCTR_PID); + break; + + case USB_FUNCTION_PIPE1: + pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE2: + pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE3: + pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE4: + pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE5: + pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_PID_SHIFT, + USB_PIPEnCTR_1_5_PID); + break; + + case USB_FUNCTION_PIPE6: + pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE7: + pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE8: + pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_PID_SHIFT, + USB_PIPEnCTR_6_8_PID); + break; + + case USB_FUNCTION_PIPE9: + pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_PID_SHIFT, + USB_PIPEnCTR_9_PID); + break; + + case USB_FUNCTION_PIPEA: + pid = RZA_IO_RegRead_16(&USB201.PIPEACTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEB: + pid = RZA_IO_RegRead_16(&USB201.PIPEBCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEC: + pid = RZA_IO_RegRead_16(&USB201.PIPECCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPED: + pid = RZA_IO_RegRead_16(&USB201.PIPEDCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEE: + pid = RZA_IO_RegRead_16(&USB201.PIPEECTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + case USB_FUNCTION_PIPEF: + pid = RZA_IO_RegRead_16(&USB201.PIPEFCTR, + USB_PIPEnCTR_A_F_PID_SHIFT, + USB_PIPEnCTR_A_F_PID); + break; + + default: + pid = 0; + break; + } + + return pid; +} + +/******************************************************************************* +* Function Name: usb1_function_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_csclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_CSCLR_SHIFT, + USB_DCPCTR_CSCLR); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_CSCLR_SHIFT, + USB_PIPEnCTR_1_5_CSCLR); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_CSCLR_SHIFT, + USB_PIPEnCTR_6_8_CSCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_CSCLR_SHIFT, + USB_PIPEnCTR_9_CSCLR); + break; + + default: + /* PIPEA-F have not CSCLR */ + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_sqclr (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_SQCLR_SHIFT, + USB_DCPCTR_SQCLR); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQCLR_SHIFT, + USB_PIPEnCTR_1_5_SQCLR); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQCLR_SHIFT, + USB_PIPEnCTR_6_8_SQCLR); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQCLR_SHIFT, + USB_PIPEnCTR_9_SQCLR); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_SQCLR_SHIFT, + USB_PIPEnCTR_A_F_SQCLR); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_function_set_sqset (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + RZA_IO_RegWrite_16(&USB201.DCPCTR, + 1, + USB_DCPCTR_SQSET_SHIFT, + USB_DCPCTR_SQSET); + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_SQSET_SHIFT, + USB_PIPEnCTR_1_5_SQSET); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_SQSET_SHIFT, + USB_PIPEnCTR_6_8_SQSET); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_SQSET_SHIFT, + USB_PIPEnCTR_9_SQSET); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_SQSET_SHIFT, + USB_PIPEnCTR_A_F_SQSET); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_get_sqmon +* Description : Toggle bit of specified pipe is obtained +* Arguments : uint16_t pipe ; Pipe number +* Return Value : sqmon +*******************************************************************************/ +uint16_t usb1_function_get_sqmon (uint16_t pipe) +{ + uint16_t sqmon; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR, + USB_DCPCTR_SQMON_SHIFT, + USB_DCPCTR_SQMON); + break; + + case USB_FUNCTION_PIPE1: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE2: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE3: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE4: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE5: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_SQMON_SHIFT, + USB_PIPEnCTR_1_5_SQMON); + break; + + case USB_FUNCTION_PIPE6: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE7: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE8: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR, + USB_PIPEnCTR_6_8_SQMON_SHIFT, + USB_PIPEnCTR_6_8_SQMON); + break; + + case USB_FUNCTION_PIPE9: + sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_SQMON_SHIFT, + USB_PIPEnCTR_9_SQMON); + break; + + case USB_FUNCTION_PIPEA: + sqmon = RZA_IO_RegRead_16(&USB201.PIPEACTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEB: + sqmon = RZA_IO_RegRead_16(&USB201.PIPEBCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEC: + sqmon = RZA_IO_RegRead_16(&USB201.PIPECCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPED: + sqmon = RZA_IO_RegRead_16(&USB201.PIPEDCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEE: + sqmon = RZA_IO_RegRead_16(&USB201.PIPEECTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + case USB_FUNCTION_PIPEF: + sqmon = RZA_IO_RegRead_16(&USB201.PIPEFCTR, + USB_PIPEnCTR_A_F_SQMON_SHIFT, + USB_PIPEnCTR_A_F_SQMON); + break; + + default: + sqmon = 0; + break; + } + + return sqmon; +} + +/******************************************************************************* +* Function Name: usb1_function_aclrm +* Description : The buffer of specified pipe is initialized +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_function_aclrm (uint16_t pipe) +{ + usb1_function_set_aclrm(pipe); + usb1_function_clr_aclrm(pipe); +} + +/******************************************************************************* +* Function Name: usb1_function_set_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_function_set_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 1, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 1, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 1, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + 1, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_clr_aclrm +* Description : The auto buffer clear mode of specified pipe is enabled +* Arguments : uint16_t pipe : Pipe +* Return Value : none +*******************************************************************************/ +void usb1_function_clr_aclrm (uint16_t pipe) +{ + switch (pipe) + { + case USB_FUNCTION_PIPE0: + break; + + case USB_FUNCTION_PIPE1: + RZA_IO_RegWrite_16(&USB201.PIPE1CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE2: + RZA_IO_RegWrite_16(&USB201.PIPE2CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE3: + RZA_IO_RegWrite_16(&USB201.PIPE3CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE4: + RZA_IO_RegWrite_16(&USB201.PIPE4CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE5: + RZA_IO_RegWrite_16(&USB201.PIPE5CTR, + 0, + USB_PIPEnCTR_1_5_ACLRM_SHIFT, + USB_PIPEnCTR_1_5_ACLRM); + break; + + case USB_FUNCTION_PIPE6: + RZA_IO_RegWrite_16(&USB201.PIPE6CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE7: + RZA_IO_RegWrite_16(&USB201.PIPE7CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE8: + RZA_IO_RegWrite_16(&USB201.PIPE8CTR, + 0, + USB_PIPEnCTR_6_8_ACLRM_SHIFT, + USB_PIPEnCTR_6_8_ACLRM); + break; + + case USB_FUNCTION_PIPE9: + RZA_IO_RegWrite_16(&USB201.PIPE9CTR, + 0, + USB_PIPEnCTR_9_ACLRM_SHIFT, + USB_PIPEnCTR_9_ACLRM); + break; + + case USB_FUNCTION_PIPEA: + RZA_IO_RegWrite_16(&USB201.PIPEACTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEB: + RZA_IO_RegWrite_16(&USB201.PIPEBCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEC: + RZA_IO_RegWrite_16(&USB201.PIPECCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPED: + RZA_IO_RegWrite_16(&USB201.PIPEDCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEE: + RZA_IO_RegWrite_16(&USB201.PIPEECTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + case USB_FUNCTION_PIPEF: + RZA_IO_RegWrite_16(&USB201.PIPEFCTR, + 0, + USB_PIPEnCTR_A_F_ACLRM_SHIFT, + USB_PIPEnCTR_A_F_ACLRM); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_get_inbuf +* Description : Returns INBUFM of the pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : inbuf +*******************************************************************************/ +uint16_t usb1_function_get_inbuf (uint16_t pipe) +{ + uint16_t inbuf; + + switch (pipe) + { + case USB_FUNCTION_PIPE0: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE1: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE2: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE3: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE4: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE5: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR, + USB_PIPEnCTR_1_5_INBUFM_SHIFT, + USB_PIPEnCTR_1_5_INBUFM); + break; + + case USB_FUNCTION_PIPE6: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE7: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE8: + inbuf = 0; + break; + + case USB_FUNCTION_PIPE9: + inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR, + USB_PIPEnCTR_9_INBUFM_SHIFT, + USB_PIPEnCTR_9_INBUFM); + break; + + case USB_FUNCTION_PIPEA: + inbuf = RZA_IO_RegRead_16(&USB201.PIPEACTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEB: + inbuf = RZA_IO_RegRead_16(&USB201.PIPEBCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEC: + inbuf = RZA_IO_RegRead_16(&USB201.PIPECCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPED: + inbuf = RZA_IO_RegRead_16(&USB201.PIPEDCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEE: + inbuf = RZA_IO_RegRead_16(&USB201.PIPEECTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + case USB_FUNCTION_PIPEF: + inbuf = RZA_IO_RegRead_16(&USB201.PIPEFCTR, + USB_PIPEnCTR_A_F_INBUFM_SHIFT, + USB_PIPEnCTR_A_F_INBUFM); + break; + + default: + inbuf = 0; + break; + } + + return inbuf; +} + +/******************************************************************************* +* Function Name: usb1_function_setting_interrupt +* Description : Sets the USB module interrupt level. +* Arguments : uint8_t level +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_setting_interrupt (uint8_t level) +{ + uint16_t d0fifo_dmaintid; + uint16_t d1fifo_dmaintid; + + R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_function_interrupt); + R_INTC_SetPriority(INTC_ID_USBI1, level); + R_INTC_Enable(INTC_ID_USBI1); + + d0fifo_dmaintid = Userdef_USB_usb1_function_d0fifo_dmaintid(); + + if (d0fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_function_dma_interrupt_d0fifo); + R_INTC_SetPriority(d0fifo_dmaintid, level); + R_INTC_Enable(d0fifo_dmaintid); + } + + d1fifo_dmaintid = Userdef_USB_usb1_function_d1fifo_dmaintid(); + + if (d1fifo_dmaintid != 0xFFFF) + { + R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_function_dma_interrupt_d1fifo); + R_INTC_SetPriority(d1fifo_dmaintid, level); + R_INTC_Enable(d1fifo_dmaintid); + } +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_reset_module +* Description : Initializes the USB module. +* : Enables providing clock to the USB module. +* : Sets USB bus wait register. +* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ +* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +void usb1_function_reset_module (uint16_t clockmode) +{ + /* UPLLE bit is only USB0 */ + if (RZA_IO_RegRead_16(&USB200.SYSCFG0, + USB_SYSCFG_UPLLE_SHIFT, + USB_SYSCFG_UPLLE) == 1) + { + if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode) + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB201.SYSCFG0 = 0; + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); + Userdef_USB_usb1_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + else + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + Userdef_USB_usb1_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + } + else + { + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 0, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + USB201.SYSCFG0 = 0; + USB200.SYSCFG0 = 0; + USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode); + Userdef_USB_usb1_function_delay_xms(1); + RZA_IO_RegWrite_16(&USB200.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + RZA_IO_RegWrite_16(&USB201.SUSPMODE, + 1, + USB_SUSPMODE_SUSPM_SHIFT, + USB_SUSPMODE_SUSPM); + } + + USB201.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT); +} + +/******************************************************************************* +* Function Name: usb1_function_get_buf_size +* Description : Obtains pipe buffer size specified by the argument and +* : maximum packet size of the USB device in use. +* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum +* : packet size of the USB device using the corresponding pipe. +* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the +* : corresponding pipe is in continuous transfer mode, +* : obtains the buffer size allocated in the corresponcing pipe, +* : when incontinuous transfer, obtains maximum packet size. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Maximum packet size or buffer size +*******************************************************************************/ +uint16_t usb1_function_get_buf_size (uint16_t pipe) +{ + uint16_t size; + uint16_t bufsize; + + if (pipe == USB_FUNCTION_PIPE0) + { + size = RZA_IO_RegRead_16(&USB201.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1) + { + bufsize = RZA_IO_RegRead_16(&g_usb1_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE); + size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF); + } + else + { + size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + } + return size; +} + +/******************************************************************************* +* Function Name: usb1_function_get_mxps +* Description : Obtains maximum packet size of the USB device using the pipe +* : specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Max Packet Size +*******************************************************************************/ +uint16_t usb1_function_get_mxps (uint16_t pipe) +{ + uint16_t size; + + if (pipe == USB_FUNCTION_PIPE0) + { + size = RZA_IO_RegRead_16(&USB201.DCPMAXP, + USB_DCPMAXP_MXPS_SHIFT, + USB_DCPMAXP_MXPS); + } + else + { + size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS); + } + return size; +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c new file mode 100644 index 0000000000..6edb9d2bf3 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c @@ -0,0 +1,441 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_api.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" +#include "dev_drv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_api_function_init +* Description : Initializes the USB module in the USB function mode. +* Arguments : uint8_t int_level ; interruput level +* : uint16_t mode : Speed modes +* : : USB_FUCNTION_HIGH_SPEED: High-speed device +* : : USB_FUCNTION_FULL_SPEED: Full-speed device +* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ +* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode) +{ + volatile uint8_t dummy_buf; + + CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */ + dummy_buf = CPG.STBCR7; /* (Dummy read) */ + + usb1_function_setting_interrupt(int_level); + + usb1_function_reset_module(clockmode); /* reset USB module with setting tranciever */ + /* and HSE=1 */ + + usb1_function_init_status(); /* clear variables */ + + usb1_function_InitModule(mode); /* select USB Function and Interrupt Enable */ + /* Detect USB Device to attach or detach */ +} +#endif + +/******************************************************************************* +* Function Name: usb1_api_function_IsConfigured +* Description : Checks if the USB device is configured to return the result as +* : the return value. +* Arguments : none +* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend +* : DEVDRV_USBF_NO : not Configured +*******************************************************************************/ +uint16_t usb1_api_function_IsConfigured (void) +{ + uint16_t dvst; + + dvst = usb1_function_GetDeviceState(); + + if ((dvst == USB_FUNCTION_DVST_CONFIGURED) || + (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND)) + { + return DEVDRV_USBF_YES; + } + + return DEVDRV_USBF_NO; +} + +/******************************************************************************* +* Function Name: usb1_function_GetDeviceState +* Description : Returns the state of USB device. +* Arguments : none +* Return Value : Device States +*******************************************************************************/ +uint16_t usb1_function_GetDeviceState (void) +{ + uint16_t dvsq; + uint16_t dvst; + + dvsq = USB201.INTSTS0; + switch (dvsq & USB_FUNCTION_BITDVSQ) + { + case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */ + dvst = USB_FUNCTION_DVST_POWERED; + break; + + case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */ + dvst = USB_FUNCTION_DVST_DEFAULT; + break; + + case USB_FUNCTION_DS_ADDS: /* Address state */ + dvst = USB_FUNCTION_DVST_ADDRESS; + break; + + case USB_FUNCTION_DS_CNFG: /* Configured state */ + dvst = USB_FUNCTION_DVST_CONFIGURED; + break; + + case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */ + dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND; + break; + + case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */ + case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */ + case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */ + dvst = USB_FUNCTION_DVST_SUSPEND; + break; + + default: /* error */ + dvst = USB_FUNCTION_DVST_SUSPEND; + break; + } + + return dvst; +} + +/******************************************************************************* +* Function Name: usb1_api_function_start_receive_transfer +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : none +*******************************************************************************/ +void usb1_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + usb1_function_start_receive_transfer(pipe, size, data); +} + +/******************************************************************************* +* Function Name: usb1_api_function_start_send_transfer +* Description : Starts the USB data communication using pipe specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t size ; Data Size +* : uint8_t *data ; Data data Address +* Return Value : DEVDRV_USBF_WRITEEND ; Write end +* : DEVDRV_USBF_WRITESHRT ; short data +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_WRITEDMA ; Write DMA +* : DEVDRV_USBF_FIFOERROR ; FIFO status +*******************************************************************************/ +uint16_t usb1_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data) +{ + uint16_t status; + + status = usb1_function_start_send_transfer(pipe, size, data); + + return status; +} + +/******************************************************************************* +* Function Name: usb1_api_function_check_pipe_status +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* : uint32_t *size ; Data Size +* Return Value : Pipe Status +*******************************************************************************/ +uint16_t usb1_api_function_check_pipe_status (uint16_t pipe, uint32_t * size) +{ + if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE) + { + *size = g_usb1_function_PipeDataSize[pipe]; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_DONE; + } + else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES) + { + *size = 0; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_NORES; + } + else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL) + { + *size = 0; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_PIPE_STALL; + } + else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR) + { + *size = 0; + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + + return DEVDRV_USBF_FIFOERROR; + } + else + { + /* Do Nothing */ + } + + return g_usb1_function_pipe_status[pipe]; +} + +/******************************************************************************* +* Function Name: usb1_api_function_clear_pipe_status +* Description : Starts USB data reception using the pipe specified in the argument. +* : The FIFO for using is set in the pipe definition table. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : Pipe Status +*******************************************************************************/ +void usb1_api_function_clear_pipe_status (uint16_t pipe) +{ + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb1_function_PipeDataSize[pipe] = 0; +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_pid_buf +* Description : Enables communicaqtion in the pipe specified by the argument +* : (BUF). +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_pid_buf (uint16_t pipe) +{ + usb1_function_set_pid_buf(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_pid_nak +* Description : Disables communication (NAK) in the pipe specified by the argument. +* : When the pipe status was enabling communication (BUF) before +* : executing before executing this function, waits in the software +* : until the pipe becomes ready after setting disabled. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_pid_nak (uint16_t pipe) +{ + usb1_function_set_pid_nak(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_pid_stall +* Description : Disables communication (STALL) in the pipe specified by the +* : argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_pid_stall (uint16_t pipe) +{ + usb1_function_set_pid_stall(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_clear_pid_stall +* Description : Disables communication (NAK) in the pipe specified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_clear_pid_stall (uint16_t pipe) +{ + usb1_function_clear_pid_stall(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_get_pid +* Description : Returns the pipe state specified by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +uint16_t usb1_api_function_get_pid (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_function_get_pid(pipe); + + return pid; +} + +/******************************************************************************* +* Function Name: usb1_api_function_check_stall +* Description : +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : PID +*******************************************************************************/ +int32_t usb1_api_function_check_stall (uint16_t pipe) +{ + uint16_t pid; + + pid = usb1_function_get_pid(pipe); + + if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL) + { + return DEVDRV_USBF_STALL; + } + + return DEVDRV_SUCCESS; +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_sqclr +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA0. +* Arguments : uint16_t pipe ; Pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_sqclr (uint16_t pipe) +{ + usb1_function_set_sqclr(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_sqset +* Description : Sets the sequence bit of the pipe specified by the argument to +* : DATA1. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_sqset (uint16_t pipe) +{ + usb1_function_set_sqset(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_csclr +* Description : CSPLIT status clear setting of sprit transaction in specified +* : pipe is performed. +* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit +* : in DCPCTR register are continuously changed (when the sequence +* : toggle bit of data PID is continuously changed over two or more pipes), +* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary. +* : Do not set both SQCLR bit and SQSET bit to 1 at the same time. +* : In addition, both bits should be operated after PID is set to NAK. +* : However, when it is set to the isochronous transfer as the transfer type +* : (TYPE=11), writing in SQSET bit is disabled. +* Arguments : uint16_t pipe ; Pipe number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_csclr (uint16_t pipe) +{ + usb1_function_set_csclr(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_set_curpipe +* Description : Allocates FIF0 specifed by the argument in the pipe assigned +* : by the argument. +* Arguments : uint16_t pipe ; Pipe Number +* : uint16_t fifosel ; Select FIFO +* : uint16_t isel ; FIFO Access Direction +* : uint16_t mbw ; FIFO Port Access Bit Width +* Return Value : none +*******************************************************************************/ +void usb1_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw) +{ + usb1_function_set_curpipe(pipe, fifosel, isel, mbw); +} + +/******************************************************************************* +* Function Name: usb1_api_function_clear_brdy_sts +* Description : Clear BRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_clear_brdy_sts (uint16_t pipe) +{ + usb1_function_clear_brdy_sts(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_clear_bemp_sts +* Description : Clear BEMP interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_clear_bemp_sts (uint16_t pipe) +{ + usb1_function_clear_bemp_sts(pipe); +} + +/******************************************************************************* +* Function Name: usb1_api_function_clear_nrdy_sts +* Description : Clear NRDY interrupt status in the pipe spceified by the argument. +* Arguments : uint16_t pipe ; pipe Number +* Return Value : none +*******************************************************************************/ +void usb1_api_function_clear_nrdy_sts (uint16_t pipe) +{ + usb1_function_clear_nrdy_sts(pipe); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c new file mode 100644 index 0000000000..45f8fa4858 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_controlrw.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_api_function_CtrlReadStart +* Description : Executes the USB control read transfer. +* : USB host controller <- USB device +* Arguments : uint16_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : DEVDRV_USBF_WRITEEND ; End of data write +* : DEVDRV_USBF_WRITESHRT ; End of short data write +* : DEVDRV_USBF_WRITING ; Continue of data write +* : DEVDRV_USBF_FIFOERROR ; FIFO access error +*******************************************************************************/ +uint16_t usb1_api_function_CtrlReadStart (uint32_t size, uint8_t * data) +{ + uint16_t status; + uint16_t mbw; + + usb1_function_set_pid_nak(USB_FUNCTION_PIPE0); + + g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size; + g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0], + (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; + + status = usb1_function_write_buffer_c(USB_FUNCTION_PIPE0); + + /* Peripheral Control sequence */ + switch (status) + { + case DEVDRV_USBF_WRITESHRT: /* End of data write */ + case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */ + case DEVDRV_USBF_WRITING: /* Continue of data write */ + usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */ + usb1_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */ + break; + + case DEVDRV_USBF_FIFOERROR: /* FIFO access error */ + break; + + default: + break; + } + + return status; /* End or Err or Continue */ +} + +/******************************************************************************* +* Function Name: usb1_api_function_CtrlWriteStart +* Description : Executes the USB control write transfer. +* : USB host controller -> USB device +* Arguments : uint16_t size ; Data Size +* : uint8_t *data ; Data Address +* Return Value : none +*******************************************************************************/ +void usb1_api_function_CtrlWriteStart (uint32_t size, uint8_t * data) +{ + uint16_t mbw; + + usb1_function_set_pid_nak(USB_FUNCTION_PIPE0); + + g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size; + g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data; + + mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0], + (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]); + usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw); + USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; + + usb1_function_enable_brdy_int(USB_FUNCTION_PIPE0); + usb1_function_set_pid_buf(USB_FUNCTION_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c new file mode 100644 index 0000000000..2ca4dac598 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c @@ -0,0 +1,144 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_global.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +const uint16_t g_usb1_function_bit_set[16] = +{ + 0x0001, 0x0002, 0x0004, 0x0008, + 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, + 0x1000, 0x2000, 0x4000, 0x8000 +}; + +uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint8_t * g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1]; + +uint16_t g_usb1_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb1_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb1_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint32_t g_usb1_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1]; + +USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[2]; +uint16_t g_usb1_function_DmaPipe[2]; +uint16_t g_usb1_function_DmaBval[2]; +uint16_t g_usb1_function_DmaStatus[2]; + +uint16_t g_usb1_function_CtrZeroLengthFlag; + +//uint16_t g_usb1_function_ConfigNum; +//uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO]; +//uint16_t g_usb1_function_RemoteWakeupFlag; +uint16_t g_usb1_function_TestModeFlag; +uint16_t g_usb1_function_TestModeSelectors; + +//uint16_t g_usb1_function_ReqType; +//uint16_t g_usb1_function_ReqTypeType; +//uint16_t g_usb1_function_ReqTypeRecip; +//uint16_t g_usb1_function_ReqRequest; +//uint16_t g_usb1_function_ReqValue; +//uint16_t g_usb1_function_ReqIndex; +//uint16_t g_usb1_function_ReqLength; + +//uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1]; + +uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1]; +uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1]; + + +/******************************************************************************* +* Function Name: usb1_function_init_status +* Description : Initialization USB Sample Driver Variable. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_init_status (void) +{ + uint16_t pipe; + + //g_usb1_function_ConfigNum = 0; + //g_usb1_function_RemoteWakeupFlag = DEVDRV_USBF_OFF; + g_usb1_function_TestModeFlag = DEVDRV_USBF_OFF; + g_usb1_function_CtrZeroLengthFlag = 0; + +#if 0 + usb1_function_clear_alt(); +#endif + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb1_function_PipeDataSize[pipe] = 0; + g_usb1_function_data_count[pipe] = 0; + + /* pipe configuration in usb1_function_ResetEP() */ + g_usb1_function_pipecfg[pipe] = 0; + g_usb1_function_pipebuf[pipe] = 0; + g_usb1_function_pipemaxp[pipe] = 0; + g_usb1_function_pipeperi[pipe] = 0; + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c new file mode 100644 index 0000000000..9c0b4af896 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c @@ -0,0 +1,330 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_sig.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_function_EnableINTModule(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_function_InitModule +* Description : Initializes the USB module in the USB function mode. +* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode +* : ; other ; Full-speed Mode +* Return Value : none +*******************************************************************************/ +void usb1_function_InitModule (uint16_t mode) +{ + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); /* USB function */ + + /* USB module operation enabled */ + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + if (mode == USB_FUNCTION_HIGH_SPEED) + { + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); /* Hi-Speed Mode */ + } + else + { + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_HSE_SHIFT, + USB_SYSCFG_HSE); + } + + /* for power-on */ + if (usb1_function_CheckVBUStaus() == DEVDRV_USBF_ON) + { + usb1_function_EnableINTModule(); /* Interrupt Enable */ + usb1_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */ + } + else + { + usb1_function_USB_FUNCTION_Detach(); /* USB Detach */ + /* with Interrupt Enable */ + } +} + +/******************************************************************************* +* Function Name: usb1_function_CheckVBUStaus +* Description : Checks the USB-VBUS state to returns the connection state to +* : the USB host. +* Arguments : none +* Return Value : DEVDRV_USBF_ON : VBUS ON +* : DEVDRV_USBF_OFF : VBUS OFF +*******************************************************************************/ +uint16_t usb1_function_CheckVBUStaus (void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + + /* monitor VBUS pins */ + do + { + buf1 = RZA_IO_RegRead_16(&USB201.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + Userdef_USB_usb1_function_delay_10us(1); + buf2 = RZA_IO_RegRead_16(&USB201.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + Userdef_USB_usb1_function_delay_10us(1); + buf3 = RZA_IO_RegRead_16(&USB201.INTSTS0, + USB_INTSTS0_VBSTS_SHIFT, + USB_INTSTS0_VBSTS); + } while ((buf1 != buf2) || (buf2 != buf3)); + + if (buf1 == DEVDRV_USBF_OFF) + { + return DEVDRV_USBF_OFF; /* detach */ + } + + return DEVDRV_USBF_ON; /* attach */ +} + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_Attach +* Description : Connects to the USB host controller. +* : This function pulls up D+. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_USB_FUNCTION_Attach (void) +{ + Userdef_USB_usb1_function_attach(); + + Userdef_USB_usb1_function_delay_xms(10); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_DPRPU_SHIFT, + USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */ +} + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_Detach +* Description : Disconnects from the USB host controller. +* : This function opens D+/D-. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_USB_FUNCTION_Detach (void) +{ + uint16_t pipe; + + Userdef_USB_usb1_function_detach(); + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE) + { + usb1_function_stop_transfer(pipe); + } + } + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_DPRPU_SHIFT, + USB_SYSCFG_DPRPU); /* open D+ and D- */ + + /* Detach Recovery */ + Userdef_USB_usb1_function_delay_500ns(); /* need 1us=500ns * 2 wait */ + Userdef_USB_usb1_function_delay_500ns(); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); + Userdef_USB_usb1_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */ + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_DCFM_SHIFT, + USB_SYSCFG_DCFM); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 0, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); /* soft reset module */ + Userdef_USB_usb1_function_delay_500ns(); + + RZA_IO_RegWrite_16(&USB201.SYSCFG0, + 1, + USB_SYSCFG_USBE_SHIFT, + USB_SYSCFG_USBE); + + usb1_function_EnableINTModule(); /* Interrupt Enable */ +} + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_BusReset +* Description : This function is executed when the USB device is transitioned +* : to POWERD_STATE. Sets the device descriptor according to the +* : connection speed determined by the USB reset hand shake. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb1_function_USB_FUNCTION_BusReset (void) +{ + usb1_function_init_status(); /* memory clear */ + + if (usb1_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) + { + usb1_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */ + } + else + { + usb1_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */ + } + + usb1_function_ResetDCP(); /* Default Control PIPE reset */ +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_Resume +* Description : This function is executed when the USB device detects a resume +* : signal. +* : The USB sample driver does not operate for this function. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb1_function_USB_FUNCTION_Resume (void) +{ + /* NOP */ +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_Suspend +* Description : This function is executed when the USB device detects a suspend +* : signal. +* : The USB sample driver does not operate for this function. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 /*The USBHAL in mbed does not need this function*/ +void usb1_function_USB_FUNCTION_Suspend (void) +{ + /* NOP */ +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_USB_FUNCTION_TestMode +* Description : This function is executed when the USB device is transitioned U +* : to TEST_MODE by the USB standard request. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_USB_FUNCTION_TestMode (void) +{ + switch (g_usb1_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT) + { + case USB_FUNCTION_FUNCTION_TEST_J: + case USB_FUNCTION_FUNCTION_TEST_K: + case USB_FUNCTION_FUNCTION_TEST_SE0_NAK: + case USB_FUNCTION_FUNCTION_TEST_PACKET: + RZA_IO_RegWrite_16(&USB201.TESTMODE, + (g_usb1_function_TestModeSelectors >> 8), + USB_TESTMODE_UTST_SHIFT, + USB_TESTMODE_UTST); + break; + + case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE: + default: + break; + } +} + +/******************************************************************************* +* Function Name: usb1_function_EnableINTModule +* Description : Enables USB interrupt. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void usb1_function_EnableINTModule (void) +{ + uint16_t buf; + + buf = USB201.INTENB0; + buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE | + USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE); + USB201.INTENB0 = buf; + + usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0); +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c new file mode 100644 index 0000000000..bdb548a5fe --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c @@ -0,0 +1,453 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_sub.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include "usb1_function.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +#if 0 +extern const uint16_t *g_usb1_function_EndPntPtr[]; +extern uint8_t g_usb1_function_DeviceDescriptor[]; +extern uint8_t *g_usb1_function_ConfigurationPtr[]; +#endif + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: usb1_function_ResetDCP +* Description : Initializes the default control pipe(DCP). +* Outline : Reset default control pipe +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_ResetDCP (void) +{ + USB201.DCPCFG = 0; +#if 0 + USB201.DCPMAXP = g_usb1_function_DeviceDescriptor[7]; +#else + USB201.DCPMAXP = 64; +#endif + + USB201.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB201.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); + USB201.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE); +} + +/******************************************************************************* +* Function Name: usb1_function_ResetEP +* Description : Initializes the end point. +* Arguments : uint16_t num ; Configuration Number +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_ResetEP (uint16_t num) +{ + uint16_t pipe; + uint16_t ep; + uint16_t index; + uint16_t buf; + uint16_t * tbl; + + tbl = (uint16_t *)(g_usb1_function_EndPntPtr[num - 1]); + + for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) + { + if (g_usb1_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR) + { + index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb1_function_EPTableIndex[ep]); + pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE); + + g_usb1_function_PipeTbl[pipe] = (uint16_t)(((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) | + ep | + (tbl[index + 0] & USB_FUNCTION_FIFO_USE)); + + if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT) + { + tbl[index + 1] |= USB_FUNCTION_SHTNAKON; +#ifdef __USB_DMA_BFRE_ENABLE__ + /* this routine cannnot be perfomred if read operation is executed in buffer size */ + if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) || + ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)) + { + tbl[index + 1] |= USB_FUNCTION_BFREON; + } +#endif + } + + /* Interrupt Disable */ + buf = USB201.BRDYENB; + buf &= (uint16_t)~g_usb1_function_bit_set[pipe]; + USB201.BRDYENB = buf; + buf = USB201.NRDYENB; + buf &= (uint16_t)~g_usb1_function_bit_set[pipe]; + USB201.NRDYENB = buf; + buf = USB201.BEMPENB; + buf &= (uint16_t)~g_usb1_function_bit_set[pipe]; + USB201.BEMPENB = buf; + + usb1_function_set_pid_nak(pipe); + + /* CurrentPIPE Clear */ + if (RZA_IO_RegRead_16(&USB201.CFIFOSEL, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB201.CFIFOSEL, + 0, + USB_CFIFOSEL_CURPIPE_SHIFT, + USB_CFIFOSEL_CURPIPE); + } + + if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, + 0, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE); + } + + if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE) == pipe) + { + RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, + 0, + USB_DnFIFOSEL_CURPIPE_SHIFT, + USB_DnFIFOSEL_CURPIPE); + } + + /* PIPE Configuration */ + USB201.PIPESEL = pipe; + USB201.PIPECFG = tbl[index + 1]; + USB201.PIPEBUF = tbl[index + 2]; + USB201.PIPEMAXP = tbl[index + 3]; + USB201.PIPEPERI = tbl[index + 4]; + + g_usb1_function_pipecfg[pipe] = tbl[index + 1]; + g_usb1_function_pipebuf[pipe] = tbl[index + 2]; + g_usb1_function_pipemaxp[pipe] = tbl[index + 3]; + g_usb1_function_pipeperi[pipe] = tbl[index + 4]; + + /* Buffer Clear */ + usb1_function_set_sqclr(pipe); + usb1_function_aclrm(pipe); + + /* init Global */ + g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE; + g_usb1_function_PipeDataSize[pipe] = 0; + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_EpToPipe +* Description : Returns the pipe which end point specified by the argument is +* : allocated to. +* Arguments : uint16_t ep ; Direction + Endpoint Number +* Return Value : USB_FUNCTION_EP_ERROR : Error +* : Others : Pipe Number +*******************************************************************************/ +uint16_t usb1_function_EpToPipe (uint16_t ep) +{ + uint16_t pipe; + + for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) + { + if ((g_usb1_function_PipeTbl[pipe] & 0x00ff) == ep) + { + return pipe; + } + } + + return USB_FUNCTION_EP_ERROR; +} + +/******************************************************************************* +* Function Name: usb1_function_InitEPTable +* Description : Sets the end point by the Alternate setting value of the +* : configuration number and the interface number specified by the +* : argument. +* Arguments : uint16_t Con_Num ; Configuration Number +* : uint16_t Int_Num ; Interface Number +* : uint16_t Alt_Num ; Alternate Setting +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num) +{ + uint8_t * ptr; + uint16_t point_interface; + uint16_t point_endpoint; + uint16_t length; + uint16_t start; + uint16_t numbers; + uint16_t endpoint; + + ptr = (uint8_t *)g_usb1_function_ConfigurationPtr[Con_Num - 1]; + point_interface = *ptr; + length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2)); + ptr += *ptr; + start = 0; + numbers = 0; + point_endpoint = 0; + + for (; point_interface < length;) + { + switch (*(ptr + 1)) /* Descriptor Type ? */ + { + case USB_FUNCTION_DT_INTERFACE: /* Interface */ + if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num)) + { + numbers = *(ptr + 4); + } + else + { + start += *(ptr + 4); + } + point_interface += *ptr; + ptr += *ptr; + break; + + case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ + if (point_endpoint < numbers) + { + endpoint = (uint16_t)(*(ptr + 2) & 0x0f); + g_usb1_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint); + ++point_endpoint; + } + point_interface += *ptr; + ptr += *ptr; + break; + + case USB_FUNCTION_DT_DEVICE: /* Device */ + case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ + case USB_FUNCTION_DT_STRING: /* String */ + default: /* Class, Vendor, else */ + point_interface += *ptr; + ptr += *ptr; + break; + } + } +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_GetConfigNum +* Description : Returns the number of configuration referring to the number of +* : configuration described in the device descriptor. +* Arguments : none +* Return Value : Number of possible configurations (bNumConfigurations). +*******************************************************************************/ +#if 0 +uint16_t usb1_function_GetConfigNum (void) +{ + return (uint16_t)g_usb1_function_DeviceDescriptor[17]; +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_GetInterfaceNum +* Description : Returns the number of interface referring to the number of +* : interface described in the configuration descriptor. +* Arguments : uint16_t num ; Configuration Number +* Return Value : Number of this interface (bNumInterfaces). +*******************************************************************************/ +#if 0 +uint16_t usb1_function_GetInterfaceNum (uint16_t num) +{ + return (uint16_t)(*(g_usb1_function_ConfigurationPtr[num - 1] + 4)); +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_GetAltNum +* Description : Returns the Alternate setting value of the configuration number +* : and the interface number specified by the argument. +* Arguments : uint16_t Con_Num ; Configuration Number +* : uint16_t Int_Num ; Interface Number +* Return Value : Value used to select this alternate setting(bAlternateSetting). +*******************************************************************************/ +#if 0 +uint16_t usb1_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num) +{ + uint8_t * ptr; + uint16_t point; + uint16_t alt_num = 0; + uint16_t length; + + ptr = (uint8_t *)(g_usb1_function_ConfigurationPtr[Con_Num - 1]); + point = ptr[0]; + ptr += ptr[0]; /* InterfaceDescriptor[0] */ + length = (uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 2)); + length |= (uint16_t)((uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8); + + for (; point < length;) /* Search Descriptor Table size */ + { + switch (ptr[1]) /* Descriptor Type ? */ + { + case USB_FUNCTION_DT_INTERFACE: /* Interface */ + if (Int_Num == ptr[2]) + { + alt_num = (uint16_t)ptr[3]; /* Alternate Number count */ + } + point += ptr[0]; + ptr += ptr[0]; + break; + + case USB_FUNCTION_DT_DEVICE: /* Device */ + case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */ + case USB_FUNCTION_DT_STRING: /* String */ + case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */ + default: /* Class, Vendor, else */ + point += ptr[0]; + ptr += ptr[0]; + break; + } + } + return alt_num; +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_CheckRemoteWakeup +* Description : Returns the result of the remote wake up function is supported +* : or not referring to the configuration descriptor. +* Arguments : none +* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup +* : DEVDRV_USBF_OFF : not Support Remote Wakeup +*******************************************************************************/ +#if 0 +uint16_t usb1_function_CheckRemoteWakeup (void) +{ + uint8_t atr; + + if (g_usb1_function_ConfigNum == 0) + { + return DEVDRV_USBF_OFF; + } + + atr = *(g_usb1_function_ConfigurationPtr[g_usb1_function_ConfigNum - 1] + 7); + + if (atr & USB_FUNCTION_CF_RWUP) + { + return DEVDRV_USBF_ON; + } + + return DEVDRV_USBF_OFF; +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_clear_alt +* Description : Initializes the Alternate setting area. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_clear_alt (void) +{ + int i; + + for (i = 0; i < USB_FUNCTION_ALT_NO; ++i) + { + g_usb1_function_Alternate[i] = 0; /* Alternate */ + } +} +#endif + +/******************************************************************************* +* Function Name: usb1_function_clear_pipe_tbl +* Description : Initializes pipe definition table. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void usb1_function_clear_pipe_tbl (void) +{ + int pipe; + + for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe) + { + g_usb1_function_PipeTbl[pipe] = 0; + } +} + +/******************************************************************************* +* Function Name: usb1_function_clear_ep_table_index +* Description : Initializes the end point table index. +* Arguments : none +* Return Value : none +*******************************************************************************/ +#if 0 +void usb1_function_clear_ep_table_index (void) +{ + int ep; + + for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep) + { + g_usb1_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR; + } +} +#endif + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c new file mode 100644 index 0000000000..809f682a03 --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c @@ -0,0 +1,698 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_dmacdrv.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_typedefs.h" +#include "iodefine.h" +#include "rza_io_regrw.h" +#include "usb1_function_dmacdrv.h" + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ + +/* ==== Request setting information for on-chip peripheral module ==== */ +typedef enum dmac_peri_req_reg_type +{ + DMAC_REQ_MID, + DMAC_REQ_RID, + DMAC_REQ_AM, + DMAC_REQ_LVL, + DMAC_REQ_REQD +} dmac_peri_req_reg_type_t; + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +/* ==== Prototype declaration ==== */ + +/* ==== Global variable ==== */ +/* On-chip peripheral module request setting table */ +static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] = +{ + /* MID,RID,AM,LVL,REQD */ + {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ + {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ + {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ + {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ + {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ + {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ + {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ + {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ +}; + + +/******************************************************************************* +* Function Name: usb1_function_DMAC3_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 1. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 1 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer +* : uint32_t request_factor : Factor for on-chip peripheral module request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit +* Return Value : none +*******************************************************************************/ +void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, + uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->daddr_dir, + DMAC3_CHCFG_n_DAD_SHIFT, + DMAC3_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->saddr_dir, + DMAC3_CHCFG_n_SAD_SHIFT, + DMAC3_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->dst_size, + DMAC3_CHCFG_n_DDS_SHIFT, + DMAC3_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + trans_info->src_size, + DMAC3_CHCFG_n_SDS_SHIFT, + DMAC3_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_DMS_SHIFT, + DMAC3_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_RSEL_SHIFT, + DMAC3_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_SBE_SHIFT, + DMAC3_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_DEM_SHIFT, + DMAC3_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_REN_SHIFT, + DMAC3_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_RSW_SHIFT, + DMAC3_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_REN_SHIFT, + DMAC3_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_RSW_SHIFT, + DMAC3_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_TM_SHIFT, + DMAC3_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 3, + DMAC3_CHCFG_n_SEL_SHIFT, + DMAC3_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 1, + DMAC3_CHCFG_n_HIEN_SHIFT, + DMAC3_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + 0, + DMAC3_CHCFG_n_LOEN_SHIFT, + DMAC3_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC3_CHCFG_n_AM_SHIFT, + DMAC3_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC3_CHCFG_n_LVL_SHIFT, + DMAC3_CHCFG_n_LVL); + + if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC3_CHCFG_n_REQD_SHIFT, + DMAC3_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, + req_direction, + DMAC3_CHCFG_n_REQD_SHIFT, + DMAC3_CHCFG_n_REQD); + } + + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC23_DMARS_CH3_RID_SHIFT, + DMAC23_DMARS_CH3_RID); + RZA_IO_RegWrite_32(&DMAC23.DMARS, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC23_DMARS_CH3_MID_SHIFT, + DMAC23_DMARS_CH3_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC3_Open +* Description : Enables DMAC channel 3 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb1_function_DMAC3_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_EN_SHIFT, + DMAC3_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_TACT_SHIFT, + DMAC3_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_SWRST_SHIFT, + DMAC3_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n, + DMAC3_CHCTRL_n_SWRST_SHIFT, + DMAC3_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_SETEN_SHIFT, + DMAC3_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_STG_SHIFT, + DMAC3_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC3_Close +* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb1_function_DMAC3_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, + 1, + DMAC3_CHCTRL_n_CLREN_SHIFT, + DMAC3_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_TACT_SHIFT, + DMAC3_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_EN_SHIFT, + DMAC3_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC3.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC3_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 3 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 3 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, + DMAC3_CHSTAT_n_SR_SHIFT, + DMAC3_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC3.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC3.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC3.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC3.N1TB_n = count; /* Total transfer byte count */ + } +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC4_PeriReqInit +* Description : Sets the register mode for DMA mode and the on-chip peripheral +* : module request for transfer request for DMAC channel 2. +* : Executes DMAC initial setting using the DMA information +* : specified by the argument *trans_info and the enabled/disabled +* : continuous transfer specified by the argument continuation. +* : Registers DMAC channel 2 interrupt handler function and sets +* : the interrupt priority level. Then enables transfer completion +* : interrupt. +* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC +* : : register +* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) +* : uint32_t continuation : Set continuous transfer to be valid +* : : after DMA transfer has been completed +* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer +* : DMAC_SAMPLE_SINGLE : Do not execute continuous +* : : transfer +* : uint32_t request_factor : Factor for on-chip peripheral module +* : : request +* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match +* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match +* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match +* : : +* : uint32_t req_direction : Setting value of CHCFG_n register +* : : REQD bit +*******************************************************************************/ +void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, + uint32_t dmamode, uint32_t continuation, + uint32_t request_factor, uint32_t req_direction) +{ + /* ==== Register mode ==== */ + if (DMAC_MODE_REGISTER == dmamode) + { + /* ==== Next0 register set ==== */ + DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ + DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ + DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */ + + /* DAD : Transfer destination address counting direction */ + /* SAD : Transfer source address counting direction */ + /* DDS : Transfer destination transfer size */ + /* SDS : Transfer source transfer size */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->daddr_dir, + DMAC4_CHCFG_n_DAD_SHIFT, + DMAC4_CHCFG_n_DAD); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->saddr_dir, + DMAC4_CHCFG_n_SAD_SHIFT, + DMAC4_CHCFG_n_SAD); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->dst_size, + DMAC4_CHCFG_n_DDS_SHIFT, + DMAC4_CHCFG_n_DDS); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + trans_info->src_size, + DMAC4_CHCFG_n_SDS_SHIFT, + DMAC4_CHCFG_n_SDS); + + /* DMS : Register mode */ + /* RSEL : Select Next0 register set */ + /* SBE : No discharge of buffer data when aborted */ + /* DEM : No DMA interrupt mask */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_DMS_SHIFT, + DMAC4_CHCFG_n_DMS); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_RSEL_SHIFT, + DMAC4_CHCFG_n_RSEL); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_SBE_SHIFT, + DMAC4_CHCFG_n_SBE); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_DEM_SHIFT, + DMAC4_CHCFG_n_DEM); + + /* ---- Continuous transfer ---- */ + if (DMAC_SAMPLE_CONTINUATION == continuation) + { + /* REN : Execute continuous transfer */ + /* RSW : Change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_REN_SHIFT, + DMAC4_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_RSW_SHIFT, + DMAC4_CHCFG_n_RSW); + } + /* ---- Single transfer ---- */ + else + { + /* REN : Do not execute continuous transfer */ + /* RSW : Do not change register set when DMA transfer is completed. */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_REN_SHIFT, + DMAC4_CHCFG_n_REN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_RSW_SHIFT, + DMAC4_CHCFG_n_RSW); + } + + /* TM : Single transfer */ + /* SEL : Channel setting */ + /* HIEN, LOEN : On-chip peripheral module request */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_TM_SHIFT, + DMAC4_CHCFG_n_TM); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 4, + DMAC4_CHCFG_n_SEL_SHIFT, + DMAC4_CHCFG_n_SEL); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 1, + DMAC4_CHCFG_n_HIEN_SHIFT, + DMAC4_CHCFG_n_HIEN); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + 0, + DMAC4_CHCFG_n_LOEN_SHIFT, + DMAC4_CHCFG_n_LOEN); + + /* ---- Set factor by specified on-chip peripheral module request ---- */ + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], + DMAC4_CHCFG_n_AM_SHIFT, + DMAC4_CHCFG_n_AM); + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], + DMAC4_CHCFG_n_LVL_SHIFT, + DMAC4_CHCFG_n_LVL); + if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) + { + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], + DMAC4_CHCFG_n_REQD_SHIFT, + DMAC4_CHCFG_n_REQD); + } + else + { + RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, + req_direction, + DMAC4_CHCFG_n_REQD_SHIFT, + DMAC4_CHCFG_n_REQD); + } + RZA_IO_RegWrite_32(&DMAC45.DMARS, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], + DMAC45_DMARS_CH4_RID_SHIFT, + DMAC45_DMARS_CH4_RID); + RZA_IO_RegWrite_32(&DMAC45.DMARS, + usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], + DMAC45_DMARS_CH4_MID_SHIFT, + DMAC45_DMARS_CH4_MID); + + /* PR : Round robin mode */ + RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, + 1, + DMAC07_DCTRL_0_7_PR_SHIFT, + DMAC07_DCTRL_0_7_PR); + } +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC4_Open +* Description : Enables DMAC channel 4 transfer. +* Arguments : uint32_t req : DMAC request mode +* Return Value : 0 : Succeeded in enabling DMA transfer +* : -1 : Failed to enable DMA transfer (due to DMA operation) +*******************************************************************************/ +int32_t usb1_function_DMAC4_Open (uint32_t req) +{ + int32_t ret; + volatile uint8_t dummy; + + /* Transferable? */ + if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_EN_SHIFT, + DMAC4_CHSTAT_n_EN)) && + (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_TACT_SHIFT, + DMAC4_CHSTAT_n_TACT))) + { + /* Clear Channel Status Register */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_SWRST_SHIFT, + DMAC4_CHCTRL_n_SWRST); + dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n, + DMAC4_CHCTRL_n_SWRST_SHIFT, + DMAC4_CHCTRL_n_SWRST); + /* Enable DMA transfer */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_SETEN_SHIFT, + DMAC4_CHCTRL_n_SETEN); + + /* ---- Request by software ---- */ + if (DMAC_REQ_MODE_SOFT == req) + { + /* DMA transfer Request by software */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_STG_SHIFT, + DMAC4_CHCTRL_n_STG); + } + + ret = 0; + } + else + { + ret = -1; + } + + return ret; +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC4_Close +* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer +* : byte count at the time of DMA transfer abort to the argument +* : *remain. +* Arguments : uint32_t * remain : Remaining transfer byte count when +* : : DMA transfer is aborted +* Return Value : none +*******************************************************************************/ +void usb1_function_DMAC4_Close (uint32_t * remain) +{ + + /* ==== Abort transfer ==== */ + RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, + 1, + DMAC4_CHCTRL_n_CLREN_SHIFT, + DMAC4_CHCTRL_n_CLREN); + + while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_TACT_SHIFT, + DMAC4_CHSTAT_n_TACT)) + { + /* Loop until transfer is aborted */ + } + + while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_EN_SHIFT, + DMAC4_CHSTAT_n_EN)) + { + /* Loop until 0 is set in EN before checking the remaining transfer byte count */ + } + /* ==== Obtain remaining transfer byte count ==== */ + *remain = DMAC4.CRTB_n; +} + +/******************************************************************************* +* Function Name: usb1_function_DMAC4_Load_Set +* Description : Sets the transfer source address, transfer destination +* : address, and total transfer byte count respectively +* : specified by the argument src_addr, dst_addr, and count to +* : DMAC channel 4 as DMA transfer information. +* : Sets the register set selected by the CHCFG_n register +* : RSEL bit from the Next0 or Next1 register set. +* : This function should be called when DMA transfer of DMAC +* : channel 4 is aboted. +* Arguments : uint32_t src_addr : Transfer source address +* : uint32_t dst_addr : Transfer destination address +* : uint32_t count : Total transfer byte count +* Return Value : none +*******************************************************************************/ +void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) +{ + uint8_t reg_set; + + /* Obtain register set in use */ + reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, + DMAC4_CHSTAT_n_SR_SHIFT, + DMAC4_CHSTAT_n_SR); + + /* ==== Load ==== */ + if (0 == reg_set) + { + /* ---- Next0 Register Set ---- */ + DMAC4.N0SA_n = src_addr; /* Start address of transfer source */ + DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */ + DMAC4.N0TB_n = count; /* Total transfer byte count */ + } + else + { + /* ---- Next1 Register Set ---- */ + DMAC4.N1SA_n = src_addr; /* Start address of transfer source */ + DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */ + DMAC4.N1TB_n = count; /* Total transfer byte count */ + } +} + +/* End of File */ diff --git a/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c new file mode 100644 index 0000000000..77c62132dc --- /dev/null +++ b/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c @@ -0,0 +1,762 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb1_function_userdef.c +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Device(s) : RZ/A1H +* Tool-Chain : +* OS : None +* H/W Platform : +* Description : RZ/A1H R7S72100 USB Sample Program +* Operation : +* Limitations : +*******************************************************************************/ + + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_typedefs.h" +#include "iodefine.h" +#include "devdrv_usb_function_api.h" +#include "usb1_function_dmacdrv.h" /* common DMAC driver for USB */ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DUMMY_ACCESS OSTM0CNT + +/* #define CACHE_WRITEBACK */ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int32_t io_cwb(unsigned long start, unsigned long end); + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +static void usb1_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void usb1_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc); +static void Userdef_USB_usb1_function_delay_10us_2(void); + + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_d0fifo_dmaintid +* Description : get D0FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D0FIFO DMA Interrupt ID +*******************************************************************************/ +IRQn_Type Userdef_USB_usb1_function_d0fifo_dmaintid (void) +{ +#if 0 + return DMAINT1_IRQn; +#else + return 0xFFFF; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_d1fifo_dmaintid +* Description : get D1FIFO DMA Interrupt ID +* Arguments : none +* Return Value : D1FIFO DMA Interrupt ID +*******************************************************************************/ +IRQn_Type Userdef_USB_usb1_function_d1fifo_dmaintid (void) +{ +#if 0 + return DMAINT1_IRQn; +#else + return 0xFFFF; +#endif +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_attach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_attach (void) +{ + printf("\n"); + printf("channel 1 attach device\n"); + printf("\n"); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_detach +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_detach (void) +{ + printf("\n"); + printf("channel 1 detach device\n"); + printf("\n"); +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_delay_1ms +* Description : Wait for the software of 1ms. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_delay_1ms (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* + * Wait 1ms (Please change for your MCU). + */ + for (i = 0; i < 1440; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_delay_xms +* Description : Wait for the software in the period of time specified by the +* : argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t msec ; Wait Time (msec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_delay_xms (uint32_t msec) +{ + volatile unsigned short i; + + for (i = 0; i < msec; ++i) + { + Userdef_USB_usb1_function_delay_1ms(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_delay_10us +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : uint32_t usec ; Wait Time(x 10usec) +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_delay_10us (uint32_t usec) +{ + volatile int i; + + /* Wait 10us (Please change for your MCU) */ + for (i = 0; i < usec; ++i) + { + Userdef_USB_usb1_function_delay_10us_2(); + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_delay_10us_2 +* Description : Waits for software for the period specified by the argument. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void Userdef_USB_usb1_function_delay_10us_2 (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 1us (Please change for your MCU) */ + for (i = 0; i < 14; ++i) + { + tmp = DUMMY_ACCESS; + } +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_delay_500ns +* Description : Wait for software for 500ns. +* : Alter this function according to the user's system. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_delay_500ns (void) +{ + volatile int i; + volatile unsigned long tmp; + + /* Wait 500ns (Please change for your MCU) */ + /* Wait 500ns I clock 266MHz */ + tmp = DUMMY_ACCESS; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_start_dma +* Description : Enables DMA transfer on the information specified by the argument. +* : Set DMAC register by this function to enable DMA transfer. +* : After executing this function, USB module is set to start DMA +* : transfer. DMA transfer should not wait for DMA transfer complete. +* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter +* : typedef struct{ +* : uint32_t fifo; FIFO for using +* : uint32_t buffer; Start address of transfer source/destination +* : uint32_t bytes; Transfer size(Byte) +* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer) +* : uint32_t size; DMA transfer size +* : } USB_FUNCTION_DMA_t; +* : uint16_t dfacc ; 0 : cycle steal mode +* : 1 : 16byte continuous mode +* : 2 : 32byte continuous mode +* Return Value : none +*******************************************************************************/ +void Userdef_USB_usb1_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc) +{ + uint32_t trncount; + uint32_t src; + uint32_t dst; + uint32_t size; + uint32_t dir; +#ifdef CACHE_WRITEBACK + uint32_t ptr; +#endif + + trncount = dma->bytes; + dir = dma->dir; + + if (dir == USB_FUNCTION_FIFO2BUF) + { + /* DxFIFO determination */ + dst = dma->buffer; +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + src += 3; /* byte access */ + } + else if (size == 1) + { + src += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB201.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + src = (uint32_t)(&USB201.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + src += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + src = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + src = (uint32_t)(&USB201.D1FIFO.UINT32); + } + src += 3; /* byte access */ + } +#endif + } + else + { + /* DxFIFO determination */ + src = dma->buffer; +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + size = dma->size; + + if (size == 0) + { + dst += 3; /* byte access */ + } + else if (size == 1) + { + dst += 2; /* short access */ + } + else + { + /* Do Nothing */ + } +#else + size = dma->size; + + if (size == 2) + { + /* 32bit access */ + if (dfacc == 2) + { + /* 32byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB201.D1FIFOB0); + } + } + else if (dfacc == 1) + { + /* 16byte access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFOB0); + } + else + { + dst = (uint32_t)(&USB201.D1FIFOB0); + } + } + else + { + /* normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + } + } + else if (size == 1) + { + /* 16bit access */ + dfacc = 0; /* force normal access */ + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + dst += 2; /* short access */ + } + else + { + /* 8bit access */ + dfacc = 0; /* force normal access */ + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + dst = (uint32_t)(&USB201.D0FIFO.UINT32); + } + else + { + dst = (uint32_t)(&USB201.D1FIFO.UINT32); + } + dst += 3; /* byte access */ + } +#endif + } + +#ifdef CACHE_WRITEBACK + ptr = (uint32_t)dma->buffer; + + if ((ptr & 0x20000000ul) == 0) + { + io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount); + } +#endif + + if (dma->fifo == USB_FUNCTION_D0FIFO_DMA) + { + usb1_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc); + } + else + { + usb1_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc); + } +} + +/******************************************************************************* +* Function Name: usb1_function_enable_dmac0 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb1_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } + } +#endif + + if (dir == USB_FUNCTION_FIFO2BUF) + { + request_factor =DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_FUNCTION_BUF2FIFO) + { + request_factor =DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb1_function_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in + usb1_function_DMAC3_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb1_function_DMAC3_Open(DMAC_REQ_MODE_PERI); + if (ret != 0) + { + printf("DMAC3 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: usb1_function_enable_dmac1 +* Description : Enables DMA transfer on the information specified by the argument. +* Arguments : uint32_t src : src address +* : uint32_t dst : dst address +* : uint32_t count : transfer byte +* : uint32_t size : transfer size +* : uint32_t dir : direction +* : uint32_t fifo : FIFO(D0FIFO or D1FIFO) +* : uint16_t dfacc : 0 : normal access +* : : 1 : 16byte access +* : : 2 : 32byte access +* Return Value : none +*******************************************************************************/ +static void usb1_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count, + uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc) +{ + dmac_transinfo_t trans_info; + uint32_t request_factor = 0; + int32_t ret; + + /* ==== Variable setting for DMAC initialization ==== */ + trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */ + trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */ + trans_info.count = (uint32_t)count; /* Total byte count to be transferred */ +#ifndef __USB_FUNCTION_DF_ACC_ENABLE__ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } +#else + if (dfacc == 2) + { + /* 32byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */ + } + else if (dfacc == 1) + { + /* 16byte access */ + trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */ + } + else + { + /* normal access */ + if (size == 0) + { + trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */ + } + else if (size == 1) + { + trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */ + } + else if (size == 2) + { + trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */ + trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */ + } + else + { + printf("size error!!\n"); + } + } +#endif + + if (dir == USB_FUNCTION_FIFO2BUF) + { + request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */ + trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */ + } + else if (dir == USB_FUNCTION_BUF2FIFO) + { + request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */ + trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */ + trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */ + } + else + { + /* Do Nothing */ + } + + /* ==== DMAC initialization ==== */ + usb1_function_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info, + DMAC_MODE_REGISTER, + DMAC_SAMPLE_SINGLE, + request_factor, + 0); /* Don't care DMAC_REQ_REQD is setting in + usb1_function_DMAC4_PeriReqInit() */ + + /* ==== DMAC startup ==== */ + ret = usb1_function_DMAC4_Open(DMAC_REQ_MODE_PERI); + if (ret != 0) + { + printf("DMAC4 Open error!!\n"); + } + + return; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_stop_dma0 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D0_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb1_function_stop_dma0 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb1_function_DMAC3_Close(&remain); + + return remain; +} + +/******************************************************************************* +* Function Name: Userdef_USB_usb1_function_stop_dma1 +* Description : Disables DMA transfer. +* : This function should be executed to DMAC executed at the time +* : of specification of D1_FIF0_DMA in dma->fifo. +* Arguments : none +* Return Value : uint32_t return Transfer Counter register(DMATCRn) value +* : regarding to the bus width. +*******************************************************************************/ +uint32_t Userdef_USB_usb1_function_stop_dma1 (void) +{ + uint32_t remain; + + /* ==== DMAC release ==== */ + usb1_function_DMAC4_Close(&remain); + + return remain; +} + +/* End of File */ From 04d5c19e690376d3311e0b52ff268e665940d0c4 Mon Sep 17 00:00:00 2001 From: Rob Meades Date: Mon, 23 Mar 2015 14:58:30 +0000 Subject: [PATCH 033/143] Vector table must be 256 aligned The vector table must be 256 aligned to work reliably, it must have been working by accident up to now. This modification tested on a u-blox c027 board. Without the change the value of `SCB->VTOR` and int_table are as follows: `SCB->VTOR 0x10000280, int_table 0x100002a0` ...with the change they are as follows: `SCB->VTOR 0x10000400, int_table 0x10000400` ...and the test passes. See issue: https://github.com/mbedmicro/mbed/issues/992 --- libraries/tests/mbed/vtor_reloc/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/tests/mbed/vtor_reloc/main.cpp b/libraries/tests/mbed/vtor_reloc/main.cpp index e43c179c7a..c7e654e8c0 100644 --- a/libraries/tests/mbed/vtor_reloc/main.cpp +++ b/libraries/tests/mbed/vtor_reloc/main.cpp @@ -14,7 +14,7 @@ DigitalOut out(PIN_OUT); DigitalOut myled(LED1); volatile int checks = 0; -uint32_t int_table[NUM_VECTORS]; +uint32_t int_table[NUM_VECTORS] __attribute__ ((aligned(256))); #define FALLING_EDGE_COUNT 5 From 31a3cff74d44e979ddcd90c2652116973ac29bc7 Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 20 Mar 2015 11:10:03 +0100 Subject: [PATCH 034/143] [NUCLEO_F091RC/F303RE] Fix wrong detect_code field --- workspace_tools/targets.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index b6dba7b2c4..69959e0749 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -513,7 +513,7 @@ class NUCLEO_F091RC(Target): self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = ["0731"] + self.detect_code = ["0750"] class NUCLEO_F103RB(Target): def __init__(self): @@ -543,7 +543,7 @@ class NUCLEO_F303RE(Target): self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] - self.detect_code = ["0706"] + self.detect_code = ["0745"] class NUCLEO_F334R8(Target): def __init__(self): From 8d8b485ce7ab7e4f358a895307f2d9e666b1fb1c Mon Sep 17 00:00:00 2001 From: Clement Leger Date: Tue, 24 Mar 2015 10:29:32 +0100 Subject: [PATCH 035/143] USBDevice: fix missing defined check for TARGET_F411RE --- libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp b/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp index 2bfa9d627a..8faac61704 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp @@ -48,7 +48,7 @@ USBHAL::USBHAL(void) { // Enable power and clocking RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; -#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) +#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS)); pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); From 40ccdd5b1f5c79e2fe0706b00f23c08fa714ba1a Mon Sep 17 00:00:00 2001 From: Power User Date: Wed, 25 Mar 2015 13:03:50 +0100 Subject: [PATCH 036/143] ISSUE #996 Fixed linux paths for IAR exporter --- workspace_tools/export/iar.py | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 6c3ea0d0ca..4b65e3d88d 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -16,7 +16,8 @@ limitations under the License. """ from exporters import Exporter import re - +import os +from os.path import join, dirname class IAREmbeddedWorkbench(Exporter): NAME = 'IAR' TOOLCHAIN = 'IAR' @@ -115,7 +116,7 @@ class IAR_FOLDER: #Add files in current folder if self.source_files: for src in self.source_files: - str_content += "\n$PROJ_DIR$\\%s\n\n" % src + str_content += "\n$PROJ_DIR$/%s\n\n" % src ##Add sub folders if self.sub_folders: for folder_name in self.sub_folders.iterkeys(): @@ -126,12 +127,13 @@ class IAR_FOLDER: def insert_file(self, source_input): - if self.source_files: + + if self.source_files: dir_sources = IAR_FOLDER.get_directory(self.source_files[0]) ##All source_files in a IAR_FOLDER must be in same directory. if not self.folder_level == dir_sources: ## Check if sources are already at their deepest level. _reg_exp = r"^" + re.escape(self.folder_level) + r"[/\\]?([^/\\]+)" - folder_name = re.match( _reg_exp, dir_sources).group(1) - self.sub_folders[folder_name] = IAR_FOLDER(self.folder_level + "\\" + folder_name, folder_name, self.source_files) + folder_name = re.match( _reg_exp, dir_sources).group(1) + self.sub_folders[folder_name] = IAR_FOLDER(os.path.join(self.folder_level,folder_name), folder_name, self.source_files) self.source_files = [] dir_input = IAR_FOLDER.get_directory(source_input) @@ -146,14 +148,10 @@ class IAR_FOLDER: if self.folder_level == "": #Top level exception self.sub_folders[folder_name] = IAR_FOLDER(folder_name, folder_name, [source_input]) else: - self.sub_folders[folder_name] = IAR_FOLDER(self.folder_level + "\\" + folder_name, folder_name, [source_input]) + self.sub_folders[folder_name] = IAR_FOLDER(os.path.join(self.folder_level,folder_name), folder_name, [source_input]) @staticmethod def get_directory(file_path): - dir_Match = re.match( r'(.*)[/\\][^/\\]+', file_path) - if dir_Match is not None: - return dir_Match.group(1) - else: - return "" + return os.path.dirname(file_path) + - \ No newline at end of file From 7a68bd3b7830c1ee2fc73115f78cdea1c345beed Mon Sep 17 00:00:00 2001 From: dinau Date: Wed, 25 Mar 2015 21:29:02 +0900 Subject: [PATCH 037/143] [DISCO_F100RB] Support HAL driver --- .../startup_stm32f10x_md_vl.s | 398 - .../TARGET_STM/TARGET_DISCO_F100RB/misc.c | 240 - .../TARGET_STM/TARGET_DISCO_F100RB/misc.h | 235 - .../TARGET_DISCO_F100RB/stm32f10x.h | 8397 ----------------- .../TARGET_DISCO_F100RB/stm32f10x_adc.c | 1322 --- .../TARGET_DISCO_F100RB/stm32f10x_adc.h | 498 - .../TARGET_DISCO_F100RB/stm32f10x_bkp.c | 323 - .../TARGET_DISCO_F100RB/stm32f10x_bkp.h | 210 - .../TARGET_DISCO_F100RB/stm32f10x_can.c | 1430 --- .../TARGET_DISCO_F100RB/stm32f10x_can.h | 712 -- .../TARGET_DISCO_F100RB/stm32f10x_cec.c | 448 - .../TARGET_DISCO_F100RB/stm32f10x_cec.h | 225 - .../TARGET_DISCO_F100RB/stm32f10x_conf.h | 92 - .../TARGET_DISCO_F100RB/stm32f10x_crc.c | 175 - .../TARGET_DISCO_F100RB/stm32f10x_dac.c | 586 -- .../TARGET_DISCO_F100RB/stm32f10x_dac.h | 332 - .../TARGET_DISCO_F100RB/stm32f10x_dbgmcu.c | 177 - .../TARGET_DISCO_F100RB/stm32f10x_dbgmcu.h | 134 - .../TARGET_DISCO_F100RB/stm32f10x_dma.c | 729 -- .../TARGET_DISCO_F100RB/stm32f10x_dma.h | 454 - .../TARGET_DISCO_F100RB/stm32f10x_exti.c | 284 - .../TARGET_DISCO_F100RB/stm32f10x_exti.h | 199 - .../TARGET_DISCO_F100RB/stm32f10x_flash.c | 1694 ---- .../TARGET_DISCO_F100RB/stm32f10x_flash.h | 441 - .../TARGET_DISCO_F100RB/stm32f10x_fsmc.c | 881 -- .../TARGET_DISCO_F100RB/stm32f10x_fsmc.h | 748 -- .../TARGET_DISCO_F100RB/stm32f10x_gpio.c | 665 -- .../TARGET_DISCO_F100RB/stm32f10x_gpio.h | 400 - .../TARGET_DISCO_F100RB/stm32f10x_i2c.c | 1346 --- .../TARGET_DISCO_F100RB/stm32f10x_i2c.h | 699 -- .../TARGET_DISCO_F100RB/stm32f10x_iwdg.c | 205 - .../TARGET_DISCO_F100RB/stm32f10x_iwdg.h | 155 - .../TARGET_DISCO_F100RB/stm32f10x_pwr.c | 322 - .../TARGET_DISCO_F100RB/stm32f10x_pwr.h | 171 - .../TARGET_DISCO_F100RB/stm32f10x_rcc.c | 1485 --- .../TARGET_DISCO_F100RB/stm32f10x_rcc.h | 742 -- .../TARGET_DISCO_F100RB/stm32f10x_rtc.c | 367 - .../TARGET_DISCO_F100RB/stm32f10x_rtc.h | 150 - .../TARGET_DISCO_F100RB/stm32f10x_sdio.c | 813 -- .../TARGET_DISCO_F100RB/stm32f10x_sdio.h | 546 -- .../TARGET_DISCO_F100RB/stm32f10x_spi.c | 923 -- .../TARGET_DISCO_F100RB/stm32f10x_spi.h | 502 - .../TARGET_DISCO_F100RB/stm32f10x_tim.c | 2905 ------ .../TARGET_DISCO_F100RB/stm32f10x_tim.h | 1179 --- .../TARGET_DISCO_F100RB/stm32f10x_usart.c | 1074 --- .../TARGET_DISCO_F100RB/stm32f10x_usart.h | 438 - .../TARGET_DISCO_F100RB/stm32f10x_wwdg.c | 239 - .../TARGET_DISCO_F100RB/stm32f10x_wwdg.h | 130 - .../TARGET_DISCO_F100RB/system_stm32f10x.c | 1109 --- .../TOOLCHAIN_GCC_ARM/STM32F100.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s | 423 + .../TARGET_DISCO_F100RB/cmsis.h | 2 +- .../TARGET_DISCO_F100RB/cmsis_nvic.c | 0 .../TARGET_DISCO_F100RB/cmsis_nvic.h | 6 +- .../TARGET_DISCO_F100RB/hal_tick.c | 145 + .../TARGET_DISCO_F100RB/hal_tick.h | 60 + .../TARGET_DISCO_F100RB/stm32f100xb.h | 4073 ++++++++ .../TARGET_DISCO_F100RB/stm32f1xx.h | 238 + .../TARGET_DISCO_F100RB/system_stm32f1xx.c | 603 ++ .../TARGET_DISCO_F100RB/system_stm32f1xx.h | 116 + .../TARGET_DISCO_F100RB/PeripheralNames.h | 4 +- .../TARGET_DISCO_F100RB/PeripheralPins.c | 165 + .../TARGET_DISCO_F100RB/PeripheralPins.h} | 91 +- .../TARGET_STM/TARGET_DISCO_F100RB/PinNames.h | 23 +- .../TARGET_DISCO_F100RB/analogin_api.c | 140 +- .../TARGET_STM/TARGET_DISCO_F100RB/device.h | 9 +- .../TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c | 25 +- .../TARGET_DISCO_F100RB/gpio_irq_api.c | 257 +- .../TARGET_DISCO_F100RB/gpio_object.h | 9 +- .../TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c | 341 +- .../TARGET_DISCO_F100RB/mbed_overrides.c} | 90 +- .../TARGET_STM/TARGET_DISCO_F100RB/objects.h | 8 + .../TARGET_STM/TARGET_DISCO_F100RB/pinmap.c | 120 +- .../TARGET_STM/TARGET_DISCO_F100RB/port_api.c | 28 +- .../TARGET_DISCO_F100RB/pwmout_api.c | 185 +- .../TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c | 181 +- .../TARGET_DISCO_F100RB/serial_api.c | 262 +- .../TARGET_STM/TARGET_DISCO_F100RB/sleep.c | 34 +- .../TARGET_STM/TARGET_DISCO_F100RB/spi_api.c | 293 +- .../TARGET_DISCO_F100RB/us_ticker.c | 109 +- 80 files changed, 7154 insertions(+), 38815 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f10x_md_vl.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_conf.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.c rename libraries/mbed/targets/cmsis/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld (100%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s rename libraries/mbed/targets/cmsis/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/cmsis.h (98%) rename libraries/mbed/targets/cmsis/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/cmsis_nvic.h (92%) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c rename libraries/mbed/targets/{cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.h => hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h} (58%) rename libraries/mbed/targets/{cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.h => hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c} (51%) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f10x_md_vl.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f10x_md_vl.s deleted file mode 100644 index 2c729afb7f..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f10x_md_vl.s +++ /dev/null @@ -1,398 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_md_vl.s - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl _start - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x01CC. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices. */ - -/******************************************************************************* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.c deleted file mode 100644 index e1eb6d6551..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.c +++ /dev/null @@ -1,240 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/** @defgroup MISC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Defines - * @{ - */ - -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) -/** - * @} - */ - -/** @defgroup MISC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple - * of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.h deleted file mode 100644 index b7cbcbda9e..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.h +++ /dev/null @@ -1,235 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32f10x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x.h deleted file mode 100644 index 4fa5c22490..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x.h +++ /dev/null @@ -1,8397 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.6.2 - * @date 28-February-2013 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, - * High density, High density value line, Medium density, - * Medium density Value line, Low density, Low density Value line - * and XL-density devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - #define STM32F10X_MD_VL /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ - /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - High-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_STDPERIPH_DRIVER -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ - TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ - TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at position 60 only if the MISC_REMAP bit in - the AFIO_MAPR2 register is set) */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_HD_VL - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_HD_VL -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */ - #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */ -#endif - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* CEC */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CEC_CFGR register ******************/ -#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ -#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ -#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ - -/******************** Bit definition for CEC_OAR register ******************/ -#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ -#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ - -/******************** Bit definition for CEC_PRES register ******************/ -#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ - -/******************** Bit definition for CEC_ESR register ******************/ -#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ -#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ -#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ -#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ -#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ -#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ -#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ - -/******************** Bit definition for CEC_CSR register ******************/ -#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ -#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ -#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ -#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ -#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ -#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ -#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ -#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ - -/******************** Bit definition for CEC_TXD register ******************/ -#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ - -/******************** Bit definition for CEC_RXD register ******************/ -#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ -#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ -#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ -#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ -#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* USB Device FS */ -/* */ -/******************************************************************************/ - -/*!< Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/*!< Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ -#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ -#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ -#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ -#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ -#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ -#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ -#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ -#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ -#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ -#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ -#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ -#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ -#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ -#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ -#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ -#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ -#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ -#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ -#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ -#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ -#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ - -/*!< Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/****************** FLASH Keys **********************************************/ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ -#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ -#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ -#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -#ifdef STM32F10X_CL -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ - #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ -#endif /* STM32F10X_CL */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F10x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.c deleted file mode 100644 index 1378ff9674..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.c +++ /dev/null @@ -1,1322 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the ADC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibration registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.h deleted file mode 100644 index 08eda8cf8c..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_adc.h +++ /dev/null @@ -1,498 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.c deleted file mode 100644 index ab0e666e74..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.c +++ /dev/null @@ -1,323 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the BKP firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_bkp.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ - -/* ------------ BKP registers bit address in the alias region --------------- */ -#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) - -/* --- CR Register ----*/ - -/* Alias word address of TPAL bit */ -#define CR_OFFSET (BKP_OFFSET + 0x30) -#define TPAL_BitNumber 0x01 -#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) - -/* Alias word address of TPE bit */ -#define TPE_BitNumber 0x00 -#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TPIE bit */ -#define CSR_OFFSET (BKP_OFFSET + 0x34) -#define TPIE_BitNumber 0x02 -#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) - -/* Alias word address of TIF bit */ -#define TIF_BitNumber 0x09 -#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) - -/* Alias word address of TEF bit */ -#define TEF_BitNumber 0x08 -#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) - -/* ---------------------- BKP registers bit mask ------------------------ */ - -/* RTCCR register bit mask */ -#define RTCCR_CAL_MASK ((uint16_t)0xFF80) -#define RTCCR_MASK ((uint16_t)0xFC7F) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/** - * @brief Configures the Tamper Pin active level. - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * This parameter can be one of the following values: - * @arg BKP_TamperPinLevel_High: Tamper pin active on high level - * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level - * @retval None - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - /* Check the parameters */ - assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); - *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; -} - -/** - * @brief Enables or disables the Tamper Pin activation. - * @param NewState: new state of the Tamper Pin activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Tamper Pin Interrupt. - * @param NewState: new state of the Tamper Pin Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; -} - -/** - * @brief Select the RTC output source to output on the Tamper pin. - * @param BKP_RTCOutputSource: specifies the RTC output source. - * This parameter can be one of the following values: - * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. - * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency - * divided by 64 on the Tamper pin. - * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on - * the Tamper pin. - * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on - * the Tamper pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); - tmpreg = BKP->RTCCR; - /* Clear CCO, ASOE and ASOS bits */ - tmpreg &= RTCCR_MASK; - - /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ - tmpreg |= BKP_RTCOutputSource; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Sets RTC Clock Calibration value. - * @param CalibrationValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); - tmpreg = BKP->RTCCR; - /* Clear CAL[6:0] bits */ - tmpreg &= RTCCR_CAL_MASK; - /* Set CAL[6:0] bits according to CalibrationValue value */ - tmpreg |= CalibrationValue; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Writes user data to the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Reads data from the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @retval The content of the specified Data Backup Register - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Checks whether the Tamper Pin Event flag is set or not. - * @param None - * @retval The new state of the Tamper Pin Event flag (SET or RESET). - */ -FlagStatus BKP_GetFlagStatus(void) -{ - return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); -} - -/** - * @brief Clears Tamper Pin Event pending flag. - * @param None - * @retval None - */ -void BKP_ClearFlag(void) -{ - /* Set CTE bit to clear Tamper Pin Event flag */ - BKP->CSR |= BKP_CSR_CTE; -} - -/** - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * @param None - * @retval The new state of the Tamper Pin Interrupt (SET or RESET). - */ -ITStatus BKP_GetITStatus(void) -{ - return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); -} - -/** - * @brief Clears Tamper Pin Interrupt pending bit. - * @param None - * @retval None - */ -void BKP_ClearITPendingBit(void) -{ - /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ - BKP->CSR |= BKP_CSR_CTI; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.h deleted file mode 100644 index b651d67098..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_bkp.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.c deleted file mode 100644 index d0989e8fb7..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.c +++ /dev/null @@ -1,1430 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the CAN firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_can.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - -/* CAN Master Control Register bits */ - -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - - - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_FunctionPrototypes - * @{ - */ - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN - * peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the - * CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration - * information. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. - * @retval None. - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @note This function applies only to STM32 Connectivity line devices. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None. - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. This parameter can - * be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disabes the CAN Time TriggerOperation communication mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState : Mode new state , can be one of @ref FunctionalState. - * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last - * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 - * and TIME[15:8] in data byte 7 - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * @retval The number of the mailbox that is used for transmission - * or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the - * CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for - * transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed - * in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} - - -/** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} - - -/** - * @brief Select the CAN Operation mode. - * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one - * of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed CAN failed entering the specific mode - * - CAN_ModeStatus_Success CAN Succeed entering the specific mode - - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an - * other case. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an - * other case. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} - - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN_ErrorCode: specifies the Error code : - * - CAN_ERRORCODE_NoErr No Error - * - CAN_ERRORCODE_StuffErr Stuff Error - * - CAN_ERRORCODE_FormErr Form Error - * - CAN_ERRORCODE_ACKErr Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error - * - CAN_ERRORCODE_CRCErr CRC Error - * - CAN_ERRORCODE_SoftwareSetErr Software Set Error - */ - -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} - - -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * - CAN_IT_TME, - * - CAN_IT_FMP0, - * - CAN_IT_FF0, - * - CAN_IT_FOV0, - * - CAN_IT_FMP1, - * - CAN_IT_FF1, - * - CAN_IT_FOV1, - * - CAN_IT_EWG, - * - CAN_IT_EPV, - * - CAN_IT_LEC, - * - CAN_IT_ERR, - * - CAN_IT_WKU or - * - CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following flags: - * - CAN_FLAG_EWG - * - CAN_FLAG_EPV - * - CAN_FLAG_BOF - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FMP1 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FMP0 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following flags: - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval None. - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following flags: - * - CAN_IT_TME - * - CAN_IT_FMP0 - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FMP1 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the enable interrupt bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default : - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * - CAN_IT_TME - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval None. - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending - of the CAN Bus status*/ - break; - default : - break; - } -} - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.h deleted file mode 100644 index f1ee85d087..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_can.h +++ /dev/null @@ -1,712 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CAN_H -#define __STM32F10x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ - -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ - -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - -/** - * @} - */ - -/** @defgroup CAN_Mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - -/** - * @defgroup CAN_Operating_Mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_Mode_Status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ - - -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ - -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ - -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ - -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) - -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#ifndef STM32F10X_CL - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) -#else - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ - -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ - -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) - -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ - -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) -/** - * @} - */ - -/** @defgroup Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ - -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ - -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ - -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ - -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ - -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ - -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ - -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ - - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ - - - -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -/** - * @} - */ - -/** @defgroup CAN_Legacy - * @{ - */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions - * @{ - */ -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* Transmit functions *********************************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* Receive functions **********************************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* Error management functions *************************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.c deleted file mode 100644 index fc1028a9b6..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.c +++ /dev/null @@ -1,448 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the CEC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_cec.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CEC - * @brief CEC driver modules - * @{ - */ - -/** @defgroup CEC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Defines - * @{ - */ - -/* ------------ CEC registers bit address in the alias region ----------- */ -#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) - -/* --- CFGR Register ---*/ - -/* Alias word address of PE bit */ -#define CFGR_OFFSET (CEC_OFFSET + 0x00) -#define PE_BitNumber 0x00 -#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) - -/* Alias word address of IE bit */ -#define IE_BitNumber 0x01 -#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TSOM bit */ -#define CSR_OFFSET (CEC_OFFSET + 0x10) -#define TSOM_BitNumber 0x00 -#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) - -/* Alias word address of TEOM bit */ -#define TEOM_BitNumber 0x01 -#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) - -#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CEC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void CEC_DeInit(void) -{ - /* Enable CEC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); - /* Release CEC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); -} - - -/** - * @brief Initializes the CEC peripheral according to the specified - * parameters in the CEC_InitStruct. - * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that - * contains the configuration information for the specified - * CEC peripheral. - * @retval None - */ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); - assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); - - /*---------------------------- CEC CFGR Configuration -----------------*/ - /* Get the CEC CFGR value */ - tmpreg = CEC->CFGR; - - /* Clear BTEM and BPEM bits */ - tmpreg &= CFGR_CLEAR_Mask; - - /* Configure CEC: Bit Timing Error and Bit Period Error */ - tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); - - /* Write to CEC CFGR register*/ - CEC->CFGR = tmpreg; - -} - -/** - * @brief Enables or disables the specified CEC peripheral. - * @param NewState: new state of the CEC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; - - if(NewState == DISABLE) - { - /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ - while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) - { - } - } -} - -/** - * @brief Enables or disables the CEC interrupt. - * @param NewState: new state of the CEC interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; -} - -/** - * @brief Defines the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address - * @retval None - */ -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); - - /* Set the CEC own address */ - CEC->OAR = CEC_OwnAddress; -} - -/** - * @brief Sets the CEC prescaler value. - * @param CEC_Prescaler: CEC prescaler new value - * @retval None - */ -void CEC_SetPrescaler(uint16_t CEC_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); - - /* Set the Prescaler value*/ - CEC->PRES = CEC_Prescaler; -} - -/** - * @brief Transmits single data through the CEC peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void CEC_SendDataByte(uint8_t Data) -{ - /* Transmit Data */ - CEC->TXD = Data ; -} - - -/** - * @brief Returns the most recent received data by the CEC peripheral. - * @param None - * @retval The received data. - */ -uint8_t CEC_ReceiveDataByte(void) -{ - /* Receive Data */ - return (uint8_t)(CEC->RXD); -} - -/** - * @brief Starts a new message. - * @param None - * @retval None - */ -void CEC_StartOfMessage(void) -{ - /* Starts of new message */ - *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; -} - -/** - * @brief Transmits message with or without an EOM bit. - * @param NewState: new state of the CEC Tx End Of Message. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_EndOfMessageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The data byte will be transmitted with or without an EOM bit*/ - *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; -} - -/** - * @brief Gets the CEC flag status - * @param CEC_FLAG: specifies the CEC flag to check. - * This parameter can be one of the following values: - * @arg CEC_FLAG_BTE: Bit Timing Error - * @arg CEC_FLAG_BPE: Bit Period Error - * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error - * @arg CEC_FLAG_SBE: Start Bit Error - * @arg CEC_FLAG_ACKE: Block Acknowledge Error - * @arg CEC_FLAG_LINE: Line Error - * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error - * @arg CEC_FLAG_TEOM: Tx End Of Message - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval The new state of CEC_FLAG (SET or RESET) - */ -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t cecreg = 0, cecbase = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); - - /* Get the CEC peripheral base address */ - cecbase = (uint32_t)(CEC_BASE); - - /* Read flag register index */ - cecreg = CEC_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - CEC_FLAG &= FLAG_Mask; - - if(cecreg != 0) - { - /* Flag in CEC ESR Register */ - CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); - - /* Get the CEC ESR register address */ - cecbase += 0xC; - } - else - { - /* Get the CEC CSR register address */ - cecbase += 0x10; - } - - if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) - { - /* CEC_FLAG is set */ - bitstatus = SET; - } - else - { - /* CEC_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CEC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's pending flags. - * @param CEC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval None - */ -void CEC_ClearFlag(uint32_t CEC_FLAG) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC flags */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); -} - -/** - * @brief Checks whether the specified CEC interrupt has occurred or not. - * @param CEC_IT: specifies the CEC interrupt source to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval The new state of CEC_IT (SET or RESET). - */ -ITStatus CEC_GetITStatus(uint8_t CEC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - /* Get the CEC IT enable bit status */ - enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; - - /* Check the status of the specified CEC interrupt */ - if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) - { - /* CEC_IT is set */ - bitstatus = SET; - } - else - { - /* CEC_IT is reset */ - bitstatus = RESET; - } - /* Return the CEC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's interrupt pending bits. - * @param CEC_IT: specifies the CEC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval None - */ -void CEC_ClearITPendingBit(uint16_t CEC_IT) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC interrupt pending bits */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.h deleted file mode 100644 index b020345d1a..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_cec.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CEC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CEC_H -#define __STM32F10x_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - - -/** @defgroup CEC_Exported_Types - * @{ - */ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. - This parameter can be a value of @ref CEC_BitTiming_Mode */ - uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. - This parameter can be a value of @ref CEC_BitPeriod_Mode */ -}CEC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_BitTiming_Mode - * @{ - */ -#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ -#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ - -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ - ((MODE) == CEC_BitTimingErrFreeMode)) -/** - * @} - */ - -/** @defgroup CEC_BitPeriod_Mode - * @{ - */ -#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ -#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ - -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ - ((MODE) == CEC_BitPeriodFlexibleMode)) -/** - * @} - */ - - -/** @defgroup CEC_interrupts_definition - * @{ - */ -#define CEC_IT_TERR CEC_CSR_TERR -#define CEC_IT_TBTRF CEC_CSR_TBTRF -#define CEC_IT_RERR CEC_CSR_RERR -#define CEC_IT_RBTF CEC_CSR_RBTF -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ - ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) -/** - * @} - */ - - -/** @defgroup CEC_Own_Address - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) -/** - * @} - */ - -/** @defgroup CEC_Prescaler - * @{ - */ -#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) - -/** - * @} - */ - -/** @defgroup CEC_flags_definition - * @{ - */ - -/** - * @brief ESR register flags - */ -#define CEC_FLAG_BTE ((uint32_t)0x10010000) -#define CEC_FLAG_BPE ((uint32_t)0x10020000) -#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) -#define CEC_FLAG_SBE ((uint32_t)0x10080000) -#define CEC_FLAG_ACKE ((uint32_t)0x10100000) -#define CEC_FLAG_LINE ((uint32_t)0x10200000) -#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) - -/** - * @brief CSR register flags - */ -#define CEC_FLAG_TEOM ((uint32_t)0x00000002) -#define CEC_FLAG_TERR ((uint32_t)0x00000004) -#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) -#define CEC_FLAG_RSOM ((uint32_t)0x00000010) -#define CEC_FLAG_REOM ((uint32_t)0x00000020) -#define CEC_FLAG_RERR ((uint32_t)0x00000040) -#define CEC_FLAG_RBTF ((uint32_t)0x00000080) - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ - ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ - ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ - ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ - ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ - ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ - ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions - * @{ - */ -void CEC_DeInit(void); -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ITConfig(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_SetPrescaler(uint16_t CEC_Prescaler); -void CEC_SendDataByte(uint8_t Data); -uint8_t CEC_ReceiveDataByte(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessageCmd(FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint8_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_conf.h deleted file mode 100644 index 44bd0e2ab9..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_conf.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - ****************************************************************************** - * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief Library configuration file. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ -#include "stm32f10x_adc.h" -#include "stm32f10x_bkp.h" -#include "stm32f10x_can.h" -#include "stm32f10x_cec.h" -#include "stm32f10x_crc.h" -#include "stm32f10x_dac.h" -#include "stm32f10x_dbgmcu.h" -#include "stm32f10x_dma.h" -#include "stm32f10x_exti.h" -#include "stm32f10x_flash.h" -#include "stm32f10x_fsmc.h" -#include "stm32f10x_gpio.h" -#include "stm32f10x_i2c.h" -#include "stm32f10x_iwdg.h" -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" -#include "stm32f10x_rtc.h" -#include "stm32f10x_sdio.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_tim.h" -#include "stm32f10x_usart.h" -#include "stm32f10x_wwdg.h" -#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F10x_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.c deleted file mode 100644 index 14a1edc755..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.c +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the CRC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_crc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.c deleted file mode 100644 index 9174d18c02..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.c +++ /dev/null @@ -1,586 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the DAC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); - } -} -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} -#endif - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.h deleted file mode 100644 index 110c649d0d..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dac.h +++ /dev/null @@ -1,332 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line, Medium-density and Low-density Value Line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel - only in Medium-density and Low-density Value Line devices*/ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ -#endif - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -#endif -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.c deleted file mode 100644 index 30530b69d9..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.c +++ /dev/null @@ -1,177 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the DBGMCU firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dbgmcu.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/** @defgroup DBGMCU_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param DBGMCU_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.h deleted file mode 100644 index 75d9bde354..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dbgmcu.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DBGMCU_H -#define __STM32F10x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/** @defgroup DBGMCU_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) -#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) -#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) -#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) -#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Functions - * @{ - */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_DBGMCU_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.c deleted file mode 100644 index 65658cd48e..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.c +++ /dev/null @@ -1,729 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the DMA firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dma.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/** - * @} - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_Channel4_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_Channel5_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_Channel6_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_Channel7_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_Mask; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR1_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - } -} - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMAy_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMAy_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy flags */ - DMA2->IFCR = DMAy_FLAG; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMAy_IT: specifies the DMAy interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy interrupt pending bits */ - DMA2->IFCR = DMAy_IT; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.h deleted file mode 100644 index afb258504e..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_dma.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DMA_H -#define __STM32F10x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Exported_Types - * @{ - */ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ - ((DIR) == DMA_DIR_PeripheralSRC)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions - * @{ - */ - -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DMA_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.c deleted file mode 100644 index d7094ef2c4..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.c +++ /dev/null @@ -1,284 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the EXTI firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_exti.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x000FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt. - * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.h deleted file mode 100644 index 2e6a9f9a25..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_exti.h +++ /dev/null @@ -1,199 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.c deleted file mode 100644 index cf01b56954..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.c +++ /dev/null @@ -1,1694 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the FLASH firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_flash.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/** @defgroup FLASH_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Defines - * @{ - */ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup FLASH_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** -@code - - This driver provides functions to configure and program the Flash memory of all STM32F10x devices, - including the latest STM32F10x_XL density devices. - - STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: - - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) - - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) - While other STM32F10x devices features only one bank with memory up to 512 Kbytes. - - In version V3.3.0, some functions were updated and new ones were added to support - STM32F10x_XL devices. Thus some functions manages all devices, while other are - dedicated for XL devices only. - - The table below presents the list of available functions depending on the used STM32F10x devices. - - *************************************************** - * Legacy functions used for all STM32F10x devices * - *************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_SetLatency | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_PrefetchBufferCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | - | | | | - For other devices: unlock Bank1 and it is equivalent | - | | | | to FLASH_UnlockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | - | | | | - For other devices: lock Bank1 and it is equivalent | - | | | | to FLASH_LockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | - | | | | - For other devices: erase a page in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | - | | | | - For other devices: erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseOptionBytes | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramOptionByteData | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EnableWriteProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ReadOutProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_UserOptionByteConfig | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetUserOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| - | | | | - For other devices: enable Bank1's interrupts | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| - | | | | - For other devices: return Bank1's flag status | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | - | | | | - For other devices: clear Bank1's flag | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | - | | | | equivalent to FLASH_GetBank1Status function | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | - | | | | equivalent to: FLASH_WaitForLastBank1Operation function | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ************************************************************************************************************************ - * New functions used for all STM32F10x devices to manage Bank1: * - * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * - * - For other devices, these functions are optional (covered by functions listed above) * - ************************************************************************************************************************ - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ***************************************************************************** - * New Functions used only with STM32F10x_XL density devices to manage Bank2 * - ***************************************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank2 | Yes | No | - Lock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | - +----------------------------------------------------------------------------------------------------------------------------------+ -@endcode -*/ - - -/** - * @brief Sets the code latency value. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. - * - For all other devices it unlocks Bank1 and it is equivalent - * to FLASH_UnlockBank1 function.. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - -#ifdef STM32F10X_XL - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; -#endif /* STM32F10X_XL */ -} -/** - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1. - * - For all other devices it unlocks Bank1 and it is - * equivalent to FLASH_Unlock function. - * @param None - * @retval None - */ -void FLASH_UnlockBank1(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -#ifdef STM32F10X_XL -/** - * @brief Unlocks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_UnlockBank2(void) -{ - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; - -} -#endif /* STM32F10X_XL */ - -/** - * @brief Locks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_LockBank1 function. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; - -#ifdef STM32F10X_XL - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Locks the FLASH Bank1 Program Erase Controller. - * @note this function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_Lock function. - * @param None - * @retval None - */ -void FLASH_LockBank1(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; -} - -#ifdef STM32F10X_XL -/** - * @brief Locks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_LockBank2(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases a specified FLASH page. - * @note This function can be used for all STM32F10x devices. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - -#ifdef STM32F10X_XL - if(Page_Address < FLASH_BANK1_END_ADDRESS) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR2|= CR_PER_Set; - FLASH->AR2 = Page_Address; - FLASH->CR2|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR2 &= CR_PER_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all Bank1 FLASH pages. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function erases all Bank1 pages. - * - For all other devices it erases all Bank1 pages and it is equivalent - * to FLASH_EraseAllPages function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Erases all Bank2 FLASH pages. - * @note This function can be used only for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank2Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - if(Address < FLASH_BANK1_END_ADDRESS - 2) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - FLASH->CR2 |= CR_PG_Set; - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(Address < FLASH_BANK1_END_ADDRESS) - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 - * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127 - * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 - * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 - * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note If the user has already programmed the other option bytes before calling - * this function, he must re-program them since this function erases all option bytes. - * @note This function can be used for all STM32F10x devices. - * @param Newstate: new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note This function can be used for all STM32F10x devices. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Configures to boot from Bank1 or Bank2. - * @note This function can be used only for STM32F10x_XL density devices. - * @param FLASH_BOOT: select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * For more information, please refer to AN2606 from www.st.com. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) -{ - FLASH_Status status = FLASH_COMPLETE; - assert_param(IS_FLASH_BOOT(FLASH_BOOT)); - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - if(FLASH_BOOT == FLASH_BOOT_Bank1) - { - OB->USER |= OB_USER_BFB2; - } - else - { - OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Returns the FLASH User Option Bytes values. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - /* Return the User Option Byte */ - return (uint32_t)(FLASH->OBR >> 2); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Flash write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts - for Bank1 and Bank2. - * - For other devices it enables or disables the specified FLASH interrupts for Bank1. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((FLASH_IT & 0x80000000) != 0x0) - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); - } - else - { - /* Disable the interrupt sources */ - FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); - } - } - else - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -#endif /* STM32F10X_XL */ -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function checks whether the specified - * Bank1 or Bank2 flag is set or not. - * - For other devices, it checks whether the specified Bank1 flag is - * set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH_FLAG & 0x80000000) != 0x0) - { - if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } -#endif /* STM32F10X_XL */ - - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags - * - For other devices, it clears Bank1’s pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - if((FLASH_FLAG & 0x80000000) != 0x0) - { - /* Clear the flags */ - FLASH->SR2 = FLASH_FLAG; - } - else - { - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; - } - -#else - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Returns the FLASH Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetBank1Status function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Returns the FLASH Bank1 Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetStatus function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -#ifdef STM32F10X_XL -/** - * @brief Returns the FLASH Bank2 Status. - * @note This function can be used for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank2Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} -#endif /* STM32F10X_XL */ -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastBank1Operation. - * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation - * to complete or a TIMEOUT to occur. - * - For all other devices it waits for a Flash operation to complete - * or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastOperation. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. - * @note This function can be used only for STM32F10x_XL density devices. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank2Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) - { - status = FLASH_GetBank2Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.h deleted file mode 100644 index b726527cb8..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.h +++ /dev/null @@ -1,441 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ -#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -#ifdef STM32F10X_XL -/** - * @} - */ -/** @defgroup FLASH_Boot - * @{ - */ -#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 or Bank 1, - depending on the activation of the bank */ -#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) -#endif -/** - * @} - */ -/** @defgroup FLASH_Interrupts - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ -#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ - -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#else -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ -#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ -#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ -#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)|| \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) -#else -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32F10x devices -----*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/*------------ New function used for all STM32F10x devices -----*/ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef STM32F10X_XL -/*---- New Functions used only with STM32F10x_XL density devices -----*/ -void FLASH_UnlockBank2(void); -void FLASH_LockBank2(void); -FLASH_Status FLASH_EraseAllBank2Pages(void); -FLASH_Status FLASH_GetBank2Status(void); -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c deleted file mode 100644 index 44362d8b02..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.c +++ /dev/null @@ -1,881 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the FSMC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC - * NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC - * PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.h deleted file mode 100644 index a2d1385364..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.h +++ /dev/null @@ -1,748 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FSMC_H -#define __STM32F10x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/** @defgroup FSMC_Exported_Types - * @{ - */ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ - -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ - -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) - -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ - -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) - -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ - -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ - -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ - -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ - -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ - -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) - -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ - -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ - -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ - -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) - -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ - -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ - -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) - -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ - -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ - -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Functions - * @{ - */ - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_PCCARDDeInit(void); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_PCCARDCmd(FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.c deleted file mode 100644 index 391c9422b7..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.c +++ /dev/null @@ -1,665 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the GPIO firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_gpio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------------*/ -#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - -/* --- EVENTCR Register -----*/ - -/* Alias word address of EVOE bit */ -#define EVCR_OFFSET (AFIO_OFFSET + 0x00) -#define EVOE_BitNumber ((uint8_t)0x07) -#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - - -/* --- MAPR Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((u8)0x17) -#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - - -#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup GPIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if (GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/** - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - -/*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - /* Check the parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -/*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << pinpos); - } - else - { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CRL = tmpreg; - } -/*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @brief Selects the GPIO pin used as Event output. - * @param GPIO_PortSource: selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * @param GPIO_PinSource: specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmpreg = AFIO->EVCR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - tmpreg &= EVCR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->EVCR = tmpreg; -} - -/** - * @brief Enables or disables the Event Output. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; -} - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping - * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping - * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping - * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping - * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping - * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping - * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping - * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping - * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping - * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping - * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration - * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) - * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) - * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled - * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) - * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) - * When the SPI3/I2S3 is remapped using this function, the SWJ is configured - * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. - * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) - * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to - * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. - * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) - * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) - * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) - * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) - * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - * only for High density Value line devices) - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_REMAP(GPIO_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->MAPR2; - } - else - { - tmpreg = AFIO->MAPR; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->MAPR2 = tmpreg; - } - else - { - AFIO->MAPR = tmpreg; - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/** - * @brief Selects the Ethernet media interface. - * @note This function applies only to STM32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MediaInterface_MII: MII mode - * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.h deleted file mode 100644 index 7f4ca0bafe..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.h +++ /dev/null @@ -1,400 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ - -#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ - -#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ -#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ -#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - only for High density Value line devices) */ - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ - ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ - ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ - ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ - ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ - ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ - ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ - ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.c deleted file mode 100644 index 294b9dc358..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.c +++ /dev/null @@ -1,1346 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the I2C firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_i2c.h" -#include "stm32f10x_rcc.h" - - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C SPE mask */ -#define CR1_PE_Set ((uint16_t)0x0001) -#define CR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CR1_START_Set ((uint16_t)0x0100) -#define CR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CR1_STOP_Set ((uint16_t)0x0200) -#define CR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CR1_ACK_Set ((uint16_t)0x0400) -#define CR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CR1_ENGC_Set ((uint16_t)0x0040) -#define CR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CR1_SWRST_Set ((uint16_t)0x8000) -#define CR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CR1_PEC_Set ((uint16_t)0x1000) -#define CR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CR1_ENPEC_Set ((uint16_t)0x0020) -#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CR1_ENARP_Set ((uint16_t)0x0010) -#define CR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CR2_DMAEN_Set ((uint16_t)0x0800) -#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CR2_LAST_Set ((uint16_t)0x1000) -#define CR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint16_t)0x0001) -#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OAR2_ENDUAL_Set ((uint16_t)0x0001) -#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OAR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CCR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CCR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksTypeDef rcc_clocks; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= CR2_FREQ_Reset; - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= CR1_PE_Reset; - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & CCR_CCR_Set) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | CCR_FS_Set); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= CR1_PE_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= CR2_DMAEN_Set; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= CR2_DMAEN_Reset; - } -} - -/** - * @brief Specifies if the next DMA transfer will be the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= CR2_LAST_Set; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= CR2_LAST_Reset; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= CR1_START_Set; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= CR1_START_Reset; - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= CR1_STOP_Set; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= CR1_STOP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= CR1_ACK_Reset; - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= OAR2_ADD2_Reset; - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= OAR2_ENDUAL_Set; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= OAR2_ENDUAL_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= CR1_ENGC_Set; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= CR1_ENGC_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= CR1_SWRST_Set; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= CR1_SWRST_Reset; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= CR1_PEC_Set; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= CR1_PEC_Reset; - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= CR1_ENPEC_Set; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= CR1_ENPEC_Reset; - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= CR1_ENARP_Set; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= CR1_ENARP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= CR1_NOSTRETCH_Set; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= CR1_NOSTRETCH_Reset; - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - - - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the mentioned limitation of I2C_GetFlagStatus() function. - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - * For detailed description of Events, please refer to section I2C_Events in - * stm32f10x_i2c.h file. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Return status */ - return lastevent; -} - -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - - - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_Mask; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx’s interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.h deleted file mode 100644 index b487e27caf..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_i2c.h +++ /dev/null @@ -1,699 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_NCAK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/*======================================== - - I2C Master Events (Events grouped in order of communication) - ==========================================*/ -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/*======================================== - - I2C Slave Events (Events grouped in order of communication) - ==========================================*/ - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/*=========================== End of Events Description ==========================================*/ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occurred. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the limitations of I2C_GetFlagStatus() function (see below). - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -/** - * - ******************************************************************************* - */ - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.c deleted file mode 100644 index 29d112bdf6..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.c +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the IWDG firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_iwdg.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Defines - * @{ - */ - -/* ---------------------- IWDG registers bit mask ----------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_Reload ((uint16_t)0xAAAA) -#define KR_KEY_Enable ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.h deleted file mode 100644 index abadb7b0c9..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_iwdg.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IWDG_H -#define __STM32F10x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions - * @{ - */ - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_IWDG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.c deleted file mode 100644 index 778575916e..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.c +++ /dev/null @@ -1,322 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the PWR firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ - -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - - -/** - * @} - */ - -/** @defgroup PWR_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V - * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V - * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - tmpreg = PWR->CR; - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @brief Enters STOP mode. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - /* Set LPDS bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - /* Store the new value */ - PWR->CR = tmpreg; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); -} - -/** - * @brief Enters STANDBY mode. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wake-up flag */ - PWR->CR |= PWR_CR_CWUF; - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_PVDO: PVD Output - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.h deleted file mode 100644 index 256807972d..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_pwr.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.c deleted file mode 100644 index 10c4cff0ca..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.c +++ /dev/null @@ -1,1485 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the RCC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#endif -#ifdef STM32F10X_CL - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - * this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line and Value line - * devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @note - * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} -#endif - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @note The result of this function could be not correct when using - * fractional value for HSE crystal. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.h deleted file mode 100644 index 79436362d9..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rcc.h +++ /dev/null @@ -1,742 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup PREDIV1_division_factor - * @{ - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -#endif -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -#ifdef STM32F10X_CL -/* PREDIV1 clock source (for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/* PREDIV1 clock source (for STM32 Value line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) -#endif -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -#endif - -#ifdef STM32F10X_CL - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.c deleted file mode 100644 index 2f659b3107..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the RTC firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rtc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= (uint16_t)~RTC_IT; - } -} - -/** - * @brief Enters the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CRL_CNF; -} - -/** - * @brief Exits from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); -} - -/** - * @brief Gets the RTC counter value. - * @param None - * @retval RTC counter value. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t high1 = 0, high2 = 0, low = 0; - - high1 = RTC->CNTH; - low = RTC->CNTL; - high2 = RTC->CNTH; - - if (high1 != high2) - { /* In this case the counter roll over during reading of CNTL and CNTH registers, - read again CNTL register then return the counter value */ - return (((uint32_t) high2 << 16 ) | RTC->CNTL); - } - else - { /* No counter roll over during reading of CNTL and CNTH registers, counter - value is equal to first value of CNTL and CNTH */ - return (((uint32_t) high1 << 16 ) | low); - } -} - -/** - * @brief Sets the RTC counter value. - * @param CounterValue: RTC counter new value. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set RTC COUNTER MSB word */ - RTC->CNTH = CounterValue >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC prescaler value. - * @param PrescalerValue: RTC prescaler new value. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - /* Check the parameters */ - assert_param(IS_RTC_PRESCALER(PrescalerValue)); - - RTC_EnterConfigMode(); - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC alarm value. - * @param AlarmValue: RTC alarm new value. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the ALARM MSB word */ - RTC->ALRH = AlarmValue >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Gets the RTC divider value. - * @param None - * @retval RTC Divider value. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/** - * @brief Waits until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; - /* Loop until RSF flag is set */ - while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval None - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the corresponding RTC flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - bitstatus = (ITStatus)(RTC->CRL & RTC_IT); - if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - - /* Clear the corresponding RTC pending bit */ - RTC->CRL &= (uint16_t)~RTC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.h deleted file mode 100644 index 9e68868934..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_rtc.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.c deleted file mode 100644 index 3505d1209d..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.c +++ /dev/null @@ -1,813 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the SDIO firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.h deleted file mode 100644 index 9b5fd0d759..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_sdio.h +++ /dev/null @@ -1,546 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SDIO_H -#define __STM32F10x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Functions - * @{ - */ - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.c deleted file mode 100644 index 9965870108..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.c +++ /dev/null @@ -1,923 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the SPI firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_spi.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI SPE mask */ -#define CR1_SPE_Set ((uint16_t)0x0040) -#define CR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CR1_CRCEN_Set ((uint16_t)0x2000) -#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CR2_SSOE_Set ((uint16_t)0x0004) -#define CR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/** - * @} - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= SPI_Mode_Select; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the I2S clock source mask depending on the peripheral number */ - if(((uint32_t)SPIx) == SPI2_BASE) - { - /* The mask is relative to I2S2 */ - tmp = I2S2_CLOCK_SRC; - } - else - { - /* The mask is relative to I2S3 */ - tmp = I2S3_CLOCK_SRC; - } - - /* Check the I2S clock source configuration depending on the Device: - Only Connectivity line devices have the PLL3 VCO clock */ -#ifdef STM32F10X_CL - if((RCC->CFGR2 & tmp) != 0) - { - /* Get the configuration bits of RCC PLL3 multiplier */ - tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - - /* Get the value of the PLL3 multiplier */ - if((tmp > 5) && (tmp < 15)) - { - /* Multiplier is between 8 and 14 (value 15 is forbidden) */ - tmp += 2; - } - else - { - if (tmp == 15) - { - /* Multiplier is 20 */ - tmp = 20; - } - } - /* Get the PREDIV2 value */ - sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - } - else - { - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - } -#else /* STM32F10X_HD */ - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; -#endif /* STM32F10X_CL */ - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the floating point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= CR1_SPE_Set; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= CR1_SPE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - /* Disable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI/I2S interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI/I2S interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI/I2S DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI/I2S DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param Data : Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= CR2_SSOE_Set; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= CR2_SSOE_Reset; - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= CR1_CRCNext_Set; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= CR1_CRCEN_Set; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= CR1_CRCEN_Reset; - } -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Checks whether the specified SPI/I2S flag is set or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - /* Check the status of the specified SPI/I2S flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI/I2S IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI/I2S interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.h deleted file mode 100644 index 6bf717955d..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_spi.h +++ /dev/null @@ -1,502 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.c deleted file mode 100644 index bffb61f0bb..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.c +++ /dev/null @@ -1,2905 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the TIM firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_tim.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/** @defgroup TIM_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Defines - * @{ - */ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_Mask ((uint16_t)0x00FF) -#define CCMR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval None - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the - * specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| - (TIMx == TIM16)|| (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - } - else - { - assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 - * to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 - * to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_Mask; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 - * to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_Set << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_Set << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_Offset; - - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST7_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select - * the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - else - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - } - else - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - } - else - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); - } - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - } - else - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); - } - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.h deleted file mode 100644 index 630a254fc8..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_tim.h +++ /dev/null @@ -1,1179 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TIM_H -#define __STM32F10x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/** @defgroup TIM_Exported_Types - * @{ - */ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 1 and 8 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) - -/* LIST2: TIM 1, 8, 15 16 and 17 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) - -/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)) - -/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ -#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)) -#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) -#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions - * @{ - */ - -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_TIM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.c deleted file mode 100644 index 57b3e11558..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.c +++ /dev/null @@ -1,1074 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the USART firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_usart.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Defines - * @{ - */ - -#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ -#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - -#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - -#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ -#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ -#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ -#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ -#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - -#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ -#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - -#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ -#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ -#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - -#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ -#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - -#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ -#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - -#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ -#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - -#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ -#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - -#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ -#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ -#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ -#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ -#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART - * peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= CR2_STOP_CLEAR_Mask; - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= CR3_CLEAR_Mask; - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= CR2_CLOCK_CLEAR_Mask; - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= CR1_UE_Set; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= CR1_UE_Reset; - } -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables or disables the USART’s DMA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @note The DMA mode is not available for UART5 except in the STM32 - * High density value line devices(STM32F10X_HD_VL). - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= CR2_Address_Mask; - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= CR1_WAKE_Mask; - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= CR1_RWU_Set; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= CR1_RWU_Reset; - } -} - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= CR2_LBDL_Mask; - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART’s LIN mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= CR2_LINEN_Set; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= CR2_LINEN_Reset; - } -} - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= CR1_SBK_Set; -} - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @note The guard time bits are not available for UART4 and UART5. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= GTPR_LSB_Mask; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= GTPR_MSB_Mask; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART’s Smart Card mode. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= CR3_SCEN_Set; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= CR3_SCEN_Reset; - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= CR3_NACK_Set; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= CR3_NACK_Reset; - } -} - -/** - * @brief Enables or disables the USART’s Half Duplex communication. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= CR3_HDSEL_Set; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= CR3_HDSEL_Reset; - } -} - - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= CR1_OVER8_Set; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= CR1_OVER8_Reset; - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= CR3_ONEBITE_Set; - } - else - { - /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= CR3_ONEBITE_Reset; - } -} - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= CR3_IRLP_Mask; - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= CR3_IREN_Set; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= CR3_IREN_Reset; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.h deleted file mode 100644 index f73fc7dbba..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_usart.h +++ /dev/null @@ -1,438 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) - -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) - -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.c deleted file mode 100644 index 9e792cc91d..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.c +++ /dev/null @@ -1,239 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file provides all the WWDG firmware functions. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_wwdg.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/** @defgroup WWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Defines - * @{ - */ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) - -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_WDGA_Set ((uint32_t)0x00000080) - -/* CFR register bit mask */ -#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_Mask; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_Mask; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_Mask; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_Mask; -} - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = CR_WDGA_Set | Counter; -} - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->SR); -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.h deleted file mode 100644 index 25fb2c1c75..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_wwdg.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_WWDG_H -#define __STM32F10x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.c deleted file mode 100644 index d0efcf5e84..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.c +++ /dev/null @@ -1,1109 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f10x_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on - * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -#include "stm32f10x.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low, Medium and High density Value line devices an external 8MHz - crystal is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ - #define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -/* #define SYSCLK_FREQ_72MHz 72000000 */ -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) or on - STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) -/* #define DATA_IN_ExtSRAM */ -#endif - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x44444B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - -#ifndef STM32F10X_CL - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#else - if (HSE_VALUE <= 24000000) - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; - } - else - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - } -#endif /* STM32F10X_CL */ -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s new file mode 100644 index 0000000000..c1bf0b23a6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s @@ -0,0 +1,423 @@ +/** + *************** (C) COPYRIGHT 2014 STMicroelectronics ************************ + * @file startup_stm32f100xb.s + * @author MCD Application Team + * @version V4.0.0 + * @date 16-December-2014 + * @brief STM32F100xB Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ +/* bl main */ + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10xB Value Line devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h similarity index 98% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h index a5af399c54..8bd1a4d1c5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "stm32f10x.h" +#include "stm32f1xx.h" #include "cmsis_nvic.h" #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h similarity index 92% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h index 3711fee67b..1410b207e1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h @@ -33,9 +33,9 @@ #define MBED_CMSIS_NVIC_H // CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F) -// MCU Peripherals: 43 vectors (= 172 bytes from 0x40 to 0xEB) -// Total: 236 bytes to be reserved in RAM (see scatter file) -#define NVIC_NUM_VECTORS (16 + 43) +// MCU Peripherals: 100 vectors (= 400 bytes from 0x40 to 0x1CC) +// Total: 464 bytes to be reserved in RAM (see scatter file) +#define NVIC_NUM_VECTORS (16 + 100) #define NVIC_USER_IRQ_OFFSET 16 #include "cmsis.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c new file mode 100644 index 0000000000..9e42da7a4e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); +void set_compare(uint16_t count); + +extern volatile uint32_t SlaveCounter; +extern volatile uint32_t oc_int_part; +extern volatile uint16_t oc_rem_part; + +void timer_irq_handler(void) { + uint16_t cval = TIM_MST->CNT; + + TimMasterHandle.Instance = TIM_MST; + + // Clear Update interrupt flag + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) { + __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE); + SlaveCounter++; + } + + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { + __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); + if (oc_rem_part > 0) { + set_compare(oc_rem_part); // Finish the remaining time left + oc_rem_part = 0; + } else { + if (oc_int_part > 0) { + set_compare(0xFFFF); + oc_rem_part = cval; // To finish the counter loop the next time + oc_int_part--; + } else { + us_ticker_irq_handler(); + } + } + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) { + __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + HAL_TIM_Base_Init(&TimMasterHandle); + + // Configure output compare channel 1 for mbed timeout (enabled later when used) + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Configure output compare channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + + // Configure interrupts + // Update interrupt used for 32-bit counter + // Output compare channel 1 interrupt for mbed timeout + // Output compare channel 2 interrupt for HAL tick + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Enable interrupts + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick + + // Enable timer + HAL_TIM_Base_Start(&TimMasterHandle); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h new file mode 100644 index 0000000000..09c66b92ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f1xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM4 +#define TIM_MST_IRQ TIM4_IRQn +#define TIM_MST_RCC __TIM4_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h new file mode 100644 index 0000000000..41a76df4dd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h @@ -0,0 +1,4073 @@ +/** + ****************************************************************************** + * @file stm32f100xb.h + * @author MCD Application Team + * @version V4.0.0 + * @date 16-December-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f100xb + * @{ + */ + +#ifndef __STM32F100xB_H +#define __STM32F100xB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ +} IRQn_Type; + + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; +} BKP_TypeDef; + + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; + __IO uint32_t SR; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + + uint32_t RESERVED0; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */ + +#define RTC_BKP_NUMBER 10 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ + +#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ + + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ + + + +#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ + + + +#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ + + + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ + +#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ + + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ + + + +#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ + + + +#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ + +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ + + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ +#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ +#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ +#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ +#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + + #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */ + #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint32_t)0x00000002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint32_t)0x00000004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint32_t)0x00000008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint32_t)0x0000000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint32_t)0x00003FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint32_t)0x00000001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint32_t)0x00000002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint32_t)0x00000004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint32_t)0x00000008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint32_t)0x00000010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint32_t)0x00000020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint32_t)0x00000040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint32_t)0x00000001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint32_t)0x00000002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint32_t)0x00000004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint32_t)0x00000008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint32_t)0x00000010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint32_t)0x00000020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint32_t)0x00000040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint32_t)0x00000080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint32_t)0x000000FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint32_t)0x000000FF) /*!< Rx Data register */ + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) +#define STM32F100xB /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ + /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V4.0.0 + */ +#define __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c new file mode 100644 index 0000000000..937b24e597 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c @@ -0,0 +1,603 @@ +/** + ****************************************************************************** + * @file system_stm32f1xx.c + * @author MCD Application Team + * @version V4.0.0 + * @date 16-December-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f1xx_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE". + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 8 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 24 | 24 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 24 | 24 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 24 | 24 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 24 | 24 + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx_system + * @{ + */ + +/** @addtogroup STM32F1xx_System_Private_Includes + * @{ + */ + +#include "stm32f1xx.h" +#include "hal_tick.h" + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM */ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#if defined(STM32F100xB) ||defined(STM32F100xE) + uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ +#endif + +__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#if !defined(STM32F105xC) && !defined(STM32F107xC) + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F105xC */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined(STM32F100xB) || defined(STM32F100xE) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F105xC */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F105xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) + uint32_t prediv1factor = 0; +#endif /* STM32F100xB or STM32F100xE */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#if !defined(STM32F105xC) && !defined(STM32F107xC) + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined(STM32F100xB) || defined(STM32F100xE) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F105xC */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/** + * @brief Setup the external memory controller. Called in startup_stm32f1xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f1xx_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmpreg; + /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); + + (void)(tmpreg); + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x444B4B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001091; + FSMC_Bank1->BTCR[5] = 0x00110212; +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h new file mode 100644 index 0000000000..e344021f31 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V4.0.0 + * @date 16-December-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h index 52406109a8..48dcb1480f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h @@ -37,8 +37,7 @@ extern "C" { #endif typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE + ADC_1 = (int)ADC1_BASE } ADCName; typedef enum { @@ -62,6 +61,7 @@ typedef enum { } I2CName; typedef enum { + PWM_1 = (int)TIM1_BASE, PWM_2 = (int)TIM2_BASE, PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c new file mode 100644 index 0000000000..058fa5d861 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c @@ -0,0 +1,165 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN9 + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN10 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN11 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN12 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN13 + {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN14 + {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN15 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1 + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1 + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM4 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM2_CH2 - Default + {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM2_CH3 - Default (warning: not connected on D1 per default) + {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM2_CH4 - Default (warning: not connected on D0 per default) + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM3_CH1 - Default + {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM3_CH2 - Default +// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 6)}, // TIM1_CH1N - GPIO_PartialRemap_TIM1 + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH1 - Default + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH2 - Default + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH3 - Default + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH4 - Default + {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 8)}, // TIM2_CH1_ETR - GPIO_FullRemap_TIM2 + + {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM3_CH3 - Default +// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 6)}, // TIM1_CH2N - GPIO_PartialRemap_TIM1 + {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM3_CH4 - Default +// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 6)}, // TIM1_CH3N - GPIO_PartialRemap_TIM1 + {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 8)}, // TIM2_CH2 - GPIO_FullRemap_TIM2 + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 7)}, // TIM3_CH1 - GPIO_PartialRemap_TIM3 + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 7)}, // TIM3_CH2 - GPIO_PartialRemap_TIM3 +// {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM4_CH1 - Default (used by ticker) +// {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM4_CH2 - Default (used by ticker) +// {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM4_CH3 - Default (used by ticker) +// {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM4_CH4 - Default (used by ticker) + {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 8)}, // TIM2_CH3 - GPIO_FullRemap_TIM2 + {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 8)}, // TIM2_CH4 - GPIO_FullRemap_TIM2 + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH1N - Default + {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH2N - Default + {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // TIM1_CH3N - Default + + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 9)}, // TIM3_CH1 - GPIO_FullRemap_TIM3 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 9)}, // TIM3_CH2 - GPIO_FullRemap_TIM3 + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 9)}, // TIM3_CH3 - GPIO_FullRemap_TIM3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 9)}, // TIM3_CH4 - GPIO_FullRemap_TIM3 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1 + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1 + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3 + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h similarity index 58% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h index 6c726a13ee..383d022e69 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h @@ -1,10 +1,4 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.h - * @author MCD Application Team - * @version V3.6.2 - * @date 28-February-2013 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. +/* mbed Microcontroller Library ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -34,80 +28,35 @@ ******************************************************************************* */ -/** @addtogroup CMSIS - * @{ - */ +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H +#include "pinmap.h" +#include "PeripheralNames.h" -#ifdef __cplusplus - extern "C" { -#endif +//*** ADC *** -/** @addtogroup STM32F10x_System_Includes - * @{ - */ +extern const PinMap PinMap_ADC[]; -/** - * @} - */ +//*** I2C *** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ +//*** PWM *** -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const PinMap PinMap_PWM[]; -/** - * @} - */ +//*** SERIAL *** -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; -/** - * @} - */ +//*** SPI *** -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} #endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h index 017a28b45a..9f9c2073ac 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h @@ -36,11 +36,24 @@ extern "C" { #endif -// MODE (see GPIOMode_TypeDef structure) -// AFNUM (see AF_mapping constant table) -#define STM_PIN_DATA(MODE, AFNUM) (((MODE) << 8) | (AFNUM)) -#define STM_PIN_MODE(X) ((X) >> 8) -#define STM_PIN_AFNUM(X) ((X) & 0xFF) +// See stm32f3xx_hal_gpio.h and stm32f3xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) // High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) // Low nibble = pin number diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c index b9e0a58db7..72bfcfcf8e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c @@ -27,31 +27,23 @@ */ #include "mbed_assert.h" #include "analogin_api.h" -#include "wait_api.h" #if DEVICE_ANALOGIN +#include "wait_api.h" #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" -static const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {NC, NC, 0} -}; +ADC_HandleTypeDef AdcHandle; int adc_inited = 0; -void analogin_init(analogin_t *obj, PinName pin) { +void analogin_init(analogin_t *obj, PinName pin) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit; - ADC_TypeDef *adc; - ADC_InitTypeDef ADC_InitStructure; - - // Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object + // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); @@ -65,73 +57,117 @@ void analogin_init(analogin_t *obj, PinName pin) { if (adc_inited == 0) { adc_inited = 1; - // Get ADC registers structure address - adc = (ADC_TypeDef *)(obj->adc); - // Enable ADC clock - RCC_ADCCLKConfig(RCC_PCLK2_Div4); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + __HAL_RCC_ADC1_CLK_ENABLE(); + + // Configure ADC clock prescaler + // Caution: On STM32F1, ADC clock frequency max is 14 MHz (refer to device datasheet). + // Therefore, ADC clock prescaler must be configured in function + // of ADC clock source frequency to remain below this maximum frequency. + // with 8 MHz external xtal: PCLK2 = 72 MHz --> ADC clock = 72/6 = 12 MHz + // with internal clock : PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.67 MHz + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); // Configure ADC - ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_InitStructure.ADC_ScanConvMode = DISABLE; - ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; - ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_NbrOfChannel = 1; - ADC_Init(adc, &ADC_InitStructure); - - // Enable ADC - ADC_Cmd(adc, ENABLE); - - // Calibrate ADC - ADC_ResetCalibration(adc); - while(ADC_GetResetCalibrationStatus(adc)); - ADC_StartCalibration(adc); - while(ADC_GetCalibrationStatus(adc)); + AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); + AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + AdcHandle.Init.ScanConvMode = DISABLE; + AdcHandle.Init.ContinuousConvMode = DISABLE; + AdcHandle.Init.NbrOfConversion = 1; + AdcHandle.Init.DiscontinuousConvMode = DISABLE; + AdcHandle.Init.NbrOfDiscConversion = 0; + AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + HAL_ADC_Init(&AdcHandle); } } -static inline uint16_t adc_read(analogin_t *obj) { - // Get ADC registers structure address - ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc); +static inline uint16_t adc_read(analogin_t *obj) +{ + ADC_ChannelConfTypeDef sConfig; + + AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); // Configure ADC channel + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; + switch (obj->pin) { case PA_0: - ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_7Cycles5); + sConfig.Channel = ADC_CHANNEL_0; break; case PA_1: - ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_7Cycles5); + sConfig.Channel = ADC_CHANNEL_1; + break; + case PA_2: + sConfig.Channel = ADC_CHANNEL_2; + break; + case PA_3: + sConfig.Channel = ADC_CHANNEL_3; break; case PA_4: - ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5); + sConfig.Channel = ADC_CHANNEL_4; + break; + case PA_5: + sConfig.Channel = ADC_CHANNEL_5; + break; + case PA_6: + sConfig.Channel = ADC_CHANNEL_6; + break; + case PA_7: + sConfig.Channel = ADC_CHANNEL_7; break; case PB_0: - ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_7Cycles5); + sConfig.Channel = ADC_CHANNEL_8; break; - case PC_1: - ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_7Cycles5); + case PB_1: + sConfig.Channel = ADC_CHANNEL_9; break; case PC_0: - ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_7Cycles5); + sConfig.Channel = ADC_CHANNEL_10; + break; + case PC_1: + sConfig.Channel = ADC_CHANNEL_11; + break; + case PC_2: + sConfig.Channel = ADC_CHANNEL_12; + break; + case PC_3: + sConfig.Channel = ADC_CHANNEL_13; + break; + case PC_4: + sConfig.Channel = ADC_CHANNEL_14; + break; + case PC_5: + sConfig.Channel = ADC_CHANNEL_15; break; default: return 0; } - ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion + HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion + HAL_ADC_Start(&AdcHandle); // Start conversion - return(ADC_GetConversionValue(adc)); // Get conversion value + // Wait end of conversion and get value + if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { + return (HAL_ADC_GetValue(&AdcHandle)); + } else { + return 0; + } } -uint16_t analogin_read_u16(analogin_t *obj) { - return(adc_read(obj)); +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + // 12-bit to 16-bit conversion + value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); + return value; } -float analogin_read(analogin_t *obj) { +float analogin_read(analogin_t *obj) +{ uint16_t value = adc_read(obj); return (float)value * (1.0f / (float)0xFFF); // 12 bits range } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h index a8f3e46ffe..57a7aa227d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h @@ -37,15 +37,15 @@ #define DEVICE_INTERRUPTIN 1 #define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 +#define DEVICE_ANALOGOUT 0 // Not present on this device #define DEVICE_SERIAL 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 +#define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 @@ -53,7 +53,6 @@ #define DEVICE_SLEEP 1 -#define DEVICE_ERROR_PATTERN 1 //fast blink green and blue leds on error //======================================= #define DEVICE_SEMIHOST 0 @@ -64,7 +63,7 @@ #define DEVICE_STDIO_MESSAGES 1 -//#define DEVICE_ERROR_RED 0 +#define DEVICE_ERROR_RED 0 #include "objects.h" diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c index 4931950566..48fb0b5d54 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c @@ -34,17 +34,21 @@ extern uint32_t Set_GPIO_Clock(uint32_t port_idx); -uint32_t gpio_set(PinName pin) { +uint32_t gpio_set(PinName pin) +{ MBED_ASSERT(pin != (PinName)NC); - pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)); + pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask } -void gpio_init(gpio_t *obj, PinName pin) { +void gpio_init(gpio_t *obj, PinName pin) +{ obj->pin = pin; - if (pin == (PinName)NC) + if (pin == (PinName)NC) { return; + } uint32_t port_index = STM_PORT(pin); @@ -59,16 +63,17 @@ void gpio_init(gpio_t *obj, PinName pin) { obj->reg_clr = &gpio->BRR; } -void gpio_mode(gpio_t *obj, PinMode mode) { +void gpio_mode(gpio_t *obj, PinMode mode) +{ pin_mode(obj->pin, mode); } -void gpio_dir(gpio_t *obj, PinDirection direction) { +void gpio_dir(gpio_t *obj, PinDirection direction) +{ MBED_ASSERT(obj->pin != (PinName)NC); if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_Out_PP, 0)); - } - else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)); + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c index df00593f79..59de6ff5b7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c @@ -39,56 +39,139 @@ #define EDGE_FALL (2) #define EDGE_BOTH (3) -#define CHANNEL_NUM (16) +// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15) +#define CHANNEL_NUM (7) -static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +// Max pins for one line (max with EXTI10_15) +#define MAX_PIN_LINE (6) + +typedef struct gpio_channel { + uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts + uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance + uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group + uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group +} gpio_channel_t; + +static gpio_channel_t channels[CHANNEL_NUM] = { + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0}, + {.pin_mask = 0} +}; + +// Used to return the index for channels array. +static uint32_t pin_base_nr[16] = { + // EXTI0 + 0, // pin 0 + // EXTI1 + 0, // pin 1 + // EXTI2 + 0, // pin 2 + // EXTI3 + 0, // pin 3 + // EXTI4 + 0, // pin 4 + // EXTI5_9 + 0, // pin 5 + 1, // pin 6 + 2, // pin 7 + 3, // pin 8 + 4, // pin 9 + // EXTI10_15 + 0, // pin 10 + 1, // pin 11 + 2, // pin 12 + 3, // pin 13 + 4, // pin 14 + 5 // pin 15 +}; static gpio_irq_handler irq_handler; -static void handle_interrupt_in(uint32_t irq_index) { - //if irq_index==5 loop exti 5 to 9 - //if irq_index==10 loop exti 10 to 15 - //else exti loop one irq_index - uint32_t to_irq_index=(irq_index==5)?9:((irq_index==10)?15:irq_index); - GPIO_TypeDef *gpio; - uint32_t pin; - do{ +static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) +{ + gpio_channel_t *gpio_channel = &channels[irq_index]; + uint32_t gpio_idx; + + for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { + uint32_t current_mask = (1 << gpio_idx); + + if (gpio_channel->pin_mask & current_mask) { // Retrieve the gpio and pin that generate the irq - gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]); - pin = (uint32_t)(1 << channel_pin[irq_index]); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); + uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); + // Clear interrupt flag - if (EXTI_GetITStatus(pin) != RESET) - { - EXTI_ClearITPendingBit(pin); - if (channel_ids[irq_index] == 0) return; + if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { + __HAL_GPIO_EXTI_CLEAR_FLAG(pin); + + if (gpio_channel->channel_ids[gpio_idx] == 0) continue; + // Check which edge has generated the irq if ((gpio->IDR & pin) == 0) { - irq_handler(channel_ids[irq_index], IRQ_FALL); + irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); } else { - irq_handler(channel_ids[irq_index], IRQ_RISE); + irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); + } + } } } - }while(irq_index++ < to_irq_index); } +// EXTI line 0 +static void gpio_irq0(void) +{ + handle_interrupt_in(0, 1); +} -// The irq_index is passed to the function -static void gpio_irq0(void) {handle_interrupt_in(0);} // EXTI line 0 -static void gpio_irq1(void) {handle_interrupt_in(1);} // EXTI line 1 -static void gpio_irq2(void) {handle_interrupt_in(2);} // EXTI line 2 -static void gpio_irq3(void) {handle_interrupt_in(3);} // EXTI line 3 -static void gpio_irq4(void) {handle_interrupt_in(4);} // EXTI line 4 -static void gpio_irq5(void) {handle_interrupt_in(5);} // EXTI lines 5 to 9 -static void gpio_irq6(void) {handle_interrupt_in(10);} // EXTI lines 10 to 15 +// EXTI line 1 +static void gpio_irq1(void) +{ + handle_interrupt_in(1, 1); +} + +// EXTI line 2 +static void gpio_irq2(void) +{ + handle_interrupt_in(2, 1); +} + +// EXTI line 3 +static void gpio_irq3(void) +{ + handle_interrupt_in(3, 1); +} + +// EXTI line 4 +static void gpio_irq4(void) +{ + handle_interrupt_in(4, 1); +} + +// EXTI lines 5 to 9 +static void gpio_irq5(void) +{ + handle_interrupt_in(5, 5); +} + +// EXTI lines 10 to 15 +static void gpio_irq6(void) +{ + handle_interrupt_in(6, 6); +} extern uint32_t Set_GPIO_Clock(uint32_t port_idx); -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; uint32_t irq_index; + gpio_channel_t *gpio_channel; + uint32_t gpio_idx; if (pin == NC) return -1; @@ -129,7 +212,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 case 9: irq_n = EXTI9_5_IRQn; vector = (uint32_t)&gpio_irq5; - irq_index = pin_index; + irq_index = 5; break; case 10: case 11: @@ -139,7 +222,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 case 15: irq_n = EXTI15_10_IRQn; vector = (uint32_t)&gpio_irq6; - irq_index = pin_index; + irq_index = 6; break; default: error("InterruptIn error: pin not supported.\n"); @@ -148,28 +231,10 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // Enable GPIO clock uint32_t gpio_add = Set_GPIO_Clock(port_index); - // Enable AFIO clock - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - - // Connect EXTI line to pin - GPIO_EXTILineConfig(port_index, pin_index); - - // Configure EXTI line - EXTI_InitTypeDef EXTI_InitStructure; - EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index); - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - // Enable and set EXTI interrupt to the lowest priority - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = irq_n; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + // Configure GPIO + pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); + // Enable EXTI interrupt NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); @@ -177,71 +242,91 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->irq_n = irq_n; obj->irq_index = irq_index; obj->event = EDGE_NONE; - channel_ids[irq_index] = id; - channel_gpio[irq_index] = gpio_add; - channel_pin[irq_index] = pin_index; + obj->pin = pin; + + gpio_channel = &channels[irq_index]; + gpio_idx = pin_base_nr[pin_index]; + gpio_channel->pin_mask |= (1 << gpio_idx); + gpio_channel->channel_ids[gpio_idx] = id; + gpio_channel->channel_gpio[gpio_idx] = gpio_add; + gpio_channel->channel_pin[gpio_idx] = pin_index; irq_handler = handler; return 0; } -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->irq_index] = 0; - channel_gpio[obj->irq_index] = 0; - channel_pin[obj->irq_index] = 0; +void gpio_irq_free(gpio_irq_t *obj) +{ + gpio_channel_t *gpio_channel = &channels[obj->irq_index]; + uint32_t pin_index = STM_PIN(obj->pin); + uint32_t gpio_idx = pin_base_nr[pin_index]; + + gpio_channel->pin_mask &= ~(1 << gpio_idx); + gpio_channel->channel_ids[gpio_idx] = 0; + gpio_channel->channel_gpio[gpio_idx] = 0; + gpio_channel->channel_pin[gpio_idx] = 0; + // Disable EXTI line - EXTI_InitTypeDef EXTI_InitStructure; - EXTI_StructInit(&EXTI_InitStructure); - EXTI_Init(&EXTI_InitStructure); + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); obj->event = EDGE_NONE; } -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - EXTI_InitTypeDef EXTI_InitStructure; - - uint32_t pin_index = channel_pin[obj->irq_index]; - - EXTI_InitStructure.EXTI_Line = (uint32_t)(1 << pin_index); - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t mode = STM_MODE_IT_EVT_RESET; + uint32_t pull = GPIO_NOPULL; + if (enable) { if (event == IRQ_RISE) { if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + mode = STM_MODE_IT_RISING_FALLING; obj->event = EDGE_BOTH; - } - else { // NONE or RISE - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + } else { // NONE or RISE + mode = STM_MODE_IT_RISING; obj->event = EDGE_RISE; } } - if (event == IRQ_FALL) { if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + mode = STM_MODE_IT_RISING_FALLING; obj->event = EDGE_BOTH; + } else { // NONE or FALL + mode = STM_MODE_IT_FALLING; + obj->event = EDGE_FALL; + } } - else { // NONE or FALL - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + } else { // Disable + if (event == IRQ_RISE) { + if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_FALLING; obj->event = EDGE_FALL; + } else { // NONE or RISE + mode = STM_MODE_IT_EVT_RESET; + obj->event = EDGE_NONE; } } - - if (enable) { - EXTI_InitStructure.EXTI_LineCmd = ENABLE; + if (event == IRQ_FALL) { + if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { + mode = STM_MODE_IT_RISING; + obj->event = EDGE_RISE; + } else { // NONE or FALL + mode = STM_MODE_IT_EVT_RESET; + obj->event = EDGE_NONE; + } } - else { - EXTI_InitStructure.EXTI_LineCmd = DISABLE; } - EXTI_Init(&EXTI_InitStructure); + pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); } -void gpio_irq_enable(gpio_irq_t *obj) { +void gpio_irq_enable(gpio_irq_t *obj) +{ NVIC_EnableIRQ(obj->irq_n); } -void gpio_irq_disable(gpio_irq_t *obj) { +void gpio_irq_disable(gpio_irq_t *obj) +{ NVIC_DisableIRQ(obj->irq_n); obj->event = EDGE_NONE; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h index d97ee5bf12..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h @@ -48,17 +48,18 @@ typedef struct { __IO uint32_t *reg_clr; } gpio_t; -static inline void gpio_write(gpio_t *obj, int value) { +static inline void gpio_write(gpio_t *obj, int value) +{ MBED_ASSERT(obj->pin != (PinName)NC); if (value) { *obj->reg_set = obj->mask; - } - else { + } else { *obj->reg_clr = obj->mask; } } -static inline int gpio_read(gpio_t *obj) { +static inline int gpio_read(gpio_t *obj) +{ MBED_ASSERT(obj->pin != (PinName)NC); return ((*obj->reg_in & obj->mask) ? 1 : 0); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c index 48d9467ca1..f7882ec7a5 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c @@ -34,6 +34,7 @@ #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" /* Timeout values for flags and events waiting loops. These timeouts are not based on accurate values, they just guarantee that the application will @@ -41,17 +42,13 @@ #define FLAG_TIMEOUT ((int)0x1000) #define LONG_TIMEOUT ((int)0x8000) -static const PinMap PinMap_I2C_SDA[] = { - {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1 - {NC, NC, 0} -}; +I2C_HandleTypeDef I2cHandle; -static const PinMap PinMap_I2C_SCL[] = { - {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1 - {NC, NC, 0} -}; +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + static int i2c1_inited = 0; + static int i2c2_inited = 0; -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { // Determine the I2C to use I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -59,62 +56,80 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); MBED_ASSERT(obj->i2c != (I2CName)NC); - // Enable I2C clock + // Check if I2C peripherals are already configured + if ((obj->i2c == I2C_1) && i2c1_inited) return; + if ((obj->i2c == I2C_2) && i2c2_inited) return; + + // Set I2C clock if (obj->i2c == I2C_1) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); + i2c1_inited = 1; + __I2C1_CLK_ENABLE(); } if (obj->i2c == I2C_2) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE); + i2c2_inited = 1; + __I2C2_CLK_ENABLE(); } // Configure I2C pins - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); // Reset to clear pending flags if any i2c_reset(obj); // I2C configuration i2c_frequency(obj, 100000); // 100 kHz per default + + // I2C master by default + obj->slave = 0; } -void i2c_frequency(i2c_t *obj, int hz) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2C_InitTypeDef I2C_InitStructure; +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT((hz != 0) && (hz <= 400000)); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + int timeout; - if ((hz != 0) && (hz <= 400000)) { - I2C_DeInit(i2c); + // wait before init + timeout = LONG_TIMEOUT; + while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); // I2C configuration - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = hz; - I2C_Init(i2c, &I2C_InitStructure); - - I2C_Cmd(i2c, ENABLE); + I2cHandle.Init.ClockSpeed = hz; + I2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; + I2cHandle.Init.OwnAddress1 = 0; + I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; + I2cHandle.Init.OwnAddress2 = 0; + I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; + I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; + HAL_I2C_Init(&I2cHandle); + + if (obj->slave) { + // Enable Address Acknowledge + I2cHandle.Instance->CR1 |= I2C_CR1_ACK; } } -inline int i2c_start(i2c_t *obj) { +inline int i2c_start(i2c_t *obj) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); int timeout; - I2C_ClearFlag(i2c, I2C_FLAG_AF); // Clear Acknowledge failure flag + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + // Clear Acknowledge failure flag + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); // Generate the START condition - I2C_GenerateSTART(i2c, ENABLE); + i2c->CR1 |= I2C_CR1_START; // Wait the START condition has been correctly sent timeout = FLAG_TIMEOUT; - //while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_MODE_SELECT) == ERROR) { - while (I2C_GetFlagStatus(i2c, I2C_FLAG_SB) == RESET) { - timeout--; - if (timeout == 0) { + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { + if ((timeout--) == 0) { return 1; } } @@ -122,46 +137,39 @@ inline int i2c_start(i2c_t *obj) { return 0; } -inline int i2c_stop(i2c_t *obj) { +inline int i2c_stop(i2c_t *obj) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2C_GenerateSTOP(i2c, ENABLE); + // Generate the STOP condition + i2c->CR1 |= I2C_CR1_STOP; return 0; } -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; int count; int value; - if (length == 0) return 0; - -/* - // Wait until the bus is not busy anymore - timeout = LONG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) { - timeout--; - if (timeout == 0) { - return 0; - } - } -*/ - + // Generate start condition i2c_start(obj); - // Send slave address for read - I2C_Send7bitAddress(i2c, address, I2C_Direction_Receiver); + // Send address for read + i2c->DR = __HAL_I2C_7BIT_ADD_READ(address); // Wait address is acknowledged timeout = FLAG_TIMEOUT; - while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) == ERROR) { + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { timeout--; if (timeout == 0) { - return 0; + return -1; } } + __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); // Read all bytes except last one for (count = 0; count < (length - 1); count++) { @@ -182,40 +190,34 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { return length; } -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; int count; -/* - // Wait until the bus is not busy anymore - timeout = LONG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) { - timeout--; - if (timeout == 0) { - return 0; - } - } -*/ - + // Generate start condition i2c_start(obj); - // Send slave address for write - I2C_Send7bitAddress(i2c, address, I2C_Direction_Transmitter); + // Send address for write + i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address); // Wait address is acknowledged timeout = FLAG_TIMEOUT; - while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR) { + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { timeout--; if (timeout == 0) { - return 0; + return -1; } } + __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); + // Write all bytes for (count = 0; count < length; count++) { if (i2c_byte_write(obj, data[count]) != 1) { i2c_stop(obj); - return 0; + return -1; } } @@ -227,46 +229,42 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { return count; } -int i2c_byte_read(i2c_t *obj, int last) { +int i2c_byte_read(i2c_t *obj, int last) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint8_t data; int timeout; if (last) { // Don't acknowledge the last byte - I2C_AcknowledgeConfig(i2c, DISABLE); + i2c->CR1 &= ~I2C_CR1_ACK; } else { // Acknowledge the byte - I2C_AcknowledgeConfig(i2c, ENABLE); + i2c->CR1 |= I2C_CR1_ACK; } // Wait until the byte is received timeout = FLAG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_FLAG_RXNE) == RESET) { - timeout--; - if (timeout == 0) { - return 0; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { + if ((timeout--) == 0) { + return -1; } } - data = I2C_ReceiveData(i2c); - - return (int)data; + return (int)i2c->DR; } -int i2c_byte_write(i2c_t *obj, int data) { +int i2c_byte_write(i2c_t *obj, int data) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); int timeout; - I2C_SendData(i2c, (uint8_t)data); + i2c->DR = (uint8_t)data; // Wait until the byte is transmitted timeout = FLAG_TIMEOUT; - //while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR) { - while ((I2C_GetFlagStatus(i2c, I2C_FLAG_TXE) == RESET) && - (I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) { - timeout--; - if (timeout == 0) { + while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) && + (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) { + if ((timeout--) == 0) { return 0; } } @@ -274,22 +272,30 @@ int i2c_byte_write(i2c_t *obj, int data) { return 1; } -void i2c_reset(i2c_t *obj) { +void i2c_reset(i2c_t *obj) +{ + int timeout; + + // Wait before reset + timeout = LONG_TIMEOUT; + while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); + if (obj->i2c == I2C_1) { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + __I2C1_FORCE_RESET(); + __I2C1_RELEASE_RESET(); } if (obj->i2c == I2C_2) { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + __I2C2_FORCE_RESET(); + __I2C2_RELEASE_RESET(); } } #if DEVICE_I2CSLAVE -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; + uint16_t tmpreg = 0; // Get the old register value tmpreg = i2c->OAR1; @@ -301,8 +307,14 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { i2c->OAR1 = tmpreg; } -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - // Nothing to do +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + if (enable_slave) { + obj->slave = 1; + /* Enable Address Acknowledge */ + I2cHandle.Instance->CR1 |= I2C_CR1_ACK; + } } // See I2CSlave.h @@ -311,31 +323,132 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) { #define WriteGeneral 2 // the master is writing to all slave #define WriteAddressed 3 // the master is writing to this slave (slave = receiver) -int i2c_slave_receive(i2c_t *obj) { - // TO BE DONE - return(0); +int i2c_slave_receive(i2c_t *obj) +{ + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + int retValue = NoData; + + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { + if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1) { + retValue = ReadAddressed; + } else { + retValue = WriteAddressed; + } + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); + } } -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count = 0; + return (retValue); +} - // Read all bytes - for (count = 0; count < length; count++) { - data[count] = i2c_byte_read(obj, 0); +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + uint32_t Timeout; + int size = 0; + + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + while (length > 0) { + // Wait until RXNE flag is set + // Wait until the byte is received + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } } - return count; + // Read data + (*data++) = I2cHandle.Instance->DR; + length--; + size++; + + if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { + // Read data + (*data++) = I2cHandle.Instance->DR; + length--; + size++; + } } -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count = 0; + // Wait until STOP flag is set + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } - // Write all bytes - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); + // Clear STOP flag + __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle); + + // Wait until BUSY flag is reset + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { + Timeout--; + if (Timeout == 0) { + return -1; + } } - return count; + return size; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + uint32_t Timeout; + int size = 0; + + I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); + + while (length > 0) { + // Wait until TXE flag is set + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + // Write data + I2cHandle.Instance->DR = (*data++); + length--; + size++; + + if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { + // Write data to DR + I2cHandle.Instance->DR = (*data++); + length--; + size++; + } + } + + // Wait until AF flag is set + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + // Clear AF flag + __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); + + // Wait until BUSY flag is reset + Timeout = FLAG_TIMEOUT; + while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { + Timeout--; + if (Timeout == 0) { + return -1; + } + } + + return size; } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c similarity index 51% rename from libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c index 153175de7e..9783dd90a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_crc.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c @@ -1,12 +1,4 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.h - * @author MCD Application Team - * @version V3.6.1 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ******************************************************************************* +/* mbed Microcontroller Library * Copyright (c) 2014, STMicroelectronics * All rights reserved. * @@ -32,78 +24,14 @@ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* */ +#include "cmsis.h" -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CRC_H -#define __STM32F10x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus +// This function is called after RAM initialization and before main. +void mbed_sdk_init() +{ + // Update the SystemCoreClock variable. + SystemCoreClockUpdate(); + // Need to restart HAL driver after the RAM is initialized + HAL_Init(); } -#endif - -#endif /* __STM32F10x_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h index 2e1a43b421..a75a3e96b1 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h @@ -43,6 +43,7 @@ struct gpio_irq_s { IRQn_Type irq_n; uint32_t irq_index; uint32_t event; + PinName pin; }; struct port_s { @@ -65,6 +66,8 @@ struct serial_s { uint32_t databits; uint32_t stopbits; uint32_t parity; + PinName pin_tx; + PinName pin_rx; }; struct spi_s { @@ -75,10 +78,15 @@ struct spi_s { uint32_t mode; uint32_t nss; uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; }; struct i2c_s { I2CName i2c; + uint32_t slave; }; struct pwmout_s { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c index 7f1ab299f5..78a4cf9ec1 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c @@ -28,45 +28,51 @@ ******************************************************************************* */ #include "mbed_assert.h" -#include "device.h" #include "pinmap.h" +#include "PortNames.h" #include "mbed_error.h" -// Alternate-function mapping -static const uint32_t AF_mapping[] = { - 0, // 0 = No AF - GPIO_Remap_SPI1, // 1 - GPIO_Remap_I2C1, // 2 - GPIO_Remap_USART1, // 3 - GPIO_Remap_USART2, // 4 - GPIO_FullRemap_TIM2, // 5 - GPIO_FullRemap_TIM3, // 6 - GPIO_PartialRemap_TIM3, // 7 - GPIO_Remap_I2C1 // 8 +// GPIO mode look-up table +// Warning: the elements order must be the same as the one defined in PinNames.h +static const uint32_t gpio_mode[13] = { + GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT + GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP + GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD + GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP + GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD + GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG + GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING + GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING + GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING + GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING + GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING + GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING + 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL) }; // Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) { +uint32_t Set_GPIO_Clock(uint32_t port_idx) +{ uint32_t gpio_add = 0; switch (port_idx) { case PortA: gpio_add = GPIOA_BASE; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + __GPIOA_CLK_ENABLE(); break; case PortB: gpio_add = GPIOB_BASE; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + __GPIOB_CLK_ENABLE(); break; case PortC: gpio_add = GPIOC_BASE; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + __GPIOC_CLK_ENABLE(); break; case PortD: gpio_add = GPIOD_BASE; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); + __GPIOD_CLK_ENABLE(); break; default: - error("Port number is not correct."); + error("Pinmap error: wrong port number."); break; } return gpio_add; @@ -75,10 +81,12 @@ uint32_t Set_GPIO_Clock(uint32_t port_idx) { /** * Configure pin (input, output, alternate function or analog) + output speed + AF */ -void pin_function(PinName pin, int data) { +void pin_function(PinName pin, int data) +{ MBED_ASSERT(pin != (PinName)NC); // Get the pin informations uint32_t mode = STM_PIN_MODE(data); + uint32_t pupd = STM_PIN_PUPD(data); uint32_t afnum = STM_PIN_AFNUM(data); uint32_t port_index = STM_PORT(pin); @@ -89,37 +97,68 @@ void pin_function(PinName pin, int data) { GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; // Enable AFIO clock - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + __HAL_RCC_AFIO_CLK_ENABLE(); // Configure Alternate Function // Warning: Must be done before the GPIO is initialized if (afnum > 0) { - GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE); + switch (afnum) { + case 1: // Remap SPI1 + __HAL_AFIO_REMAP_SPI1_ENABLE(); + break; + case 2: // Remap I2C1 + __HAL_AFIO_REMAP_I2C1_ENABLE(); + break; + case 3: // Remap USART1 + __HAL_AFIO_REMAP_USART1_ENABLE(); + break; + case 4: // Remap USART2 + __HAL_AFIO_REMAP_USART2_ENABLE(); + break; + case 5: // Partial Remap USART3 + __HAL_AFIO_REMAP_USART3_PARTIAL(); + break; + case 6: // Partial Remap TIM1 + __HAL_AFIO_REMAP_TIM1_PARTIAL(); + break; + case 7: // Partial Remap TIM3 + __HAL_AFIO_REMAP_TIM3_PARTIAL(); + break; + case 8: // Full Remap TIM2 + __HAL_AFIO_REMAP_TIM2_ENABLE(); + break; + case 9: // Full Remap TIM3 + __HAL_AFIO_REMAP_TIM3_ENABLE(); + break; + default: + break; + } } // Configure GPIO GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index); - GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(gpio, &GPIO_InitStructure); + GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); + GPIO_InitStructure.Mode = gpio_mode[mode]; + GPIO_InitStructure.Pull = pupd; + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(gpio, &GPIO_InitStructure); // Disconnect JTAG-DP + SW-DP signals. // Warning: Need to reconnect under reset if ((pin == PA_13) || (pin == PA_14)) { - GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE); + __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled } if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) { - GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); + __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled } } /** * Configure pin pull-up/pull-down */ -void pin_mode(PinName pin, PinMode mode) { +void pin_mode(PinName pin, PinMode mode) +{ MBED_ASSERT(pin != (PinName)NC); - GPIO_InitTypeDef GPIO_InitStructure; uint32_t port_index = STM_PORT(pin); uint32_t pin_index = STM_PIN(pin); @@ -131,14 +170,22 @@ void pin_mode(PinName pin, PinMode mode) { // Configure open-drain and pull-up/down switch (mode) { case PullNone: - return; - case PullUp: - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; break; + case PullUp: case PullDown: - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + // Set pull-up / pull-down for Input mode + if (pin_index < 8) { + if ((gpio->CRL & (0x03 << (pin_index * 4))) == 0) { // MODE bits = Input mode + gpio->CRL |= (0x08 << (pin_index * 4)); // Set pull-up / pull-down + } + } else { + if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) == 0) { // MODE bits = Input mode + gpio->CRH |= (0x08 << ((pin_index % 8) * 4)); // Set pull-up / pull-down + } + } break; case OpenDrain: + // Set open-drain for Output mode (General Purpose or Alternate Function) if (pin_index < 8) { if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain @@ -148,13 +195,8 @@ void pin_mode(PinName pin, PinMode mode) { gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain } } - return; + break; default: break; } - - // Configure GPIO - GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index); - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(gpio, &GPIO_InitStructure); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c index 48447ce6a1..ecfded6e59 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c @@ -38,11 +38,13 @@ extern uint32_t Set_GPIO_Clock(uint32_t port_idx); // high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) // low nibble = pin number -PinName port_pin(PortName port, int pin_n) { +PinName port_pin(PortName port, int pin_n) +{ return (PinName)(pin_n + (port << 4)); } -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ uint32_t port_index = (uint32_t)port; // Enable GPIO clock @@ -59,22 +61,23 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { port_dir(obj, dir); } -void port_dir(port_t *obj, PinDirection dir) { +void port_dir(port_t *obj, PinDirection dir) +{ uint32_t i; obj->direction = dir; for (i = 0; i < 16; i++) { // Process all pins if (obj->mask & (1 << i)) { // If the pin is used if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_Out_PP, 0)); - } - else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)); + pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } } } } -void port_mode(port_t *obj, PinMode mode) { +void port_mode(port_t *obj, PinMode mode) +{ uint32_t i; for (i = 0; i < 16; i++) { // Process all pins if (obj->mask & (1 << i)) { // If the pin is used @@ -83,15 +86,16 @@ void port_mode(port_t *obj, PinMode mode) { } } -void port_write(port_t *obj, int value) { +void port_write(port_t *obj, int value) +{ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); } -int port_read(port_t *obj) { +int port_read(port_t *obj) +{ if (obj->direction == PIN_OUTPUT) { return (*obj->reg_out & obj->mask); - } - else { // PIN_INPUT + } else { // PIN_INPUT return (*obj->reg_in & obj->mask); } } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c index adfe65f386..887ceb1b65 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c @@ -27,31 +27,30 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" #include "pwmout_api.h" +#if DEVICE_PWMOUT + #include "cmsis.h" #include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" -static const PinMap PinMap_PWM[] = { - // TIM2 full remap - {PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 5)}, // TIM2fr_CH2 - ARDUINO D3 - // TIM3 partial remap - {PB_4, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3pr_CH1 - ARDUINO D5 - // TIM4 default - {PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH1 - ARDUINO D10 - {NC, NC, 0} -}; +static TIM_HandleTypeDef TimHandle; -void pwmout_init(pwmout_t* obj, PinName pin) { +void pwmout_init(pwmout_t* obj, PinName pin) +{ // Get the peripheral name from the pin and assign it to the object obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(obj->pwm != (PWMName)NC); + + if (obj->pwm == (PWMName)NC) { + error("PWM error: pinout mapping failed."); + } // Enable TIM clock - if (obj->pwm == PWM_2) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); - if (obj->pwm == PWM_3) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); - if (obj->pwm == PWM_4) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); + if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); + if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); // Configure GPIO pinmap_pinout(pin, PinMap_PWM); @@ -63,88 +62,166 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwmout_period_us(obj, 20000); // 20 ms per default } -void pwmout_free(pwmout_t* obj) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_DeInit(tim); +void pwmout_free(pwmout_t* obj) +{ + // Configure GPIO + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -void pwmout_write(pwmout_t* obj, float value) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_OCInitTypeDef TIM_OCInitStructure; +void pwmout_write(pwmout_t* obj, float value) +{ + TIM_OC_InitTypeDef sConfig; + int channel = 0; + int complementary_channel = 0; - if (value < 0.0) { + TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); + + if (value < (float)0.0) { value = 0.0; - } else if (value > 1.0) { + } else if (value > (float)1.0) { value = 1.0; } obj->pulse = (uint32_t)((float)obj->period * value); - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = obj->pulse; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + // Configure channels + sConfig.OCMode = TIM_OCMODE_PWM1; + sConfig.Pulse = obj->pulse; + sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfig.OCFastMode = TIM_OCFAST_DISABLE; + sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - // Configure channel 1 - if ((obj->pin == PB_4) || (obj->pin == PB_6)) { - TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC1Init(tim, &TIM_OCInitStructure); + switch (obj->pin) { + + // Channels 1 + case PA_6: + case PA_8: + case PA_15: + case PB_4: + case PC_6: + channel = TIM_CHANNEL_1; + break; + + // Channels 1N + case PB_13: + channel = TIM_CHANNEL_1; + complementary_channel = 1; + break; + + // Channels 2 + case PA_1: + case PA_7: + case PA_9: + case PB_3: + case PB_5: + case PC_7: + channel = TIM_CHANNEL_2; + break; + + // Channels 2N + case PB_14: + channel = TIM_CHANNEL_2; + complementary_channel = 1; + break; + + // Channels 3 + case PA_2: + case PA_10: + case PB_0: + case PB_10: + case PC_8: + channel = TIM_CHANNEL_3; + break; + + // Channels 3N + case PB_15: + channel = TIM_CHANNEL_3; + complementary_channel = 1; + break; + + // Channels 4 + case PA_3: + case PA_11: + case PB_1: + case PB_11: + case PC_9: + channel = TIM_CHANNEL_4; + break; + + default: + return; } - // Configure channel 2 - if (obj->pin == PB_3) { - TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC2Init(tim, &TIM_OCInitStructure); + HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); + + if (complementary_channel) { + HAL_TIMEx_PWMN_Start(&TimHandle, channel); + } else { + HAL_TIM_PWM_Start(&TimHandle, channel); } } -float pwmout_read(pwmout_t* obj) { +float pwmout_read(pwmout_t* obj) +{ float value = 0; if (obj->period > 0) { value = (float)(obj->pulse) / (float)(obj->period); } - return ((value > 1.0) ? (1.0) : (value)); + return ((value > (float)1.0) ? (float)(1.0) : (value)); } -void pwmout_period(pwmout_t* obj, float seconds) { +void pwmout_period(pwmout_t* obj, float seconds) +{ pwmout_period_us(obj, seconds * 1000000.0f); } -void pwmout_period_ms(pwmout_t* obj, int ms) { +void pwmout_period_ms(pwmout_t* obj, int ms) +{ pwmout_period_us(obj, ms * 1000); } -void pwmout_period_us(pwmout_t* obj, int us) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +void pwmout_period_us(pwmout_t* obj, int us) +{ + TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); + float dc = pwmout_read(obj); - TIM_Cmd(tim, DISABLE); + __HAL_TIM_DISABLE(&TimHandle); - obj->period = us; + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); - TIM_TimeBaseStructure.TIM_Period = obj->period - 1; - TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure); + TimHandle.Init.Period = us - 1; + TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimHandle.Init.ClockDivision = 0; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + HAL_TIM_PWM_Init(&TimHandle); // Set duty cycle again pwmout_write(obj, dc); - TIM_ARRPreloadConfig(tim, ENABLE); - TIM_Cmd(tim, ENABLE); + // Save for future use + obj->period = us; + + __HAL_TIM_ENABLE(&TimHandle); } -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ pwmout_pulsewidth_us(obj, seconds * 1000000.0f); } -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ pwmout_pulsewidth_us(obj, ms * 1000); } -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ float value = (float)us / (float)obj->period; pwmout_write(obj, value); } + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c index b3a88b10fa..badd51f70d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c @@ -29,58 +29,161 @@ */ #include "rtc_api.h" +#if DEVICE_RTC + +#include "mbed_error.h" + static int rtc_inited = 0; - -void rtc_init(void) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); // Enable PWR and Backup clock - - PWR_BackupAccessCmd(ENABLE); // Allow access to Backup Domain - BKP_DeInit(); // Reset Backup Domain +static RTC_HandleTypeDef RtcHandle; - // Uncomment these lines if you use the LSE - // Enable LSE and wait till it's ready - //RCC_LSEConfig(RCC_LSE_ON); - //while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {} - //RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select LSE as RTC Clock Source - - // Uncomment these lines if you use the LSI - // Enable LSI and wait till it's ready - RCC_LSICmd(ENABLE); - while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source - - RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock - - RTC_WaitForSynchro(); // Wait for RTC registers synchronization - - RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished - - // Set RTC period to 1 sec - // For LSE: prescaler = RTCCLK/RTC period = 32768Hz/1Hz = 32768 - // For LSI: prescaler = RTCCLK/RTC period = 40000Hz/1Hz = 40000 - RTC_SetPrescaler(39999); - - RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished +void rtc_init(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + if (rtc_inited) return; rtc_inited = 1; + + RtcHandle.Instance = RTC; + + // Enable Power clock + __HAL_RCC_PWR_CLK_ENABLE(); + + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); + + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + // Enable LSE Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + // Connect LSE to RTC + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); + } else { + // Enable LSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("RTC error: LSI clock initialization failed."); + } + // Connect LSI to RTC + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); + } + + // Enable RTC + __HAL_RCC_RTC_ENABLE(); + + RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND; + + if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { + error("RTC error: RTC initialization failed."); + } } -void rtc_free(void) { - RCC_DeInit(); // Resets the RCC clock configuration to the default reset state +void rtc_free(void) +{ + // Enable Power clock + __PWR_CLK_ENABLE(); + + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); + + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + // Disable access to Backup domain + HAL_PWR_DisableBkUpAccess(); + + // Disable LSI and LSE clocks + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_OFF; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + rtc_inited = 0; } -int rtc_isenabled(void) { +int rtc_isenabled(void) +{ return rtc_inited; } -time_t rtc_read(void) { - return (time_t)RTC_GetCounter(); +/* + RTC Registers + RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday + RTC_Month 1=january, 2=february, ..., 12=december + RTC_Date day of the month 1-31 + RTC_Year year 0-99 + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +time_t rtc_read(void) +{ + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + struct tm timeinfo; + + RtcHandle.Instance = RTC; + + // Read actual date and time + // Warning: the time must be read first! + HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); + HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); + + // Setup a tm structure based on the RTC + timeinfo.tm_wday = dateStruct.WeekDay; + timeinfo.tm_mon = dateStruct.Month - 1; + timeinfo.tm_mday = dateStruct.Date; + timeinfo.tm_year = dateStruct.Year + 100; + timeinfo.tm_hour = timeStruct.Hours; + timeinfo.tm_min = timeStruct.Minutes; + timeinfo.tm_sec = timeStruct.Seconds; + + // Convert to timestamp + time_t t = mktime(&timeinfo); + + return t; } -void rtc_write(time_t t) { - RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished - RTC_SetCounter(t); // Change the current time - RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished +void rtc_write(time_t t) +{ + RTC_DateTypeDef dateStruct; + RTC_TimeTypeDef timeStruct; + + RtcHandle.Instance = RTC; + + // Convert the time into a tm + struct tm *timeinfo = localtime(&t); + + // Fill RTC structures + dateStruct.WeekDay = timeinfo->tm_wday; + dateStruct.Month = timeinfo->tm_mon + 1; + dateStruct.Date = timeinfo->tm_mday; + dateStruct.Year = timeinfo->tm_year - 100; + timeStruct.Hours = timeinfo->tm_hour; + timeStruct.Minutes = timeinfo->tm_min; + timeStruct.Seconds = timeinfo->tm_sec; + + // Change the RTC current date/time + HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); + HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); } + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c index 7a9cbe8bd5..6a34be2ca0 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c @@ -29,23 +29,13 @@ */ #include "mbed_assert.h" #include "serial_api.h" + +#if DEVICE_SERIAL + #include "cmsis.h" #include "pinmap.h" #include - -static const PinMap PinMap_UART_TX[] = { - {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {PB_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, - {PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, - {PB_11, UART_3, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, - {NC, NC, 0} -}; +#include "PeripheralPins.h" #define UART_NUM (3) @@ -53,27 +43,34 @@ static uint32_t serial_irq_ids[UART_NUM] = {0,0,0}; static uart_irq_handler irq_handler; +UART_HandleTypeDef UartHandle; + int stdio_uart_inited = 0; serial_t stdio_uart; -static void init_usart(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_InitTypeDef USART_InitStructure; +static void init_uart(serial_t *obj) +{ + UartHandle.Instance = (USART_TypeDef *)(obj->uart); - USART_Cmd(usart, DISABLE); + UartHandle.Init.BaudRate = obj->baudrate; + UartHandle.Init.WordLength = obj->databits; + UartHandle.Init.StopBits = obj->stopbits; + UartHandle.Init.Parity = obj->parity; + UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - USART_InitStructure.USART_BaudRate = obj->baudrate; - USART_InitStructure.USART_WordLength = obj->databits; - USART_InitStructure.USART_StopBits = obj->stopbits; - USART_InitStructure.USART_Parity = obj->parity; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(usart, &USART_InitStructure); + if (obj->pin_rx == NC) { + UartHandle.Init.Mode = UART_MODE_TX; + } else if (obj->pin_tx == NC) { + UartHandle.Init.Mode = UART_MODE_RX; + } else { + UartHandle.Init.Mode = UART_MODE_TX_RX; + } - USART_Cmd(usart, ENABLE); + HAL_UART_Init(&UartHandle); } -void serial_init(serial_t *obj, PinName tx, PinName rx) { +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ // Determine the UART to use (UART_1, UART_2, ...) UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); @@ -82,112 +79,157 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); MBED_ASSERT(obj->uart != (UARTName)NC); - // Enable USART clock + // Enable UART clock if (obj->uart == UART_1) { - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); - } else if (obj->uart == UART_2 ) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - } else if (obj->uart == UART_3 ) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + __HAL_RCC_USART1_CLK_ENABLE(); + obj->index = 0; + } + if (obj->uart == UART_2) { + __HAL_RCC_USART2_CLK_ENABLE(); + obj->index = 1; + } + if (obj->uart == UART_3) { + __HAL_RCC_USART3_CLK_ENABLE(); + obj->index = 2; } - // Configure the UART pins + // Configure UART pins pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } // Configure UART obj->baudrate = 9600; - obj->databits = USART_WordLength_8b; - obj->stopbits = USART_StopBits_1; - obj->parity = USART_Parity_No; + obj->databits = UART_WORDLENGTH_8B; + obj->stopbits = UART_STOPBITS_1; + obj->parity = UART_PARITY_NONE; - init_usart(obj); + obj->pin_tx = tx; + obj->pin_rx = rx; - // The index is used by irq - if (obj->uart == UART_1) obj->index = 0; - if (obj->uart == UART_2) obj->index = 1; - if (obj->uart == UART_3) obj->index = 2; + init_uart(obj); // For stdio management if (obj->uart == STDIO_UART) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } +} +void serial_free(serial_t *obj) +{ + // Reset UART and disable clock + if (obj->uart == UART_1) { + __USART1_FORCE_RESET(); + __USART1_RELEASE_RESET(); + __USART1_CLK_DISABLE(); + } + if (obj->uart == UART_2) { + __USART2_FORCE_RESET(); + __USART2_RELEASE_RESET(); + __USART2_CLK_DISABLE(); + } + if (obj->uart == UART_3) { + __USART3_FORCE_RESET(); + __USART3_RELEASE_RESET(); + __USART3_CLK_DISABLE(); } -void serial_free(serial_t *obj) { + // Configure GPIOs + pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + serial_irq_ids[obj->index] = 0; } -void serial_baud(serial_t *obj, int baudrate) { +void serial_baud(serial_t *obj, int baudrate) +{ obj->baudrate = baudrate; - init_usart(obj); + init_uart(obj); } -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - if (data_bits == 8) { - obj->databits = USART_WordLength_8b; - } - else { - obj->databits = USART_WordLength_9b; +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + if (data_bits == 9) { + obj->databits = UART_WORDLENGTH_9B; + } else { + obj->databits = UART_WORDLENGTH_8B; } switch (parity) { case ParityOdd: case ParityForced0: - obj->parity = USART_Parity_Odd; + obj->parity = UART_PARITY_ODD; break; case ParityEven: case ParityForced1: - obj->parity = USART_Parity_Even; + obj->parity = UART_PARITY_EVEN; break; default: // ParityNone - obj->parity = USART_Parity_No; + obj->parity = UART_PARITY_NONE; break; } if (stop_bits == 2) { - obj->stopbits = USART_StopBits_2; - } - else { - obj->stopbits = USART_StopBits_1; + obj->stopbits = UART_STOPBITS_2; + } else { + obj->stopbits = UART_STOPBITS_1; } - init_usart(obj); + init_uart(obj); } /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ -// not api -static void uart_irq(USART_TypeDef* usart, int id) { +static void uart_irq(UARTName name, int id) +{ + UartHandle.Instance = (USART_TypeDef *)name; if (serial_irq_ids[id] != 0) { - if (USART_GetITStatus(usart, USART_IT_TC) != RESET) { + if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { irq_handler(serial_irq_ids[id], TxIrq); - USART_ClearITPendingBit(usart, USART_IT_TC); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC); } - if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) { + if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { irq_handler(serial_irq_ids[id], RxIrq); - USART_ClearITPendingBit(usart, USART_IT_RXNE); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); + } } } + +static void uart1_irq(void) +{ + uart_irq(UART_1, 0); } -static void uart1_irq(void) {uart_irq((USART_TypeDef*)UART_1, 0);} -static void uart2_irq(void) {uart_irq((USART_TypeDef*)UART_2, 1);} -static void uart3_irq(void) {uart_irq((USART_TypeDef*)UART_3, 2);} +static void uart2_irq(void) +{ + uart_irq(UART_2, 1); +} -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +static void uart3_irq(void) +{ + uart_irq(UART_3, 2); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ irq_handler = handler; serial_irq_ids[obj->index] = id; } -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); + + UartHandle.Instance = (USART_TypeDef *)(obj->uart); if (obj->uart == UART_1) { irq_n = USART1_IRQn; @@ -207,10 +249,9 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { if (enable) { if (irq == RxIrq) { - USART_ITConfig(usart, USART_IT_RXNE, ENABLE); - } - else { // TxIrq - USART_ITConfig(usart, USART_IT_TC, ENABLE); + __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); + } else { // TxIrq + __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); } NVIC_SetVector(irq_n, vector); @@ -221,14 +262,13 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { int all_disabled = 0; if (irq == RxIrq) { - USART_ITConfig(usart, USART_IT_RXNE, DISABLE); + __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); // Check if TxIrq is disabled too - if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1; - } - else { // TxIrq - USART_ITConfig(usart, USART_IT_TXE, DISABLE); + if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; + } else { // TxIrq + __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); // Check if RxIrq is disabled too - if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; + if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; } if (all_disabled) NVIC_DisableIRQ(irq_n); @@ -240,48 +280,66 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { * READ/WRITE ******************************************************************************/ -int serial_getc(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); +int serial_getc(serial_t *obj) +{ + USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); while (!serial_readable(obj)); - return (int)(USART_ReceiveData(usart)); + if (obj->databits == UART_WORDLENGTH_8B) { + return (int)(uart->DR & (uint8_t)0xFF); + } else { + return (int)(uart->DR & (uint16_t)0x1FF); + } } -void serial_putc(serial_t *obj, int c) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); +void serial_putc(serial_t *obj, int c) +{ + USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); while (!serial_writable(obj)); - USART_SendData(usart, (uint16_t)c); + if (obj->databits == UART_WORDLENGTH_8B) { + uart->DR = (uint8_t)(c & (uint8_t)0xFF); + } else { + uart->DR = (uint16_t)(c & (uint16_t)0x1FF); + } } -int serial_readable(serial_t *obj) { +int serial_readable(serial_t *obj) +{ int status; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); + UartHandle.Instance = (USART_TypeDef *)(obj->uart); // Check if data is received - status = ((USART_GetFlagStatus(usart, USART_FLAG_RXNE) != RESET) ? 1 : 0); + status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); return status; } -int serial_writable(serial_t *obj) { +int serial_writable(serial_t *obj) +{ int status; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); + UartHandle.Instance = (USART_TypeDef *)(obj->uart); // Check if data is transmitted - status = ((USART_GetFlagStatus(usart, USART_FLAG_TXE) != RESET) ? 1 : 0); + status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); return status; } -void serial_clear(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_ClearFlag(usart, USART_FLAG_TXE); - USART_ClearFlag(usart, USART_FLAG_RXNE); +void serial_clear(serial_t *obj) +{ + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE); + __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); } -void serial_pinout_tx(PinName tx) { +void serial_pinout_tx(PinName tx) +{ pinmap_pinout(tx, PinMap_UART_TX); } -void serial_break_set(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_SendBreak(usart); +void serial_break_set(serial_t *obj) +{ + UartHandle.Instance = (USART_TypeDef *)(obj->uart); + HAL_LIN_SendBreak(&UartHandle); } -void serial_break_clear(serial_t *obj) { +void serial_break_clear(serial_t *obj) +{ } + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c index 4cc5d17f4b..1d7df4131b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c @@ -28,31 +28,35 @@ ******************************************************************************* */ #include "sleep_api.h" + +#if DEVICE_SLEEP + #include "cmsis.h" +#include "hal_tick.h" + +static TIM_HandleTypeDef TimMasterHandle; void sleep(void) { - // Disable us_ticker update interrupt - TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE); + TimMasterHandle.Instance = TIM_MST; + + // Disable HAL tick and us_ticker update interrupts + __HAL_TIM_DISABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE)); - SCB->SCR = 0; // Normal sleep mode for ARM core - __WFI(); + // Request to enter SLEEP mode + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - // Re-enable us_ticker update interrupt - TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); + // Enable HAL tick and us_ticker update interrupts + __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE)); } void deepsleep(void) { - // Disable us_ticker update interrupt - TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE); - - // Enable PWR clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - // Request to enter STOP mode with regulator in low power mode - PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - // Re-enable us_ticker update interrupt - TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); + // After wake-up from STOP reconfigure the PLL + SetSysClock(); } + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c index b2d53cd3e1..d3e0a25e56 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c @@ -35,52 +35,35 @@ #include #include "cmsis.h" #include "pinmap.h" +#include "PeripheralPins.h" -static const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {PB_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap - {NC, NC, 0} -}; +static SPI_HandleTypeDef SpiHandle; -static const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {PB_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap - {NC, NC, 0} -}; +static void init_spi(spi_t *obj) +{ + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); -static const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, - {PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap - {NC, NC, 0} -}; + __HAL_SPI_DISABLE(&SpiHandle); -// Only used in Slave mode -static const PinMap PinMap_SPI_SSEL[] = { - {PB_6, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, // Generic IO, not real H/W NSS pin - {NC, NC, 0} -}; + SpiHandle.Init.Mode = obj->mode; + SpiHandle.Init.BaudRatePrescaler = obj->br_presc; + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = obj->cpha; + SpiHandle.Init.CLKPolarity = obj->cpol; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + SpiHandle.Init.CRCPolynomial = 7; + SpiHandle.Init.DataSize = obj->bits; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.NSS = obj->nss; + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; -static void init_spi(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - SPI_InitTypeDef SPI_InitStructure; + HAL_SPI_Init(&SpiHandle); - SPI_Cmd(spi, DISABLE); - - SPI_InitStructure.SPI_Mode = obj->mode; - SPI_InitStructure.SPI_NSS = obj->nss; - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_DataSize = obj->bits; - SPI_InitStructure.SPI_CPOL = obj->cpol; - SPI_InitStructure.SPI_CPHA = obj->cpha; - SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(spi, &SPI_InitStructure); - - SPI_Cmd(spi, ENABLE); + __HAL_SPI_ENABLE(&SpiHandle); } -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ // Determine the SPI to use SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); @@ -95,7 +78,10 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel // Enable SPI clock if (obj->spi == SPI_1) { - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); + __SPI1_CLK_ENABLE(); + } + if (obj->spi == SPI_2) { + __SPI2_CLK_ENABLE(); } // Configure the SPI pins @@ -104,146 +90,231 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel pinmap_pinout(sclk, PinMap_SPI_SCLK); // Save new values - obj->bits = SPI_DataSize_8b; - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_1Edge; - obj->br_presc = SPI_BaudRatePrescaler_256; // 1MHz - - if (ssel == NC) { // Master - obj->mode = SPI_Mode_Master; - obj->nss = SPI_NSS_Soft; - } - else { // Slave + obj->bits = SPI_DATASIZE_8BIT; + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_1EDGE; + obj->br_presc = SPI_BAUDRATEPRESCALER_256; + + obj->pin_miso = miso; + obj->pin_mosi = mosi; + obj->pin_sclk = sclk; + obj->pin_ssel = ssel; + + if (ssel == NC) { // SW NSS Master mode + obj->mode = SPI_MODE_MASTER; + obj->nss = SPI_NSS_SOFT; + } else { // Slave pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_Mode_Slave; - obj->nss = SPI_NSS_Soft; + obj->mode = SPI_MODE_SLAVE; + obj->nss = SPI_NSS_HARD_INPUT; } init_spi(obj); } -void spi_free(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - SPI_I2S_DeInit(spi); +void spi_free(spi_t *obj) +{ + // Reset SPI and disable clock + if (obj->spi == SPI_1) { + __SPI1_FORCE_RESET(); + __SPI1_RELEASE_RESET(); + __SPI1_CLK_DISABLE(); } -void spi_format(spi_t *obj, int bits, int mode, int slave) { - // Save new values - if (bits == 8) { - obj->bits = SPI_DataSize_8b; + if (obj->spi == SPI_2) { + __SPI2_FORCE_RESET(); + __SPI2_RELEASE_RESET(); + __SPI2_CLK_DISABLE(); } - else { - obj->bits = SPI_DataSize_16b; + + // Configure GPIOs + pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Save new values + if (bits == 16) { + obj->bits = SPI_DATASIZE_16BIT; + } else { + obj->bits = SPI_DATASIZE_8BIT; } switch (mode) { case 0: - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_1Edge; + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_1EDGE; break; case 1: - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_2Edge; + obj->cpol = SPI_POLARITY_LOW; + obj->cpha = SPI_PHASE_2EDGE; break; case 2: - obj->cpol = SPI_CPOL_High; - obj->cpha = SPI_CPHA_1Edge; + obj->cpol = SPI_POLARITY_HIGH; + obj->cpha = SPI_PHASE_1EDGE; break; default: - obj->cpol = SPI_CPOL_High; - obj->cpha = SPI_CPHA_2Edge; + obj->cpol = SPI_POLARITY_HIGH; + obj->cpha = SPI_PHASE_2EDGE; break; } if (slave == 0) { - obj->mode = SPI_Mode_Master; - obj->nss = SPI_NSS_Soft; - } - else { - obj->mode = SPI_Mode_Slave; - obj->nss = SPI_NSS_Hard; + obj->mode = SPI_MODE_MASTER; + obj->nss = SPI_NSS_SOFT; + } else { + obj->mode = SPI_MODE_SLAVE; + obj->nss = SPI_NSS_HARD_INPUT; } init_spi(obj); } -void spi_frequency(spi_t *obj, int hz) { - // Choose the baud rate divisor (between 2 and 256) - uint32_t divisor = SystemCoreClock / hz; - - // Find the nearest power-of-2 - divisor = (divisor > 0 ? divisor-1 : 0); - divisor |= divisor >> 1; - divisor |= divisor >> 2; - divisor |= divisor >> 4; - divisor |= divisor >> 8; - divisor |= divisor >> 16; - divisor++; - - uint32_t baud_rate = __builtin_ffs(divisor) - 2; +void spi_frequency(spi_t *obj, int hz) +{ + if (obj->spi == SPI_1) { + // Values depend of PCLK2: 64 MHz if HSI is used, 72 MHz if HSE is used + if (hz < 500000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 281 kHz + } else if ((hz >= 500000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 563 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz + } else if ((hz >= 2000000) && (hz < 4000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz + } else if ((hz >= 4000000) && (hz < 8000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz + } else if ((hz >= 8000000) && (hz < 16000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz + } else if ((hz >= 16000000) && (hz < 32000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz + } else { // >= 32000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz + } + } - // Save new value - obj->br_presc = ((baud_rate > 7) ? (7 << 3) : (baud_rate << 3)); + if (obj->spi == SPI_2) { + // Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used + if (hz < 250000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz + } else if ((hz >= 250000) && (hz < 500000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 281 kHz + } else if ((hz >= 500000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 563 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz + } else if ((hz >= 2000000) && (hz < 4000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz + } else if ((hz >= 4000000) && (hz < 8000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz + } else if ((hz >= 8000000) && (hz < 16000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz + } else { // >= 16000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz + } + } init_spi(obj); } -static inline int ssp_readable(spi_t *obj) { +static inline int ssp_readable(spi_t *obj) +{ int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); // Check if data is received - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0); + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); return status; } -static inline int ssp_writeable(spi_t *obj) { +static inline int ssp_writeable(spi_t *obj) +{ int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); // Check if data is transmitted - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_TXE) != RESET) ? 1 : 0); + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); return status; } -static inline void ssp_write(spi_t *obj, int value) { +static inline void ssp_write(spi_t *obj, int value) +{ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_writeable(obj)); - SPI_I2S_SendData(spi, (uint16_t)value); + if (obj->bits == SPI_DATASIZE_8BIT) { + // Force 8-bit access to the data register + uint8_t *p_spi_dr = 0; + p_spi_dr = (uint8_t *) & (spi->DR); + *p_spi_dr = (uint8_t)value; + } else { // SPI_DATASIZE_16BIT + spi->DR = (uint16_t)value; + } } -static inline int ssp_read(spi_t *obj) { +static inline int ssp_read(spi_t *obj) +{ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_readable(obj)); - return (int)SPI_I2S_ReceiveData(spi); + if (obj->bits == SPI_DATASIZE_8BIT) { + // Force 8-bit access to the data register + uint8_t *p_spi_dr = 0; + p_spi_dr = (uint8_t *) & (spi->DR); + return (int)(*p_spi_dr); + } else { + return (int)spi->DR; + } } -static inline int ssp_busy(spi_t *obj) { +static inline int ssp_busy(spi_t *obj) +{ int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_BSY) != RESET) ? 1 : 0); + SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); + status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); return status; } -int spi_master_write(spi_t *obj, int value) { +int spi_master_write(spi_t *obj, int value) +{ ssp_write(obj, value); return ssp_read(obj); } -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +int spi_slave_receive(spi_t *obj) +{ + return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); }; -int spi_slave_read(spi_t *obj) { +int spi_slave_read(spi_t *obj) +{ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - return (int)SPI_I2S_ReceiveData(spi); + while (!ssp_readable(obj)); + if (obj->bits == SPI_DATASIZE_8BIT) { + // Force 8-bit access to the data register + uint8_t *p_spi_dr = 0; + p_spi_dr = (uint8_t *) & (spi->DR); + return (int)(*p_spi_dr); + } else { + return (int)spi->DR; + } } -void spi_slave_write(spi_t *obj, int value) { +void spi_slave_write(spi_t *obj, int value) +{ SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_writeable(obj)); - SPI_I2S_SendData(spi, (uint16_t)value); + if (obj->bits == SPI_DATASIZE_8BIT) { + // Force 8-bit access to the data register + uint8_t *p_spi_dr = 0; + p_spi_dr = (uint8_t *) & (spi->DR); + *p_spi_dr = (uint8_t)value; + } else { // SPI_DATASIZE_16BIT + spi->DR = (uint16_t)value; + } } -int spi_busy(spi_t *obj) { +int spi_busy(spi_t *obj) +{ return ssp_busy(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c index 7fdf4752c3..fe6e44896c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c @@ -29,90 +29,35 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" -// Timer selection: -#define TIM_MST TIM1 -#define TIM_MST_UP_IRQ TIM1_UP_TIM16_IRQn -#define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE) +// Timer selection +#define TIM_MST TIM4 +static TIM_HandleTypeDef TimMasterHandle; static int us_ticker_inited = 0; -static volatile uint32_t SlaveCounter = 0; -static volatile uint32_t oc_int_part = 0; -static volatile uint16_t oc_rem_part = 0; -void set_compare(uint16_t count) { +volatile uint32_t SlaveCounter = 0; +volatile uint32_t oc_int_part = 0; +volatile uint16_t oc_rem_part = 0; + +void set_compare(uint16_t count) +{ + TimMasterHandle.Instance = TIM_MST; // Set new output compare value - TIM_SetCompare1(TIM_MST, count); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); // Enable IT - TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -// Used to increment the slave counter -static void tim_update_irq_handler(void) { - if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update); - SlaveCounter++; - } -} - -// Used by interrupt system -static void tim_oc_irq_handler(void) { - uint16_t cval = TIM_MST->CNT; - - // Clear interrupt flag - if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { - TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); - } - - if (oc_rem_part > 0) { - set_compare(oc_rem_part); // Finish the remaining time left - oc_rem_part = 0; - } - else { - if (oc_int_part > 0) { - set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time - oc_int_part--; - } - else { - us_ticker_irq_handler(); - } - } -} - -void us_ticker_init(void) { - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - +void us_ticker_init(void) +{ if (us_ticker_inited) return; us_ticker_inited = 1; - // Enable Timer clock - TIM_MST_RCC; - - // Configure time base - TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.TIM_Period = 0xFFFF; - TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); - - // Configure interrupts - TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE); - - // Update interrupt used for 32-bit counter - NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); - NVIC_EnableIRQ(TIM_MST_UP_IRQ); - - // Output compare interrupt used for timeout feature - NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); - NVIC_EnableIRQ(TIM_MST_OC_IRQ); - - // Enable timer - TIM_Cmd(TIM_MST, ENABLE); + HAL_InitTick(0); // The passed value is not used } -uint32_t us_ticker_read() { +uint32_t us_ticker_read() +{ uint32_t counter, counter2; if (!us_ticker_inited) us_ticker_init(); // A situation might appear when Master overflows right after Slave is read and before the @@ -133,14 +78,14 @@ uint32_t us_ticker_read() { return counter2; } -void us_ticker_set_interrupt(timestamp_t timestamp) { +void us_ticker_set_interrupt(timestamp_t timestamp) +{ int delta = (int)((uint32_t)timestamp - us_ticker_read()); uint16_t cval = TIM_MST->CNT; if (delta <= 0) { // This event was in the past us_ticker_irq_handler(); - } - else { + } else { oc_int_part = (uint32_t)(delta >> 16); oc_rem_part = (uint16_t)(delta & 0xFFFF); if (oc_rem_part <= (0xFFFF - cval)) { @@ -153,12 +98,16 @@ void us_ticker_set_interrupt(timestamp_t timestamp) { } } -void us_ticker_disable_interrupt(void) { - TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE); +void us_ticker_disable_interrupt(void) +{ + TimMasterHandle.Instance = TIM_MST; + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_clear_interrupt(void) { - if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { - TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); +void us_ticker_clear_interrupt(void) +{ + TimMasterHandle.Instance = TIM_MST; + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { + __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); } } From 94e6ba94416d5d41bf8f4b644029f25b749a4fb4 Mon Sep 17 00:00:00 2001 From: GustavWi Date: Wed, 25 Mar 2015 14:43:06 +0100 Subject: [PATCH 038/143] Fixed documentation and pylint messages --- workspace_tools/export/iar.py | 85 ++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 31 deletions(-) diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 4b65e3d88d..d13cdc9473 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -14,11 +14,13 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ -from exporters import Exporter +from workspace_tools.export.exporters import Exporter import re import os -from os.path import join, dirname class IAREmbeddedWorkbench(Exporter): + """ + Exporter class for IAR Systems. + """ NAME = 'IAR' TOOLCHAIN = 'IAR' @@ -71,15 +73,18 @@ class IAREmbeddedWorkbench(Exporter): ] def generate(self): + """ + Generates the project files + """ sources = [] sources += self.resources.c_sources sources += self.resources.cpp_sources sources += self.resources.s_sources - - iar_files = IAR_FOLDER("","",[]) + + iar_files = IarFolder("", "", []) for source in sources: iar_files.insert_file(source) - + ctx = { 'name': self.program_name, 'include_paths': self.resources.inc_dirs, @@ -94,18 +99,31 @@ class IAREmbeddedWorkbench(Exporter): self.gen_file('iar.eww.tmpl', ctx, '%s.eww' % self.program_name) self.gen_file('iar_%s.ewd.tmpl' % self.target.lower(), ctx, '%s.ewd' % self.program_name) -class IAR_FOLDER: - #input: - #folder_level : folder path to current folder - #folder_name : name of current folder - #source_files : list of source_files (all must be in same directory) +class IarFolder(): + """ + This is a recursive folder object. + To present the folder structure in the IDE as it is presented on the disk. + This can be used for uvision as well if you replace the __str__ method. + Example: + files: ./main.cpp, ./apis/I2C.h, ./mbed/common/I2C.cpp + in the project this would look like: + main.cpp + common/I2C.cpp + input: + folder_level : folder path to current folder + folder_name : name of current folder + source_files : list of source_files (all must be in same directory) + """ def __init__(self, folder_level, folder_name, source_files): self.folder_level = folder_level self.folder_name = folder_name self.source_files = source_files - self.sub_folders = {}; - + self.sub_folders = {} + def __str__(self): + """ + converts the folder structue to IAR project format. + """ group_start = "" group_end = "" if self.folder_name != "": @@ -117,41 +135,46 @@ class IAR_FOLDER: if self.source_files: for src in self.source_files: str_content += "\n$PROJ_DIR$/%s\n\n" % src - ##Add sub folders + #Add sub folders if self.sub_folders: for folder_name in self.sub_folders.iterkeys(): str_content += self.sub_folders[folder_name].__str__() - + str_content += group_end return str_content - - + def insert_file(self, source_input): - - if self.source_files: - dir_sources = IAR_FOLDER.get_directory(self.source_files[0]) ##All source_files in a IAR_FOLDER must be in same directory. - if not self.folder_level == dir_sources: ## Check if sources are already at their deepest level. + """ + Inserts a source file into the folder tree + """ + if self.source_files: + #All source_files in a IarFolder must be in same directory. + dir_sources = IarFolder.get_directory(self.source_files[0]) + #Check if sources are already at their deepest level. + if not self.folder_level == dir_sources: _reg_exp = r"^" + re.escape(self.folder_level) + r"[/\\]?([^/\\]+)" - folder_name = re.match( _reg_exp, dir_sources).group(1) - self.sub_folders[folder_name] = IAR_FOLDER(os.path.join(self.folder_level,folder_name), folder_name, self.source_files) + folder_name = re.match(_reg_exp, dir_sources).group(1) + self.sub_folders[folder_name] = IarFolder(os.path.join(self.folder_level, folder_name), folder_name, self.source_files) self.source_files = [] - - dir_input = IAR_FOLDER.get_directory(source_input) + + dir_input = IarFolder.get_directory(source_input) if dir_input == self.folder_level: self.source_files.append(source_input) else: _reg_exp = r"^" + re.escape(self.folder_level) + r"[/\\]?([^/\\]+)" - folder_name = re.match( _reg_exp, dir_input).group(1) + folder_name = re.match(_reg_exp, dir_input).group(1) if self.sub_folders.has_key(folder_name): self.sub_folders[folder_name].insert_file(source_input) else: - if self.folder_level == "": #Top level exception - self.sub_folders[folder_name] = IAR_FOLDER(folder_name, folder_name, [source_input]) + if self.folder_level == "": + #Top level exception + self.sub_folders[folder_name] = IarFolder(folder_name, folder_name, [source_input]) else: - self.sub_folders[folder_name] = IAR_FOLDER(os.path.join(self.folder_level,folder_name), folder_name, [source_input]) + self.sub_folders[folder_name] = IarFolder(os.path.join(self.folder_level, folder_name), folder_name, [source_input]) - @staticmethod + @staticmethod def get_directory(file_path): + """ + Returns the directory of the file + """ return os.path.dirname(file_path) - - From e5f05b803368550a4a27abd59c5d2cbc01f08052 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 12 Jan 2015 09:58:15 -0600 Subject: [PATCH 039/143] [mbed][MTS_DRAGONFLY_F411RE] preliminary support for dragonfly bootloader. changed linker files to put application at 32kB offset added VECT_TAB_OFFSET define in targets.py so application runs properly after jump from bootloader --- .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 7 ++++--- .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 7 ++++--- .../TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld | 3 ++- workspace_tools/targets.py | 2 +- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct index c018724bf7..395f105294 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -27,10 +27,11 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) -LR_IROM1 0x08000000 0x80000 { ; load region size_region +; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000) +; FIRST 32 KB FLASH FOR BOOTLOADER +LR_IROM1 0x08008000 0x78000 { ; load region size_region - ER_IROM1 0x08000000 0x80000 { ; load address = execution address + ER_IROM1 0x08008000 0x78000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct index c018724bf7..395f105294 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -27,10 +27,11 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) -LR_IROM1 0x08000000 0x80000 { ; load region size_region +; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000) +; FIRST 32 KB FLASH FOR BOOTLOADER +LR_IROM1 0x08008000 0x78000 { ; load region size_region - ER_IROM1 0x08000000 0x80000 { ; load address = execution address + ER_IROM1 0x08008000 0x78000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld index 76a7538cde..b5ea4dd53e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld @@ -3,7 +3,8 @@ /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + /* First 32kB of flash reserved for bootloader */ + FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 480K /* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 } diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 69959e0749..c46b5aa65a 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -711,7 +711,7 @@ class MTS_DRAGONFLY_F411RE(Target): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] - self.macros = ['HSE_VALUE=26000000'] + self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08008000'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "ARM" From 952cc7551b4e70cc2850cd15473490b9e6efdaff Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 12 Jan 2015 15:20:18 -0600 Subject: [PATCH 040/143] [mbed][MTS_DRAGONFLY_F411RE] update application offset to 64kB --- .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 9 +++++---- .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 9 +++++---- .../TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld | 5 +++-- workspace_tools/targets.py | 2 +- 4 files changed, 14 insertions(+), 11 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct index 395f105294..491087ba47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -27,11 +27,12 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000) -; FIRST 32 KB FLASH FOR BOOTLOADER -LR_IROM1 0x08008000 0x78000 { ; load region size_region +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region - ER_IROM1 0x08008000 0x78000 { ; load address = execution address + ER_IROM1 0x08010000 0x70000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct index 395f105294..491087ba47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -27,11 +27,12 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000) -; FIRST 32 KB FLASH FOR BOOTLOADER -LR_IROM1 0x08008000 0x78000 { ; load region size_region +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region - ER_IROM1 0x08008000 0x78000 { ; load address = execution address + ER_IROM1 0x08010000 0x70000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld index b5ea4dd53e..a832fffb7e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld @@ -3,8 +3,9 @@ /* Linker script to configure memory regions. */ MEMORY { - /* First 32kB of flash reserved for bootloader */ - FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 480K + /* First 64kB of flash reserved for bootloader */ + /* Other 448kB for application */ + FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 } diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index c46b5aa65a..c3b7bcba8d 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -711,7 +711,7 @@ class MTS_DRAGONFLY_F411RE(Target): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] - self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08008000'] + self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08010000'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "ARM" From d41ef07d3263c16abb38f78c8467809005ca0445 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Tue, 13 Jan 2015 15:13:45 -0600 Subject: [PATCH 041/143] add precompiled bootloaders for supported toolchains (based on commit 9de96dce). add support for automatically generating bootloader+application binary --- .../bootloader-ARM_MICRO.bin | Bin 0 -> 31988 bytes .../bootloader-ARM_STD.bin | Bin 0 -> 43948 bytes .../bootloader-GCC_ARM.bin | Bin 0 -> 30352 bytes workspace_tools/paths.py | 1 + workspace_tools/targets.py | 26 ++++++++++++++++++ 5 files changed, 27 insertions(+) create mode 100644 workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader-ARM_MICRO.bin create mode 100644 workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader-ARM_STD.bin create mode 100755 workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader-GCC_ARM.bin diff --git a/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader-ARM_MICRO.bin b/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader-ARM_MICRO.bin new file mode 100644 index 0000000000000000000000000000000000000000..4beb95b7af0d58b81e572a7d27abf6d4cbf70481 GIT binary patch literal 31988 zcmb@v3w#vS**|_}c6N7mvq>fpAcQ5%ZUSrq=z>%O-ZqyeiCb4~INy2Wjo9ypbD=RD`R90*~>R)+9xc-rwC#q%DX_wkUg{P#PgeK?Z-2mF4F z=l}cv@%c)16j|YM(xOeSR=GlX-T)xrpg|>>KBpE1S~DQ6s$NZ`|^(ZYad-?-?8aRCn21J zYcOi=0fUeC(Knj2H2!5AT+!n0x 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zAsp-Vnl~^k(?Y{~J;JvU{ty%RJ%nR@AMv+&aG0^mLq@_>Ve3YsyYia|cV#vc?#jH2 za98Ht9{fHJ{!PMNey@C}$5;~j01=L9f-N=uw?Y39V`40q{x#xv@eaaW9HF+ogN;6hpoe`O-F3;k3z# zky^IAUAfX!|2))m{#(O9H= z?r?A4p1u9|f9rvL`{n6uPMKNTjwgnaDQR7%+O9QbHat4T4opt5_+$8(0E_~L04YEm zFh<*{DKtATPwS`ujOOJ~dSf^DP5~2myX|$hH`uM+YL$L02 zfbm_C-fqqc+Ciqw Date: Wed, 14 Jan 2015 10:07:27 -0600 Subject: [PATCH 042/143] [mbed][MTS_DRAGONFLY_F411RE] added custom linker file for IAR toolchain --- .../TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf | 2 +- workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf index f481cdbf14..d472306bb0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -1,6 +1,6 @@ /* [ROM = 512kb = 0x80000] */ define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08010000; define symbol __region_ROM_end__ = 0x0807FFFF; /* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ diff --git a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl b/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl index b20bc2d512..2f6173a5ff 100644 --- a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl +++ b/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl @@ -711,7 +711,7 @@ N6^lj$FZ<>R={b?utl;-}p_wi}bCSYHkR=g}d>Y(y$~flgb1G|umm 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zi^|jY7&Fx4`rqVVM&D;i4QuOXtzG49SYJQu-iGye%_7d8Wh?79)vr;UvzFiEU9(bk z-r`tPS#ispoQ*PTMuS3sQJ4GEMNBwsv}5;wIS#|Q`P)dG~B(Z ze*Fe0JxFtnrSn?lSy8`{qJGJ}1cfJ5m~`681!-o0u(QM1T#CSz@ zxN_e}@(}V?(CNTQO zp!!$+Ip{a|^5s*9)B4b#aOs!!ZB%}yEBw>|JC&c|3P1X8M>+mq{|IQ8-~so@zob&v z Date: Tue, 20 Jan 2015 09:26:01 -0600 Subject: [PATCH 044/143] [mbed][MTS_DRAGONFLY_F411RE] append MD5 checksum to combined binary for Dragonfly --- workspace_tools/targets.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 8ae06e047c..05984c5422 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -29,6 +29,7 @@ CORE_LABELS = { } import os +import hashlib import shutil from workspace_tools.patch import patch from paths import TOOLS_BOOTLOADERS @@ -720,6 +721,8 @@ class MTS_DRAGONFLY_F411RE(Target): if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']: hook.hook_add_binary("post", self.combine_bins) + # combine application binary with bootloader + # bootloader + padding to 64kB + application + md5sum (16 bytes) @staticmethod def combine_bins(t_self, resources, elf, binf): loader = os.path.join(TOOLS_BOOTLOADERS, "MTS_DRAGONFLY_F411RE", "bootloader.bin") @@ -727,7 +730,7 @@ class MTS_DRAGONFLY_F411RE(Target): if not os.path.exists(loader): print "Can't find bootloader binary: " + loader return - outbin = open(target, 'wb') + outbin = open(target, 'w+b') part = open(loader, 'rb') data = part.read() outbin.write(data) @@ -737,6 +740,9 @@ class MTS_DRAGONFLY_F411RE(Target): data = part.read() outbin.write(data) part.close() + data = outbin.read() + md5 = hashlib.md5(data) + outbin.write(md5.digest()) outbin.close() os.remove(binf) os.rename(target, binf) From da7c5fbc0fa58f514d8b224563e0dd2178bd5d12 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Fri, 6 Feb 2015 09:48:21 -0600 Subject: [PATCH 045/143] [mbed][MTS_DRAGONFLY_F411RE] use CRC32 instead of MD5 for checksum of binary --- workspace_tools/targets.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 05984c5422..d27fc5548c 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -29,7 +29,8 @@ CORE_LABELS = { } import os -import hashlib +import binascii +import struct import shutil from workspace_tools.patch import patch from paths import TOOLS_BOOTLOADERS @@ -740,9 +741,10 @@ class MTS_DRAGONFLY_F411RE(Target): data = part.read() outbin.write(data) part.close() + outbin.seek(0, 0) data = outbin.read() - md5 = hashlib.md5(data) - outbin.write(md5.digest()) + crc = struct.pack(' Date: Fri, 6 Feb 2015 15:15:30 -0600 Subject: [PATCH 046/143] [mbed][MTS_DRAGONFLY_F411RE] update to latest bootloader with full fw upgrade support including CRC32 checksum --- .../MTS_DRAGONFLY_F411RE/bootloader.bin | Bin 30352 -> 48656 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git 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ztz)*0w%8rRY)VLo`5kZ6r@`Vzydy&7^L^!b7s=mWia#U|@BhW9pL+1_^$K{~g7=6e zZ|`qu3V1KvL+y9vz2kP@!@<<~xynE1@j2q;47f&Ux>KR5@Ih6Tem1*1;$>wh9IG@Z zc(goO{SP<`!Irp)AkXX=Ef)d4J#3UmL)%TR959c%6jsW6IyChYfbwYg$W|S^t+G<% zNK0C85ron4s8Y6f&y+Rw5$|(k&MT$ZL^i)N8a&_qN)zV{k@nw|5Zl3xcoDgIP={xc z)I(+XAEfe7{@{TWaB(5q{wxiU=MHV>G$E3F_-nk7_zz#i>Ey##U&ixE{gL7L4YKt} zY1uL>5Zn#7?$TRJ^ar39mo?SD0A^FWo4LNmkMbmvNm#nC-Yk0KIUSG0^P5k5Ewvlk2 z01OaDK~Y~f3W-Yq2578hH^e1y@tX$UX94^!8jUh~)_q9K0GI}_8eloV(*WxL{t08Y z!I%eUzyLGAq1%J5!iQb(fe9G+>j2tU00aI1UvTGlog;aoee(?Y{LM!4NY{|g#;%D1 zK0_R5MkE{ukNyup`)cyNBA<>ZsrzRMZH5rLl0CoVKasMAt)kkmu From 3b896d64813ac8ea055565c4a4a1886ccb9082b1 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Fri, 6 Feb 2015 17:11:37 -0600 Subject: [PATCH 047/143] [mbed][MTS_DRAGONFLY_F411RE] update bootloader to latest from git revision 80ff13fc47f41e758441af83259755580cae7bfb --- .../MTS_DRAGONFLY_F411RE/bootloader.bin | Bin 48656 -> 48784 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git 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2015 15:22:07 -0600 Subject: [PATCH 048/143] [mbed][MTS_MDOT_F411RE] update pin names --- .../TARGET_MTS_MDOT_F411RE/PinNames.h | 109 +++++++++++------- 1 file changed, 70 insertions(+), 39 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h index 6f557726d5..fda0a86b8f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h @@ -122,48 +122,79 @@ typedef enum { PH_1 = 0x71, // Generic signals namings - DOUT = PA_2, - DIN = PA_3, - AD0 = PB_1, - AD1 = PB_0, - AD2 = PA_5, - AD3 = PA_4, - AD4 = PA_7, - AD5 = PC_1, - AD6 = PA_1, - DIO0 = PB_1, - DIO1 = PB_0, - DIO2 = PA_5, - DIO3 = PA_4, - DIO4 = PA_7, - DIO5 = PC_1, - DIO6 = PA_1, - DO8 = PA_6, - DI8 = PA_11, - PWM0 = PA_8, - PWM1 = PC_9, - NCTS = PA_0, - RTS = PA_1, - NDTR = PA_11, - RSSI = PA_8, - SLEEPRQ = PA_11, - ON_SLEEP = PA_12, - ASSOCIATE = PC_1, + XBEE_DOUT = PA_2, + XBEE_DIN = PA_3, + XBEE_AD0 = PB_1, + XBEE_AD1 = PB_0, + XBEE_AD2 = PA_5, + XBEE_AD3 = PA_4, + XBEE_AD4 = PA_7, + XBEE_AD5 = PC_1, + XBEE_AD6 = PA_1, + XBEE_DIO0 = PB_1, + XBEE_DIO1 = PB_0, + XBEE_DIO2 = PA_5, + XBEE_DIO3 = PA_4, + XBEE_DIO4 = PA_7, + XBEE_DIO5 = PC_1, + XBEE_DIO6 = PA_1, + XBEE_DO8 = PA_6, + XBEE_DI8 = PA_11, + XBEE_PWM0 = PA_8, + XBEE_PWM1 = PC_9, + XBEE_CTS = PA_0, + XBEE_RTS = PA_1, + XBEE_DTR = PA_11, + XBEE_RSSI = PA_8, + XBEE_SLEEPRQ = PA_11, + XBEE_ON_SLEEP = PC_13, + XBEE_ASSOCIATE = PC_1, + XBEE_USB_RES = PA_12, - LED1 = PA_2, - LED2 = PA_2, - LED3 = PA_2, - LED4 = PA_2, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_2, - USBRX = PA_3, + // needed for mbed to build tests + LED1 = PA_0, + + // XBEE_DOUT/DIN, RS232 port on UDK board + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + + // DB_TX/RX, USB port on UDK board + DB_TX = PA_9, + DB_RX = PA_10, + USBTX = PA_9, + USBRX = PA_10, + + // Multiplexed with XBEE pins I2C_SCL = PA_8, I2C_SDA = PC_9, - SPI_MOSI = PA_7, - SPI_MISO = PA_6, - SPI_SCK = PA_5, - SPI_CS = PA_4, + SPI1_MOSI = PA_7, + SPI1_MISO = PA_6, + SPI1_SCK = PA_5, + SPI1_CS = PA_4, + + // SPI flash + SPI3_MOSI = PC_12, + SPI3_MISO = PC_11, + SPI3_SCK = PC_10, + SPI3_CS = PC_6, + FLASH_HOLD = PC_7, + FLASH_WP = PC_8, + + // LoRa + LORA_RESET = PC_0, + LORA_RXCTL = PC_2, + LORA_TXCTL = PC_3, + LORA_DIO0 = PB_5, + LORA_DIO1 = PB_6, + LORA_DIO2 = PB_7, + LORA_DIO3 = PB_8, + LORA_DIO4 = PB_9, + LORA_DIO5 = PB_10, + // LoRa/SPI2 + LORA_NSS = PB_12, + LORA_SCK = PB_13, + LORA_MISO = PB_14, + LORA_MOSI = PB_15, // Not connected NC = (int)0xFFFFFFFF From 101141f55fda82fe78d21970de69fdff0f7e5333 Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Thu, 12 Feb 2015 10:36:11 -0600 Subject: [PATCH 049/143] [mbed][MTS_MDOT_F411RE] change STDIO_UART to UART_1 --- .../TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h index 9046d68c2d..e9aef7cb17 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h @@ -46,9 +46,9 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 +#define STDIO_UART_TX PA_9 +#define STDIO_UART_RX PA_10 +#define STDIO_UART UART_1 typedef enum { SPI_1 = (int)SPI1_BASE, From 90f6719b62777c6a72ffe961ad6b1b2d03898338 Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Fri, 13 Feb 2015 13:25:31 -0600 Subject: [PATCH 050/143] [mbed][MTS_MDOT_F411RE] preliminary bootloader+app support --- .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 6 ++-- .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 6 ++-- .../TOOLCHAIN_GCC_ARM/STM32F411XE.ld | 6 ++-- .../TOOLCHAIN_IAR/stm32f411xe.icf | 2 +- workspace_tools/targets.py | 33 ++++++++++++++++++- 5 files changed, 45 insertions(+), 8 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct index c018724bf7..491087ba47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -28,9 +28,11 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) -LR_IROM1 0x08000000 0x80000 { ; load region size_region +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region - ER_IROM1 0x08000000 0x80000 { ; load address = execution address + ER_IROM1 0x08010000 0x70000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct index c018724bf7..491087ba47 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -28,9 +28,11 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) -LR_IROM1 0x08000000 0x80000 { ; load region size_region +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region - ER_IROM1 0x08000000 0x80000 { ; load address = execution address + ER_IROM1 0x08010000 0x70000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld index c028371d60..9a906395ea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld @@ -1,8 +1,10 @@ /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 + /* First 64kB of flash reserved for bootloader */ + /* Other 448kB for application */ + FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K + RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 } /* Linker script to place sections and symbol values. Should be used together diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf index f481cdbf14..d472306bb0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -1,6 +1,6 @@ /* [ROM = 512kb = 0x80000] */ define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08010000; define symbol __region_ROM_end__ = 0x0807FFFF; /* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index d27fc5548c..3a3286a625 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -705,10 +705,41 @@ class MTS_MDOT_F411RE(Target): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] - self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0'] + self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0', 'VECT_TAB_OFFSET=0x00010000'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" + def init_hooks(self, hook, toolchain_name): + if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']: + hook.hook_add_binary("post", self.combine_bins) + + # combine application binary with bootloader + # bootloader + padding to 64kB + application + md5sum (16 bytes) + @staticmethod + def combine_bins(t_self, resources, elf, binf): + loader = os.path.join(TOOLS_BOOTLOADERS, "MTS_MDOT_F411RE", "bootloader.bin") + target = binf + ".tmp" + if not os.path.exists(loader): + print "Can't find bootloader binary: " + loader + return + outbin = open(target, 'w+b') + part = open(loader, 'rb') + data = part.read() + outbin.write(data) + outbin.write('\xFF' * (64*1024 - len(data))) + part.close() + part = open(binf, 'rb') + data = part.read() + outbin.write(data) + part.close() + outbin.seek(0, 0) + data = outbin.read() + crc = struct.pack(' Date: Fri, 13 Feb 2015 13:26:49 -0600 Subject: [PATCH 051/143] [mbed][MTS_MDOT_F411RE] system_stm32f4xx.c: allow override of VECT_TAB_OFFSET --- .../TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c index 71197ae02e..036582380a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c @@ -125,8 +125,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ +#ifndef VECT_TAB_OFFSET #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /******************************************************************************/ /** From 6bd25a13d34b46f9f0a07aa3d1492c21688dc340 Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Fri, 13 Feb 2015 13:27:18 -0600 Subject: [PATCH 052/143] [mbed][MTS_MDOT_F411RE] cmsis_nvic.c: fix NVIC_FLASH_VECTOR_ADDRESS with custom VECT_TAB_OFFSET --- .../TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c index 2da63fc9af..9fb76a72a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c @@ -31,7 +31,7 @@ #include "cmsis_nvic.h" #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash +#define NVIC_FLASH_VECTOR_ADDRESS (FLASH_BASE | VECT_TAB_OFFSET) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; From b1c4a63f235b9f4773bf7d07ed491ffb44a6eb10 Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Fri, 13 Feb 2015 13:28:36 -0600 Subject: [PATCH 053/143] [mbed][MTS_MDOT_F411RE] add debug bootloader.bin --- .../bootloaders/MTS_MDOT_F411RE/bootloader.bin | Bin 0 -> 49184 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100755 workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin diff --git a/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin b/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin new file mode 100755 index 0000000000000000000000000000000000000000..0cc372c13ea9d122a9ab5249fdb52152ff23b5dd GIT binary patch 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zWg6(3m!M}sG+y(Pn%uAnRAP&R02uNF!s9YIcumUDV{*->IGss3o!BYXNqiGT1##&K zC~A;K&Q>?15w!CZEU9;bQ2|#~yU~R$gX*kpSqG9%UPMHzH#fWIPM^Nc;h45=Q_Hl5 z#&wVttZSMkHE*mhoSVqwkCha+t~Ae>SvqU>jW?CevDZ54oNKQK8KS+I5ve6}vKZv3W>QJgnl`|f}8OyhQh!(G-qrVC7Cy6=O=JasSAJ?>#}QWh)w{{Z@6 B*M9&2 literal 0 HcmV?d00001 From 506ead1387fff00abc62a3d2caf4b40ae1c2dd25 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 16 Feb 2015 10:56:42 -0600 Subject: [PATCH 054/143] [mbed][MTS_DRAGONFLY_F411RE] add pin names for radio RTS/CTS and external serial RX/TX/RTS/CTS --- .../TARGET_MTS_DRAGONFLY_F411RE/PinNames.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h index 20a80678e6..5f25f3dd2c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h @@ -151,12 +151,16 @@ typedef enum { LED3 = D3, LED4 = D3, USER_BUTTON = PC_13, - SERIAL_TX = PB_6, - SERIAL_RX = PB_7, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + SERIAL_RTS = PA_1, + SERIAL_CTS = PA_0, + USBTX = PB_6, + USBRX = PB_7, RADIO_TX = PC_7, RADIO_RX = PC_6, + RADIO_RTS = PB_10, + RADIO_CTS = PB_12, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = PC_12, From 6b1bf31865e5f334f17ff4e18a1b635440fc444e Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 16 Feb 2015 12:18:04 -0600 Subject: [PATCH 055/143] [mbed][MTS_DRAGONFLY_F411RE] fix NVIC_FLASH_VECTOR_ADDRESS with custom VECT_TAB_OFFSET, allow for override of VECT_TAB_OFFSET --- .../TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c | 2 +- .../TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c index 2da63fc9af..9fb76a72a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c @@ -31,7 +31,7 @@ #include "cmsis_nvic.h" #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash +#define NVIC_FLASH_VECTOR_ADDRESS (FLASH_BASE | VECT_TAB_OFFSET) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c index 447ba61405..47507ff930 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c @@ -124,8 +124,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ +#ifndef VECT_TAB_OFFSET #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /******************************************************************************/ /** From 2f56029f55123ce163d76ca365d65421fa35bf8f Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 16 Feb 2015 15:05:31 -0600 Subject: [PATCH 056/143] [mbed][MTS_DRAGONFLY_F411RE] correct vector table start address for IAR toolchain --- .../TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf index d472306bb0..1d635eea62 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -1,5 +1,5 @@ /* [ROM = 512kb = 0x80000] */ -define symbol __intvec_start__ = 0x08000000; +define symbol __intvec_start__ = 0x08010000; define symbol __region_ROM_start__ = 0x08010000; define symbol __region_ROM_end__ = 0x0807FFFF; From 67f660337bb734a3e77548dd892e0f4720bc4956 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Tue, 17 Feb 2015 08:20:31 -0600 Subject: [PATCH 057/143] [mbed][MTS_DRAGONFLY_F411RE] override default binary name with constant name in IAR export. necessary for post-build script --- workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl b/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl index 2f6173a5ff..757a964198 100644 --- a/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl +++ b/workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl @@ -593,11 +593,11 @@

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ziXvWOag^JCgvkNy6Expo2shbxI~+!gi5NCE;hJXGg^g!8oZI4BSDnpacMCbT=^gBC zA=5UG!M#2pJ2n@yr@w4|5f^;mnzm($4)1f5Gq3EAvbaGRK&9I?`)3Qdj31xj_Fod4 z`4R!{#Sk6T!b26S`95oflLh?awve0KpBVBeJ1*fQ#_}g%VZp+|2jK>k6Tmw6)iFI{ zYms3Dz;b}ywdCDbU(qu`1Gkc#9V?kR@9uc?oma|gFg^r+CMGnQF30RehRyjH%O_D2fnMC zYuEm*T#rXN!0P0K$s8V5>l%M(2roW5_rERqbAW7p`}+T*0)9JM|4t2F8z4Q7h`2C7 zEJq;S1YBiD+Hu^&-B^2=?F8Eqm-Oytt(bam_ zTMd0Ua=D>TY~}og%NMT}SFf#H92?~tRKJNMt6d}cXBRA9L|m?dal?LExwK+l#e!vv z7p~5BGQkTfDps@ch033dd5CYDlHdhuAaYg_0s2lDt6Ojqo85>+3Bf!8`qQE z-}WMFPxmBQzgl`H;vRq4qinbYqpYqHalGhTF&4um8Iv$kk{RPs$!poQwhKn zvA+|~A;UND{M{ooMlYBIbbwD_z7614nx--OQTP!48sIX3Pzk3WAQB)JU@`DVLM3(? z_&)`Bt9#9}K<@=~SU!Tu2>*=(;tK!|pZ{;ct|vac`!6r- Date: Fri, 6 Mar 2015 15:17:36 -0600 Subject: [PATCH 066/143] [mbed][MTS_DRAGONFLY_F411RE] update IAR linker file for Dragonfly, larger stack and heap --- .../TOOLCHAIN_IAR/stm32f411xe.icf | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf index 1d635eea62..8dfb4f3275 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -15,9 +15,10 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; /* Stack and Heap */ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __size_cstack__ = 0x4000; -define symbol __size_heap__ = 0x8000; +/* Stack: 32kB - 408B for vector table */ +/* Heap: 80kB */ +define symbol __size_cstack__ = 0x7e68; +define symbol __size_heap__ = 0x14000; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; define block STACKHEAP with fixed order { block HEAP, block CSTACK }; From 2d65b89b78f3905d106a40e21f390ccb1d770dba Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 23 Mar 2015 14:44:40 -0500 Subject: [PATCH 067/143] [mbed][MTS_DRAGONFLY_F411RE] update stack and heap size for Dragonfly in IAR --- .../TOOLCHAIN_IAR/stm32f411xe.icf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf index 8dfb4f3275..8200cc69c4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -15,10 +15,10 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; /* Stack and Heap */ -/* Stack: 32kB - 408B for vector table */ -/* Heap: 80kB */ -define symbol __size_cstack__ = 0x7e68; -define symbol __size_heap__ = 0x14000; +/* Stack: 4kB - 408B for vector table */ +/* Heap: 96kB */ +define symbol __size_cstack__ = 0xe68; +define symbol __size_heap__ = 0x18000; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; define block STACKHEAP with fixed order { block HEAP, block CSTACK }; From 54f4391f79d9cc80b9b1192563760495003dc93e Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Mon, 23 Mar 2015 15:51:33 -0500 Subject: [PATCH 068/143] [mbed][MTS_DRAGONFLY_F411RE][MTS_MDOT_F411RE] update bootloader to revision 53f849fca694138b944a3e4518e63a2881167cff --- .../MTS_DRAGONFLY_F411RE/bootloader.bin | Bin 51344 -> 54992 bytes .../MTS_MDOT_F411RE/bootloader.bin | Bin 48936 -> 54984 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin b/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin index 1f306d5bf858a3cf7d2bf84a27870f807112d70f..cba01d00c1c8244335e8eefa170fdf412df8c60b 100755 GIT binary patch delta 13630 zcmaKS30zdw{`k3f?ksFFDk>tvWd?O%P=`gsEpfyv0~olk+2B%xrjS@sYBS)Hrj~lN zP_$=JJuppHlMErPm#^$KW6xijn!M^c8uq+n=-gTF|9gfdU%&tV@5e9a%=diHcR%~x zvsYq0A*rpU=+7_XdMc3=KT;Ydh`;Z_!F0Sbh#%l#Q368zlP(2+QpAtbOBgwCKZD<< zM-5+a1}XTaKHS#YF$O6Y%#Zc3&8ay)UOqvuN%s+P;TKLym@kHr(`nIp3R9Y*e_ng6rp(&(T8afJ!hSx(s zp=sfALw5LZxnia7O;*M)1KNQRlzHSGeoA>Q2uVZxkGNP%$dMzi_~IijjgjGGyv2>w zTLhhM`SPmeKQC9Wn8Gm*9g^`Az587{-LREZYN_?-)$hI@WnnpqN)adH>)b3i$spsK z-7iN+SR+_DpDQ4>l#>)sHEuSZH%bb|0pDov0T{zRS( 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zDi$t)_t{TQUt0OZq8a70`ju5IK#nG7H%#t2XyKe$GnXvxKfi2NdHAny*}{cO<}Cy%i~5!=t(aF%zB*kJLy5G__6Eo^ z=X#J2&y6N$&aWfs?{p^4b1@|Ooq1%$yPL?z@0v->-*ZUUivnr7I7Jy12^ERZJd`~C zUJu9S_kO_t|R|I=AOha#%EYafK_pM)+4=&-88+TTBi=}2~SibH7b!$x+2 z4J8gB{w&#dDSJ@a6 Date: Fri, 27 Mar 2015 13:10:14 +0900 Subject: [PATCH 069/143] Fix a bug that heap area and stack for interrupt area were duplicated in GCC. --- .../TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s index 68134a3828..95326c0287 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s @@ -173,7 +173,7 @@ goToSleep: @ Setup Stack for each exceptional mode /* ldr r0, =__StackTop */ - ldr r0, =__initial_sp + ldr r0, =(__StackTop - USR_Stack_Size) @ Enter Undefined Instruction Mode and set its Stack Pointer msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) @@ -521,9 +521,9 @@ ret_irq: __user_initial_stackheap: LDR R0, = __HeapBase - LDR R1, =(__StackLimit + USR_Stack_Size) + LDR R1, =(__StackTop) LDR R2, = (__HeapBase + Heap_Size) - LDR R3, = __StackLimit + LDR R3, = (__StackTop - USR_Stack_Size) BX LR .endif From 6cd12e34293fdf1bce366a373fc02ead75d4dbfb Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Tue, 31 Mar 2015 18:39:49 +0200 Subject: [PATCH 070/143] workspace_tools/setup.py: install requirement jinja2 Adding a missing install requirement: Jinja2 --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index adbee4d9cf..eb420b96b4 100644 --- a/setup.py +++ b/setup.py @@ -40,7 +40,7 @@ setup(name='mbed-tools', url='https://github.com/mbedmicro/mbed', packages=find_packages(), license=LICENSE, - install_requires=["PrettyTable>=0.7.2", "PySerial>=2.7", "IntelHex>=1.3", "colorama>=0.3.3"]) + install_requires=["PrettyTable>=0.7.2", "PySerial>=2.7", "IntelHex>=1.3", "colorama>=0.3.3", "Jinja2>=2.7.3"]) # Restore previous private_settings if needed if backup: From e8348cffee9a7f2e55e7543b9b561a0462241ae6 Mon Sep 17 00:00:00 2001 From: Mike Fiore Date: Wed, 1 Apr 2015 15:29:49 -0500 Subject: [PATCH 071/143] [MTS_DRAGONFLY_F411RE][MTS_MDOT_F411RE] add explicit seek() call when combining bootloader and application binaries so Windows builds succeed --- workspace_tools/targets.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 3a3286a625..ef8b759249 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -734,6 +734,7 @@ class MTS_MDOT_F411RE(Target): part.close() outbin.seek(0, 0) data = outbin.read() + outbin.seek(0, 1) crc = struct.pack(' Date: Fri, 3 Apr 2015 13:27:35 +0900 Subject: [PATCH 072/143] Fix a bug that build error will occur in GCC. When export RZ/A1H project of GCC from web compiler, build will be error because some assembler file use // comments. --- .../TOOLCHAIN_GCC_ARM/startup_RZ1AH.s | 16 +++--- .../TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s | 52 +++++++++---------- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s index 95326c0287..f6cf2082bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s @@ -113,14 +113,14 @@ __HeapLimit: .align 2 .globl __isr_vector __isr_vector: - .long 0xe59ff018 // 0x00 - .long 0xe59ff018 // 0x04 - .long 0xe59ff018 // 0x08 - .long 0xe59ff018 // 0x0c - .long 0xe59ff018 // 0x10 - .long 0xe59ff018 // 0x14 - .long 0xe59ff018 // 0x18 - .long 0xe59ff018 // 0x1c + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ .long Reset_Handler /* 0x20 */ .long Undef_Handler /* 0x24 */ diff --git a/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s b/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s index 47963d724a..d37f889191 100644 --- a/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s +++ b/libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s @@ -38,47 +38,47 @@ __v7_all_cache: PUSH {R4-R11} - MRC p15, 1, R6, c0, c0, 1 // Read CLIDR - ANDS R3, R6, #0x07000000 // Extract coherency level - MOV R3, R3, LSR #23 // Total cache levels << 1 - BEQ Finished // If 0, no need to clean + MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ + ANDS R3, R6, #0x07000000 /* Extract coherency level */ + MOV R3, R3, LSR #23 /* Total cache levels << 1 */ + BEQ Finished /* If 0, no need to clean */ - MOV R10, #0 // R10 holds current cache level << 1 -Loop1: ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position - MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level - AND R1, R1, #7 // Isolate those lower 3 bits + MOV R10, #0 /* R10 holds current cache level << 1 */ +Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ + MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ + AND R1, R1, #7 /* Isolate those lower 3 bits */ CMP R1, #2 - BLT Skip // No cache or only instruction cache at this level + BLT Skip /* No cache or only instruction cache at this level */ - MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register - ISB // ISB to sync the change to the CacheSizeID reg - MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register - AND R2, R1, #7 // Extract the line length field - ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) + MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ + ISB /* ISB to sync the change to the CacheSizeID reg */ + MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ + AND R2, R1, #7 /* Extract the line length field */ + ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) - CLZ R5, R4 // R5 is the bit position of the way size increment + ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ + CLZ R5, R4 /* R5 is the bit position of the way size increment */ LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) + ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ -Loop2: MOV R9, R4 // R9 working copy of the max way size (right aligned) +Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ -Loop3: ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 - ORR R11, R11, R7, LSL R2 // Factor in the Set number +Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ + ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ CMP R0, #0 BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way + MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ B cont Dccsw: CMP R0, #1 BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way + MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ B cont -Dccisw: MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way -cont: SUBS R9, R9, #1 // Decrement the Way number +Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ +cont: SUBS R9, R9, #1 /* Decrement the Way number */ BGE Loop3 - SUBS R7, R7, #1 // Decrement the Set number + SUBS R7, R7, #1 /* Decrement the Set number */ BGE Loop2 -Skip: ADD R10, R10, #2 // increment the cache number +Skip: ADD R10, R10, #2 /* increment the cache number */ CMP R3, R10 BGT Loop1 From 2bc9c4299b4121bbe3b603e26c842003a7f10744 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Fri, 3 Apr 2015 18:03:31 +0900 Subject: [PATCH 073/143] [LPC824] Add UART channel dupilication check - Add check_duplication() function to detect UART duplication which is reported https://github.com/mbedmicro/mbed/issues/942 - Confirmed to pass MBED_A9 test case (Serial Echo at 115200) - Add a variable initialize code to prevent GCC warning --- .../hal/TARGET_NXP/TARGET_LPC82X/serial_api.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c index e3dc97e200..a6fa658d04 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c @@ -90,10 +90,39 @@ static uart_irq_handler irq_handler; int stdio_uart_inited = 0; serial_t stdio_uart; +static int check_duplication(serial_t *obj, PinName tx, PinName rx) +{ + if (uart_used == 0) + return 0; + + const SWM_Map *swm; + uint32_t assigned_tx, assigned_rx; + int ch; + for (ch=0; chPINASSIGN[swm->n] & (0xFF << swm->offset); + assigned_tx = assigned_tx >> swm->offset; + // read assigned RX in the UART channel of switch matrix + swm = &SWM_UART_RX[ch]; + assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset); + assigned_rx = assigned_rx >> swm->offset; + if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) { + obj->index = ch; + obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch)); + return 1; + } + } + return 0; +} + void serial_init(serial_t *obj, PinName tx, PinName rx) { int is_stdio_uart = 0; + if (check_duplication(obj, tx, rx) == 1) + return; + int uart_n = get_available_uart(); if (uart_n == -1) { error("No available UART"); @@ -192,7 +221,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b stop_bits -= 1; data_bits -= 7; - int paritysel; + int paritysel = 0; switch (parity) { case ParityNone: paritysel = 0; break; case ParityEven: paritysel = 2; break; From dcd864171de3588952bf08bc7dd03f1b6209bf33 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Fri, 3 Apr 2015 17:17:17 +0200 Subject: [PATCH 074/143] [NUCLEO_F303RE] RTOS singletest adding RTOS tests for NUCLEO_F303RE in singletest.py --- workspace_tools/tests.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 6cd9dc595c..f73c203e7d 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -612,7 +612,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -625,7 +625,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -638,7 +638,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -650,7 +650,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -662,7 +662,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -674,7 +674,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_7", "description": "Timer", @@ -688,7 +688,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -700,7 +700,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC"], + "DISCO_F401VC", "NUCLEO_F303RE"], }, { "id": "RTOS_9", "description": "SD File write-read", From 61ce8ac1321836383ea93f08bcde94a064609751 Mon Sep 17 00:00:00 2001 From: Jurgis Jurksta Date: Sun, 5 Apr 2015 19:01:45 +0300 Subject: [PATCH 075/143] Enable LPC1549 usart when configuring it --- .../hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c index 667c7833e9..237ffa991a 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c @@ -211,8 +211,18 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b default: break; } - - obj->uart->CFG = (data_bits << 2) + + // First disable the the usart as described in documentation and then enable while updating CFG + + // 24.6.1 USART Configuration register + // Remark: If software needs to change configuration values, the following sequence should + // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable + // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) + // Write the new configuration value, with the ENABLE bit set to 1. + obj->uart->CFG &= ~(1 << 0); + + obj->uart->CFG = (1 << 0) // this will enable the usart + | (data_bits << 2) | (paritysel << 4) | (stop_bits << 6); } From 93af661dbf8a7e0bb393acee30ce84d110372198 Mon Sep 17 00:00:00 2001 From: Jurgis Jurksta Date: Sun, 5 Apr 2015 22:28:49 +0300 Subject: [PATCH 076/143] Properly disable LPC1549 usart interrupt --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c index 667c7833e9..462b364874 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c @@ -251,7 +251,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); + obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2)); // disable the interrupt all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; if (all_disabled) NVIC_DisableIRQ(irq_n); From dc10337427cc90356a30face4195354934e75069 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Tue, 7 Apr 2015 00:45:57 +0200 Subject: [PATCH 077/143] [STM32F1xx] hal reorganization Reorganization of all STM32F1 targets in the same way as already done with all other STM32 families. Code of both NUCLEO_F103 and DISCO_F100 was already identical. This commit just moves the code files to the new folder structure. --- .../TARGET_DISCO_F100RB/analogin_api.c | 175 ------- .../TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c | 79 --- .../TARGET_DISCO_F100RB/gpio_irq_api.c | 332 ------------- .../TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c | 457 ------------------ .../TARGET_STM/TARGET_DISCO_F100RB/pinmap.c | 202 -------- .../TARGET_STM/TARGET_DISCO_F100RB/port_api.c | 103 ---- .../TARGET_DISCO_F100RB/pwmout_api.c | 227 --------- .../TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c | 189 -------- .../TARGET_DISCO_F100RB/serial_api.c | 345 ------------- .../TARGET_STM/TARGET_DISCO_F100RB/sleep.c | 62 --- .../TARGET_STM/TARGET_DISCO_F100RB/spi_api.c | 321 ------------ .../TARGET_DISCO_F100RB/us_ticker.c | 113 ----- .../TARGET_NUCLEO_F103RB/PeripheralPins.h | 62 --- .../TARGET_NUCLEO_F103RB/gpio_object.h | 75 --- .../TARGET_NUCLEO_F103RB/mbed_overrides.c | 37 -- .../PeripheralPins.h | 0 .../TARGET_DISCO_F100RB/PeripheralNames.h | 0 .../TARGET_DISCO_F100RB/PeripheralPins.c | 0 .../TARGET_DISCO_F100RB/PinNames.h | 0 .../TARGET_DISCO_F100RB/PortNames.h | 0 .../TARGET_DISCO_F100RB/device.h | 0 .../TARGET_DISCO_F100RB/objects.h | 0 .../TARGET_NUCLEO_F103RB/PeripheralNames.h | 0 .../TARGET_NUCLEO_F103RB/PeripheralPins.c | 0 .../TARGET_NUCLEO_F103RB/PinNames.h | 0 .../TARGET_NUCLEO_F103RB/PortNames.h | 0 .../TARGET_NUCLEO_F103RB/device.h | 0 .../TARGET_NUCLEO_F103RB/objects.h | 0 .../analogin_api.c | 0 .../gpio_api.c | 0 .../gpio_irq_api.c | 0 .../gpio_object.h | 0 .../i2c_api.c | 0 .../mbed_overrides.c | 0 .../pinmap.c | 0 .../port_api.c | 0 .../pwmout_api.c | 0 .../rtc_api.c | 0 .../serial_api.c | 0 .../sleep.c | 0 .../spi_api.c | 0 .../us_ticker.c | 0 42 files changed, 2779 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_DISCO_F100RB => TARGET_STM32F1}/PeripheralPins.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_DISCO_F100RB/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/device.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{ => TARGET_STM32F1}/TARGET_NUCLEO_F103RB/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/analogin_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/gpio_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_DISCO_F100RB => TARGET_STM32F1}/gpio_object.h (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_DISCO_F100RB => TARGET_STM32F1}/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/pinmap.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/port_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/pwmout_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/rtc_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/sleep.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/spi_api.c (100%) rename libraries/mbed/targets/hal/TARGET_STM/{TARGET_NUCLEO_F103RB => TARGET_STM32F1}/us_ticker.c (100%) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c deleted file mode 100644 index 72bfcfcf8e..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/analogin_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -ADC_HandleTypeDef AdcHandle; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - RCC_PeriphCLKInitTypeDef PeriphClkInit; - - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __HAL_RCC_ADC1_CLK_ENABLE(); - - // Configure ADC clock prescaler - // Caution: On STM32F1, ADC clock frequency max is 14 MHz (refer to device datasheet). - // Therefore, ADC clock prescaler must be configured in function - // of ADC clock source frequency to remain below this maximum frequency. - // with 8 MHz external xtal: PCLK2 = 72 MHz --> ADC clock = 72/6 = 12 MHz - // with internal clock : PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.67 MHz - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.NbrOfConversion = 1; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.NbrOfDiscConversion = 0; - AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - HAL_ADC_Init(&AdcHandle); - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig; - - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - - // Configure ADC channel - sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; - - switch (obj->pin) { - case PA_0: - sConfig.Channel = ADC_CHANNEL_0; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PA_5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PA_6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case PA_7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_8; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_9; - break; - case PC_0: - sConfig.Channel = ADC_CHANNEL_10; - break; - case PC_1: - sConfig.Channel = ADC_CHANNEL_11; - break; - case PC_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PC_3: - sConfig.Channel = ADC_CHANNEL_13; - break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PC_5: - sConfig.Channel = ADC_CHANNEL_15; - break; - default: - return 0; - } - - HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - - HAL_ADC_Start(&AdcHandle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&AdcHandle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c deleted file mode 100644 index 48fb0b5d54..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c deleted file mode 100644 index 59de6ff5b7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_irq_api.c +++ /dev/null @@ -1,332 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15) -#define CHANNEL_NUM (7) - -// Max pins for one line (max with EXTI10_15) -#define MAX_PIN_LINE (6) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0 - 0, // pin 0 - // EXTI1 - 0, // pin 1 - // EXTI2 - 0, // pin 2 - // EXTI3 - 0, // pin 3 - // EXTI4 - 0, // pin 4 - // EXTI5_9 - 0, // pin 5 - 1, // pin 6 - 2, // pin 7 - 3, // pin 8 - 4, // pin 9 - // EXTI10_15 - 0, // pin 10 - 1, // pin 11 - 2, // pin 12 - 3, // pin 13 - 4, // pin 14 - 5 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI line 0 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 1); -} - -// EXTI line 1 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 1); -} - -// EXTI line 2 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 1); -} - -// EXTI line 3 -static void gpio_irq3(void) -{ - handle_interrupt_in(3, 1); -} - -// EXTI line 4 -static void gpio_irq4(void) -{ - handle_interrupt_in(4, 1); -} - -// EXTI lines 5 to 9 -static void gpio_irq5(void) -{ - handle_interrupt_in(5, 5); -} - -// EXTI lines 10 to 15 -static void gpio_irq6(void) -{ - handle_interrupt_in(6, 6); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("InterruptIn error: pin not supported.\n"); - return -1; - } - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c deleted file mode 100644 index f7882ec7a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/i2c_api.c +++ /dev/null @@ -1,457 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - static int i2c1_inited = 0; - static int i2c2_inited = 0; - - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Check if I2C peripherals are already configured - if ((obj->i2c == I2C_1) && i2c1_inited) return; - if ((obj->i2c == I2C_2) && i2c2_inited) return; - - // Set I2C clock - if (obj->i2c == I2C_1) { - i2c1_inited = 1; - __I2C1_CLK_ENABLE(); - } - if (obj->i2c == I2C_2) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - } - - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default - - // I2C master by default - obj->slave = 0; -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz != 0) && (hz <= 400000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // I2C configuration - I2cHandle.Init.ClockSpeed = hz; - I2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - HAL_I2C_Init(&I2cHandle); - - if (obj->slave) { - // Enable Address Acknowledge - I2cHandle.Instance->CR1 |= I2C_CR1_ACK; - } -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR1 |= I2C_CR1_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR1 |= I2C_CR1_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Generate start condition - i2c_start(obj); - - // Send address for read - i2c->DR = __HAL_I2C_7BIT_ADD_READ(address); - - // Wait address is acknowledged - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); - - // Read all bytes except last one - for (count = 0; count < (length - 1); count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // If not repeated start, send stop. - // Warning: must be done BEFORE the data is read. - if (stop) { - i2c_stop(obj); - } - - // Read the last byte - value = i2c_byte_read(obj, 1); - data[count] = (char)value; - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Generate start condition - i2c_start(obj); - - // Send address for write - i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address); - - // Wait address is acknowledged - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); - - // Write all bytes - for (count = 0; count < length; count++) { - if (i2c_byte_write(obj, data[count]) != 1) { - i2c_stop(obj); - return -1; - } - } - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - if (last) { - // Don't acknowledge the last byte - i2c->CR1 &= ~I2C_CR1_ACK; - } else { - // Acknowledge the byte - i2c->CR1 |= I2C_CR1_ACK; - } - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->DR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - i2c->DR = (uint8_t)data; - - // Wait until the byte is transmitted - timeout = FLAG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) && - (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) { - if ((timeout--) == 0) { - return 0; - } - } - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - if (enable_slave) { - obj->slave = 1; - /* Enable Address Acknowledge */ - I2cHandle.Instance->CR1 |= I2C_CR1_ACK; - } -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1) { - retValue = ReadAddressed; - } else { - retValue = WriteAddressed; - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } -} - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - uint32_t Timeout; - int size = 0; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - while (length > 0) { - // Wait until RXNE flag is set - // Wait until the byte is received - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Read data - (*data++) = I2cHandle.Instance->DR; - length--; - size++; - - if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { - // Read data - (*data++) = I2cHandle.Instance->DR; - length--; - size++; - } -} - - // Wait until STOP flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Clear STOP flag - __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle); - - // Wait until BUSY flag is reset - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - uint32_t Timeout; - int size = 0; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - while (length > 0) { - // Wait until TXE flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Write data - I2cHandle.Instance->DR = (*data++); - length--; - size++; - - if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { - // Write data to DR - I2cHandle.Instance->DR = (*data++); - length--; - size++; - } - } - - // Wait until AF flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Clear AF flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Wait until BUSY flag is reset - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c deleted file mode 100644 index 78a4cf9ec1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pinmap.c +++ /dev/null @@ -1,202 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -// Warning: the elements order must be the same as the one defined in PinNames.h -static const uint32_t gpio_mode[13] = { - GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT - GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP - GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD - GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP - GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD - GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG - GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING - GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING - GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING - GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING - GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING - GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (input, output, alternate function or analog) + output speed + AF - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Enable AFIO clock - __HAL_RCC_AFIO_CLK_ENABLE(); - - // Configure Alternate Function - // Warning: Must be done before the GPIO is initialized - if (afnum > 0) { - switch (afnum) { - case 1: // Remap SPI1 - __HAL_AFIO_REMAP_SPI1_ENABLE(); - break; - case 2: // Remap I2C1 - __HAL_AFIO_REMAP_I2C1_ENABLE(); - break; - case 3: // Remap USART1 - __HAL_AFIO_REMAP_USART1_ENABLE(); - break; - case 4: // Remap USART2 - __HAL_AFIO_REMAP_USART2_ENABLE(); - break; - case 5: // Partial Remap USART3 - __HAL_AFIO_REMAP_USART3_PARTIAL(); - break; - case 6: // Partial Remap TIM1 - __HAL_AFIO_REMAP_TIM1_PARTIAL(); - break; - case 7: // Partial Remap TIM3 - __HAL_AFIO_REMAP_TIM3_PARTIAL(); - break; - case 8: // Full Remap TIM2 - __HAL_AFIO_REMAP_TIM2_ENABLE(); - break; - case 9: // Full Remap TIM3 - __HAL_AFIO_REMAP_TIM3_ENABLE(); - break; - default: - break; - } - } - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - if ((pin == PA_13) || (pin == PA_14)) { - __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled - } - if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) { - __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled - } -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure open-drain and pull-up/down - switch (mode) { - case PullNone: - break; - case PullUp: - case PullDown: - // Set pull-up / pull-down for Input mode - if (pin_index < 8) { - if ((gpio->CRL & (0x03 << (pin_index * 4))) == 0) { // MODE bits = Input mode - gpio->CRL |= (0x08 << (pin_index * 4)); // Set pull-up / pull-down - } - } else { - if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) == 0) { // MODE bits = Input mode - gpio->CRH |= (0x08 << ((pin_index % 8) * 4)); // Set pull-up / pull-down - } - } - break; - case OpenDrain: - // Set open-drain for Output mode (General Purpose or Alternate Function) - if (pin_index < 8) { - if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode - gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain - } - } else { - if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode - gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain - } - } - break; - default: - break; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c deleted file mode 100644 index ecfded6e59..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c deleted file mode 100644 index 887ceb1b65..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/pwmout_api.c +++ /dev/null @@ -1,227 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static TIM_HandleTypeDef TimHandle; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->pwm == (PWMName)NC) { - error("PWM error: pinout mapping failed."); - } - - // Enable TIM clock - if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); - if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - TIM_OC_InitTypeDef sConfig; - int channel = 0; - int complementary_channel = 0; - - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - sConfig.OCMode = TIM_OCMODE_PWM1; - sConfig.Pulse = obj->pulse; - sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - sConfig.OCFastMode = TIM_OCFAST_DISABLE; - sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; - sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - - switch (obj->pin) { - - // Channels 1 - case PA_6: - case PA_8: - case PA_15: - case PB_4: - case PC_6: - channel = TIM_CHANNEL_1; - break; - - // Channels 1N - case PB_13: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - - // Channels 2 - case PA_1: - case PA_7: - case PA_9: - case PB_3: - case PB_5: - case PC_7: - channel = TIM_CHANNEL_2; - break; - - // Channels 2N - case PB_14: - channel = TIM_CHANNEL_2; - complementary_channel = 1; - break; - - // Channels 3 - case PA_2: - case PA_10: - case PB_0: - case PB_10: - case PC_8: - channel = TIM_CHANNEL_3; - break; - - // Channels 3N - case PB_15: - channel = TIM_CHANNEL_3; - complementary_channel = 1; - break; - - // Channels 4 - case PA_3: - case PA_11: - case PB_1: - case PB_11: - case PC_9: - channel = TIM_CHANNEL_4; - break; - - default: - return; - } - - HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); - - if (complementary_channel) { - HAL_TIMEx_PWMN_Start(&TimHandle, channel); - } else { - HAL_TIM_PWM_Start(&TimHandle, channel); - } -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - float dc = pwmout_read(obj); - - __HAL_TIM_DISABLE(&TimHandle); - - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 us tick - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_PWM_Init(&TimHandle); - - // Set duty cycle again - pwmout_write(obj, dc); - - // Save for future use - obj->period = us; - - __HAL_TIM_ENABLE(&TimHandle); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c deleted file mode 100644 index badd51f70d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/rtc_api.c +++ /dev/null @@ -1,189 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __HAL_RCC_PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c deleted file mode 100644 index 6a34be2ca0..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/serial_api.c +++ /dev/null @@ -1,345 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0,0,0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable UART clock - if (obj->uart == UART_1) { - __HAL_RCC_USART1_CLK_ENABLE(); - obj->index = 0; - } - if (obj->uart == UART_2) { - __HAL_RCC_USART2_CLK_ENABLE(); - obj->index = 1; - } - if (obj->uart == UART_3) { - __HAL_RCC_USART3_CLK_ENABLE(); - obj->index = 2; - } - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); -} - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); - } - } - } - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->DR & (uint8_t)0xFF); - } else { - return (int)(uart->DR & (uint16_t)0x1FF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->DR = (uint8_t)(c & (uint8_t)0xFF); - } else { - uart->DR = (uint16_t)(c & (uint16_t)0x1FF); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); -} - -void serial_break_clear(serial_t *obj) -{ -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c deleted file mode 100644 index 1d7df4131b..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/sleep.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" -#include "hal_tick.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM_MST; - - // Disable HAL tick and us_ticker update interrupts - __HAL_TIM_DISABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE)); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick and us_ticker update interrupts - __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE)); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c deleted file mode 100644 index d3e0a25e56..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/spi_api.c +++ /dev/null @@ -1,321 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_1) { - __SPI1_CLK_ENABLE(); - } - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_1) { - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); -} - - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - if (obj->spi == SPI_1) { - // Values depend of PCLK2: 64 MHz if HSI is used, 72 MHz if HSE is used - if (hz < 500000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 250 kHz - 281 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 500 kHz - 563 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 8 MHz - 9 MHz - } else if ((hz >= 16000000) && (hz < 32000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 16 MHz - 18 MHz - } else { // >= 32000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 32 MHz - 36 MHz - } - } - - if (obj->spi == SPI_2) { - // Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used - if (hz < 250000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz - 141 kHz - } else if ((hz >= 250000) && (hz < 500000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz - 281 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz - 563 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz - 9 MHz - } else { // >= 16000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz - 18 MHz - } - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c deleted file mode 100644 index fe6e44896c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/us_ticker.c +++ /dev/null @@ -1,113 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// Timer selection -#define TIM_MST TIM4 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -volatile uint32_t SlaveCounter = 0; -volatile uint32_t oc_int_part = 0; -volatile uint16_t oc_rem_part = 0; - -void set_compare(uint16_t count) -{ - TimMasterHandle.Instance = TIM_MST; - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - uint32_t counter, counter2; - if (!us_ticker_inited) us_ticker_init(); - // A situation might appear when Master overflows right after Slave is read and before the - // new (overflowed) value of Master is read. Which would make the code below consider the - // previous (incorrect) value of Slave and the new value of Master, which would return a - // value in the past. Avoid this by computing consecutive values of the timer until they - // are properly ordered. - counter = (uint32_t)(SlaveCounter << 16); - counter += TIM_MST->CNT; - while (1) { - counter2 = (uint32_t)(SlaveCounter << 16); - counter2 += TIM_MST->CNT; - if (counter2 > counter) { - break; - } - counter = counter2; - } - return counter2; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - int delta = (int)((uint32_t)timestamp - us_ticker_read()); - uint16_t cval = TIM_MST->CNT; - - if (delta <= 0) { // This event was in the past - us_ticker_irq_handler(); - } else { - oc_int_part = (uint32_t)(delta >> 16); - oc_rem_part = (uint16_t)(delta & 0xFFFF); - if (oc_rem_part <= (0xFFFF - cval)) { - set_compare(cval + oc_rem_part); - oc_rem_part = 0; - } else { - set_compare(0xFFFF); - oc_rem_part = oc_rem_part - (0xFFFF - cval); - } - } -} - -void us_ticker_disable_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { - __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.h deleted file mode 100644 index 383d022e69..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h deleted file mode 100644 index 684d968757..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/port_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/sleep.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/sleep.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/sleep.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/spi_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c From 0228696f48258355dcc830daec454e3ca5e81971 Mon Sep 17 00:00:00 2001 From: PaggyCyntec Date: Tue, 7 Apr 2015 14:39:58 +0800 Subject: [PATCH 078/143] Update main.cpp removed "union" because it causes the result of auto-test not stable (sometimes FAIL, sometimes PASS), after removed, the test result is all PASS. --- libraries/tests/mbed/stdio/main.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libraries/tests/mbed/stdio/main.cpp b/libraries/tests/mbed/stdio/main.cpp index 0b2445de9b..bdfd53c976 100644 --- a/libraries/tests/mbed/stdio/main.cpp +++ b/libraries/tests/mbed/stdio/main.cpp @@ -15,9 +15,8 @@ int main() { DigitalOut led1(LED1); DigitalOut led2(LED2); - union { - int value_int; - }; + int value_int; + notify_start(); // Just to sync with host test supervisor From 1e7fe7474b9df6706bec648c47f5cfe5f7f16b3f Mon Sep 17 00:00:00 2001 From: Masao Hamanaka Date: Tue, 7 Apr 2015 16:46:17 +0900 Subject: [PATCH 079/143] Fix a bug that there is a case that can not be normal communication in I2C. When the following conditions, may not be the normal communication in I2C. 1. A device for I2C address was not found 2. Set "repeated = true". --- .../TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c | 77 ++++++++----------- 1 file changed, 31 insertions(+), 46 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 51e89d832a..e3732e62d2 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -58,7 +58,7 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define SR2_TEND (1 << 6) #define SR2_TDRE (1 << 7) -#define TIMEOUT_1S (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ +#define WAIT_TIMEOUT (4200) /* Loop counter : Time-out is about 1ms. By 4200 loops, measured value is 1009ms. */ static const PinMap PinMap_I2C_SDA[] = { {P1_1 , I2C_0, 1}, @@ -108,7 +108,7 @@ static inline int i2c_wait_RDRF(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_RDRF)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -122,7 +122,7 @@ static int i2c_wait_TDRE(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_TDRE)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -136,7 +136,7 @@ static int i2c_wait_TEND(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_TEND)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -151,7 +151,7 @@ static int i2c_wait_START(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_START)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -165,7 +165,7 @@ static int i2c_wait_STOP(i2c_t *obj) { /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ while (!(i2c_status(obj) & SR2_STOP)) { timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -265,17 +265,11 @@ inline int i2c_stop(i2c_t *obj) { return 0; } -static void i2c_set_err_noslave(i2c_t *obj, int stop) { - if (stop) { - (void)i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } +static void i2c_set_err_noslave(i2c_t *obj) { + (void)i2c_stop(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; } static inline int i2c_do_write(i2c_t *obj, int value) { @@ -287,7 +281,7 @@ static inline int i2c_do_write(i2c_t *obj, int value) { while (!(i2c_status(obj) & SR2_TDRE)) { /* RIICnSR2.TDRE=0 */ timeout ++; - if (timeout >= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } if (i2c_status(obj) & SR2_NACKF) { @@ -432,7 +426,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { if (obj->last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } @@ -440,7 +434,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* wait RDRF */ @@ -448,21 +442,12 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* check ACK/NACK */ if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) { /* Slave sends NACK */ - /* If not repeated start, send stop. */ - if (stop) { - i2c_stop(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } + i2c_stop(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -473,7 +458,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* Recieve the data */ @@ -494,7 +479,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } i2c_set_MR3_NACK(obj); @@ -511,7 +496,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } @@ -552,7 +537,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { if (obj->last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } @@ -560,21 +545,21 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { - i2c_set_err_noslave(obj, stop); + i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } /* Send Write data */ for (cnt=0; cnt= TIMEOUT_1S) { + if (timeout >= WAIT_TIMEOUT) { return -1; } } @@ -730,7 +715,7 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) { /* Wait send end */ status = i2c_wait_TEND(obj); if (status != 0) { - i2c_set_err_noslave(obj, 1); + i2c_set_err_noslave(obj); return 0; } } From 3f7718cec44835c18e9f457e6a28f2b773acda9f Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Thu, 9 Oct 2014 11:54:03 -0500 Subject: [PATCH 080/143] Adding MAXWSNENV platform. --- .../TOOLCHAIN_ARM_STD/MAX32610.sct | 21 + .../TOOLCHAIN_ARM_STD/startup_MAX32610.s | 256 +++++++ .../TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp | 57 ++ .../TOOLCHAIN_GCC_ARM/max32610.ld | 182 +++++ .../TOOLCHAIN_GCC_ARM/startup_max32610.S | 262 +++++++ .../TOOLCHAIN_IAR/MAX32610.icf | 29 + .../TOOLCHAIN_IAR/startup_MAX32610.s | 383 ++++++++++ .../TARGET_Maxim/TARGET_MAX32610/adc_regs.h | 466 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/aes_regs.h | 159 +++++ .../TARGET_Maxim/TARGET_MAX32610/afe_regs.h | 626 +++++++++++++++++ .../TARGET_MAX32610/clkman_regs.h | 493 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/cmsis.h | 40 ++ .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c | 65 ++ .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32610/crc_regs.h | 89 +++ .../TARGET_Maxim/TARGET_MAX32610/dac_regs.h | 180 +++++ .../TARGET_Maxim/TARGET_MAX32610/flc_regs.h | 210 ++++++ .../TARGET_Maxim/TARGET_MAX32610/gpio_regs.h | 477 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h | 192 +++++ .../TARGET_Maxim/TARGET_MAX32610/icc_regs.h | 96 +++ .../TARGET_Maxim/TARGET_MAX32610/ioman_regs.h | 508 ++++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/maa_regs.h | 124 ++++ .../TARGET_Maxim/TARGET_MAX32610/max32610.h | 655 ++++++++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/pmu_regs.h | 111 +++ .../TARGET_Maxim/TARGET_MAX32610/pt_regs.h | 175 +++++ .../TARGET_MAX32610/pwrman_regs.h | 386 +++++++++++ .../TARGET_MAX32610/pwrseq_regs.h | 299 ++++++++ .../TARGET_Maxim/TARGET_MAX32610/rtc_regs.h | 246 +++++++ .../TARGET_Maxim/TARGET_MAX32610/spi_regs.h | 215 ++++++ .../TARGET_MAX32610/system_max32610.c | 147 ++++ .../TARGET_MAX32610/system_max32610.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32610/tmr_regs.h | 146 ++++ .../TARGET_Maxim/TARGET_MAX32610/tpu_regs.h | 108 +++ .../TARGET_Maxim/TARGET_MAX32610/trim_regs.h | 92 +++ .../TARGET_Maxim/TARGET_MAX32610/uart_regs.h | 175 +++++ .../TARGET_Maxim/TARGET_MAX32610/usb_regs.h | 453 ++++++++++++ .../TARGET_Maxim/TARGET_MAX32610/wdt_regs.h | 150 ++++ .../TARGET_MAX32610/PeripheralNames.h | 87 +++ .../TARGET_MAX32610/PeripheralPins.c | 186 +++++ .../TARGET_MAX32610/PeripheralPins.h | 65 ++ .../TARGET_Maxim/TARGET_MAX32610/PinNames.h | 136 ++++ .../TARGET_Maxim/TARGET_MAX32610/PortNames.h | 50 ++ .../TARGET_MAXWSNENV/PeripheralAliases.h | 41 ++ .../TARGET_MAXWSNENV/PinAliases.h | 74 ++ .../TARGET_MAXWSNENV/low_level_init.c | 48 ++ .../TARGET_MAX32610/analogin_api.c | 144 ++++ .../TARGET_MAX32610/analogout_api.c | 213 ++++++ .../hal/TARGET_Maxim/TARGET_MAX32610/device.h | 72 ++ .../TARGET_Maxim/TARGET_MAX32610/gpio_api.c | 94 +++ .../TARGET_MAX32610/gpio_irq_api.c | 168 +++++ .../TARGET_MAX32610/gpio_object.h | 71 ++ .../TARGET_Maxim/TARGET_MAX32610/i2c_api.c | 405 +++++++++++ .../TARGET_Maxim/TARGET_MAX32610/objects.h | 118 ++++ .../hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c | 105 +++ .../TARGET_Maxim/TARGET_MAX32610/port_api.c | 97 +++ .../TARGET_Maxim/TARGET_MAX32610/pwmout_api.c | 234 +++++++ .../TARGET_Maxim/TARGET_MAX32610/rtc_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32610/serial_api.c | 355 ++++++++++ .../hal/TARGET_Maxim/TARGET_MAX32610/sleep.c | 169 +++++ .../TARGET_Maxim/TARGET_MAX32610/spi_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32610/us_ticker.c | 261 +++++++ .../rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 3 + .../rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 7 +- .../tests/mbed/digitalin_digitalout/main.cpp | 4 + libraries/tests/mbed/digitalinout/main.cpp | 4 + libraries/tests/mbed/i2c_TMP102/main.cpp | 3 +- libraries/tests/mbed/i2c_master/main.cpp | 2 +- libraries/tests/mbed/interruptin/main.cpp | 4 + libraries/tests/mbed/portinout/main.cpp | 9 + libraries/tests/mbed/portout/main.cpp | 5 + libraries/tests/mbed/portout_portin/main.cpp | 9 + libraries/tests/mbed/pwm/main.cpp | 9 + libraries/tests/mbed/pwm_led/pwm.cpp | 3 + .../tests/mbed/serial_interrupt_2/main.cpp | 2 + workspace_tools/targets.py | 13 + workspace_tools/tests.py | 19 +- 76 files changed, 12036 insertions(+), 12 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct new file mode 100644 index 0000000000..61369d3054 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct @@ -0,0 +1,21 @@ + +; MAX32610 +; 256KB FLASH (0x40000) @ 0x000000000 +; 2KB RAM (0x8000) @ 0x20000000 + + +; MAX32610: 256KB FLASH (0x40000) + 32KB RAM (0x8000) + +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment + RW_IRAM1 (0x20000000+0x140) (0x8000-0x140) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s new file mode 100644 index 0000000000..933e7871ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s @@ -0,0 +1,256 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp /* Top of Stack */ + DCD Reset_Handler /* Reset Handler */ + DCD NMI_Handler /* NMI Handler */ + DCD HardFault_Handler /* Hard Fault Handler */ + DCD DefaultIRQ_Handler /* MPU Fault Handler */ + DCD DefaultIRQ_Handler /* Bus Fault Handler */ + DCD DefaultIRQ_Handler /* Usage Fault Handler */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* SVCall Handler */ + DCD DebugMon_Handler /* Debug Monitor Handler */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* PendSV Handler */ + DCD SysTick_IRQHandler /* SysTick Handler */ + + /* Maxim 32610 Externals interrupts */ + DCD UART0_IRQHandler /* 16: 1 UART0 */ + DCD UART1_IRQHandler /* 17: 2 UART1 */ + DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ + DCD USB_IRQHandler /* 20: 5 USB */ + DCD PMU_IRQHandler /* 21: 6 DMA */ + DCD AFE_IRQHandler /* 22: 7 AFE */ + DCD MAA_IRQHandler /* 23: 8 MAA */ + DCD AES_IRQHandler /* 24: 9 AES */ + DCD SPI0_IRQHandler /* 25:10 SPI0 */ + DCD SPI1_IRQHandler /* 26:11 SPI1 */ + DCD SPI2_IRQHandler /* 27:12 SPI2 */ + DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ + DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ + DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ + DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ + DCD RSVD0_IRQHandler /* 32:17 RSVD */ + DCD RSVD1_IRQHandler /* 33:18 RSVD */ + DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + DCD ADC_IRQHandler /* 38:23 ADC */ + DCD FLC_IRQHandler /* 39:24 Flash Controller */ + DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ + DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ + DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ + DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ + DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ + DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ + DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Handler + ENDP + +DefaultIRQ_Handler PROC + EXPORT DefaultIRQ_Handler [WEAK] + B DefaultIRQ_Handler + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B DebugMon_Handler + ENDP + +SysTick_IRQHandler PROC + EXPORT SysTick_IRQHandler [WEAK] + B SysTick_IRQHandler + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2CM0_IRQHandler [WEAK] + EXPORT I2CS_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT AFE_IRQHandler [WEAK] + EXPORT MAA_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT RSVD0_IRQHandler [WEAK] + EXPORT RSVD1_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FLC_IRQHandler [WEAK] + EXPORT PWRMAN_IRQHandler [WEAK] + EXPORT CLKMAN_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT RTC2_IRQHandler [WEAK] + EXPORT RTC3_IRQHandler [WEAK] + EXPORT WDT0_IRQHandler [WEAK] + EXPORT WDT0_P_IRQHandler [WEAK] + EXPORT WDT1_IRQHandler [WEAK] + EXPORT WDT1_P_IRQHandler [WEAK] + EXPORT GPIO_P0_IRQHandler [WEAK] + EXPORT GPIO_P1_IRQHandler [WEAK] + EXPORT GPIO_P2_IRQHandler [WEAK] + EXPORT GPIO_P3_IRQHandler [WEAK] + EXPORT GPIO_P4_IRQHandler [WEAK] + EXPORT GPIO_P5_IRQHandler [WEAK] + EXPORT GPIO_P6_IRQHandler [WEAK] + EXPORT GPIO_P7_IRQHandler [WEAK] + EXPORT TMR16_0_IRQHandler [WEAK] + EXPORT TMR16_1_IRQHandler [WEAK] + EXPORT TMR16_2_IRQHandler [WEAK] + EXPORT TMR16_3_IRQHandler [WEAK] + EXPORT I2CM1_IRQHandler [WEAK] + +UART0_IRQHandler +UART1_IRQHandler +I2CM0_IRQHandler +I2CS_IRQHandler +USB_IRQHandler +PMU_IRQHandler +AFE_IRQHandler +MAA_IRQHandler +AES_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +RSVD0_IRQHandler +RSVD1_IRQHandler +DAC0_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +DAC3_IRQHandler +ADC_IRQHandler +FLC_IRQHandler +PWRMAN_IRQHandler +CLKMAN_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +GPIO_P7_IRQHandler +TMR16_0_IRQHandler +TMR16_1_IRQHandler +TMR16_2_IRQHandler +TMR16_3_IRQHandler +I2CM1_IRQHandler + + B . + ENDP + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..90d1391ba3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld new file mode 100644 index 0000000000..be14fd10a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld @@ -0,0 +1,182 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +/****************************************************************************** + * + * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S new file mode 100644 index 0000000000..cda4da904b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + .syntax unified + .arch armv7-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Externals interrupts */ + .long UART0_IRQHandler /* 16: 1 UART0 */ + .long UART1_IRQHandler /* 17: 2 UART1 */ + .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + .long I2CS_IRQHandler /* 19: 4 I2C Slave */ + .long USB_IRQHandler /* 20: 5 USB */ + .long PMU_IRQHandler /* 21: 6 DMA */ + .long AFE_IRQHandler /* 22: 7 AFE */ + .long MAA_IRQHandler /* 23: 8 MAA */ + .long AES_IRQHandler /* 24: 9 AES */ + .long SPI0_IRQHandler /* 25:10 SPI0 */ + .long SPI1_IRQHandler /* 26:11 SPI1 */ + .long SPI2_IRQHandler /* 27:12 SPI2 */ + .long TMR0_IRQHandler /* 28:13 Timer32-0 */ + .long TMR1_IRQHandler /* 29:14 Timer32-1 */ + .long TMR2_IRQHandler /* 30:15 Timer32-1 */ + .long TMR3_IRQHandler /* 31:16 Timer32-2 */ + .long RSVD0_IRQHandler /* 32:17 RSVD */ + .long RSVD1_IRQHandler /* 33:18 RSVD */ + .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + .long ADC_IRQHandler /* 38:23 ADC */ + .long FLC_IRQHandler /* 39:24 Flash Controller */ + .long PWRMAN_IRQHandler /* 40:25 PWRMAN */ + .long CLKMAN_IRQHandler /* 41:26 CLKMAN */ + .long RTC0_IRQHandler /* 42:27 RTC INT0 */ + .long RTC1_IRQHandler /* 43:28 RTC INT1 */ + .long RTC2_IRQHandler /* 44:29 RTC INT2 */ + .long RTC3_IRQHandler /* 45:30 RTC INT3 */ + .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */ + def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */ + def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */ + def_irq_default_handler USB_IRQHandler /* 20: 5 USB */ + def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */ + def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */ + def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */ + def_irq_default_handler AES_IRQHandler /* 24: 9 AES */ + def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */ + def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */ + def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */ + def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */ + def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */ + def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */ + def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */ + def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */ + def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */ + def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */ + def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */ + def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */ + def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */ + def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */ + def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */ + def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */ + def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */ + def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf new file mode 100644 index 0000000000..2b90dc973d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf @@ -0,0 +1,29 @@ +/* [ROM] */ +define symbol __intvec_start__ = 0x0; +define symbol __region_ROM_start__ = 0x0; +define symbol __region_ROM_end__ = 0x0003FFFF; + +/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */ +define symbol __NVIC_start__ = 0x00000000; +define symbol __NVIC_end__ = 0x00000140; /* to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000000; +define symbol __region_RAM_end__ = 0x20007FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x800; +define symbol __size_heap__ = 0x800; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s new file mode 100644 index 0000000000..518756c0b4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s @@ -0,0 +1,383 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) /* Top of Stack */ + DCD Reset_Handler /* Reset Handler */ + DCD NMI_Handler /* NMI Handler */ + DCD HardFault_Handler /* Hard Fault Handler */ + DCD DefaultIRQ_Handler /* MPU Fault Handler */ + DCD DefaultIRQ_Handler /* Bus Fault Handler */ + DCD DefaultIRQ_Handler /* Usage Fault Handler */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* SVCall Handler */ + DCD DebugMon_Handler /* Debug Monitor Handler */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* PendSV Handler */ + DCD SysTick_IRQHandler /* SysTick Handler */ + + /* Maxim 32610 Externals interrupts */ + DCD UART0_IRQHandler /* 16: 1 UART0 */ + DCD UART1_IRQHandler /* 17: 2 UART1 */ + DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ + DCD USB_IRQHandler /* 20: 5 USB */ + DCD PMU_IRQHandler /* 21: 6 DMA */ + DCD AFE_IRQHandler /* 22: 7 AFE */ + DCD MAA_IRQHandler /* 23: 8 MAA */ + DCD AES_IRQHandler /* 24: 9 AES */ + DCD SPI0_IRQHandler /* 25:10 SPI0 */ + DCD SPI1_IRQHandler /* 26:11 SPI1 */ + DCD SPI2_IRQHandler /* 27:12 SPI2 */ + DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ + DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ + DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ + DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ + DCD RSVD0_IRQHandler /* 32:17 RSVD */ + DCD RSVD1_IRQHandler /* 33:18 RSVD */ + DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + DCD ADC_IRQHandler /* 38:23 ADC */ + DCD FLC_IRQHandler /* 39:24 Flash Controller */ + DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ + DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ + DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ + DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ + DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ + DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ + DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK DefaultIRQ_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DefaultIRQ_Handler + B DefaultIRQ_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK SysTick_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_IRQHandler + B SysTick_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK I2CM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM0_IRQHandler + B I2CM0_IRQHandler + + PUBWEAK I2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CS_IRQHandler + B I2CS_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PMU_IRQHandler + B PMU_IRQHandler + + PUBWEAK AFE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AFE_IRQHandler + B AFE_IRQHandler + + PUBWEAK MAA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MAA_IRQHandler + B MAA_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK RSVD0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD0_IRQHandler + B RSVD0_IRQHandler + + PUBWEAK RSVD1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD1_IRQHandler + B RSVD1_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FLC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK PWRMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWRMAN_IRQHandler + B PWRMAN_IRQHandler + + PUBWEAK CLKMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLKMAN_IRQHandler + B CLKMAN_IRQHandler + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B RTC0_IRQHandler + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B RTC1_IRQHandler + + PUBWEAK RTC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC2_IRQHandler + B RTC2_IRQHandler + + PUBWEAK RTC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC3_IRQHandler + B RTC3_IRQHandler + + PUBWEAK WDT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK WDT0_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_P_IRQHandler + B WDT0_P_IRQHandler + + PUBWEAK WDT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_IRQHandler + B WDT1_IRQHandler + + PUBWEAK WDT1_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_P_IRQHandler + B WDT1_P_IRQHandler + + PUBWEAK GPIO_P0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P0_IRQHandler + B GPIO_P0_IRQHandler + + PUBWEAK GPIO_P1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P1_IRQHandler + B GPIO_P1_IRQHandler + + PUBWEAK GPIO_P2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P2_IRQHandler + B GPIO_P2_IRQHandler + + PUBWEAK GPIO_P3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P3_IRQHandler + B GPIO_P3_IRQHandler + + PUBWEAK GPIO_P4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P4_IRQHandler + B GPIO_P4_IRQHandler + + PUBWEAK GPIO_P5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P5_IRQHandler + B GPIO_P5_IRQHandler + + PUBWEAK GPIO_P6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P6_IRQHandler + B GPIO_P6_IRQHandler + + PUBWEAK GPIO_P7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P7_IRQHandler + B GPIO_P7_IRQHandler + + PUBWEAK TMR16_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_0_IRQHandler + B TMR16_0_IRQHandler + + PUBWEAK TMR16_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_1_IRQHandler + B TMR16_1_IRQHandler + + PUBWEAK TMR16_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_2_IRQHandler + B TMR16_2_IRQHandler + + PUBWEAK TMR16_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_3_IRQHandler + B TMR16_3_IRQHandler + + PUBWEAK I2CM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM1_IRQHandler + B I2CM1_IRQHandler + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h new file mode 100644 index 0000000000..4e4d5299c2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h @@ -0,0 +1,466 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ADC_REGS_H +#define _MXC_ADC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file adc_regs.h + * @addtogroup adc ADC + * @{ + */ + +/** + * @brief Defines ADC Modes. + */ +typedef enum { + /** Single Mode Full Rate */ + MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0, + /** Single Mode Low Power */ + MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1, + /** Continuous Mode Full Rate */ + MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2, + /** Continuous Mode Low Power */ + MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3, + /** Single Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8, + /** Single Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9, + /** Continuous Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10, + /** Continuous Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11 +} mxc_adc_mode_t; + +/** + * @brief Defines ADC Range Control. + */ +typedef enum { + /** Bi-polar Operation (-Vref/2 -> Vref/2) */ + MXC_E_ADC_RANGE_HALF = 0, + /** Bi-polar Operation (-Vref -> Vref) */ + MXC_E_ADC_RANGE_FULL +} mxc_adc_range_t; + +/** + * @brief Defines ADC Bipolar operation. + */ +typedef enum { + /** Uni-polar operation (0 -> Vref) */ + MXC_E_ADC_BI_POL_UNIPOLAR = 0, + /** Bi-polar operation see ADC Range Control */ + MXC_E_ADC_BI_POL_BIPOLAR +} mxc_adc_bi_pol_t; + +/** + * @brief Defines Decimation Filter Modes. + */ +typedef enum { + /** Decimation Filter ByPassed */ + MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0, + /** Output Average Only*/ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT, + /** Output Average and Raw Data (Test Mode Only) */ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW +} mxc_adc_avg_mode_t; + +/** + * @brief Defines ADC StartMode Modes. + */ +typedef enum { + /** StarMode via Software */ + MXC_E_ADC_STRT_MODE_SOFTWARE = 0, + /** StarMode via PulseTrain */ + MXC_E_ADC_STRT_MODE_PULSETRAIN +} mxc_adc_strt_mode_t; + +/** + * @brief Defines Mux Channel Select for the Positive Input to the ADC. + */ +typedef enum { + /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0, + /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1, + /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2, + /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3, + /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4, + /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5, + /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6, + /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7, + /** Single Mode Input AIN8+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8, + /** Single Mode Input AIN9+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9, + /** Single Mode Input AIN10+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10, + /** Single Mode Input AIN11+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11, + /** Single Mode Input AIN12+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12, + /** Single Mode Input AIN13+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13, + /** Single Mode Input AIN14+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14, + /** Single Mode Input AIN15+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15, + /** Positive Input VSSADC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16, + /** Positive Input TMON_R */ + MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17, + /** Positive Input VDDA/4 */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18, + /** Positive Input PWRMAN_TST */ + MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19, + /** Positive Input Ain0Div */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20, + /** Positive Input OpAmp OUTA */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32, + /** Positive Input OpAmp OUTB */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33, + /** Positive Input OpAmp OUTC */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34, + /** Positive Input OpAmp OUTD */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35, + /** Positive INA+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36, + /** Positive SNO_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37, + /** Positive SCM_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38, + /** Positive TPROBE_sense */ + MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48, + /** Positive VREFDAC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49, + /** Positive VREFADJ */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50, + /** Positive Vdd3xtal */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51 +} mxc_adc_pga_mux_ch_sel_t; + +/** + * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC. + */ +typedef enum { + /** Differential Mode Disabled */ + MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0, + /** Differential Mode Enabled */ + MXC_E_ADC_PGA_MUX_DIFF_ENABLE +} mxc_adc_pga_mux_diff_t; + +/** + * @brief Defines the PGA Gain Options. + */ +typedef enum { + /** PGA Gain = 1 */ + MXC_E_ADC_PGA_GAIN_1 = 0, + /** PGA Gain = 2 */ + MXC_E_ADC_PGA_GAIN_2, + /** PGA Gain = 4 */ + MXC_E_ADC_PGA_GAIN_4, + /** PGA Gain = 8 */ + MXC_E_ADC_PGA_GAIN_8, +} mxc_adc_pga_gain_t; + +/** + * @brief Defines the Switch Control Mode. + */ +typedef enum { + /** Switch Control Mode = Software */ + MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0, + /** Switch Control Mode = Pulse Train */ + MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN +} mxc_adc_spst_sw_ctrl_t; + +/** + * @brief Defines the number of channels to scan when Scan Mode is enabled. + */ +typedef enum { + /** Number of Channels to Scan = 1 */ + MXC_E_ADC_SCAN_CNT_1 = 0, + /** Number of Channels to Scan = 2 */ + MXC_E_ADC_SCAN_CNT_2, + /** Number of Channels to Scan = 3 */ + MXC_E_ADC_SCAN_CNT_3, + /** Number of Channels to Scan = 4 */ + MXC_E_ADC_SCAN_CNT_4, + /** Number of Channels to Scan = 5 */ + MXC_E_ADC_SCAN_CNT_5, + /** Number of Channels to Scan = 6 */ + MXC_E_ADC_SCAN_CNT_6, + /** Number of Channels to Scan = 7 */ + MXC_E_ADC_SCAN_CNT_7, + /** Number of Channels to Scan = 8 */ + MXC_E_ADC_SCAN_CNT_8, +} mxc_adc_scan_cnt_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */ + __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */ + __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */ + __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */ + __IO uint32_t limit; /* 0x0010 ADC Limit Settings */ + __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */ + __IO uint32_t out; /* 0x0018 ADC Output Register */ +} mxc_adc_regs_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */ + __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */ + __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */ + __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */ + __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */ +} mxc_adccfg_regs_t; + +typedef struct { + __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */ +} mxc_adc_fifo_regs_t; + +/* + Register offsets for module ADC, ADCCFG, ADC_FIFO +*/ +#define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL) +#define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL) +#define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL) +#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL) +#define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL) + +#define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL) +#define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL) +#define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL) +#define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL) +#define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL) +#define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module ADC. +*/ +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0 +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS)) +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5 +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6 +#define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS)) +#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7 +#define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8 +#define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_POS 9 +#define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS)) +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10 +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11 +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12 +#define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13 +#define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14 +#define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15 +#define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18 +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19 +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS)) +#define MXC_F_ADC_CTRL0_AVG_MODE_POS 20 +#define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS)) +#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22 +#define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24 +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_MODE_POS 28 +#define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS)) + +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0 +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8 +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13 +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14 +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15 +#define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20 +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24 +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS)) + +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS)) +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS)) + +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4 +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8 +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12 +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS)) + +#define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0 +#define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS)) +#define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16 +#define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS)) + +#define MXC_F_ADC_INTR_FIFO_AF_POS 6 +#define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7 +#define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IF_POS 8 +#define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IF_POS 9 +#define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS)) +#define MXC_F_ADC_INTR_DONE_IF_POS 10 +#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11 +#define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12 +#define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13 +#define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14 +#define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15 +#define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS)) +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16 +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17 +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18 +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19 +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23 +#define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IE_POS 24 +#define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IE_POS 25 +#define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS)) +#define MXC_F_ADC_INTR_DONE_IE_POS 26 +#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27 +#define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28 +#define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29 +#define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30 +#define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31 +#define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS)) + +#define MXC_F_ADC_OUT_DATA_REG_POS 0 +#define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS)) + +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16 +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS)) + +#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0 +#define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8 +#define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16 +#define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24 +#define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS)) + +#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0 +#define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8 +#define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16 +#define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24 +#define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS)) + +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) +#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 +#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) +#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 +#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) + +#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 +#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 +#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 +#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _MXC_ADC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h new file mode 100644 index 0000000000..cf9995be40 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AES_REGS_H_ +#define _MXC_AES_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file aes_regs.h + * @addtogroup aes AES + * @{ + */ + +/** + * @brief Settings for AES_CTRL.CRYPT_MODE + */ +typedef enum { + MXC_E_AES_CTRL_ENCRYPT_MODE = 0, + MXC_E_AES_CTRL_DECRYPT_MODE = 1 +} mxc_aes_ctrl_crypt_mode_t; + +/** + * @brief Settings for AES_CTRL.EXP_KEY_MODE + */ +typedef enum { + MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0, + MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1 +} mxc_aes_ctrl_exp_key_mode_t; + +/** + * @brief Settings for AES_CTRL.KEY_SIZE + */ +typedef enum { + MXC_E_AES_CTRL_KEY_SIZE_128 = 0, + MXC_E_AES_CTRL_KEY_SIZE_192 = 1, + MXC_E_AES_CTRL_KEY_SIZE_256 = 2 +} mxc_aes_ctrl_key_size_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 AES Control and Status */ + __I uint32_t rsv004; /* 0x0004 */ + __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */ +} mxc_aes_regs_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */ + __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */ + __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */ + __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */ +} mxc_aes_mem_regs_t; + +/* + Register offsets for module AES. +*/ +#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) +#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) +#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) +#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) +#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) +#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) +#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) +#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) +#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) +#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) +#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) +#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) +#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) +#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) +#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) + +#define MXC_F_AES_CTRL_START_POS 0 +#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) +#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 +#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 +#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_F_AES_CTRL_INTEN_POS 5 +#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) +#define MXC_F_AES_CTRL_INTFL_POS 6 +#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) + +#define MXC_V_AES_CTRL_ENCRYPT_MODE 0 +#define MXC_V_AES_CTRL_DECRYPT_MODE 1 +#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) + +#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0 +#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1 +#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) + +#define MXC_V_AES_CTRL_KEY_SIZE_128 0 +#define MXC_V_AES_CTRL_KEY_SIZE_192 1 +#define MXC_V_AES_CTRL_KEY_SIZE_256 2 +#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AES_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h new file mode 100644 index 0000000000..31a3f7cb80 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h @@ -0,0 +1,626 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AFE_REGS_H +#define _MXC_AFE_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file afe_regs.h + * @addtogroup afe AFE + * @{ + */ + +/** + * @brief Defines Configure Options for the LED Ports. + */ +typedef enum { + /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0, + /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D, + /** Disable LED Sink Port 0,Disable LED Sink Port 1 */ + MXC_E_AFE_LED_CFG_PORT_DISABLED, +} mxc_afe_led_cfg_port_t; + +/** + * @brief Setup of Wake Up Detector for LPCs. + */ +typedef enum { + /** IDLE */ + MXC_E_AFE_EN_WUD_COMP_IDLE = 0, + /** Activate WUD for falling edges */ + MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2, + /** Activate WUD for rising edges */ + MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3 +} mxc_afe_en_wud_comp_t; + +/** + * @brief LPC InMode. + */ +typedef enum { + /** InMode: both Nch and Pch */ + MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0, + /** InMode: only Nch */ + MXC_E_AFE_IN_MODE_COMP_NCH, + /** InMode: only Pch */ + MXC_E_AFE_IN_MODE_COMP_PCH, +} mxc_afe_in_mode_comp_t; + +/** + * @brief LPC Bias. + */ +typedef enum { + /** BIAS 0.52uA Delay 4.0us */ + MXC_E_AFE_BIAS_MODE_COMP_0 = 0, + /** BIAS 1.4uA Delay 1.7us */ + MXC_E_AFE_BIAS_MODE_COMP_1, + /** BIAS 2.8uA Delay 1.1us */ + MXC_E_AFE_BIAS_MODE_COMP_2, + /** BIAS 5.1uA Delay 0.7us */ + MXC_E_AFE_BIAS_MODE_COMP_3 +} mxc_afe_bias_mode_comp_t; + +/** + * @brief TMON Current Value. + */ +typedef enum { + /** TMON Current 4uA */ + MXC_E_AFE_TMON_CURRENT_VAL_0 = 0, + /** TMON Current 60uA */ + MXC_E_AFE_TMON_CURRENT_VAL_1, + /** TMON Current 64uA */ + MXC_E_AFE_TMON_CURRENT_VAL_2, + /** TMON Current 120uA */ + MXC_E_AFE_TMON_CURRENT_VAL_3 +} mxc_afe_tmon_current_t; + +/** + * @brief REFADC and REFDAC Voltage Select. + */ +typedef enum { + /** Voltage Reference = 1.024 V */ + MXC_E_AFE_REF_VOLT_SEL_1024 = 0, + /** Voltage Reference = 1.5 V */ + MXC_E_AFE_REF_VOLT_SEL_1500, + /** Voltage Reference = 2.048 V */ + MXC_E_AFE_REF_VOLT_SEL_2048, + /** Voltage Reference = 2.5 V */ + MXC_E_AFE_REF_VOLT_SEL_2500 +} mxc_afe_ref_volt_sel_t; + +/** + * @brief Selection for DAC VOltage Reference, REFADC or REFDAC. + */ +typedef enum { + /** DAC Voltage Reference = REFADC */ + MXC_E_AFE_DAC_REF_REFADC = 0, + /** DAC Voltage Reference = REFDAC */ + MXC_E_AFE_DAC_REF_REFDAC +} mxc_afe_dac_ref_t; + +/** + * @brief Selection for LPC Hysteresis. + */ +typedef enum { + /** LPC Hysteresis = 0 mV */ + MXC_E_AFE_HYST_COMP_0 = 0, + /** LPC Hysteresis = 7.5 mV */ + MXC_E_AFE_HYST_COMP_1, + /** LPC Hysteresis = 15 mV */ + MXC_E_AFE_HYST_COMP_2, + /** LPC Hysteresis = 30 mV */ + MXC_E_AFE_HYST_COMP_3 +} mxc_afe_hyst_comp_t; + +/** + * @brief Selection for MUX for SCM_or_sel. + */ +typedef enum { + /** SCM_or = HIZ */ + MXC_E_AFE_SCM_OR_SEL_HIZ = 0, + /** SCM_or = SCM0 */ + MXC_E_AFE_SCM_OR_SEL_SCM0, + /** SCM_or = SCM1 */ + MXC_E_AFE_SCM_OR_SEL_SCM1, + /** SCM_or = SCM2 */ + MXC_E_AFE_SCM_OR_SEL_SCM2, + /** SCM_or = SCM3 */ + MXC_E_AFE_SCM_OR_SEL_SCM3 +} mxc_afe_scm_or_sel_t; + +/** + * @brief Selection for MUX for SNO_or_sel. + */ +typedef enum { + /** SNO_or = HIZ */ + MXC_E_AFE_SNO_OR_SEL_HIZ = 0, + /** SNO_or = SNO0 */ + MXC_E_AFE_SNO_OR_SEL_SNO0, + /** SNO_or = SNO1 */ + MXC_E_AFE_SNO_OR_SEL_SNO1, + /** SNO_or = SNO2 */ + MXC_E_AFE_SNO_OR_SEL_SNO2, + /** SNO_or = SNO3 */ + MXC_E_AFE_SNO_OR_SEL_SNO3 +} mxc_afe_sno_or_sel_t; + +/** + * @brief Selection for MUX DACx_sel. + */ +typedef enum { + /** dacx = DACOP */ + MXC_E_AFE_DACX_SEL_P = 0, + /** dacx = DACON */ + MXC_E_AFE_DACX_SEL_N +} mxc_afe_dacx_sel_t; + +/** + * @brief Selection for state of Switch. + */ +typedef enum { + /** Switch is OPEN */ + MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0, + /** Switch is CLOSED */ + MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE +} mxc_afe_close_spst_t; + +/** + * @brief Switch to Connect Positive Pad to GND. + */ +typedef enum { + /** Positive Pad GND Switch OPEN */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0, + /** Positive Pad GND Switch CLOSED */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED +} mxc_afe_gnd_sel_opamp_t; + +/** + * @brief MUX Selection for OpPsel. + */ +typedef enum { + /** OpPsel = INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0, + /** OpPsel = DAC_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR, + /** OpPsel = SNO_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR, + /** OpPsel = DAC_or also output on INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS +} mxc_afe_p_in_sel_opamp_t; + +/** + * @brief MUX Selection for OpNsel. + */ +typedef enum { + /** OpNsel = INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0, + /** OpNsel = OUTx */ + MXC_E_AFE_N_IN_SEL_OPAMP_OUT, + /** OpNsel = SCM_or */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR, + /**OpNsel = SCM_or also output on INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS, +} mxc_afe_n_in_sel_opamp_t; + +/** + * @brief MUX Selection for DAC_sel. + */ +typedef enum { + /** DAC_or = DAC0 */ + MXC_E_AFE_DAC_SEL_DAC0 = 0, + /** DAC_or = DAC1 */ + MXC_E_AFE_DAC_SEL_DAC1, + /** DAC_or = DAC2P */ + MXC_E_AFE_DAC_SEL_DAC2P, + /** DAC_or = DAC3P */ + MXC_E_AFE_DAC_SEL_DAC3P +} mxc_afe_dac_sel_t; + +/** + * @brief MUX Selection for NPAD_sel. + */ +typedef enum { + /** NPAD_Sel = HIZ */ + MXC_E_AFE_NPAD_SEL_HIZ = 0, + /** NPAD_Sel = LED Observe Port */ + MXC_E_AFE_NPAD_SEL_LED_OBS_PORT, + /** NPAD_Sel = DAC_or */ + MXC_E_AFE_NPAD_SEL_DAC_OR, + /** NPAD_Sel = DAC_or and LED Observe Port */ + MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT +} mxc_afe_npad_sel_t; + +/** + * @brief MUX Selection for CmpPSel. + */ +typedef enum { + /** CmpPSel = INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0, + /** CmpPSel = SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_SCM, + /** CmpPSel = dac1 */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1, + /** CmpPSel = DAC3P */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P, + /** CmpPSel = LED Observe Port */ + MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT, + /** CmpPSel = dac1 also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS, + /** CmpPSel = DAC3P also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS, + /** CmpPSel = dac1 also output on SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM +} mxc_afe_pos_in_sel_comp_t; + +/** + * @brief MUX Selection for CmpNSel. + */ +typedef enum { + /** CmpNSel = INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0, + /** CmpNSel = SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_SNO, + /** CmpNSel = dac0 */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0, + /** CmpNSel = DAC2P */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P, + /** CmpNSel = LED Observation Port */ + MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT, + /** CmpNSel = dac0 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS, + /** CmpNSel = DAC2 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS, + /** CmpNSel = DAC2 also output on SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO +} mxc_afe_neg_in_sel_comp_t; + +/* Offset Register Description + ====== ==================================================== */ +typedef struct { + __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */ + __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */ + __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */ + __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */ + __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */ + __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */ +} mxc_afe_regs_t; + +/* + Register offsets for module AFE. +*/ +#define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL) +#define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL) +#define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL) +#define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL) +#define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL) + +/* + Field positions and masks for module AFE. +*/ +#define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0 +#define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1 +#define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2 +#define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3 +#define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4 +#define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5 +#define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6 +#define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7 +#define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8 +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9 +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10 +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11 +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12 +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13 +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14 +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15 +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16 +#define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17 +#define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18 +#define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19 +#define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20 +#define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21 +#define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22 +#define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23 +#define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24 +#define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25 +#define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26 +#define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27 +#define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28 +#define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29 +#define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30 +#define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31 +#define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS)) + +#define MXC_F_AFE_CTRL0_LED_CFG_POS 0 +#define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS)) + +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS)) +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3 +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4 +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5 +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6 +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8 +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_SEL_POS 10 +#define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11 +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12 +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13 +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14 +#define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15 +#define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16 +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18 +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20 +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS)) +#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23 +#define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS)) +#define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25 +#define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS)) +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30 +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS)) + +#define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0 +#define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2 +#define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4 +#define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6 +#define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8 +#define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9 +#define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10 +#define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11 +#define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12 +#define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13 +#define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14 +#define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15 +#define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16 +#define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17 +#define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18 +#define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19 +#define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS)) +#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20 +#define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23 +#define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26 +#define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27 +#define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS)) + +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20 +#define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21 +#define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22 +#define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23 +#define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS)) + +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16 +#define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18 +#define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20 +#define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22 +#define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24 +#define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26 +#define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28 +#define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30 +#define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS)) + +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP0_POS 24 +#define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP1_POS 25 +#define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP2_POS 26 +#define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP3_POS 27 +#define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AFE_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h new file mode 100644 index 0000000000..28a258b999 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CLKMAN_REGS_H_ +#define _MXC_CLKMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file clkman_regs.h + * @addtogroup clkman CLKMAN + * @{ + */ + +/** + * @brief Defines clock input selections for the phase locked loop. + */ +typedef enum { + /** Input select for high frequency crystal oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0, + /** Input select for 24MHz ring oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO, +} mxc_clkman_pll_input_select_t; + +/** + * @brief Defines clock input frequency for the phase locked loop. + */ +typedef enum { + /** Input frequency of 24MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0, + /** Input frequency of 12MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ, + /** Input frequency of 8MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ, +} mxc_clkman_pll_divisor_select_t; + +/** + * @brief Defines terminal count for PLL stable. + */ +typedef enum { + /** Clock stable after 2^8 = 256 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0, + /** Clock stable after 2^9 = 512 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS, + /** Clock stable after 2^10 = 1024 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS, + /** Clock stable after 2^11 = 2048 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS, + /** Clock stable after 2^12 = 4096 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS, + /** Clock stable after 2^13 = 8192 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS, + /** Clock stable after 2^14 = 16384 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS, + /** Clock stable after 2^15 = 32768 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS, + /** Clock stable after 2^16 = 65536 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS, + /** Clock stable after 2^17 = 131072 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS, + /** Clock stable after 2^18 = 262144 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS, + /** Clock stable after 2^19 = 524288 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS, + /** Clock stable after 2^20 = 1048576 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS, + /** Clock stable after 2^21 = 2097152 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS, + /** Clock stable after 2^22 = 4194304 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS, + /** Clock stable after 2^23 = 8388608 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS +} mxc_clkman_stability_count_t; + +/** + * @brief Defines clock source selections for system clock. + */ +typedef enum { + /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX, + /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 +} mxc_clkman_system_source_select_t; + +/** + * @brief Defines clock source selections for analog to digital converter clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO, +} mxc_clkman_adc_source_select_t; + +/** + * @brief Defines clock source selections for watchdog timer clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO, +} mxc_clkman_wdt_source_select_t; + +/** + * @brief Defines clock scales for various clocks. + */ +typedef enum { + /** Clock disabled */ + MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0, + /** Clock enabled */ + MXC_E_CLKMAN_CLK_SCALE_ENABLED, + /** Clock scale for dividing by 2 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_2, + /** Clock scale for dividing by 4 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_4, + /** Clock scale for dividing by 8 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_8, + /** Clock scale for dividing by 16 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_16, + /** Clock scale for dividing by 32 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_32, + /** Clock scale for dividing by 64 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_64, + /** Clock scale for dividing by 128 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_128, + /** Clock scale for dividing by 256 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_256 +} mxc_clkman_clk_scale_t; + +/** + * @brief Defines Setting of the Clock Gates . + */ +typedef enum { + /** Clock Gater is Off */ + MXC_E_CLKMAN_CLK_GATE_OFF = 0, + /** Clock Gater is Dynamic */ + MXC_E_CLKMAN_CLK_GATE_DYNAMIC, + /** Clock Gater is On */ + MXC_E_CLKMAN_CLK_GATE_ON +} mxc_clkman_clk_gate_t; + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */ + __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */ + __IO uint32_t intfl; /* 0x0008 Interrupt Flags */ + __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */ + __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */ + __I uint32_t rsv0014[4]; /* 0x0014 */ + __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */ + __I uint32_t rsv0028[6]; /* 0x0028 */ + __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */ + __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */ + __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */ + __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */ + __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */ + __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */ + __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */ + __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */ + __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */ + __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */ + __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */ + __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */ + __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */ + __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */ + __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */ + __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */ + __I uint32_t rsv0088[30]; /* 0x0088 */ + __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */ + __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */ + __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */ + __I uint32_t rsv010C[13]; /* 0x010C */ + __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */ + __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */ + __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */ +} mxc_clkman_regs_t; + +/* + Register offsets for module CLKMAN. +*/ +#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) +#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) +#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) +#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) + +/* + Field positions and masks for module CLKMAN. +*/ +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1 +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3 +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4 +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12 +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24 +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) + +#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) + +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CLKMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h new file mode 100644 index 0000000000..8ca978a2f3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max32610.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c new file mode 100644 index 0000000000..3694273047 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis_nvic.h" + +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD) +__attribute__((aligned(256))) +#endif +#if defined(TOOLCHAIN_IAR) +#pragma data_alignment=256 +#endif +static void (*ramVectorTable[MXC_IRQ_COUNT])(void); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR != (uint32_t)ramVectorTable) { + uint32_t *old_vectors = (uint32_t*)SCB->VTOR; + vectors = (uint32_t*)ramVectorTable; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)ramVectorTable; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h new file mode 100644 index 0000000000..d3e5447614 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS MXC_IRQ_COUNT +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif /* MBED_CMSIS_NVIC_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h new file mode 100644 index 0000000000..6acec11048 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h @@ -0,0 +1,89 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CRC_REGS_H_ +#define _MXC_CRC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file crc_regs.h + * @addtogroup crc CRC + * @{ + */ + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */ + __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */ + __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */ +} mxc_crc_regs_t; + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t value16[512]; /* 0x0000 Write Next CRC-16 Data Value / Read CRC-16 Result Value */ + __IO uint32_t value32[512]; /* 0x0800 Write Next CRC-32 Data Value / Read CRC-32 Result Value */ +} mxc_crc_data_regs_t; + +/* + Register offsets for module CRC. +*/ +#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) +#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) +#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) +#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) +#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module CRC. +*/ +#define MXC_F_CRC_RESEED_CRC16_POS 0 +#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) +#define MXC_F_CRC_RESEED_CRC32_POS 1 +#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CRC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h new file mode 100644 index 0000000000..2f0f4bd8c5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h @@ -0,0 +1,180 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_DAC_REGS_H +#define _MXC_DAC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file dac_regs.h + * @addtogroup dac DAC + * @{ + */ + +/** + * @brief Defines the DAC Operational Modes. + */ +typedef enum { + /** DAC OpMode FIFO */ + MXC_E_DAC_OP_MODE_FIFO = 0, + /** DAC OpMode Sample Count */ + MXC_E_DAC_OP_MODE_DACSMPLCNT, + /** DAC OpMode DAC_REG Control */ + MXC_E_DAC_OP_MODE_DAC_REG, + /** DAC OpMode Continuous */ + MXC_E_DAC_OP_MODE_CONTINUOUS +} mxc_dac_op_mode_t; + +/** + * @brief Defines the DAC Interpolation Options. + */ +typedef enum { + /** DAC Interpolation is Disabled */ + MXC_E_DAC_INTERP_MODE_DISABLED = 0, + /** DAC Interpolation 2:1 */ + MXC_E_DAC_INTERP_MODE_2_TO_1, + /** DAC Interpolation 4:1 */ + MXC_E_DAC_INTERP_MODE_4_TO_1, + /** DAC Interpolation 8:1 */ + MXC_E_DAC_INTERP_MODE_8_TO_1 +} mxc_dac_interp_mode_t; + +/** + * @brief Defines the DAC Start Modes. + */ +typedef enum { + /** Start on FIFO Not Empty */ + MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0, + /** Start on ADC generated Start Strobe */ + MXC_E_DAC_START_MODE_ADC_STROBE, + /** Start on DAC generated Start Strobe */ + MXC_E_DAC_START_MODE_DAC_STROBE +} mxc_dac_start_mode_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */ + __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */ + __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */ + __IO uint32_t reg; /* 0x000C DAC Data Register */ + __IO uint32_t trm; /* 0x0010 DAC Trim Register */ +} mxc_dac_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + union { + __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */ + __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */ + }; +} mxc_dac_fifo_t; + +/* + Register offsets for module DAC12. +*/ +#define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL) +#define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL) +#define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module DAC. +*/ +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0 +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS)) +#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6 +#define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8 +#define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS)) +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12 +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS)) +#define MXC_F_DAC_CTRL0_START_MODE_POS 16 +#define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS)) +#define MXC_F_DAC_CTRL0_CPU_START_POS 20 +#define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS)) +#define MXC_F_DAC_CTRL0_OP_MODE_POS 24 +#define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26 +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS)) +#define MXC_F_DAC_CTRL0_POWER_ON_POS 28 +#define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS)) +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29 +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30 +#define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS)) +#define MXC_F_DAC_CTRL0_RESET_POS 31 +#define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS)) + +#define MXC_F_DAC_RATE_RATE_CNT_POS 0 +#define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS)) +#define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16 +#define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS)) + +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS)) +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28 +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS)) +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29 +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _DAC12_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h new file mode 100644 index 0000000000..864c8c9b97 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h @@ -0,0 +1,210 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_FLC_REGS_H +#define _MXC_FLC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file flc_regs.h + * @addtogroup flc FLC + * @{ + */ +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t faddr; /* 0x0000 Flash Operation Address */ + __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */ + __IO uint32_t ctrl; /* 0x0008 Flash Control Register */ + __I uint32_t rsv000C[6]; /* 0x000C */ + __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */ + __I uint32_t rsv0028[2]; /* 0x0028 */ + __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */ + __I uint32_t rsv0034[7]; /* 0x0034 */ + __IO uint32_t perform; /* 0x0050 Flash Performance Settings */ + __I uint32_t rsv0054[11]; /* 0x0054 */ + __IO uint32_t status; /* 0x0080 Security Status Flags */ + __I uint32_t rsv0084; /* 0x0084 */ + __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */ + __I uint32_t rsv008C[4]; /* 0x008C */ + __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */ + __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */ + __I uint32_t rsv0104[15]; /* 0x0104 */ + __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */ + __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */ + __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */ + __I uint32_t rsv014C; /* 0x014C */ + __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */ + __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */ + __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */ + __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */ + __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */ + __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */ + __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */ + __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */ +} mxc_flc_regs_t; + +/* + Register offsets for module FLC. +*/ +#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) +#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) +#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) +#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) +#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) +#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) +#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) +#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) +#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) +#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) +#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) +#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) +#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL) +#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL) +#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL) +#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL) +#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL) +#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL) +#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL) +#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL) + +#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) +#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) + +#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) + +/* + Field positions and masks for module FLC. +*/ +#define MXC_F_FLC_FADDR_FADDR_POS 0 +#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) + +#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0 +#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) + +#define MXC_F_FLC_CTRL_WRITE_POS 0 +#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) +#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 +#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) +#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 +#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) +#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 +#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) +#define MXC_F_FLC_CTRL_PENDING_POS 24 +#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) +#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 +#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) + +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS)) + +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) +#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 +#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) + +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS)) +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS)) +#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 +#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) + +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) +#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31 +#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) + +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) + +#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 +#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) + +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) + +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_FLC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h new file mode 100644 index 0000000000..8a8122d8cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h @@ -0,0 +1,477 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_GPIO_REGS_H_ +#define _MXC_GPIO_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file gpio_regs.h + * @addtogroup gpio GPIO + * @{ + */ + +/* Offset Register Description + ============= ========================================== */ +typedef struct { + __I uint32_t rsv000[16]; /* 0x0000-0x003C */ + + __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */ + __I uint32_t rsv060[8]; /* 0x0060-0x007C */ + + __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */ + __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */ + + __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */ + __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */ + + __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */ + __I uint32_t rsv120[8]; /* 0x0120-0x013C */ + + __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */ + __I uint32_t rsv160[8]; /* 0x0160-0x017C */ + + __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */ + __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */ + + __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */ + __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */ + + __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */ + __I uint32_t rsv220[8]; /* 0x0220-0x023C */ + + __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */ +} mxc_gpio_regs_t; + +/* + Register offsets for module GPIO. +*/ +#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) +#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) +#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) +#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) +#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) +#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) +#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) +#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) +#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) +#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) +#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) +#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) +#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) +#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) +#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) +#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) +#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) +#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) +#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) +#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) +#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) +#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) +#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) +#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) + + +/* + Field positions and masks for module GPIO. +*/ +#define MXC_F_GPIO_FREE_PIN0_POS 0 +#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_F_GPIO_FREE_PIN1_POS 1 +#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_F_GPIO_FREE_PIN2_POS 2 +#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_F_GPIO_FREE_PIN3_POS 3 +#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_F_GPIO_FREE_PIN4_POS 4 +#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_F_GPIO_FREE_PIN5_POS 5 +#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_F_GPIO_FREE_PIN6_POS 6 +#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_F_GPIO_FREE_PIN7_POS 7 +#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 +#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 +#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 +#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 +#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 +#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 +#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 +#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 +#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) + +#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 +#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 +#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 +#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 +#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 +#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 +#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 +#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 +#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) + +#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 +#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) +#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 +#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) +#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 +#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) +#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 +#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) +#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 +#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) +#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 +#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) +#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 +#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) +#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 +#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) + +#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 +#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) +#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 +#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) +#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 +#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) +#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 +#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) +#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 +#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) +#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 +#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) +#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 +#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) +#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 +#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) + +#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) +#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) +#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) +#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) +#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) +#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) +#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) +#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_INTFL_PIN0_POS 0 +#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) +#define MXC_F_GPIO_INTFL_PIN1_POS 1 +#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) +#define MXC_F_GPIO_INTFL_PIN2_POS 2 +#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) +#define MXC_F_GPIO_INTFL_PIN3_POS 3 +#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) +#define MXC_F_GPIO_INTFL_PIN4_POS 4 +#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) +#define MXC_F_GPIO_INTFL_PIN5_POS 5 +#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) +#define MXC_F_GPIO_INTFL_PIN6_POS 6 +#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) +#define MXC_F_GPIO_INTFL_PIN7_POS 7 +#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) + +#define MXC_F_GPIO_INTEN_PIN0_POS 0 +#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) +#define MXC_F_GPIO_INTEN_PIN1_POS 1 +#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) +#define MXC_F_GPIO_INTEN_PIN2_POS 2 +#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) +#define MXC_F_GPIO_INTEN_PIN3_POS 3 +#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) +#define MXC_F_GPIO_INTEN_PIN4_POS 4 +#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) +#define MXC_F_GPIO_INTEN_PIN5_POS 5 +#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) +#define MXC_F_GPIO_INTEN_PIN6_POS 6 +#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) +#define MXC_F_GPIO_INTEN_PIN7_POS 7 +#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) + + +/* + Field values and shifted values for module GPIO. +*/ +#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) + +#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) + +#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) + +#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) + +#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) + +#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) + +#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) + +#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) +#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) + +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_GPIO_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h new file mode 100644 index 0000000000..173d3107a3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h @@ -0,0 +1,192 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_I2CM_REGS_H_ +#define _MXC_I2CM_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file i2cm_regs.h + * @addtogroup i2cm I2CM + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */ + __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */ + __I uint32_t rsv0008; /* 0x0008 */ + __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */ + __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */ + __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */ + __IO uint32_t intfl; /* 0x0018 Interrupt Flags */ + __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */ + __I uint32_t rsv0020[2]; /* 0x0020 */ + __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */ +} mxc_i2cm_regs_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */ + __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */ +} mxc_i2cm_fifo_regs_t; + +/* + Register offsets for module I2CM. +*/ +#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL) +#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) +#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) +#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) +#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) +#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) +#define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL) + +#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module I2CM. +*/ +#define MXC_S_I2CM_TRANS_TAG_START 0x000 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 +#define MXC_S_I2CM_TRANS_TAG_STOP 0x700 +#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 +#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 + +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0 +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8 +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20 +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS)) + +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) + +#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 +#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 +#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) + +#define MXC_F_I2CM_TRANS_TX_START_POS 0 +#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) +#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 +#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) +#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 +#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 +#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) + +#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 +#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) +#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 +#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) +#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6 +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 +#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 +#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) +#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 +#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h new file mode 100644 index 0000000000..c8407a843c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ICC_REGS_H_ +#define _MXC_ICC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file icc_regs.h + * @addtogroup icc ICC + * @{ + */ + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t id; /* 0x0000 Device ID Register */ + __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */ + __I uint32_t rsv0008[62]; /* 0x0008 */ + __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */ + __I uint32_t rsv0104[383]; /* 0x0104 */ + __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */ +} mxc_icc_regs_t; + +/* + Register offsets for module ICC. +*/ +#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) +#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) +#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) +#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) + +/* + Field positions and masks for module ICC. +*/ +#define MXC_F_ICC_ID_RTL_VERSION_POS 0 +#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) +#define MXC_F_ICC_ID_PART_NUM_POS 6 +#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) +#define MXC_F_ICC_ID_CACHE_ID_POS 10 +#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) + +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) + +#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 +#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) +#define MXC_F_ICC_CTRL_STAT_READY_POS 16 +#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_ICC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h new file mode 100644 index 0000000000..930a181595 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h @@ -0,0 +1,508 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_IOMAN_REGS_H_ +#define _MXC_IOMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file ioman_regs.h + * @addtogroup ioman IO MUX Manager + * @{ + */ + +typedef enum { + /** Pin Mapping 'A' */ + MXC_E_IOMAN_MAPPING_A = 0, + /** Pin Mapping 'B' */ + MXC_E_IOMAN_MAPPING_B, + /** Pin Mapping 'C' */ + MXC_E_IOMAN_MAPPING_C, + /** Pin Mapping 'D' */ + MXC_E_IOMAN_MAPPING_D, + /** Pin Mapping 'E' */ + MXC_E_IOMAN_MAPPING_E, + /** Pin Mapping 'F' */ + MXC_E_IOMAN_MAPPING_F, + /** Pin Mapping 'G' */ + MXC_E_IOMAN_MAPPING_G, + /** Pin Mapping 'H' */ + MXC_E_IOMAN_MAPPING_H, +} ioman_mapping_t; + +/* Offset Register Description + ====== ========================================== */ +typedef struct { + __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */ + __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */ + __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */ + __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */ + __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */ + __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */ + __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */ + __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */ + __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */ + __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */ + __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */ + __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */ + __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */ + __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */ + __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */ + __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */ + __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */ + __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */ + __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */ + __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */ + __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */ + __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */ + __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */ + __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */ + __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */ + __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */ + __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */ + __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */ + __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */ + __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */ + __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */ + __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */ + __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */ + __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */ + __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */ + __IO uint32_t padx_control; /* 0x008C PADX Control */ +} mxc_ioman_regs_t; + + +/* + Register offsets for module IOMAN. +*/ +#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) +#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) +#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) +#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) +#define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL) +#define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL) +#define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL) +#define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL) +#define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL) +#define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL) +#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL) +#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL) +#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL) +#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL) +#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL) +#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL) +#define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL) +#define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL) +#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL) +#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL) +#define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL) + + +/* + Field positions and masks for module IOMAN. +*/ +#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_SPI_MAPPING_POS 0 +#define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS)) +#define MXC_F_IOMAN_SPI_CORE_IO_POS 4 +#define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS)) +#define MXC_F_IOMAN_SPI_SS0_IO_POS 8 +#define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS)) +#define MXC_F_IOMAN_SPI_SS1_IO_POS 9 +#define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS)) +#define MXC_F_IOMAN_SPI_SS2_IO_POS 10 +#define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS)) +#define MXC_F_IOMAN_SPI_SS3_IO_POS 11 +#define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS)) +#define MXC_F_IOMAN_SPI_SS4_IO_POS 12 +#define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS)) +#define MXC_F_IOMAN_SPI_SR0_IO_POS 16 +#define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS)) +#define MXC_F_IOMAN_SPI_SR1_IO_POS 17 +#define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS)) +#define MXC_F_IOMAN_SPI_QUAD_IO_POS 20 +#define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS)) +#define MXC_F_IOMAN_SPI_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS)) + +#define MXC_F_IOMAN_UART_MAPPING_POS 0 +#define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS)) +#define MXC_F_IOMAN_UART_CORE_IO_POS 4 +#define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS)) +#define MXC_F_IOMAN_UART_CTS_IO_POS 5 +#define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS)) +#define MXC_F_IOMAN_UART_RTS_IO_POS 6 +#define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS)) + +#define MXC_F_IOMAN_I2CM_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS)) +#define MXC_F_IOMAN_I2CM_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS)) + +#define MXC_F_IOMAN_I2CS_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS)) +#define MXC_F_IOMAN_I2CS_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS)) + +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS)) + +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_IOMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h new file mode 100644 index 0000000000..e8c80c712b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h @@ -0,0 +1,124 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_MAA_REGS_H_ +#define _MXC_MAA_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file maa_regs.h + * @addtogroup maa MAA + * @{ + */ + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */ + __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */ +} mxc_maa_regs_t; + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t seg0[16]; /* 0x0000 [64 bytes] MAA Memory Segment 0 */ + __IO uint32_t seg1[16]; /* 0x0040 [64 bytes] MAA Memory Segment 1 */ + __IO uint32_t seg2[16]; /* 0x0080 [64 bytes] MAA Memory Segment 2 */ + __IO uint32_t seg3[16]; /* 0x00C0 [64 bytes] MAA Memory Segment 3 */ + __IO uint32_t seg4[16]; /* 0x0100 [64 bytes] MAA Memory Segment 4 */ + __IO uint32_t seg5[16]; /* 0x0140 [64 bytes] MAA Memory Segment 5 */ +} mxc_maa_mem_regs_t; + +/* + Register offsets for module MAA. +*/ +#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) +#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) +#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000040UL) +#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000080UL) +#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x000000C0UL) +#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000100UL) +#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000140UL) + +/* + Field positions and masks for module MAA. +*/ +#define MXC_F_MAA_CTRL_START_POS 0 +#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) +#define MXC_F_MAA_CTRL_OPSEL_POS 1 +#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) +#define MXC_F_MAA_CTRL_OCALC_POS 4 +#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) +#define MXC_F_MAA_CTRL_INTEN_POS 5 +#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) +#define MXC_F_MAA_CTRL_IF_DONE_POS 6 +#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) +#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 +#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) +#define MXC_F_MAA_CTRL_OFS_A_POS 8 +#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) +#define MXC_F_MAA_CTRL_OFS_B_POS 10 +#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) +#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 +#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) +#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 +#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) +#define MXC_F_MAA_CTRL_SEG_A_POS 16 +#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) +#define MXC_F_MAA_CTRL_SEG_B_POS 20 +#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) +#define MXC_F_MAA_CTRL_SEG_RES_POS 24 +#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) +#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 +#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) + +#define MXC_F_MAA_MAWS_MODLEN_POS 0 +#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) +#define MXC_F_MAA_MAWS_BYTESWAP_POS 16 +#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_MAA_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h new file mode 100644 index 0000000000..182a9078fe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h @@ -0,0 +1,655 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MAX32610_H_ +#define _MAX32610_H_ + +#include + +typedef enum IRQn_Type { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Externals interrupts */ + UART0_IRQn = 0, /* 16:01 UART0 */ + UART1_IRQn, /* 17: 2 UART1 */ + I2CM0_IRQn, /* 18: 3 I2C Master 0 */ + I2CS_IRQn, /* 19: 4 I2C Slave */ + USB_IRQn, /* 20: 5 USB */ + PMU_IRQn, /* 21: 6 DMA */ + AFE_IRQn, /* 22: 7 AFE */ + MAA_IRQn, /* 23: 8 MAA */ + AES_IRQn, /* 24: 9 AES */ + SPI0_IRQn, /* 25:10 SPI0 */ + SPI1_IRQn, /* 26:11 SPI1 */ + SPI2_IRQn, /* 27:12 SPI2 */ + TMR0_IRQn, /* 28:13 Timer32-0 */ + TMR1_IRQn, /* 29:14 Timer32-1 */ + TMR2_IRQn, /* 30:15 Timer32-1 */ + TMR3_IRQn, /* 31:16 Timer32-2 */ + RSVD0_IRQn, /* 32:17 RSVD */ + RSVD1_IRQn, /* 33:18 RSVD */ + DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */ + DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */ + DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */ + DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */ + ADC_IRQn, /* 38:23 ADC */ + FLC_IRQn, /* 39:24 Flash Controller */ + PWRMAN_IRQn, /* 40:25 PWRMAN */ + CLKMAN_IRQn, /* 41:26 CLKMAN */ + RTC0_IRQn, /* 42:27 RTC INT0 */ + RTC1_IRQn, /* 43:28 RTC INT1 */ + RTC2_IRQn, /* 44:29 RTC INT2 */ + RTC3_IRQn, /* 45:30 RTC INT3 */ + WDT0_IRQn, /* 46:31 WATCHDOG0 */ + WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */ + WDT1_IRQn, /* 48:33 WATCHDOG1 */ + WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */ + GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */ + GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */ + GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */ + GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */ + GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */ + GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */ + GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */ + GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */ + TMR16_0_IRQn, /* 58:43 Timer16-s0 */ + TMR16_1_IRQn, /* 59:44 Timer16-s1 */ + TMR16_2_IRQn, /* 60:45 Timer16-s2 */ + TMR16_3_IRQn, /* 61:46 Timer16-s3 */ + I2CM1_IRQn, /* 62:47 I2C Master 1 */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ + +#include /* Processor and core peripherals */ +#include "system_max32610.h" /* System Header */ + + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_SYS_MEM_BASE 0x20000000UL + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/*******************************************************************************/ +/* General Purpose I/O Ports (GPIO) */ + + +#define MXC_BASE_GPIO ((uint32_t)0x40000000UL) +#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) +#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL) + +#define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn) + + +/*******************************************************************************/ +/* Pulse Train Generation */ + +#define MXC_CFG_PT_INSTANCES (13) + +#define MXC_BASE_PTG ((uint32_t)0x40001000UL) +#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) +#define MXC_BASE_PT ((uint32_t)0x40001008UL) +#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT) +#define MXC_BASE_PT0 ((uint32_t)0x40001008UL) +#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) +#define MXC_BASE_PT1 ((uint32_t)0x40001010UL) +#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) +#define MXC_BASE_PT2 ((uint32_t)0x40001018UL) +#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) +#define MXC_BASE_PT3 ((uint32_t)0x40001020UL) +#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) +#define MXC_BASE_PT4 ((uint32_t)0x40001028UL) +#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) +#define MXC_BASE_PT5 ((uint32_t)0x40001030UL) +#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) +#define MXC_BASE_PT6 ((uint32_t)0x40001038UL) +#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) +#define MXC_BASE_PT7 ((uint32_t)0x40001040UL) +#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) + +/* PT12, PT13, PT14 are not used */ + +/*******************************************************************************/ +/* CRC-16/CRC-32 Engine */ + +#define MXC_BASE_CRC ((uint32_t)0x40010000UL) +#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC) + +#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL) +#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) + +/*******************************************************************************/ +/* Trust Protection Unit (TPU) */ + +#define MXC_BASE_TPU ((uint32_t)0x40011000UL) +#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) + +#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL) +#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) + +/*******************************************************************************/ +/* AES Cryptographic Engine */ + +#define MXC_BASE_AES ((uint32_t)0x40011400UL) +#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) + +#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL) +#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) + + +/*******************************************************************************/ +/* MAA Cryptographic Engine */ + +#define MXC_BASE_MAA ((uint32_t)0x40011800UL) +#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) + +#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL) +#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) + +/*******************************************************************************/ +/* 32-Bit PWM Timer/Counter */ + +#define MXC_CFG_TMR_INSTANCES (4) + +#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL) +#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0) + +#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL) +#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1) + +#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL) +#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2) + +#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL) +#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL) +#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3) + + +#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : 0) + +#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR16_0_IRQn : \ + (i) == 5 ? TMR16_1_IRQn : \ + (i) == 6 ? TMR16_2_IRQn : \ + (i) == 7 ? TMR16_3_IRQn : 0) + +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : 0) + +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : 0) +/*******************************************************************************/ +/* Watchdog Timer */ + +#define MXC_CFG_WDT_INSTANCES (2) + +#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL) +#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) + +#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL) +#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL) +#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) + +#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \ + (i) == 1 ? WDT1_IRQn : 0) + +#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \ + (i) == 1 ? WDT1_P_IRQn : 0) + +#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ + (i) == 1 ? MXC_BASE_WDT1 : 0) + +#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ + (i) == 1 ? MXC_WDT1 : 0) + +/*******************************************************************************/ +/* SPI Interface */ + +#define MXC_CFG_SPI_INSTANCES (3) +#define MXC_CFG_SPI_FIFO_DEPTH (16) + +#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL) +#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) + +#define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL) +#define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO) +#define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL) +#define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO) + +#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL) +#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) + +#define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL) +#define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO) +#define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL) +#define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO) + +#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL) +#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) + +#define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL) +#define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO) +#define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL) +#define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO) + + +#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \ + (i) == 1 ? SPI1_IRQn : \ + (i) == 2 ? SPI2_IRQn : 0) + +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ + (i) == 1 ? MXC_BASE_SPI1 : \ + (i) == 2 ? MXC_BASE_SPI2 : 0) + +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ + (i) == 1 ? MXC_SPI1 : \ + (i) == 2 ? MXC_SPI2 : 0) + +#define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \ + (i) == 1 ? MXC_SPI1_RXFIFO : \ + (i) == 2 ? MXC_SPI2_RXFIFO : 0) + +#define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \ + (i) == 1 ? MXC_SPI1_TXFIFO : \ + (i) == 2 ? MXC_SPI2_TXFIFO : 0) + +#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0) +#define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12) + + +/*******************************************************************************/ +/* UART Interface */ + +#define MXC_CFG_UART_INSTANCES (2) + +#define MXC_BASE_UART0 ((uint32_t)0x40038000UL) +#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) + +#define MXC_BASE_UART1 ((uint32_t)0x40039000UL) +#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) + + +#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : 0) + +#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0) +#define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12) + + +/*******************************************************************************/ +/* I2C Master Interface */ + +#define MXC_CFG_I2CM_INSTANCES (2) + +#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL) +#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL) +#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) +#define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL) +#define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL) + +#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL) +#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL) +#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) +#define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL) +#define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL) + +#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \ + (i) == 1 ? I2CM1_IRQn : 0) + +#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ + (i) == 1 ? MXC_BASE_I2CM1 : 0) + +#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ + (i) == 1 ? MXC_I2CM1 : 0) + +#define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0) + +#define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0) + +#define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0) +#define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13) + + +/*******************************************************************************/ +/* I2C Slave Interface */ + +#define MXC_CFG_I2CS_INSTANCES (1) + +#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL) +#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL) +#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0) + +#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL) +#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0) + + + +/*******************************************************************************/ +/* DACs */ + +#define MXC_CFG_DAC_INSTANCES (4) +#define MXC_CFG_DAC_FIFO_DEPTH (32) + +#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL) +#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0) +#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL) +#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO) +#define MXC_DAC0_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL) +#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1) +#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL) +#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO) +#define MXC_DAC1_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL) +#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2) +#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL) +#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO) +#define MXC_DAC2_WIDTH ((uint8_t)(1)) + +#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL) +#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3) +#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL) +#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO) +#define MXC_DAC3_WIDTH ((uint8_t)(1)) + + +#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \ + (i) == 1 ? DAC1_IRQn : \ + (i) == 2 ? DAC2_IRQn : \ + (i) == 3 ? DAC3_IRQn : 0) + + +#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \ + i == 1 ? MXC_BASE_DAC1 : \ + i == 2 ? MXC_BASE_DAC2 : \ + i == 3 ? MXC_BASE_DAC3 : 0) + +#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \ + i == 1 ? MXC_BASE_DAC1_FIFO : \ + i == 2 ? MXC_BASE_DAC2_FIFO : \ + i == 3 ? MXC_BASE_DAC3_FIFO : 0) + +#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \ + i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \ + i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \ + i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0) + +#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \ + i == 1 ? MXC_DAC1 : \ + i == 2 ? MXC_DAC2 : \ + i == 3 ? MXC_DAC3 : 0) + +#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \ + i == 1 ? MXC_DAC1_WIDTH : \ + i == 2 ? MXC_DAC2_WIDTH : \ + i == 3 ? MXC_DAC3_WIDTH : 0) + + +/*******************************************************************************/ +/* Analog Front End */ + +#define MXC_BASE_AFE ((uint32_t)0x4005401CUL) +#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE) + + + +/*******************************************************************************/ +/* ADC */ + +#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32)) + +#define MXC_BASE_ADC ((uint32_t)0x40054000UL) +#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) + +#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL) +#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG) + +#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL) +#define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO) + + + +/*******************************************************************************/ +/* Peripheral Management Unit (PMU) - formerly DMA Controller */ + +#define MXC_CFG_PMU_CHANNELS (6) + +#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL) +#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) +#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL) +#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) +#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL) +#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) +#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL) +#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) +#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL) +#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) +#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL) +#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) + +#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL) +#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL) +/*******************************************************************************/ + +typedef enum { + PMU_IRQ_DAC0_FIFO_AE, + PMU_IRQ_DAC1_FIFO_AE, + PMU_IRQ_DAC2_FIFO_AE, + PMU_IRQ_DAC3_FIFO_AE, + PMU_IRQ_DAC0_DONE, + PMU_IRQ_DAC1_DONE, + PMU_IRQ_DAC2_DONE, + PMU_IRQ_DAC3_DONE, + PMU_IRQ_ADC_FIFO_AF, + PMU_IRQ_ADC_DONE, + PMU_IRQ_I2C_MST0_DONE, + PMU_IRQ_I2C_MST1_DONE, + PMU_IRQ_SPI0_RSLTS_DONE, + PMU_IRQ_SPI1_RSLTS_DONE, + PMU_IRQ_SPI2_RSLTS_DONE, + PMU_IRQ_MAA_DONE, + PMU_IRQ_SPI0_TX_FIFO_AE, + PMU_IRQ_SPI0_RSLTS_FIFO_AF, + PMU_IRQ_SPI1_TX_FIFO_AE, + PMU_IRQ_SPI1_RSLTS_FIFO_AF, + PMU_IRQ_SPI2_TX_FIFO_AE, + PMU_IRQ_SPI3_RSLTS_FIFO_AF, + PMU_IRQ_I2C_MST0_TRANS_FIFO, + PMU_IRQ_I2C_MST0_RSLT_FIFO, + PMU_IRQ_I2C_MST1_TRANS_FIFO, + PMU_IRQ_I2C_MST2_RSLT_FIFO, + PMU_IRQ_I2C_SLV_TRANS_FIFO, + PMU_IRQ_I2C_SLV_RSLT_FIFO, + PMU_IRQ_UART0_TX_FIFO, + PMU_IRQ_UART0_RX_FIFO, + PMU_IRQ_UART1_TX_FIFO, + PMU_IRQ_UART1_RX_FIFO, + PMU_IRQ_SPI0_EXCP, + PMU_IRQ_SPI1_EXCP, + PMU_IRQ_SPI2_EXCP, + PMU_IRQ_RSVD0, + PMU_IRQ_I2C_MST0_EXCP, + PMU_IRQ_I2C_MST1_EXCP, + PMU_IRQ_I2C_SLV_EXCP, + PMU_IRQ_RSVD1, + PMU_IRQ_GPIO0, + PMU_IRQ_GPIO1, + PMU_IRQ_GPIO2, + PMU_IRQ_GPIO3, + PMU_IRQ_GPIO4, + PMU_IRQ_GPIO5, + PMU_IRQ_GPIO6, + PMU_IRQ_GPIO7, + PMU_IRQ_GPIO8, + PMU_IRQ_AFE_COMP_NMI, + PMU_IRQ_AES_ENGINE, +} pmu_int_mask_t; + +/*******************************************************************************/ +/* USB */ + +#define MXC_BASE_USB ((uint32_t)0x4010C000UL) +#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) + +#define MXC_USB_MAX_PACKET (64) +#define MXC_USB_NUM_EP (8) + + +/*******************************************************************************/ +/* Instruction Cache Controller */ + +#define MXC_BASE_ICC ((uint32_t)0x40080000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) + +/* System Manager */ + +#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL) + +/*******************************************************************************/ +/* Clock Manager */ + +#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL) +#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) + + +/*******************************************************************************/ +/* Power Manager */ + +#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL) +#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) + +/*******************************************************************************/ +/* I/O Manager */ + +#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL) +#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) + + +/*******************************************************************************/ +/* RTC: Timer/Alarms */ + +#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL) +#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) + +#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \ + i == 1 ? RTC1_IRQn : \ + i == 2 ? RTC2_IRQn : \ + i == 3 ? RTC3_IRQn : 0) + +#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL) +#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) +/*******************************************************************************/ +/* RTC: Power Sequencer */ + +#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) + +/*******************************************************************************/ +/* Trim Shadow Registers */ + +#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL) +#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM) + +/*******************************************************************************/ +/* Flash Memory Controller / Security */ + +#define MXC_BASE_FLC ((uint32_t)0x400F0000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) +#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL) +#define MXC_FLC_PAGE_SIZE_SHIFT 11 +#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) +#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT + +/*******************************************************************************/ + +#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) + +/*******************************************************************************/ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0 +#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1 +#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +/*******************************************************************************/ + +#endif /* _MAX32610_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h new file mode 100644 index 0000000000..e36b9b04e6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PMU_REGS_H_ +#define _MXC_PMU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pmu_regs.h + * @addtogroup pmu PMU + * @{ + */ + +/* Offset Register Description + ====== ======================================================== */ +typedef struct { + __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */ + __IO uint32_t cfg; /* 0x0004 Channel Configuration */ + __IO uint32_t loop; /* 0x0008 Channel Loop Counters */ + __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */ + __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */ + __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */ + __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */ + __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */ +} mxc_pmu_regs_t; + +/* + Register offsets for module PMU. +*/ +#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) +#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) +#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) +#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL) +#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL) +#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL) +#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL) +#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL) + +/* + Field positions and masks for module PMU. +*/ +#define MXC_F_PMU_CFG_ENABLE_POS 0 +#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) +#define MXC_F_PMU_CFG_LL_STOPPED_POS 2 +#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) +#define MXC_F_PMU_CFG_MANUAL_POS 3 +#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) +#define MXC_F_PMU_CFG_BUS_ERROR_POS 4 +#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) +#define MXC_F_PMU_CFG_TO_STAT_POS 6 +#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) +#define MXC_F_PMU_CFG_TO_SEL_POS 11 +#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) +#define MXC_F_PMU_CFG_PS_SEL_POS 14 +#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) +#define MXC_F_PMU_CFG_INTERRUPT_POS 16 +#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) +#define MXC_F_PMU_CFG_INT_EN_POS 17 +#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) +#define MXC_F_PMU_CFG_BURST_SIZE_POS 24 +#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) + +#define MXC_F_PMU_LOOP_COUNTER_0_POS 0 +#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) +#define MXC_F_PMU_LOOP_COUNTER_1_POS 16 +#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PMU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h new file mode 100644 index 0000000000..53936e390f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PT_REGS_H_ +#define _MXC_PT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pt_regs.h + * @addtogroup pt PT + * @{ + */ + +typedef struct { + __IO uint32_t ctrl; + __IO uint32_t resync; +} mxc_ptg_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */ + __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ +} mxc_pt_regs_t; + +/* + Register offsets for module PT. +*/ +#define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) +#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) +#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) + + +/* + Field positions and masks for module PT. +*/ +#define MXC_F_PT_CTRL_ENABLE_ALL_POS 1 +#define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS)) + +#define MXC_F_PT_RESYNC_PT0_POS 0 +#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) +#define MXC_F_PT_RESYNC_PT1_POS 1 +#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) +#define MXC_F_PT_RESYNC_PT2_POS 2 +#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) +#define MXC_F_PT_RESYNC_PT3_POS 3 +#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) +#define MXC_F_PT_RESYNC_PT4_POS 4 +#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) +#define MXC_F_PT_RESYNC_PT5_POS 5 +#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) +#define MXC_F_PT_RESYNC_PT6_POS 6 +#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) +#define MXC_F_PT_RESYNC_PT7_POS 7 +#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) + +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) +#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 +#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +/* + Field values and shifted values for module PT. +*/ +#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL)) + +#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PT_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h new file mode 100644 index 0000000000..cc717dd659 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRMAN_REGS_H_ +#define _MXC_PWRMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrman_regs.h + * @addtogroup pwrman PWRMAN + * @{ + */ + +/** + * @brief Defines PAD Modes for Wake Up Detection. + */ +typedef enum { + /** WUD Mode for Selected PAD = Clear/Activate */ + MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, + /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ + MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, + /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ + MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, + /** WUD Mode for Selected PAD = No pad state change */ + MXC_E_PWRMAN_PAD_MODE_NONE +} mxc_pwrman_pad_mode_t; + +/* Offset Register Description + ====== =========================================== */ +typedef struct { + __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ + __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ + __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ + __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ + __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ + __I uint32_t rsv001C[5]; /* 0x001C */ + + __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */ + __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */ + __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */ + __IO uint32_t base_part_num; /* 0x003C Base Part Number */ + __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ + __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ + __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ +} mxc_pwrman_regs_t; + +/* + Register offsets for module PWRMAN. +*/ +#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) +#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) +#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL) +#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) +#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) +#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) +#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) +#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) + +/* + Field positions and masks for module PWRMAN. +*/ +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) + +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS)) + +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28 +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS)) + +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) + +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) + +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h new file mode 100644 index 0000000000..506b11bda1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h @@ -0,0 +1,299 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRSEQ_REGS_H +#define _MXC_PWRSEQ_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrseq_regs.h + * @addtogroup pwrseq PWRSEQ + * @{ + */ + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ + __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ + __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ + __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ + __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */ + __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ + __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ + __I uint32_t rsv001C; /* 0x001C */ + __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ + __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ +} mxc_pwrseq_regs_t; + + +/* + Register offsets for module PWRSEQ. +*/ +#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) +#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) +#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) +#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) +#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) +#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) +#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) +#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) +#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) + + +/* + Field positions and masks for module PWRSEQ. +*/ +#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 +#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19 +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS)) + +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0 +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9 +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14 +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS)) + +#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0 +#define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5 +#define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10 +#define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15 +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20 +#define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25 +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS)) + +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5 +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13 +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15 +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16 +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17 +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS)) + +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2 +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4 +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5 +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6 +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS)) + +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS)) + +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) + +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS)) + +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRSEQ_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h new file mode 100644 index 0000000000..3c947b028f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h @@ -0,0 +1,246 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_RTC_REGS_H +#define _MXC_RTC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file rtc_regs.h + * @addtogroup rtc RTCTMR + * @{ + */ + +/** + * @brief Defines clock divider for 4096Hz input clock. + */ +typedef enum { + /** (4kHz) divide input clock by 2^0 = 1 */ + MXC_E_RTC_PRESCALE_DIV_2_0 = 0, + /** (2kHz) divide input clock by 2^1 = 2 */ + MXC_E_RTC_PRESCALE_DIV_2_1, + /** (1kHz) divide input clock by 2^2 = 4 */ + MXC_E_RTC_PRESCALE_DIV_2_2, + /** (512Hz) divide input clock by 2^3 = 8 */ + MXC_E_RTC_PRESCALE_DIV_2_3, + /** (256Hz) divide input clock by 2^4 = 16 */ + MXC_E_RTC_PRESCALE_DIV_2_4, + /** (128Hz) divide input clock by 2^5 = 32 */ + MXC_E_RTC_PRESCALE_DIV_2_5, + /** (64Hz) divide input clock by 2^6 = 64 */ + MXC_E_RTC_PRESCALE_DIV_2_6, + /** (32Hz) divide input clock by 2^7 = 128 */ + MXC_E_RTC_PRESCALE_DIV_2_7, + /** (16Hz) divide input clock by 2^8 = 256 */ + MXC_E_RTC_PRESCALE_DIV_2_8, + /** (8Hz) divide input clock by 2^9 = 512 */ + MXC_E_RTC_PRESCALE_DIV_2_9, + /** (4Hz) divide input clock by 2^10 = 1024 */ + MXC_E_RTC_PRESCALE_DIV_2_10, + /** (2Hz) divide input clock by 2^11 = 2048 */ + MXC_E_RTC_PRESCALE_DIV_2_11, + /** (1Hz) divide input clock by 2^12 = 4096 */ + MXC_E_RTC_PRESCALE_DIV_2_12, +} mxc_rtc_prescale_t; + +/* Offset Register Description + ====== ========================================= */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */ + __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */ + __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */ + __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */ + __I uint32_t rsv0014; /* 0x0014 */ + __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */ + __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */ + __I uint32_t rsv0020; /* 0x0020 */ + __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */ + __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */ + __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */ +} mxc_rtctmr_regs_t; + +/* + Register offsets for module RTCTMR. +*/ +#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) +#define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL) +#define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL) +#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) +#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) +#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) +#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) +#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) +#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) + +/* + Field positions and masks for module RTCTMR. +*/ +#define MXC_F_RTC_CTRL_ENABLE_POS 0 +#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) +#define MXC_F_RTC_CTRL_CLEAR_POS 1 +#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) +#define MXC_F_RTC_CTRL_PENDING_POS 2 +#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) +#define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16 +#define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20 +#define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21 +#define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) + +#define MXC_F_RTC_FLAGS_COMP0_POS 0 +#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) +#define MXC_F_RTC_FLAGS_COMP1_POS 1 +#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) +#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 +#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) +#define MXC_F_RTC_FLAGS_TRIM_POS 4 +#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) + +#define MXC_F_RTC_INTEN_COMP0_POS 0 +#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) +#define MXC_F_RTC_INTEN_COMP1_POS 1 +#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) +#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) +#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 +#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) +#define MXC_F_RTC_INTEN_TRIM_POS 4 +#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) + +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0 +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS)) + +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0 +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS)) + +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) + +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18 +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS)) + +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) + +#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 +#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 +#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 +#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) + +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0 +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS)) + +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */ + __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */ + __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */ + __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */ +} mxc_rtccfg_regs_t; + +/* + Register offsets for module RTCCFG. +*/ +#define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL) +#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_RTC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h new file mode 100644 index 0000000000..645178ca37 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h @@ -0,0 +1,215 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_SPI_REGS_H +#define _MXC_SPI_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file spi_regs.h + * @addtogroup spi SPI + * @{ + */ + +/* Offset Register Description + ====== ============================================ */ +typedef struct { + __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */ + __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */ + __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */ + __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */ + __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */ + __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */ + __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */ + __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */ +} mxc_spi_regs_t; + +/** + * @brief TX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __O uint8_t txfifo_8; + __O uint16_t txfifo_16; + __O uint32_t txfifo_32; + }; +} mxc_spi_txfifo_regs_t; + +/** + * @brief RX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __I uint8_t rxfifo_8; + __I uint16_t rxfifo_16; + __I uint32_t rxfifo_32; + }; +} mxc_spi_rxfifo_regs_t; + +/* + Register offsets for module SPI. +*/ +#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) +#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) +#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) +#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL) +#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL) + +#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module SPI. +*/ +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0 +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS)) +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3 +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4 +#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6 +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8 +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12 +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16 +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18 +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS)) + +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0 +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS)) +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8 +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS)) + +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0 +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1 +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2 +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3 +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4 +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5 +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6 +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS)) + +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS)) +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1 +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_INTFL_TX_STALLED_POS 0 +#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS)) +#define MXC_F_SPI_INTFL_RX_STALLED_POS 1 +#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS)) +#define MXC_F_SPI_INTFL_TX_READY_POS 2 +#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS)) +#define MXC_F_SPI_INTFL_RX_DONE_POS 3 +#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS)) +#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_INTEN_TX_STALLED_POS 0 +#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS)) +#define MXC_F_SPI_INTEN_RX_STALLED_POS 1 +#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS)) +#define MXC_F_SPI_INTEN_TX_READY_POS 2 +#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS)) +#define MXC_F_SPI_INTEN_RX_DONE_POS 3 +#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS)) +#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_FIFO_DIR_POS 0 +#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS)) +#define MXC_F_SPI_FIFO_UNIT_POS 2 +#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS)) +#define MXC_F_SPI_FIFO_SIZE_POS 4 +#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS)) +#define MXC_F_SPI_FIFO_WIDTH_POS 9 +#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS)) +#define MXC_F_SPI_FIFO_ALT_POS 11 +#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS)) +#define MXC_F_SPI_FIFO_FLOW_POS 12 +#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS)) +#define MXC_F_SPI_FIFO_DASS_POS 13 +#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_SPI_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c new file mode 100644 index 0000000000..36a77b601d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "max32610.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "ioman_regs.h" +#include "trim_regs.h" +#include "flc_regs.h" +#include "pwrseq_regs.h" +#include "dac_regs.h" +#include "icc_regs.h" + +/* Application developer should override where necessary with different external HFX source */ +#ifndef __SYSTEM_HFX +#define __SYSTEM_HFX 24000000 +#endif + +uint32_t SystemCoreClock = 24000000; + +void SystemCoreClockUpdate(void) +{ + switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8: + SystemCoreClock = 3000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO: + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2: + SystemCoreClock = 24000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX: + SystemCoreClock = __SYSTEM_HFX; + break; + } + + uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system; + if (shift) { + SystemCoreClock = SystemCoreClock >> (shift - 1); + } +} + +/* power seq registers */ +static void set_pwr_regs(void) +{ + uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff; + uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff; + dac2trim = dac2trim + MXC_TRIM->trim_reg_36; + dac3trim = dac3trim + MXC_TRIM->trim_reg_37; + MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13; + MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14; + MXC_DAC0->trm = MXC_TRIM->trim_reg_34; + MXC_DAC1->trm = MXC_TRIM->trim_reg_35; + MXC_DAC2->reg = dac2trim; + MXC_DAC3->reg = dac3trim; +} + +void ICC_Enable(void) +{ + /* clock gater must be 'on' not 'dynamic' for cache control */ + uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; + + + /* invalidate, wait, enable */ + MXC_ICC->invdt_all = 0xFFFF; + while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); + MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; + + /* must invalidate a second time for proper use */ + MXC_ICC->invdt_all = 1; + + /* clock gater 'dynamic' safe again */ + temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; +} + +// This function to be implemented by the hal +extern void low_level_init(); + +void SystemInit(void) +{ + set_pwr_regs(); + + // Turn off PADX + MXC_IOMAN->padx_control = 0x00000441; + + // enable instruction cache + ICC_Enable(); + + low_level_init(); + + // Clear IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE); + + // Set WUD Clear + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR); + + // Set IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED); + + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN; + + // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; + + SystemCoreClockUpdate(); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h new file mode 100644 index 0000000000..094e5de6bd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef SYSTEM_MAX32610_H_ +#define SYSTEM_MAX32610_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit (void); + +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_MAX32610_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h new file mode 100644 index 0000000000..1803814ee5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TMR_REGS_H +#define _MXC_TMR_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tmr_regs.h + * @addtogroup tmr TMR + * @{ + */ + +/** + * @brief Defines timer modes for 16 and 32-bit timers + */ +typedef enum { + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_ONE_SHOT = 0, + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_CONTINUOUS, + /** 32-bit timer counter mode */ + MXC_E_TMR_MODE_COUNTER, + /** 32-bit timer pulse width modulation mode */ + MXC_E_TMR_MODE_PWM, + /** 32-bit timer capture mode */ + MXC_E_TMR_MODE_CAPTURE, + /** 32-bit timer compare mode */ + MXC_E_TMR_MODE_COMPARE, + /** 32-bit timer gated mode */ + MXC_E_TMR_MODE_GATED, + /** 32-bit timer measure mode */ + MXC_E_TMR_MODE_MEASURE +} mxc_tmr_mode_t; + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Timer Control Register */ + __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */ + __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */ + __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */ + __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */ + __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */ + __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */ + __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */ + __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */ + __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */ +} mxc_tmr_regs_t; + +/* + Register offsets for module TMR. +*/ +#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) +#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) +#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) +#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) +#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) +#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) +#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) + +/* + Field positions and masks for module TMR. +*/ +#define MXC_F_TMR_CTRL_MODE_POS 0 +#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) +#define MXC_F_TMR_CTRL_TMR2X16_POS 3 +#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) +#define MXC_F_TMR_CTRL_PRESCALE_POS 4 +#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) +#define MXC_F_TMR_CTRL_POLARITY_POS 8 +#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) +#define MXC_F_TMR_CTRL_ENABLE0_POS 12 +#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) +#define MXC_F_TMR_CTRL_ENABLE1_POS 13 +#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) + +#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) + +#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) + +#define MXC_F_TMR_INTFL_TIMER0_POS 0 +#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) +#define MXC_F_TMR_INTFL_TIMER1_POS 1 +#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) + +#define MXC_F_TMR_INTEN_TIMER0_POS 0 +#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) +#define MXC_F_TMR_INTEN_TIMER1_POS 1 +#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TMR_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h new file mode 100644 index 0000000000..1a0c8f49b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TPU_REGS_H_ +#define _MXC_TPU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tpu_regs.h + * @addtogroup tpu TPU + * @{ + */ + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __I uint32_t rsv0000; /* 0x0000 Reserved */ + __I uint32_t rsv0004; /* 0x0004 Reserved - PUF Control (Deprecated) */ + __I uint32_t rsv0008; /* 0x0008 Reserved - PUF Output (Deprecated) */ + __I uint32_t rsv000C[125]; /* 0x000C */ + __IO uint32_t prng_user_entropy; /* 0x0200 PRNG User Entropy Value */ + __IO uint32_t prng_rnd_num; /* 0x0204 PRNG Random Number Output */ +} mxc_tpu_regs_t; + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t status; /* 0x0000 Dynamic Tamper Sensor Status */ + __IO uint32_t ctrl0; /* 0x0004 Dynamic Tamper Sensor Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Dynamic Tamper Sensor Control 1 */ + __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 0 */ +} mxc_tpu_tsr_regs_t; + +/* + Register offsets for module TPU. +*/ +#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000200UL) +#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000204UL) +#define MXC_R_TPU_TSR_OFFS_STATUS ((uint32_t)0x00000000UL) +#define MXC_R_TPU_TSR_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_TPU_TSR_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL) +#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL) +#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL) +#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL) + + +/* + Field positions and masks for module TPU. +*/ +#define MXC_F_TPU_CTRL0_ERR_THR_POS 0 +#define MXC_F_TPU_CTRL0_ERR_THR ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS)) +#define MXC_F_TPU_CTRL0_OUT_FREQ_POS 5 +#define MXC_F_TPU_CTRL0_OUT_FREQ ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS)) +#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS 8 +#define MXC_F_TPU_CTRL0_CLOCK_DIV ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS)) +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS 14 +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS)) +#define MXC_F_TPU_CTRL0_LOCK_POS 15 +#define MXC_F_TPU_CTRL0_LOCK ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TPU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h new file mode 100644 index 0000000000..2c6ecac55c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h @@ -0,0 +1,92 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TRIM_REGS_H +#define _MXC_TRIM_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef struct { + __IO uint32_t trim_reg_00; + __IO uint32_t trim_reg_01; + __IO uint32_t trim_reg_02; + __IO uint32_t trim_reg_03; + __IO uint32_t trim_reg_04; + __IO uint32_t trim_reg_05; + __IO uint32_t trim_reg_06; + __IO uint32_t trim_reg_07; + __IO uint32_t trim_reg_08; + __IO uint32_t trim_reg_09; + __IO uint32_t trim_reg_10; + __IO uint32_t trim_reg_11; + __IO uint32_t trim_reg_12; + __IO uint32_t trim_reg_13; + __IO uint32_t trim_reg_14; + __IO uint32_t trim_reg_15; + __IO uint32_t trim_reg_16; + __IO uint32_t trim_reg_17; + __IO uint32_t trim_reg_18; + __IO uint32_t trim_reg_19; + __IO uint32_t trim_reg_20; + __IO uint32_t trim_reg_21; + __IO uint32_t trim_reg_22; + __IO uint32_t trim_reg_23; + __IO uint32_t trim_reg_24; + __IO uint32_t trim_reg_25; + __IO uint32_t trim_reg_26; + __IO uint32_t trim_reg_27; + __IO uint32_t trim_reg_28; + __IO uint32_t trim_reg_29; + __IO uint32_t trim_reg_30; + __IO uint32_t trim_reg_31; + __IO uint32_t trim_reg_32; + __IO uint32_t trim_reg_33; + __IO uint32_t trim_reg_34; + __IO uint32_t trim_reg_35; + __IO uint32_t trim_reg_36; + __IO uint32_t trim_reg_37; + __IO uint32_t trim_reg_38; + __IO uint32_t trim_reg_39; + __IO uint32_t trim_reg_40; + __IO uint32_t trim_reg_41; +} mxc_ftr_regs_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TRIM_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h new file mode 100644 index 0000000000..49fbe5d967 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_UART_REGS_H_ +#define _MXC_UART_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file uart_regs.h + * @addtogroup uart UART + * @{ + */ + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 UART Control Register */ + __IO uint32_t status; /* 0x0004 UART Status Register */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t intfl; /* 0x000C Interrupt Flags */ + __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */ + __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */ + __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */ + __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */ + __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */ +} mxc_uart_regs_t; + + +/* + Register offsets for module UART. +*/ +#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL) +#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL) +#define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL) +#define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL) +#define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL) +#define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL) +#define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL) + +/* + Field positions and masks for module UART. +*/ +#define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0 +#define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS)) +#define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4 +#define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS)) +#define MXC_F_UART_CTRL_PARITY_MODE_POS 5 +#define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS)) +#define MXC_F_UART_CTRL_PARITY_BIAS_POS 6 +#define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS)) +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8 +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9 +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10 +#define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS)) +#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12 +#define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS)) +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13 +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS)) +#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14 +#define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS)) + +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4 +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5 +#define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6 +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7 +#define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8 +#define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12 +#define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS)) + +#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTEN_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS)) +#define MXC_F_UART_INTEN_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS)) +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTFL_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS)) +#define MXC_F_UART_INTFL_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS)) +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_BAUD_INT_FBAUD_POS 0 +#define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS)) + +#define MXC_F_UART_BAUD_DIV_128_DIV_POS 0 +#define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS)) + +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0 +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS)) + +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0 +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS)) +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1 +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS)) + +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0 +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS)) +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8 +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_UART_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h new file mode 100644 index 0000000000..bea640a78f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h @@ -0,0 +1,453 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_USB_REGS_H_ +#define _MXC_USB_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file usb_regs.h + * @addtogroup usb USB + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t cn; /* 0x0000 USB Control Register */ + __I uint32_t rsv0004[127]; /* 0x0004 */ + __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ + __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ + __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ + __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ + __I uint32_t rsv0210[4]; /* 0x0210 */ + __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ + __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ + __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ + __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ + __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ + __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ + __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ + __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ + __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ + __I uint32_t rsv0244[7]; /* 0x0244 */ + __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ + __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ + __I uint32_t rsv0268[6]; /* 0x0268 */ + __IO uint32_t ep[MXC_USB_NUM_EP]; /* 0x0280 USB Endpoint Control Registers */ +} mxc_usb_regs_t; + + +/* + Register offsets for module USB. +*/ +#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) +#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) +#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) +#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) +#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) +#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) +#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) +#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) +#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) +#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) +#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) +#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) +#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) +#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) +#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) +#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) +#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) +#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) +#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) +#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) +#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) +#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) +#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) +#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) + + +/* + Field positions and masks for module USB. +*/ +#define MXC_F_USB_CN_USB_EN_POS 0 +#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) + +#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 +#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) + +#define MXC_F_USB_DEV_CN_SIGRWU_POS 2 +#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) +#define MXC_F_USB_DEV_CN_CONNECT_POS 3 +#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) +#define MXC_F_USB_DEV_CN_ULPM_POS 4 +#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) +#define MXC_F_USB_DEV_CN_URST_POS 5 +#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) +#define MXC_F_USB_DEV_CN_VBGATE_POS 6 +#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) +#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 +#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) + +#define MXC_F_USB_DEV_INTFL_DPACT_POS 0 +#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) +#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTFL_BACT_POS 2 +#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_POS 3 +#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) +#define MXC_F_USB_DEV_INTFL_SUSP_POS 4 +#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) +#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_POS 6 +#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTFL_SETUP_POS 8 +#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) +#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) +#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 +#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) + +#define MXC_F_USB_DEV_INTEN_DPACT_POS 0 +#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) +#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTEN_BACT_POS 2 +#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_POS 3 +#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) +#define MXC_F_USB_DEV_INTEN_SUSP_POS 4 +#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) +#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_VBUS_POS 6 +#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTEN_SETUP_POS 8 +#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) +#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) +#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) + +#define MXC_F_USB_EP_BASE_EP_BASE_POS 9 +#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) + +#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 +#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) +#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 +#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) + +#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_IN_INT_INBAV0_POS 0 +#define MXC_F_USB_IN_INT_INBAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS)) +#define MXC_F_USB_IN_INT_INBAV1_POS 1 +#define MXC_F_USB_IN_INT_INBAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS)) +#define MXC_F_USB_IN_INT_INBAV2_POS 2 +#define MXC_F_USB_IN_INT_INBAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS)) +#define MXC_F_USB_IN_INT_INBAV3_POS 3 +#define MXC_F_USB_IN_INT_INBAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS)) +#define MXC_F_USB_IN_INT_INBAV4_POS 4 +#define MXC_F_USB_IN_INT_INBAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS)) +#define MXC_F_USB_IN_INT_INBAV5_POS 5 +#define MXC_F_USB_IN_INT_INBAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS)) +#define MXC_F_USB_IN_INT_INBAV6_POS 6 +#define MXC_F_USB_IN_INT_INBAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS)) +#define MXC_F_USB_IN_INT_INBAV7_POS 7 +#define MXC_F_USB_IN_INT_INBAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS)) + +#define MXC_F_USB_OUT_INT_OUTDAV0_POS 0 +#define MXC_F_USB_OUT_INT_OUTDAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV1_POS 1 +#define MXC_F_USB_OUT_INT_OUTDAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV2_POS 2 +#define MXC_F_USB_OUT_INT_OUTDAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV3_POS 3 +#define MXC_F_USB_OUT_INT_OUTDAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV4_POS 4 +#define MXC_F_USB_OUT_INT_OUTDAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV5_POS 5 +#define MXC_F_USB_OUT_INT_OUTDAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV6_POS 6 +#define MXC_F_USB_OUT_INT_OUTDAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV7_POS 7 +#define MXC_F_USB_OUT_INT_OUTDAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS)) + +#define MXC_F_USB_NAK_INT_NAK0_POS 0 +#define MXC_F_USB_NAK_INT_NAK0 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS)) +#define MXC_F_USB_NAK_INT_NAK1_POS 1 +#define MXC_F_USB_NAK_INT_NAK1 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS)) +#define MXC_F_USB_NAK_INT_NAK2_POS 2 +#define MXC_F_USB_NAK_INT_NAK2 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS)) +#define MXC_F_USB_NAK_INT_NAK3_POS 3 +#define MXC_F_USB_NAK_INT_NAK3 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS)) +#define MXC_F_USB_NAK_INT_NAK4_POS 4 +#define MXC_F_USB_NAK_INT_NAK4 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS)) +#define MXC_F_USB_NAK_INT_NAK5_POS 5 +#define MXC_F_USB_NAK_INT_NAK5 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS)) +#define MXC_F_USB_NAK_INT_NAK6_POS 6 +#define MXC_F_USB_NAK_INT_NAK6 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS)) +#define MXC_F_USB_NAK_INT_NAK7_POS 7 +#define MXC_F_USB_NAK_INT_NAK7 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS)) + +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS 0 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS 1 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS 2 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS 3 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS 4 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS 5 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS 6 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS 7 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS)) + +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS 0 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS 1 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS 2 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS 3 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS 4 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS 5 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS 6 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS 7 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS)) + +#define MXC_F_USB_SETUP0_BYTE0_POS 0 +#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) +#define MXC_F_USB_SETUP0_BYTE1_POS 8 +#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) +#define MXC_F_USB_SETUP0_BYTE2_POS 16 +#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) +#define MXC_F_USB_SETUP0_BYTE3_POS 24 +#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) + +#define MXC_F_USB_SETUP1_BYTE4_POS 0 +#define MXC_F_USB_SETUP1_BYTE4 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS)) +#define MXC_F_USB_SETUP1_BYTE5_POS 8 +#define MXC_F_USB_SETUP1_BYTE5 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS)) +#define MXC_F_USB_SETUP1_BYTE6_POS 16 +#define MXC_F_USB_SETUP1_BYTE6 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS)) +#define MXC_F_USB_SETUP1_BYTE7_POS 24 +#define MXC_F_USB_SETUP1_BYTE7 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS)) + + +#define MXC_F_USB_EP0_EP_DIR_POS 0 +#define MXC_F_USB_EP0_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS)) +#define MXC_F_USB_EP0_EP_BUF2_POS 3 +#define MXC_F_USB_EP0_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS)) +#define MXC_F_USB_EP0_EP_INT_EN_POS 4 +#define MXC_F_USB_EP0_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS)) +#define MXC_F_USB_EP0_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP0_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS)) +#define MXC_F_USB_EP0_EP_DT_POS 6 +#define MXC_F_USB_EP0_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS)) +#define MXC_F_USB_EP0_EP_STALL_POS 8 +#define MXC_F_USB_EP0_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP0_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP0_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP1_EP_DIR_POS 0 +#define MXC_F_USB_EP1_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS)) +#define MXC_F_USB_EP1_EP_BUF2_POS 3 +#define MXC_F_USB_EP1_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS)) +#define MXC_F_USB_EP1_EP_INT_EN_POS 4 +#define MXC_F_USB_EP1_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS)) +#define MXC_F_USB_EP1_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP1_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS)) +#define MXC_F_USB_EP1_EP_DT_POS 6 +#define MXC_F_USB_EP1_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS)) +#define MXC_F_USB_EP1_EP_STALL_POS 8 +#define MXC_F_USB_EP1_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP1_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP1_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP2_EP_DIR_POS 0 +#define MXC_F_USB_EP2_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS)) +#define MXC_F_USB_EP2_EP_BUF2_POS 3 +#define MXC_F_USB_EP2_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS)) +#define MXC_F_USB_EP2_EP_INT_EN_POS 4 +#define MXC_F_USB_EP2_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS)) +#define MXC_F_USB_EP2_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP2_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS)) +#define MXC_F_USB_EP2_EP_DT_POS 6 +#define MXC_F_USB_EP2_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS)) +#define MXC_F_USB_EP2_EP_STALL_POS 8 +#define MXC_F_USB_EP2_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP2_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP2_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP3_EP_DIR_POS 0 +#define MXC_F_USB_EP3_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS)) +#define MXC_F_USB_EP3_EP_BUF2_POS 3 +#define MXC_F_USB_EP3_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS)) +#define MXC_F_USB_EP3_EP_INT_EN_POS 4 +#define MXC_F_USB_EP3_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS)) +#define MXC_F_USB_EP3_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP3_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS)) +#define MXC_F_USB_EP3_EP_DT_POS 6 +#define MXC_F_USB_EP3_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS)) +#define MXC_F_USB_EP3_EP_STALL_POS 8 +#define MXC_F_USB_EP3_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP3_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP3_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP4_EP_DIR_POS 0 +#define MXC_F_USB_EP4_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS)) +#define MXC_F_USB_EP4_EP_BUF2_POS 3 +#define MXC_F_USB_EP4_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS)) +#define MXC_F_USB_EP4_EP_INT_EN_POS 4 +#define MXC_F_USB_EP4_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS)) +#define MXC_F_USB_EP4_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP4_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS)) +#define MXC_F_USB_EP4_EP_DT_POS 6 +#define MXC_F_USB_EP4_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS)) +#define MXC_F_USB_EP4_EP_STALL_POS 8 +#define MXC_F_USB_EP4_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP4_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP4_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP5_EP_DIR_POS 0 +#define MXC_F_USB_EP5_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS)) +#define MXC_F_USB_EP5_EP_BUF2_POS 3 +#define MXC_F_USB_EP5_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS)) +#define MXC_F_USB_EP5_EP_INT_EN_POS 4 +#define MXC_F_USB_EP5_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS)) +#define MXC_F_USB_EP5_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP5_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS)) +#define MXC_F_USB_EP5_EP_DT_POS 6 +#define MXC_F_USB_EP5_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS)) +#define MXC_F_USB_EP5_EP_STALL_POS 8 +#define MXC_F_USB_EP5_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP5_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP5_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP6_EP_DIR_POS 0 +#define MXC_F_USB_EP6_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS)) +#define MXC_F_USB_EP6_EP_BUF2_POS 3 +#define MXC_F_USB_EP6_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS)) +#define MXC_F_USB_EP6_EP_INT_EN_POS 4 +#define MXC_F_USB_EP6_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS)) +#define MXC_F_USB_EP6_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP6_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS)) +#define MXC_F_USB_EP6_EP_DT_POS 6 +#define MXC_F_USB_EP6_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS)) +#define MXC_F_USB_EP6_EP_STALL_POS 8 +#define MXC_F_USB_EP6_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP6_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP6_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP7_EP_DIR_POS 0 +#define MXC_F_USB_EP7_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS)) +#define MXC_F_USB_EP7_EP_BUF2_POS 3 +#define MXC_F_USB_EP7_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS)) +#define MXC_F_USB_EP7_EP_INT_EN_POS 4 +#define MXC_F_USB_EP7_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS)) +#define MXC_F_USB_EP7_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP7_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS)) +#define MXC_F_USB_EP7_EP_DT_POS 6 +#define MXC_F_USB_EP7_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS)) +#define MXC_F_USB_EP7_EP_STALL_POS 8 +#define MXC_F_USB_EP7_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP7_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP7_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_USB_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h new file mode 100644 index 0000000000..906e801460 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_WDT_REGS_H_ +#define _MXC_WDT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file wdt_regs.h + * @addtogroup wdt WDT + * @{ + */ + +/** + * @brief Defines watchdog timer periods + */ +typedef enum { + /** 2^31 cycle period */ + MXC_E_WDT_PERIOD_2_31_CLKS = 0, + /** 2^30 cycle period */ + MXC_E_WDT_PERIOD_2_30_CLKS, + /** 2^29 cycle period */ + MXC_E_WDT_PERIOD_2_29_CLKS, + /** 2^28 cycle period */ + MXC_E_WDT_PERIOD_2_28_CLKS, + /** 2^27 cycle period */ + MXC_E_WDT_PERIOD_2_27_CLKS, + /** 2^26 cycle period */ + MXC_E_WDT_PERIOD_2_26_CLKS, + /** 2^25 cycle period */ + MXC_E_WDT_PERIOD_2_25_CLKS, + /** 2^24 cycle period */ + MXC_E_WDT_PERIOD_2_24_CLKS, + /** 2^23 cycle period */ + MXC_E_WDT_PERIOD_2_23_CLKS, + /** 2^22 cycle period */ + MXC_E_WDT_PERIOD_2_22_CLKS, + /** 2^21 cycle period */ + MXC_E_WDT_PERIOD_2_21_CLKS, + /** 2^20 cycle period */ + MXC_E_WDT_PERIOD_2_20_CLKS, + /** 2^19 cycle period */ + MXC_E_WDT_PERIOD_2_19_CLKS, + /** 2^18 cycle period */ + MXC_E_WDT_PERIOD_2_18_CLKS, + /** 2^17 cycle period */ + MXC_E_WDT_PERIOD_2_17_CLKS, + /** 2^16 cycle period */ + MXC_E_WDT_PERIOD_2_16_CLKS, +} mxc_wdt_period_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */ + __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */ + __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */ + __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */ + __I uint32_t rsv0010; /* 0x0010 */ + __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */ +} mxc_wdt_regs_t; + +/* + Register offsets for module WDT. +*/ +#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) +#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL) +#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL) +#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) + +#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24) +#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42) + + +/* + Field positions and masks for module WDT. +*/ +#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 +#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) +#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 +#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) +#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 +#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) +#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 +#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) +#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 +#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) + +#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 +#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) +#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 +#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) +#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 +#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) + +#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 +#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) +#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 +#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) +#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 +#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) + +#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 +#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_WDT_REGS_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h new file mode 100644 index 0000000000..5000bc6451 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPI0, + SPI_1 = MXC_BASE_SPI1, + SPI_2 = MXC_BASE_SPI2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +typedef enum { + DAC0 = MXC_BASE_DAC0, + DAC1 = MXC_BASE_DAC1, + DAC2 = MXC_BASE_DAC2, + DAC3 = MXC_BASE_DAC3, +} DACName; + +#include "PeripheralAliases.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c new file mode 100644 index 0000000000..def88c99aa --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c @@ -0,0 +1,186 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "device.h" +#include "PeripheralPins.h" +#include "ioman_regs.h" + +/* + * To select a peripheral function on Maxim microcontrollers, multiple + * configurations must be made. The mbed PinMap structure only includes one + * data member to hold this information. To extend the configuration storage, + * the "function" data member is used as a pointer to a pin_function_t + * structure. This structure is defined in objects.h. The definitions below + * include the creation of the pin_function_t structures and the assignment of + * the pointers to the "function" data members. + */ + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_I2C_SCL[] = { + { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RX[] = { + { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_CTS[] = { + { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RTS[] = { + { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { NC, NC, 0 } +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) }, + { NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3}, + {P0_1, PWM_0, 3}, {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, + {P0_2, PWM_1, 2}, {P0_2, PWM_2, 1}, {P0_2, PWM_5, 3}, + {P0_3, PWM_1, 3}, {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, + {P0_4, PWM_2, 2}, {P0_4, PWM_4, 1}, {P0_4, PWM_6, 3}, + {P0_5, PWM_2, 3}, {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, + {P0_6, PWM_3, 2}, {P0_6, PWM_6, 1}, {P0_6, PWM_7, 3}, + {P0_7, PWM_3, 3}, {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, + + {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3}, + {P1_1, PWM_0, 3}, {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, + {P1_2, PWM_1, 2}, {P1_2, PWM_2, 1}, {P1_2, PWM_5, 3}, + {P1_3, PWM_1, 3}, {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, + {P1_4, PWM_2, 2}, {P1_4, PWM_4, 1}, {P1_4, PWM_6, 3}, + {P1_5, PWM_2, 3}, {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, + {P1_6, PWM_3, 2}, {P1_6, PWM_6, 1}, {P1_6, PWM_7, 3}, + {P1_7, PWM_3, 3}, {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, + + {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3}, + {P2_1, PWM_0, 3}, {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, + {P2_2, PWM_1, 2}, {P2_2, PWM_2, 1}, {P2_2, PWM_5, 3}, + {P2_3, PWM_1, 3}, {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, + {P2_4, PWM_2, 2}, {P2_4, PWM_4, 1}, {P2_4, PWM_6, 3}, + {P2_5, PWM_2, 3}, {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, + {P2_6, PWM_3, 2}, {P2_6, PWM_6, 1}, {P2_6, PWM_7, 3}, + {P2_7, PWM_3, 3}, {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {AIN_0P, ADC, 0}, + {AIN_1P, ADC, 0}, + {AIN_2P, ADC, 0}, + {AIN_3P, ADC, 0}, + {AIN_4P, ADC, 0}, + {AIN_5P, ADC, 0}, + {AIN_0N, ADC, 0}, + {AIN_1N, ADC, 0}, + {AIN_2N, ADC, 0}, + {AIN_3N, ADC, 0}, + {AIN_4N, ADC, 0}, + {AIN_5N, ADC, 0}, + {AIN_0D, ADC, 1}, + {AIN_1D, ADC, 1}, + {AIN_2D, ADC, 1}, + {AIN_3D, ADC, 1}, + {AIN_4D, ADC, 1}, + {AIN_5D, ADC, 1}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {AOUT_AO, DAC0, 0}, + {AOUT_BO, DAC1, 0}, + {AOUT_CO, DAC2, 0}, + {AOUT_DO, DAC3, 0}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h new file mode 100644 index 0000000000..c06ab368b6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h new file mode 100644 index 0000000000..b172fc608b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = MXC_V_GPIO_OUT_MODE_HIGH_Z, + PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +typedef enum { + P0_0 = (0 << PORT_SHIFT) | 0, + P0_1 = (0 << PORT_SHIFT) | 1, + P0_2 = (0 << PORT_SHIFT) | 2, + P0_3 = (0 << PORT_SHIFT) | 3, + P0_4 = (0 << PORT_SHIFT) | 4, + P0_5 = (0 << PORT_SHIFT) | 5, + P0_6 = (0 << PORT_SHIFT) | 6, + P0_7 = (0 << PORT_SHIFT) | 7, + P1_0 = (1 << PORT_SHIFT) | 0, + P1_1 = (1 << PORT_SHIFT) | 1, + P1_2 = (1 << PORT_SHIFT) | 2, + P1_3 = (1 << PORT_SHIFT) | 3, + P1_4 = (1 << PORT_SHIFT) | 4, + P1_5 = (1 << PORT_SHIFT) | 5, + P1_6 = (1 << PORT_SHIFT) | 6, + P1_7 = (1 << PORT_SHIFT) | 7, + P2_0 = (2 << PORT_SHIFT) | 0, + P2_1 = (2 << PORT_SHIFT) | 1, + P2_2 = (2 << PORT_SHIFT) | 2, + P2_3 = (2 << PORT_SHIFT) | 3, + P2_4 = (2 << PORT_SHIFT) | 4, + P2_5 = (2 << PORT_SHIFT) | 5, + P2_6 = (2 << PORT_SHIFT) | 6, + P2_7 = (2 << PORT_SHIFT) | 7, + + // Analog ADC pins + AIN_0P = (0xA << PORT_SHIFT) | 0, + AIN_1P = (0xA << PORT_SHIFT) | 1, + AIN_2P = (0xA << PORT_SHIFT) | 2, + AIN_3P = (0xA << PORT_SHIFT) | 3, + AIN_4P = (0xA << PORT_SHIFT) | 4, + AIN_5P = (0xA << PORT_SHIFT) | 5, + AIN_0N = (0xB << PORT_SHIFT) | 0, + AIN_1N = (0xB << PORT_SHIFT) | 1, + AIN_2N = (0xB << PORT_SHIFT) | 2, + AIN_3N = (0xB << PORT_SHIFT) | 3, + AIN_4N = (0xB << PORT_SHIFT) | 4, + AIN_5N = (0xB << PORT_SHIFT) | 5, + + // Analog differential ADC + AIN_0D = (0xC << PORT_SHIFT) | 0, + AIN_1D = (0xC << PORT_SHIFT) | 1, + AIN_2D = (0xC << PORT_SHIFT) | 2, + AIN_3D = (0xC << PORT_SHIFT) | 3, + AIN_4D = (0xC << PORT_SHIFT) | 4, + AIN_5D = (0xC << PORT_SHIFT) | 5, + + // OPAMP Positive supply pins + AOUT_AP = (0xD << PORT_SHIFT) | 0, + AOUT_BP = (0xD << PORT_SHIFT) | 1, + AOUT_CP = (0xD << PORT_SHIFT) | 2, + AOUT_DP = (0xD << PORT_SHIFT) | 3, + + // OPAMP Negative supply pins + AOUT_AN = (0xE << PORT_SHIFT) | 0, + AOUT_BN = (0xE << PORT_SHIFT) | 1, + AOUT_CN = (0xE << PORT_SHIFT) | 2, + AOUT_DN = (0xE << PORT_SHIFT) | 3, + + // DAC Output pins + AOUT_AO = (0xF << PORT_SHIFT) | 0, + AOUT_BO = (0xF << PORT_SHIFT) | 1, + AOUT_CO = (0xF << PORT_SHIFT) | 2, + AOUT_DO = (0xF << PORT_SHIFT) | 3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +#include "PinAliases.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h new file mode 100644 index 0000000000..9dd2de18f2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h @@ -0,0 +1,50 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h new file mode 100644 index 0000000000..0fdf2267e3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _PERIPHERAL_ALIASES_H +#define _PERIPHERAL_ALIASES_H + +#define STDIO_UART UART_1 +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#endif /* _PERIPHERAL_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h new file mode 100644 index 0000000000..95ebfa14d4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _PIN_ALIASES_H +#define _PIN_ALIASES_H + +#define LED_RED P1_7 +#define LED_GREEN P1_6 +#define LED_BLUE P1_4 + +// mbed original LED naming +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define LED4 LED_BLUE + +#define LED_OFF 1 +#define LED_ON !LED_OFF + +// Push button +#define SW1 P1_5 + +// USB Pins +#define USBTX P1_3 +#define USBRX P1_2 + +#define I2C_SCL P0_5 +#define I2C_SDA P0_4 + +#define HCI_SCK P2_0 +#define HCI_MOSI P2_1 +#define HCI_MISO P2_2 +#define HCI_CSN P2_3 +#define HCI_IRQ P2_4 +#define HCI_RST P2_5 + +#define TP1 P1_1 +#define TP2 P1_0 +#define TP3 P0_1 +#define TP4 P0_0 +#define TP5 P0_5 +#define TP6 P0_4 + +#endif /* _PIN_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c new file mode 100644 index 0000000000..906fa7d81e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +//****************************************************************************** +// This function will get called early in system initialization +void low_level_init(void) +{ + /* set pins connected to EM9301 to output low */ + MXC_GPIO->out_val[2] = 0x00; + MXC_GPIO->out_mode[2] = 0x00555555; + + /* wait for the RO to stabilize */ + while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_RING_STABLE)); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c new file mode 100644 index 0000000000..2d64a187e0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c @@ -0,0 +1,144 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogin_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +#define PGA_TRK_CNT 0x8 +#define ADC_ACT_CNT 0x1 +#define ADC_PGA_CNT 0x1 +#define ADC_ACQ_CNT 0x1 +#define ADC_SLP_CNT 0x0 + +//****************************************************************************** +void analogin_init(analogin_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC); + + // Set the object pointer + obj->adc = MXC_ADC; + obj->adccfg = MXC_ADCCFG; + obj->adc_fifo = MXC_ADC_FIFO; + obj->adc_pin = pin; + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup and hold window + MXC_SET_FIELD(&obj->adc->tg_ctrl0, MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT, PGA_TRK_CNT); + + // Setup sampling count and timing + MXC_SET_FIELD(&obj->adc->tg_ctrl1, (MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT | + MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT | MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT), + ((ADC_PGA_CNT << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS) | + (ADC_ACQ_CNT << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS) | + (ADC_SLP_CNT << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS) | + (MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT))); +} + +//****************************************************************************** +float analogin_read(analogin_t *obj) +{ + // Convert integer to float + return (((float)analogin_read_u16(obj)/(float)0xFFFF)); +} + +//****************************************************************************** +uint16_t analogin_read_u16(analogin_t *obj) +{ + // Set the pin to take readings from + unsigned mux_pos; + unsigned diff = 0; + if(obj->adc_pin >> PORT_SHIFT == 0xB) { + mux_pos = (obj->adc_pin & 0xF) + 8; + } else { + mux_pos = (obj->adc_pin & 0xF); + } + + if(obj->adc_pin >> PORT_SHIFT == 0xC) { + diff = 1; + mux_pos = (obj->adc_pin & 0xF) + 8; + } + + // Setup the ADC clock + MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE | + MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL), + ((MXC_E_ADC_MODE_SMPLCNT_FULL_RATE << MXC_F_ADC_CTRL0_ADC_MODE_POS) | + (MXC_E_ADC_AVG_MODE_FILTER_OUTPUT << MXC_F_ADC_CTRL0_AVG_MODE_POS) | + (0x2 << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS) | + MXC_F_ADC_CTRL0_ADC_CLK_EN)); + + // Setup the input multiplexor + MXC_SET_FIELD(&obj->adc->pga_ctrl, (MXC_F_ADC_PGA_CTRL_MUX_CH_SEL | + MXC_F_ADC_PGA_CTRL_MUX_DIFF | MXC_F_ADC_PGA_CTRL_PGA_GAIN), + ((mux_pos << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS) | + (diff << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))); + + // Setup voltage reference + MXC_SET_FIELD(&MXC_AFE->ctrl1, MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL, + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Enable the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN; + + // Clear the done bit + obj->adc->intr = MXC_F_ADC_INTR_DONE_IF; + + // Take one sample + obj->adc->tg_ctrl0 |= (1 << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS); + + // Set the start bit to take the sample + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_START; + + // Wait for the conversion to complete + while(!(obj->adc->intr & MXC_F_ADC_INTR_DONE_IF)) {} + + // Get sample from the fifo + uint16_t sample = (uint16_t)(obj->adc->out & 0xFFFF); + + // Disable ADC + obj->adc->ctrl0 &= ~MXC_F_ADC_CTRL0_CPU_ADC_EN; + + return (sample - 1); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c new file mode 100644 index 0000000000..00ca4e9936 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c @@ -0,0 +1,213 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogout_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void analogout_init(dac_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + DACName dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT((DACName)dac != (DACName)NC); + + // Set the object pointer + obj->dac = ((mxc_dac_regs_t*)MXC_DAC_GET_DAC((pin & 0x3))); + obj->dac_fifo = ((mxc_dac_fifo_t*)MXC_DAC_GET_FIFO((pin & 0x3))); + obj->index = (pin & 0x3); + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_14_dac0 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP0; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_A | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS) | + (0x0 << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP0); + break; + case 1: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_15_dac1 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP1; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_B | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP1); + + break; + case 2: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_16_dac2 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP2; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_C | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS) | + (0x2 << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP2); + break; + case 3: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_17_dac3 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP3; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_D | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS) | + (0x3 << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP3); + break; + } + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup internal voltage references + MXC_SET_FIELD(&MXC_AFE->ctrl1, (MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL | MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL), + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Disable interpolation + obj->dac->ctrl0 &= MXC_F_DAC_CTRL0_INTERP_MODE; +} + +//****************************************************************************** +void analogout_write(dac_t *obj, float value) +{ + analogout_write_u16(obj, (uint16_t)((value/1.0) * 0xFFFF)); +} + +//****************************************************************************** +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Enable the OPAMP + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP0; + break; + case 1: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP1; + break; + case 2: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP2; + break; + case 3: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP3; + break; + } + + // Output 1 sample with minimal delay + obj->dac->rate |= 0x1; + + // Set the start mode to output once data is in the FIFO + obj->dac->ctrl0 &= ~(MXC_F_DAC_CTRL0_START_MODE | MXC_F_DAC_CTRL0_OP_MODE); + + // Enable the DAC + obj->dac->ctrl0 |= (MXC_F_DAC_CTRL0_POWER_MODE_2 | + MXC_F_DAC_CTRL0_POWER_MODE_1_0 | MXC_F_DAC_CTRL0_POWER_ON | + MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START); + + if(obj->index < 2) { + // Convert 16 bits to 12 bits + obj->out = (value >> 4); + obj->dac_fifo->output_16 = (obj->out); + + } else { + // Convert 16 bits to 8 bits + obj->out = (value >> 8); + obj->dac_fifo->output_8 = (obj->out); + } +} + +//****************************************************************************** +float analogout_read(dac_t *obj) +{ + return (((float)analogout_read_u16(obj) / (float)0xFFFF) * 1.5); +} + +//****************************************************************************** +uint16_t analogout_read_u16(dac_t *obj) +{ + if(obj->index < 2) { + // Convert 12 bits to 16 bits + return (obj->out << 4); + } else { + // Convert 8 bits to 16 bits + return (obj->out << 8); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h new file mode 100644 index 0000000000..59ff712fe9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_SPI 1 + +#define DEVICE_I2C 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_ANALOGIN 1 + +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_RTC 1 + +#define DEVICE_SLEEP 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#define DEVICE_CAN 0 +#define DEVICE_ETHERNET 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c new file mode 100644 index 0000000000..2b1c1986ec --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +uint32_t gpio_set(PinName name) +{ + MBED_ASSERT(name != (PinName)NC); + pin_function(name, 0); + return 1 << PINNAME_TO_PIN(name); +} + +void gpio_init(gpio_t *obj, PinName name) +{ + obj->name = name; + if (name == (PinName)NC) { + return; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin); + obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin); + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->name, mode); +} + +void pin_dir(PinName name, PinDirection direction) +{ + MBED_ASSERT(name != (PinName)NC); + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Set function */ + MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin)); + + /* Normal input is always enabled */ + MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); + + /* Set requested output mode */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + out_mode &= ~(0xF << (4 * pin)); + out_mode |= (direction << (4 * pin)); + MXC_GPIO->out_mode[port] = out_mode; +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + pin_dir(obj->name, direction); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c new file mode 100644 index 0000000000..4e153cd01a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c @@ -0,0 +1,168 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define NUM_PORTS 3 +#define NUM_PINS_PER_PORT 8 + +static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}}; +static gpio_irq_handler irq_handler; + +static void handle_irq(unsigned int port) +{ + uint32_t intfl, in_val; + uint32_t mask; + unsigned int pin; + + /* Read pin state */ + in_val = MXC_GPIO->in_val[port]; + + /* Read interrupts */ + intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; + + mask = 1; + + for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) { + if (intfl & mask) { + if (ids[port][pin]) { + if (in_val & mask) { + irq_handler(ids[port][pin], IRQ_RISE); + } else { + irq_handler(ids[port][pin], IRQ_FALL); + } + } + MXC_GPIO->intfl[port] = mask; /* clear interrupt */ + } + mask <<= 1; + } +} + +void gpio_irq_0(void) +{ + handle_irq(0); +} + +void gpio_irq_1(void) +{ + handle_irq(1); +} + +void gpio_irq_2(void) +{ + handle_irq(2); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +{ + if (name == NC) + return -1; + + uint8_t port = PINNAME_TO_PORT(name); + uint8_t pin = PINNAME_TO_PIN(name); + + if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) { + return 1; + } + + obj->port = port; + obj->pin = pin; + + irq_handler = handler; + + ids[port][pin] = id; + + /* register handlers */ + NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); + NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); + NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); + + /* disable the interrupt locally */ + MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); + + /* clear a pending request */ + MXC_GPIO->intfl[port] = 1 << pin; + + /* enable the requested interrupt */ + MXC_GPIO->inten[port] |= (1 << pin); + NVIC_EnableIRQ(GPIO_P0_IRQn + port); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + /* disable interrupt */ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); + MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4)); + + ids[obj->port][obj->pin] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; + uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3; /* only supporting edge interrupts */ + + uint32_t new_mode = curr_mode; + if (event == IRQ_FALL) { + if (enable) { + new_mode |= 0x1; + } else { + new_mode &= ~0x1; + } + } else if (event == IRQ_RISE) { + if (enable) { + new_mode |= 0x2; + } else { + new_mode &= ~0x2; + } + } + + int_mode &= ~(0xF << (obj->pin*4)); + int_mode |= (new_mode << (obj->pin*4)); + MXC_GPIO->int_mode[obj->port] = int_mode; +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] |= (1 << obj->pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h new file mode 100644 index 0000000000..0c064f9068 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h @@ -0,0 +1,71 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName name; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->name != (PinName)NC); + *obj->reg_out = !!value; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->name != (PinName)NC); + return *obj->reg_in; +} + +void pin_dir(PinName name, PinDirection direction); + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->name != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c new file mode 100644 index 0000000000..cb986662db --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "i2cm_regs.h" +#include "clkman_regs.h" +#include "ioman_regs.h" +#include "PeripheralPins.h" + +#define I2C_SLAVE_ADDR_READ_BIT 0x0001 + +#ifndef MXC_I2CM_TX_TIMEOUT +#define MXC_I2CM_TX_TIMEOUT 0x5000 +#endif + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 +#endif + +typedef enum { + /** 100KHz */ + MXC_E_I2CM_SPEED_100KHZ = 0, + /** 400KHz */ + MXC_E_I2CM_SPEED_400KHZ, + /** 1MHz */ + MXC_E_I2CM_SPEED_1MHZ +} i2cm_speed_t; + +/* Clock divider lookup table */ +static const uint32_t clk_div_table[3][8] = { + /* MXC_E_I2CM_SPEED_100KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_400KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_1MHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: */ 0, /* not supported */ + /* 4: */ 0, /* not supported */ + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, +}; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c != NC); + + obj->i2c = i2c; + obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->start_pending = 0; + obj->stop_pending = 0; + + // configure the pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // enable the clock + MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // reset module + i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + i2c->ctrl = 0; + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + // set timeout to 255 ms and turn on the auto-stop option + i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN; + + // enable tx_fifo and rx_fifo + i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + // compute clock array index + int clki = ((SystemCoreClock + 1500000) / 3000000) - 1; + + // get clock divider settings from lookup table + if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki]; + } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki]; + } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) { + obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki]; + } +} + +static int write_tx_fifo(i2c_t *obj, const uint16_t data) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while (*obj->txfifo) { + uint32_t intfl = obj->i2c->intfl; + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + return I2C_ERROR_NO_SLAVE; + } + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + return I2C_ERROR_BUS_BUSY; + } + timeout--; + } + *obj->txfifo = data; + + return 0; +} + +static int wait_tx_in_progress(i2c_t *obj) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout); + + uint32_t intfl = obj->i2c->intfl; + + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + i2c_reset(obj); + return I2C_ERROR_NO_SLAVE; + } + + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + i2c_reset(obj); + return I2C_ERROR_BUS_BUSY; + } + + return 0; +} + +int i2c_start(i2c_t *obj) +{ + obj->start_pending = 1; + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + obj->start_pending = 0; + write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP); + + return wait_tx_in_progress(obj); +} + +void i2c_reset(i2c_t *obj) +{ + obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + obj->i2c->intfl = 0x3FF; // clear all interrupts + obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN; + obj->start_pending = 0; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (obj->start_pending) { + obj->start_pending = 0; + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START; + } else { + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK; + } + + if ((err = write_tx_fifo(obj, data)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + return 0; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + uint16_t fifo_value; + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (last) { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK; + } else { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT; + } + + if ((err = write_tx_fifo(obj, fifo_value)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + int timeout = MXC_I2CM_RX_TIMEOUT; + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + break; + } + } + + if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) { + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + return *obj->rxfifo; + } + + return -1; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int err, retval = 0; + int i; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // write the address to the fifo + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write) + return err; + } + obj->start_pending = 0; + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + // load as much of the cmd into the FIFO as possible + for (i = 0; i < length; i++) { + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK) + retval = (retval ? retval : err); + break; + } + } + + if (stop) { + obj->stop_pending = 0; + if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + retval = (retval ? retval : err); + } + + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + int timeout = MXC_I2CM_TX_TIMEOUT; + // Wait for TX fifo to be empty + while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {} + } + + if (retval == 0) { + return length; + } + + return retval; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int err, retval = 0; + int i = length; + int timeout; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // start + addr (read) + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) { + goto read_done; + } + obj->start_pending = 0; + + while (i > 256) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) { + goto read_done; + } + i -= 256; + } + + if (i > 1) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) { + goto read_done; + } + } + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte + goto read_done; + } + + if (stop) { + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + i = 0; + while (i < length) { + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + retval = -3; + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + + uint16_t temp = *obj->rxfifo; + + if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) { + continue; + } + data[i++] = (uint8_t) temp; + } + +read_done: + + if (stop) { + obj->stop_pending = 0; + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + } + + if (retval == 0) { + return length; + } + + return retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h new file mode 100644 index 0000000000..442ab5e248 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "gpio_regs.h" +#include "uart_regs.h" +#include "i2cm_regs.h" +#include "spi_regs.h" +#include "pt_regs.h" +#include "adc_regs.h" +#include "dac_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + PortName port; + uint32_t mask; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +}; + +struct gpio_irq_s { + uint8_t port; + uint8_t pin; +}; + +struct serial_s { + int index; + mxc_uart_regs_t *uart; +}; + +struct i2c_s { + int index; + mxc_i2cm_regs_t *i2c; + volatile uint16_t *txfifo; + volatile uint16_t *rxfifo; + int start_pending; + int stop_pending; +}; + +struct spi_s { + int index; + mxc_spi_regs_t *spi; + mxc_spi_rxfifo_regs_t *rxfifo; + mxc_spi_txfifo_regs_t *txfifo; +}; + +struct pwmout_s { + mxc_pt_regs_t *pwm; + int period; + int pulse_width; +}; + +struct analogin_s { + mxc_adc_regs_t *adc; + mxc_adccfg_regs_t *adccfg; + mxc_adc_fifo_regs_t * adc_fifo; + PinName adc_pin; +}; + +struct dac_s { + int index; + uint16_t out; + mxc_dac_regs_t *dac; + mxc_dac_fifo_t * dac_fifo; +}; + +typedef struct { + volatile uint32_t *reg_req; + volatile uint32_t *reg_ack; + uint32_t req_val; + uint32_t ack_mask; +} pin_function_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c new file mode 100644 index 0000000000..099c77a307 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "objects.h" +#include "gpio_regs.h" +#include "ioman_regs.h" + +void pin_function(PinName name, int function) +{ + MBED_ASSERT(name != (PinName)NC); + + if ((function >= 0) && (function <= 0xF)) { + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4)); + MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4)); + } else { + /* Assume this is a pointer to a pin function object */ + pin_function_t *obj = (pin_function_t*)function; + + if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) { + /* Request pin mapping */ + *obj->reg_req |= obj->req_val; + + /* Check for acknowledgment */ + MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val); + } + } +} + +void pin_mode(PinName name, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Must set mode while retaining direction */ + + /* Get the current direction */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + uint32_t curr_mode = (out_mode >> (pin*4)) & 0xF; + PinDirection dir = PIN_OUTPUT; + if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z)) { + dir = PIN_INPUT; + } + + /* Set mode based on current direction */ + uint32_t new_mode; + if (dir == PIN_OUTPUT) { + // PullUp = not valid, + // OpenDrain = MXC_V_GPIO_OUT_MODE_OD, + // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL, + if (mode == OpenDrain) { + new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE; + } + } else { + // PullUp = MXC_V_GPIO_OUT_MODE_HIZPU, + // OpenDrain = not valid, + // PullNone = MXC_V_GPIO_OUT_MODE_HIZ, + if (mode == PullUp) { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z; + } + } + + /* Set new mode */ + out_mode &= ~(0xF << (pin*4)); + out_mode |= (new_mode << (pin*4)); + MXC_GPIO->out_mode[port] = out_mode; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c new file mode 100644 index 0000000000..f8b7e0884c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c @@ -0,0 +1,97 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->reg_out = &MXC_GPIO->out_val[port]; + obj->reg_in = &MXC_GPIO->in_val[port]; + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i)); + pin_dir(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + // The mode is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), dir); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + return (*obj->reg_in & obj->mask); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c new file mode 100644 index 0000000000..1a412248de --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c @@ -0,0 +1,234 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "cmsis.h" +#include "pwmout_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void pwmout_init(pwmout_t* obj, PinName pin) +{ + // Make sure the pin is free for GPIO use + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT); + MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin)); + + int i = 0; + PinMap pwm = PinMap_PWM[0]; + + // Check if there is a pulse train already active on this port + int pin_func = (MXC_GPIO->func_sel[port] & (0xF << (port_pin*4))) >> (port_pin*4); + if((pin_func > 0) && (pin_func < 4)) { + // Search through PinMap_PWM to find the active PT + while(pwm.pin != (PinName)NC) { + if((pwm.pin == pin) && (pwm.function == pin_func)) { + break; + } + pwm = PinMap_PWM[++i]; + } + + } else { + // Search through PinMap_PWM to find an available PT + int i = 0; + while(pwm.pin != (PinName)NC && (i > -1)) { + pwm = PinMap_PWM[i++]; + if(pwm.pin == pin) { + // Check each instance of PT + while(1) { + // Check to see if this PT instance is already in use + if((((mxc_pt_regs_t*)pwm.peripheral)->rate_length & + MXC_F_PT_RATE_LENGTH_MODE)) { + i = -1; + break; + } + + // If all instances are in use, overwrite the last + pwm = PinMap_PWM[++i]; + if(pwm.pin != pin) { + pwm = PinMap_PWM[--i]; + i = -1; + break; + } + + } + } + } + } + + // Make sure we found an available PWM generator + MBED_ASSERT(pwm.pin != (PinName)NC); + + // Disable all pwm output + MXC_PTG->ctrl = 0; + + // Enable the clock + MXC_CLKMAN->clk_ctrl_2_pt = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Set the drive mode to normal + MXC_SET_FIELD(&MXC_GPIO->out_mode[port], (0x7 << (port_pin*4)), (MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << (port_pin*4))); + + // Set the obj pointer to the propper PWM instance + obj->pwm = (mxc_pt_regs_t*)pwm.peripheral; + + // Initialize object period and pulse width + obj->period = -1; + obj->pulse_width = -1; + + // Disable the output + obj->pwm->train = 0x0; + obj->pwm->rate_length = 0x0; + + // Configure the pin + pin_mode(pin, (PinMode)PullNone); + pin_function(pin, pwm.function); + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_us(obj, 20000); + pwmout_write (obj, 0); + + // Enable the global pwm + MXC_PTG->ctrl = MXC_F_PT_CTRL_ENABLE_ALL; +} + +//****************************************************************************** +void pwmout_free(pwmout_t* obj) +{ + // Set the registers to the reset value + obj->pwm->train = 0; + obj->pwm->rate_length = 0x08000000; +} + +//****************************************************************************** +static void pwmout_update(pwmout_t* obj) +{ + // Calculate and set the divider ratio + int div = (obj->period * (SystemCoreClock/1000000))/32; + if (div < 2){ + div = 2; + } + MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); + + // Change the duty cycle to adjust the pulse width + obj->pwm->train = (0xFFFFFFFF << (32-((32*obj->pulse_width)/obj->period))); +} + + +//****************************************************************************** +void pwmout_write(pwmout_t* obj, float percent) +{ + // Saturate percent if outside of range + if(percent < 0.0) { + percent = 0.0; + } else if(percent > 1.0) { + percent = 1.0; + } + + // Resize the pulse width to set the duty cycle + pwmout_pulsewidth_us(obj, (int)(percent*obj->period)); +} + +//****************************************************************************** +float pwmout_read(pwmout_t* obj) +{ + // Check for when pulsewidth or period equals 0 + if((obj->pulse_width == 0) || (obj->period == 0)){ + return 0; + } + + // Return the duty cycle + return ((float)obj->pulse_width / (float)obj->period); +} + +//****************************************************************************** +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_period_us(pwmout_t* obj, int us) +{ + // Check the range of the period + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Set pulse width to half the period if uninitialized + if(obj->pulse_width == -1){ + obj->pulse_width = us/2; + } + + // Save the period + obj->period = us; + + // Update the registers + pwmout_update(obj); +} + +//****************************************************************************** +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + // Check the range of the pulsewidth + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Initialize period to double the pulsewidth if uninitialized + if(obj->period == -1){ + obj->period = 2*us; + } + + // Save the pulsewidth + obj->pulse_width = us; + + // Update the register + pwmout_update(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c new file mode 100644 index 0000000000..033420d4ad --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "rtc_api.h" +#include "cmsis.h" +#include "rtc_regs.h" +#include "pwrseq_regs.h" +#include "clkman_regs.h" + +static int rtc_inited = 0; +static volatile uint32_t overflow_cnt = 0; +static uint32_t overflow_alarm = 0; + +//****************************************************************************** +static void overflow_handler(void) +{ + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; + overflow_cnt++; + + if (overflow_cnt == overflow_alarm) { + // Enable the comparator interrupt for the alarm + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } +} + +//****************************************************************************** +static void alarm_handler(void) +{ + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; +} + +//****************************************************************************** +void rtc_init(void) +{ + if(rtc_inited) { + return; + } + rtc_inited = 1; + + // Enable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable the clock to the RTC + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + + // Set the divider from the 4kHz clock + MXC_RTCTMR->prescale = MXC_E_RTC_PRESCALE_DIV_2_0; + + // Enable the overflow interrupt + MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW; + + // Prepare interrupt handlers + NVIC_SetVector(RTC0_IRQn, (uint32_t)alarm_handler); + NVIC_EnableIRQ(RTC0_IRQn); + NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler); + NVIC_EnableIRQ(RTC3_IRQn); + + // Enable the RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; +} + +//****************************************************************************** +void rtc_free(void) +{ + if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) { + // Clear and disable RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR; + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; + + // Wait for pending transactions + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + } + + // Disable the clock to the RTC + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); + + // Disable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED; +} + +//****************************************************************************** +int rtc_isenabled(void) +{ + return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE); +} + +//****************************************************************************** +time_t rtc_read(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + return (timer_cnt >> shift_amt) + (ovf_cnt_1 << (32 - shift_amt)); +} + +//****************************************************************************** +uint64_t rtc_read_us(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + uint64_t currentUs; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + currentUs = (((uint64_t)timer_cnt * 1000000) >> shift_amt) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - shift_amt)); + + return currentUs; +} + +//****************************************************************************** +void rtc_write(time_t t) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating + MXC_RTCTMR->timer = t << shift_amt; + overflow_cnt = t >> (32 - shift_amt); + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating +} + +//****************************************************************************** +void rtc_set_wakeup(uint64_t wakeupUs) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Disable the alarm while it is prepared + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt + + overflow_alarm = (wakeupUs >> (32 - shift_amt)) / 1000000; + + if (overflow_alarm == overflow_cnt) { + MXC_RTCTMR->comp[0] = (wakeupUs << shift_amt) / 1000000; + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } + + // Enable wakeup from RTC + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER | MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c new file mode 100644 index 0000000000..34fc49ce8a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c @@ -0,0 +1,355 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "serial_api.h" +#include "uart_regs.h" +#include "PeripheralPins.h" + +#define UART_NUM 2 +#define DEFAULT_BAUD 9600 +#define DEFAULT_STOP 1 +#define DEFAULT_PARITY ParityNone + +#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \ + MXC_F_UART_INTFL_RX_PARITY_ERROR | \ + MXC_F_UART_INTFL_RX_OVERRUN) + +// Variables for managing the stdio UART +int stdio_uart_inited; +serial_t stdio_uart; + +// Variables for interrupt driven +static uart_irq_handler irq_handler; +static uint32_t serial_irq_ids[UART_NUM]; + +//****************************************************************************** +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine which uart is associated with each pin + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + // Make sure that both pins are pointing to the same uart + MBED_ASSERT(uart != (UARTName)NC); + + // Set the obj pointer to the proper uart + obj->uart = (mxc_uart_regs_t*)uart; + + // Set the uart index + obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart); + + // Configure the pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // Flush the RX and TX FIFOs, clear the settings + obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH); + + // Disable interrupts + obj->uart->inten = 0; + obj->uart->intfl = 0; + + // Configure to default settings + serial_baud(obj, DEFAULT_BAUD); + serial_format(obj, 8, ParityNone, 1); + + // Manage stdio UART + if(uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +//****************************************************************************** +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t idiv = 0, ddiv = 0, div = 0; + + // Calculate the integer and decimal portions + div = SystemCoreClock / ((baudrate / 100) * 128); + idiv = (div / 100); + ddiv = (div - idiv * 100) * 128 / 100; + + obj->uart->baud_int = idiv; + obj->uart->baud_div_128 = ddiv; + + // Enable the baud clock + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + +//****************************************************************************** +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + + // Check the validity of the inputs + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || + (parity == ParityEven) || (parity == ParityForced1) || + (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + // Adjust the stop and data bits + stop_bits -= 1; + data_bits -= 5; + + // Adjust the parity setting + int paren = 0, mode = 0; + switch (parity) { + case ParityNone: + paren = 0; + mode = 0; + break; + case ParityOdd : + paren = 1; + mode = 0; + break; + case ParityEven: + paren = 1; + mode = 1; + break; + case ParityForced1: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + case ParityForced0: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + default: + paren = 1; + mode = 0; + break; + } + + obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) | + (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) | + (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) | + (mode << MXC_F_UART_CTRL_PARITY_MODE_POS)); +} + +//****************************************************************************** +void uart_handler(mxc_uart_regs_t* uart, int id) +{ + // Check for errors or RX Threshold + if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) { + irq_handler(serial_irq_ids[id], RxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS); + } + + // Check for TX Threshold + if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) { + irq_handler(serial_irq_ids[id], TxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY); + } +} + +void uart0_handler(void) +{ + uart_handler(MXC_UART0, 0); +} +void uart1_handler(void) +{ + uart_handler(MXC_UART1, 1); +} + +//****************************************************************************** +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +//****************************************************************************** +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if(obj->index == 0) { + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + } else { + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + } + + if(irq == RxIrq) { + // Set the RX FIFO Threshold to 1 + obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD; + obj->uart->ctrl |= 0x1; + // Enable RX FIFO Threshold Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } + + } else if (irq == TxIrq) { + // Enable TX Almost empty Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } + + } else { + MBED_ASSERT(0); + } +} + + +//****************************************************************************** +int serial_getc(serial_t *obj) +{ + int c; + + // Wait for data to be available + while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {} + c = obj->uart->tx_rx_fifo & 0xFF; + + // Echo characters for stdio + if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { + obj->uart->tx_rx_fifo = c; + } + + return c; +} + +//****************************************************************************** +void serial_putc(serial_t *obj, int c) +{ + // Append a carriage return for stdio + if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = '\r'; + } + + // Wait for TXFIFO to not be full + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = c; + +} + +//****************************************************************************** +int serial_readable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY)); +} + +//****************************************************************************** +int serial_writable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL)); +} + +//****************************************************************************** +void serial_clear(serial_t *obj) +{ + // Clear the rx and tx fifos + obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH ); +} + + +//****************************************************************************** +void serial_break_set(serial_t *obj) +{ + // Make sure that nothing is being sent + while(obj->uart->status & MXC_F_UART_STATUS_RX_BUSY) {} + + // Disable the clock to pause any transmission + obj->uart->ctrl &= ~MXC_F_UART_CTRL_BAUD_CLK_EN ; +} + +//****************************************************************************** +void serial_break_clear(serial_t *obj) +{ + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + + +//****************************************************************************** +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + + +//****************************************************************************** +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + if(FlowControlNone == type) { + // Disable hardware flow control + obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN); + return; + } + + // Check to see if we can use HW flow control + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_cts != (UARTName)NC); + + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + } + + if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_rts != (UARTName)NC); + + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + } + + if(FlowControlRTSCTS == type){ + // Make sure that the pins are pointing to the same UART + MBED_ASSERT(uart != (UARTName)NC); + } + + // Enable hardware flow control + obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c new file mode 100644 index 0000000000..3eb9154f03 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c @@ -0,0 +1,169 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "sleep_api.h" +#include "us_ticker_api.h" +#include "cmsis.h" +#include "pwrman_regs.h" +#include "pwrseq_regs.h" +#include "ioman_regs.h" +#include "rtc_regs.h" + +#define MIN_DEEP_SLEEP_US 500 + +uint64_t rtc_read_us(void); +void rtc_set_wakeup(uint64_t wakeupUs); +void us_ticker_deinit(void); +void us_ticker_set(timestamp_t timestamp); + +static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART; + +// Normal wait mode +void sleep(void) +{ + // Normal sleep mode for ARM core + SCB->SCR = 0; + + __DSB(); + __WFI(); +} + +// Work-around for issue of clearing power sequencer I/O flag +static void clearAllGPIOWUD(void) +{ + uint32_t wud_req0 = MXC_IOMAN->wud_req0; + uint32_t wud_req1 = MXC_IOMAN->wud_req1; + + // I/O must be a wakeup detect to clear + MXC_IOMAN->wud_req0 = 0xffffffff; + MXC_IOMAN->wud_req1 = 0xffffffff; + + // Clear all WUDs + MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL; + MXC_PWRMAN->wud_pulse0 = 1; + + // Restore WUD requests + MXC_IOMAN->wud_req0 = wud_req0; + MXC_IOMAN->wud_req1 = wud_req1; +} + +// Low-power stop mode +void deepsleep(void) +{ + uint64_t sleepStartRtcUs; + uint32_t sleepStartTickerUs; + int32_t sleepDurationUs; + uint64_t sleepEndRtcUs; + uint64_t elapsedUs; + + __disable_irq(); + + // Wait for all STDIO characters to be sent. The UART clock will stop. + while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY); + + // Record the current times + sleepStartRtcUs = rtc_read_us(); + sleepStartTickerUs = us_ticker_read(); + + // Get the next mbed timer expiration + timestamp_t next_event = 0; + us_ticker_get_next_timestamp(&next_event); + sleepDurationUs = next_event - sleepStartTickerUs; + + if (sleepDurationUs < MIN_DEEP_SLEEP_US) { + /* The next wakeup is too soon. */ + __enable_irq(); + return; + } + + // Disable the us_ticker. It won't be clocked in DeepSleep + us_ticker_deinit(); + + // Prepare to wakeup from the RTC + rtc_set_wakeup(sleepStartRtcUs + sleepDurationUs); + + // Prepare for LP1 + uint32_t reg0 = MXC_PWRSEQ->reg0; + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode + if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run + reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode + } else { + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode + } + reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode + reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1 + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag + MXC_PWRSEQ->reg0 = reg0; + + MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS); + + // Deep sleep for ARM core + SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; + + // clear latches for wakeup detect + MXC_PWRSEQ->flags = MXC_PWRSEQ->flags; + if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) { + // attempt work-around for I/O flag clearing issue + clearAllGPIOWUD(); + MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP; + } + + // Wait for pending RTC transaction + while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + // Ensure that the event register is clear + __SEV(); // set event + __WFE(); // clear event + + // Enter LP1 + __WFE(); + // Woke up from LP1 + + // The RTC timer does not update until the next tick + uint64_t tempUs = rtc_read_us(); + do { + sleepEndRtcUs = rtc_read_us(); + } while(sleepEndRtcUs == tempUs); + + // Get the elapsed time from the RTC. Wakeup could have been from some other event. + elapsedUs = sleepEndRtcUs - sleepStartRtcUs; + + // Update the us_ticker. It was not clocked during DeepSleep + us_ticker_init(); + us_ticker_set(sleepStartTickerUs + elapsedUs); + us_ticker_get_next_timestamp(&next_event); + us_ticker_set_interrupt(next_event); + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c new file mode 100644 index 0000000000..85e39db333 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "spi_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +#define DEFAULT_CHAR 8 +#define DEFAULT_MODE 0 +#define DEFAULT_FREQ 1000000 + +// Formatting settings +static int spi_bits; + +//****************************************************************************** +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Make sure pins are pointing to the same SPI instance + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl; + + // Give the application the option to manually control Slave Select + if((SPIName)spi_ssel != (SPIName)NC) { + spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + } else { + spi_cntl = spi_sclk; + } + + SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((SPIName)spi != (SPIName)NC); + + // Set the obj pointer to the proper SPI Instance + obj->spi = (mxc_spi_regs_t*)spi; + + // Set the SPI index and FIFOs + obj->index = MXC_SPI_BASE_TO_INSTANCE(obj->spi); + obj->rxfifo = MXC_SPI_GET_RXFIFO(obj->index); + obj->txfifo = MXC_SPI_GET_TXFIFO(obj->index); + + // Configure the pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + // Enable SPI and FIFOs + obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN | + MXC_F_SPI_GEN_CTRL_TX_FIFO_EN | + MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ); + + // Give instance the default settings + spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0); + spi_frequency(obj, DEFAULT_FREQ); +} + +//****************************************************************************** +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Check the validity of the inputs + MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3))); + + // Only supports master mode + MBED_ASSERT(!slave); + + // Save formatting data + spi_bits = bits; + + // Set the mode + obj->spi->mstr_cfg &= ~(MXC_F_SPI_MSTR_CFG_SPI_MODE); + obj->spi->mstr_cfg |= (mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS); +} + +//****************************************************************************** +void spi_frequency(spi_t *obj, int hz) +{ + // Maximum frequency is half the system frequency + MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2)); + unsigned clocks = ((SystemCoreClock/2)/(hz)); + + // Figure out the divider ratio + int clk_div = 1; + while(clk_div < 10) { + if(clocks < 0x10) { + break; + } + clk_div++; + clocks = clocks >> 1; + } + + // Turn on the SPI clock + if(obj->index == 0) { + MXC_CLKMAN->clk_ctrl_3_spi0 = clk_div; + } else if(obj->index == 1) { + MXC_CLKMAN->clk_ctrl_4_spi1 = clk_div; + } else if(obj->index == 2) { + MXC_CLKMAN->clk_ctrl_5_spi2 = clk_div; + } else { + MBED_ASSERT(0); + } + + // Set the number of clocks to hold sclk high and low + MXC_SET_FIELD(&obj->spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK), + ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))); +} + +//****************************************************************************** +int spi_master_write(spi_t *obj, int value) +{ + int bits = spi_bits; + if(spi_bits == 32) { + bits = 0; + } + // Create the header + uint16_t header = ((0x3 << MXC_F_SPI_FIFO_DIR_POS ) | // TX and RX + (0x0 << MXC_F_SPI_FIFO_UNIT_POS) | // Send bits + (bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units + (0x1 << MXC_F_SPI_FIFO_DASS_POS)); // Deassert SS + + // Send the message header + obj->txfifo->txfifo_16 = header; + + // Send the data + if(spi_bits < 17) { + obj->txfifo->txfifo_16 = (uint16_t)value; + } else { + obj->txfifo->txfifo_32 = (uint32_t)value; + } + + // Get the data + bits = spi_bits; + int result = 0; + int i = 0; + while(bits > 0) { + // Wait for data + while(((obj->spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) + >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1) {} + + result |= (obj->rxfifo->rxfifo_8 << (i++*8)); + bits-=8; + } + + return result; +} + +//****************************************************************************** +int spi_busy(spi_t *obj) +{ + return !(obj->spi->intfl & MXC_F_SPI_INTFL_TX_READY); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c new file mode 100644 index 0000000000..b129ae5b69 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c @@ -0,0 +1,261 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_error.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "tmr_regs.h" + +#define US_TIMER MXC_TMR0 +#define US_TIMER_IRQn TMR0_IRQn + +static int us_ticker_inited = 0; +static uint32_t ticks_per_us; +static uint32_t tick_win; +static volatile uint64_t current_cnt; // Hold the current ticks +static volatile uint64_t event_cnt; // Holds the value of the next event + +#define ticks_to_us(ticks) ((ticks) / ticks_per_us); +#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) + +//****************************************************************************** +static inline void inc_current_cnt(uint32_t inc) { + + // Overflow the ticker when the us ticker overflows + current_cnt += inc; + if(current_cnt > MAX_TICK_VAL) { + current_cnt -= (MAX_TICK_VAL + 1); + } +} + +//****************************************************************************** +static inline int event_passed(uint64_t current, uint64_t event) { + + // Determine if the event has already happened. + // If the event is behind the current ticker, within a window, + // then the event has already happened. + if(((current < tick_win) && ((event < current) || + (event > (MAX_TICK_VAL - (tick_win - current))))) || + ((event < current) && (event > (current - tick_win)))) { + return 1; + } + + return 0; +} + +//****************************************************************************** +static inline uint64_t event_diff(uint64_t current, uint64_t event) { + + // Check to see if the ticker will overflow before the event + if(current <= event) { + return (event - current); + } + + return ((MAX_TICK_VAL - current) + event); +} + +//****************************************************************************** +static void tmr_handler(void) +{ + uint32_t term_cnt32 = US_TIMER->term_cnt32; + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + + inc_current_cnt(term_cnt32); + + if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { + // the timestamp has expired + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } else { + + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + + // Since the timer keeps counting after the terminal value is reached, it is possible that the new + // terminal value is in the past. + if (US_TIMER->term_cnt32 < US_TIMER->count32) { + // the timestamp has expired + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } + } + } +} + +//****************************************************************************** +void us_ticker_init(void) +{ + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + current_cnt = 0; + event_cnt = -1; // initialize to max value + + if (SystemCoreClock <= 1000000) { + error("us_ticker cannot operate at this SystemCoreClock"); + return; + } + + // Configure timer for 32-bit continuous mode with /1 prescaler + US_TIMER->ctrl = MXC_E_TMR_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS | (0 << MXC_F_TMR_CTRL_PRESCALE_POS); + ticks_per_us = SystemCoreClock / 1000000; + + // Set the tick window to 10ms + tick_win = SystemCoreClock/100; + + // Set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->pwm_cap32 = 0xFFFFFFFF; + US_TIMER->count32 = 0; + + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear pending interrupts + + NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler); + NVIC_EnableIRQ(US_TIMER_IRQn); + + US_TIMER->inten |= MXC_F_TMR_INTEN_TIMER0; // enable interrupts + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_deinit(void) +{ + US_TIMER->ctrl = 0; // disable timer + US_TIMER->inten = 0; // disable interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupts + us_ticker_inited = 0; +} + +//****************************************************************************** +uint32_t us_ticker_read(void) +{ + uint64_t current_cnt1, current_cnt2; + uint32_t term_cnt, tmr_cnt; + int intfl1, intfl2; + + if (!us_ticker_inited) + us_ticker_init(); + + // Ensure coherency between current_cnt and US_TIMER->count32 + do { + current_cnt1 = current_cnt; + intfl1 = US_TIMER->intfl; + term_cnt = US_TIMER->term_cnt32; + tmr_cnt = US_TIMER->count32; + intfl2 = US_TIMER->intfl; + current_cnt2 = current_cnt; + } while ((current_cnt1 != current_cnt2) || (intfl1 != intfl2)); + + if (intfl1) { + current_cnt1 += term_cnt; + } + + current_cnt1 += tmr_cnt; + + return (current_cnt1 / ticks_per_us); +} + +//****************************************************************************** +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Note: interrupts are disabled before this function is called. + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + + if (US_TIMER->intfl) { + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + inc_current_cnt(US_TIMER->term_cnt32); + } + + // add and reset the current count value + inc_current_cnt(US_TIMER->count32); + US_TIMER->count32 = 0; + + // add the number of cycles that the timer is disabled here for + inc_current_cnt(200); + + event_cnt = (uint64_t)timestamp * ticks_per_us; + + // Check to see if the event has already passed + if (!event_passed(current_cnt, event_cnt)) { + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + } else { + // the event occurs after the next overflow + US_TIMER->term_cnt32 = 0xFFFFFFFF; // set to max + } + } else { + // the requested timestamp occurs in the past + // set the timer up to immediately expire + US_TIMER->term_cnt32 = 1; + } + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_disable_interrupt(void) +{ + // There are no more events, set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; +} + +//****************************************************************************** +void us_ticker_clear_interrupt(void) +{ + // cleared in the local handler +} + +//****************************************************************************** +void us_ticker_set(timestamp_t timestamp) +{ + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + current_cnt = (uint64_t)timestamp * ticks_per_us; + US_TIMER->count32 = 0; + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer + + if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) { + // The next timestamp has elapsed. Trigger the interrupt to handle it. + NVIC_SetPendingIRQ(US_TIMER_IRQn); + } +} diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index db6c237218..530046c741 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -301,6 +301,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_STM32F303RE) #define INITIAL_SP (0x20010000UL) +#elif defined(TARGET_MAX32610) +#define INITIAL_SP (0x20008000UL) + #else #error "no target defined" diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index d05145f027..0b836cd419 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -51,7 +51,7 @@ #ifndef OS_TASKCNT # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -67,7 +67,7 @@ #ifndef OS_SCHEDULERSTKSIZE # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -168,6 +168,9 @@ #elif defined(TARGET_STM32F401VC) # define OS_CLOCK 84000000 +#elif defined(TARGET_MAX32610) +# define OS_CLOCK 24000000 + # else # error "no target defined" # endif diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index a056db24e6..bd8894ced2 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -36,6 +36,10 @@ DigitalIn in(PD_0); DigitalOut out(D7); DigitalIn in(D0); +#elif defined(TARGET_MAXWSNENV) +DigitalOut out(TP3); +DigitalIn in(TP4); + #else DigitalOut out(p5); DigitalIn in(p25); diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index af937041d8..d9d91a7364 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -36,6 +36,10 @@ DigitalInOut d2(PD_0); DigitalInOut d1(D0); DigitalInOut d2(D7); +#elif defined(TARGET_MAXWSNENV) +DigitalInOut d1(TP3); +DigitalInOut d2(TP4); + #else DigitalInOut d1(p5); DigitalInOut d2(p25); diff --git a/libraries/tests/mbed/i2c_TMP102/main.cpp b/libraries/tests/mbed/i2c_TMP102/main.cpp index 388d38e13f..163ea88d2b 100644 --- a/libraries/tests/mbed/i2c_TMP102/main.cpp +++ b/libraries/tests/mbed/i2c_TMP102/main.cpp @@ -27,7 +27,8 @@ TMP102 temperature(p28, p27, 0x90); defined(TARGET_NUCLEO_L073RZ) || \ defined(TARGET_NUCLEO_L152RE) || \ defined(TARGET_LPC824) || \ - defined(TARGET_FF_ARDUINO) + defined(TARGET_FF_ARDUINO) || \ + defined(TARGET_MAXWSNENV) TMP102 temperature(I2C_SDA, I2C_SCL, 0x90); #else diff --git a/libraries/tests/mbed/i2c_master/main.cpp b/libraries/tests/mbed/i2c_master/main.cpp index ef195192bf..392be3218c 100644 --- a/libraries/tests/mbed/i2c_master/main.cpp +++ b/libraries/tests/mbed/i2c_master/main.cpp @@ -8,7 +8,7 @@ I2C i2c(PTE0, PTE1); #elif defined(TARGET_nRF51822) I2C i2c(p22,p20); -#elif defined(TARGET_FF_ARDUINO) +#elif defined(TARGET_FF_ARDUINO) || defined(TARGET_MAXWSNENV) I2C i2c(I2C_SDA, I2C_SCL); #else I2C i2c(p28, p27); diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index 45779a0970..3a55c00d8d 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -66,6 +66,10 @@ void in_handler() { #define PIN_OUT D0 #define PIN_IN D7 +#elif defined(TARGET_MAXWSNENV) +#define PIN_OUT P0_0 +#define PIN_IN P0_1 + #else #define PIN_IN (p5) #define PIN_OUT (p25) diff --git a/libraries/tests/mbed/portinout/main.cpp b/libraries/tests/mbed/portinout/main.cpp index d88ff2d934..1a30f42561 100644 --- a/libraries/tests/mbed/portinout/main.cpp +++ b/libraries/tests/mbed/portinout/main.cpp @@ -63,6 +63,15 @@ #define P2_2 (1 << 25) // p25 #define PORT_2 Port0 +#elif defined(TARGET_MAXWSNENV) +#define P1_1 (1 << 0) +#define P1_2 (1 << 1) +#define PORT_1 Port0 + +#define P2_1 (1 << 0) +#define P2_2 (1 << 1) +#define PORT_2 Port1 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp index b15383bad0..3c30032493 100644 --- a/libraries/tests/mbed/portout/main.cpp +++ b/libraries/tests/mbed/portout/main.cpp @@ -10,6 +10,11 @@ # define LED2 (1 << 9) // P1.9 # define LED3 (1 << 10) // P1.10 # define LED4 (1 << 11) // P1.11 +# elif defined(TARGET_MAXWSNENV) +# define LED1 (1 << 4) // P1.4 +# define LED2 (1 << 6) // P1.6 +# define LED3 (1 << 7) // P1.7 +# define LED4 0 # endif #define LED_MASK (LED1|LED2|LED3|LED4) diff --git a/libraries/tests/mbed/portout_portin/main.cpp b/libraries/tests/mbed/portout_portin/main.cpp index 263595d8f7..222c3c414a 100644 --- a/libraries/tests/mbed/portout_portin/main.cpp +++ b/libraries/tests/mbed/portout_portin/main.cpp @@ -63,6 +63,15 @@ #define P2_2 (1 << 25) // p25 #define PORT_2 Port0 +#elif defined(TARGET_MAXWSNENV) +#define P1_1 (1 << 0) +#define P1_2 (1 << 1) +#define PORT_1 Port0 + +#define P2_1 (1 << 0) +#define P2_2 (1 << 1) +#define PORT_2 Port1 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index fd99c96457..1f0b4bba62 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -85,6 +85,15 @@ int main() { printf("Initialize PWM on pin PA_7 with duty cycle: %.2f\n", pwm_1.read()); printf("Initialize PWM on pin PC_7 with duty cycle: %.2f\n", pwm_2.read()); +#elif defined(TARGET_MAXWSNENV) + PwmOut pwm_1(TP2); + PwmOut pwm_2(TP4); + + pwm_1.write(0.75); + pwm_2.write(0.50); + + printf("Initialize PWM on pin TP2 with duty cycle: %.2f\n", pwm_1.read()); + printf("Initialize PWM on pin TP4 with duty cycle: %.2f\n", pwm_2.read()); #else #error This test is not supported on this target. #endif diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp index 78b47c8a79..828a41cb78 100644 --- a/libraries/tests/mbed/pwm_led/pwm.cpp +++ b/libraries/tests/mbed/pwm_led/pwm.cpp @@ -22,6 +22,9 @@ defined (TARGET_LPC824) #define TEST_LED LED_GREEN +#elif defined (TARGET_MAXWSNENV) +#define TEST_LED LED_GREEN + #else #error This test is not supported on this target. #endif diff --git a/libraries/tests/mbed/serial_interrupt_2/main.cpp b/libraries/tests/mbed/serial_interrupt_2/main.cpp index 744116045e..8833c36da7 100644 --- a/libraries/tests/mbed/serial_interrupt_2/main.cpp +++ b/libraries/tests/mbed/serial_interrupt_2/main.cpp @@ -4,6 +4,8 @@ Serial pc(USBTX, USBRX); #if defined(TARGET_LPC4088) Serial uart(P4_22, P4_23); +#elif defined(TARGET_MAXWSNENV) +Serial uart(P0_1, P0_0); #else Serial uart(p9, p10); #endif diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 6f25e0a480..fa26f5da3f 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1111,6 +1111,16 @@ class RZ_A1H(Target): return 2 +### Maxim Integrated ### + +class MAXWSNENV(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['Maxim', 'MAX32610'] + self.macros = ['__SYSTEM_HFX=24000000'] + self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"] + self.default_toolchain = "ARM" # Get a single instance for each target TARGETS = [ @@ -1220,6 +1230,9 @@ TARGETS = [ ### Renesas ### RZ_A1H(), + + ### Maxim Integrated ### + MAXWSNENV(), ] # Map each target name to its unique instance diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index f73c203e7d..a2ccf52cb0 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -39,6 +39,7 @@ Wiring: * TMP102 (I2C): * LPC1*: (SDA=p28 , SCL=p27) * KL25Z: (SDA=PTC9, SCL=PTC8) + * MAXWSNENV: (SDA=TP6, SCL=TP5) * digital_loop (Digital(In|Out|InOut), InterruptIn): * Arduino headers: (D0 <-> D7) @@ -46,12 +47,14 @@ Wiring: * LPC1*: (p5 <-> p25 ) * KL25Z: (PTA5<-> PTC6) * NUCLEO_F103RB: (PC_6 <-> PB_8) + * MAXWSNENV: (TP3 <-> TP4) * port_loop (Port(In|Out|InOut)): * Arduino headers: (D0 <-> D7), (D1 <-> D6) * LPC1*: (p5 <-> p25), (p6 <-> p26) * KL25Z: (PTA5 <-> PTC6), (PTA4 <-> PTC5) * NUCLEO_F103RB: (PC_6 <-> PB_8), (PC_5 <-> PB_9) + * MAXWSNENV: (TP1 <-> TP3), (TP2 <-> TP4) * analog_loop (AnalogIn, AnalogOut): * Arduino headers: (A0 <-> A5) @@ -612,7 +615,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -625,7 +628,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -638,7 +641,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -650,7 +653,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -662,7 +665,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -674,7 +677,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_7", "description": "Timer", @@ -688,7 +691,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -700,7 +703,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], }, { "id": "RTOS_9", "description": "SD File write-read", From 41d37b5f2d4c7f348418965a4f0d5d0480c1d293 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Wed, 8 Apr 2015 14:42:17 +0900 Subject: [PATCH 081/143] [RTOS] Add workaround for internal fault * Add #pragma Ospace to prevent internal fault of armcc 5.04 and 5.05 * Reported by http://developer.mbed.org/questions/5003/Compiling-latest-github-with-ARM-DS5-fai/ --- libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c | 7 +++++++ libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c index 586eabec94..91a3584a33 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c @@ -2066,6 +2066,10 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } +#ifdef __arm__ +#pragma push +#pragma Ospace +#endif // __arm__ /// Get a mail from a queue os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { osEvent ret; @@ -2080,3 +2084,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } +#ifdef __arm__ +#pragma pop +#endif // __arm__ diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c index 19d48caaa4..13a23458af 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c @@ -1862,6 +1862,10 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } +#ifdef __arm__ +#pragma push +#pragma Ospace +#endif // __arm__ /// Get a mail from a queue os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { osEvent ret; @@ -1876,3 +1880,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } +#ifdef __arm__ +#pragma pop +#endif // __arm__ From 331dc0725ddd63483e057688dfd2f70d628f7c29 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Wed, 8 Apr 2015 08:10:42 +0200 Subject: [PATCH 082/143] Squashed commits from #1002, from Marcomissyou. Delta target - add RTC, bugfixes in mbed_overrides and pinnames --- .../TARGET_DELTA_DFCM_NNN40/PinNames.h | 25 +++--- .../TARGET_DELTA_DFCM_NNN40/device.h | 2 +- .../TARGET_DELTA_DFCM_NNN40/mbed_overrides.c | 88 ++++++++++++++++++- .../TARGET_DELTA_DFCM_NNN40/rtc_api.c | 71 +++++++++++++++ workspace_tools/targets.py | 9 -- 5 files changed, 174 insertions(+), 21 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h index c6c288ec62..3db5f772a8 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -62,7 +62,7 @@ typedef enum { p28 = NC, p29 = 29, p30 = 30, - p31 = 31, + p31 = 31, LED1 = p7, LED2 = p13, @@ -96,19 +96,24 @@ typedef enum { A3 = p3, A4 = p4, A5 = p5, - - SWIO = p19, - VERF0 = p0, + + SWIO = p19, + VERF0 = p0, + + // SPI for controlling internal flash, don't use it. + FLASH_SPIMOSI = 15, + FLASH_SPIMISO = 9, + FLASH_SPICS = 28, + FLASH_SPICLK = 11, // Not connected - - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - SPI_PSELMOSI1 = NC, + CTS_PIN_NUMBER= NC, + RTS_PIN_NUMBER= NC, + SPI_PSELMOSI1 = NC, SPI_PSELMISO1 = NC, SPI_PSELSS1 = NC, SPI_PSELSCK1 = NC, - LED3 = NC, - LED4 = NC + LED3 = NC, + LED4 = NC } PinName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h index 21442bcf3a..2b5a0b6b3f 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h @@ -35,7 +35,7 @@ #define DEVICE_CAN 0 -#define DEVICE_RTC 0 +#define DEVICE_RTC 1 #define DEVICE_ETHERNET 0 diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c index 68809a503b..d3d2fe0d64 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -13,9 +13,89 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "cmsis.h" + +#define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */ +#define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */ +#define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */ +#define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */ + +#define CMD_POWER_UP (0xAB) +#define CMD_POWER_DOWN (0xB9) + +void spi_flash_init(void) +{ + NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + NRF_SPI1->ENABLE = 1; + NRF_SPI1->PSELSCK = SPIM1_SCK_PIN; + NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN; + NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN; + //spi.frequency(1000000); + NRF_SPI1->FREQUENCY = 0x10000000; //1MHz + + //spi.format(8,0); + uint32_t config_mode = 0; + config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0 + NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); + //cs = 0; + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_UP); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + //wait_ms(30); + // Deselect the device + //cs = 1; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + +} + +void spi_flash_powerDown(void) +{ + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos); + //spi.write(CMD_POWER_DOWN); + while (!NRF_SPI1->EVENTS_READY == 0) { + } + NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN; + while (!NRF_SPI1->EVENTS_READY == 1) { + } + NRF_SPI1->EVENTS_READY = 0; + NRF_SPI1->RXD; + NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos); + + //wait for sleep + //wait_us(3); +} + void mbed_sdk_init() { // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path @@ -34,4 +114,10 @@ void mbed_sdk_init() while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {// Do nothing. } + + spi_flash_init(); + + //nrf_delay_ms(10); + spi_flash_powerDown(); + } diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c new file mode 100644 index 0000000000..527d308058 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + + +#define LFCLK_FREQUENCY (32768UL) +#define RTC0_COUNTER_PRESCALER ((LFCLK_FREQUENCY/8) - 1) +#define COMPARE_COUNTERTIME (691200UL) //86400 x 8 + + +time_t initTime; + +void rtc_init(void) { + + NVIC_EnableIRQ(RTC0_IRQn); // Enable Interrupt for the RTC in the core. + //NRF_RTC0->TASKS_STOP =1; + NRF_RTC0->PRESCALER = RTC0_COUNTER_PRESCALER; // Set prescaler to a TICK of RTC_FREQUENCY. + NRF_RTC0->CC[0] = COMPARE_COUNTERTIME; // Compare0 after approx COMPARE_COUNTERTIME seconds. + + // Enable COMPARE0 event and COMPARE0 interrupt: + NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk; + NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk; + NRF_RTC0->TASKS_START = 1; +} + +void rtc_free(void) { + // [TODO] +} + +/* + * Little check routine to see if the RTC has been enabled + * + * Clock Control Register + * RTC_CCR[0] : 0 = Disabled, 1 = Enabled + * + */ +int rtc_isenabled(void) { + // [TODO] return(((NRF_RTC0->TASKS_START) & 0x01) != 0); +} + +time_t rtc_read(void) { + + time_t t = initTime; + t += (86400*NRF_RTC0->EVENTS_COMPARE[0]); + t += (int)((NRF_RTC0->COUNTER)/8); + return(t); +} + +void rtc_write(time_t t) { + // Convert the time in to a tm + + // Pause clock, and clear counter register (clears us count) + NRF_RTC0->TASKS_STOP = 1; + + initTime = t; + // Restart clock + NRF_RTC0->TASKS_START = 1; +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 6f25e0a480..b1d85b3659 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1027,15 +1027,6 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False self.macros += self.common_macros - -class DELTA_DFCM_NNN40_OTA(NRF51822): - def __init__(self): - NRF51822.__init__(self) - self.core = "Cortex-M0" - self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] - self.MERGE_SOFT_DEVICE = False - self.macros += self.common_macros - ### ARM ### class ARM_MPS2_M0(Target): From 66c194537bbad39cbb8086362c9d68989fad68c4 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Wed, 8 Apr 2015 15:51:51 -0500 Subject: [PATCH 083/143] [MAXWSNENV] Removed pin alias macros --- .../TARGET_MAXWSNENV/PeripheralAliases.h | 41 ---------- .../{ => TARGET_MAXWSNENV}/PeripheralNames.h | 5 +- .../TARGET_MAXWSNENV/PinAliases.h | 74 ------------------- .../{ => TARGET_MAXWSNENV}/PinNames.h | 45 ++++++++++- 4 files changed, 45 insertions(+), 120 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h rename libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/{ => TARGET_MAXWSNENV}/PeripheralNames.h (97%) delete mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h rename libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/{ => TARGET_MAXWSNENV}/PinNames.h (86%) diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h deleted file mode 100644 index 0fdf2267e3..0000000000 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralAliases.h +++ /dev/null @@ -1,41 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _PERIPHERAL_ALIASES_H -#define _PERIPHERAL_ALIASES_H - -#define STDIO_UART UART_1 -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -#endif /* _PERIPHERAL_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralNames.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralNames.h index 5000bc6451..150331bae2 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralNames.h @@ -42,7 +42,8 @@ extern "C" { typedef enum { UART_0 = MXC_BASE_UART0, - UART_1 = MXC_BASE_UART1 + UART_1 = MXC_BASE_UART1, + STDIO_UART = UART_1 } UARTName; typedef enum { @@ -78,8 +79,6 @@ typedef enum { DAC3 = MXC_BASE_DAC3, } DACName; -#include "PeripheralAliases.h" - #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h deleted file mode 100644 index 95ebfa14d4..0000000000 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinAliases.h +++ /dev/null @@ -1,74 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ - -#ifndef _PIN_ALIASES_H -#define _PIN_ALIASES_H - -#define LED_RED P1_7 -#define LED_GREEN P1_6 -#define LED_BLUE P1_4 - -// mbed original LED naming -#define LED1 LED_RED -#define LED2 LED_GREEN -#define LED3 LED_BLUE -#define LED4 LED_BLUE - -#define LED_OFF 1 -#define LED_ON !LED_OFF - -// Push button -#define SW1 P1_5 - -// USB Pins -#define USBTX P1_3 -#define USBRX P1_2 - -#define I2C_SCL P0_5 -#define I2C_SDA P0_4 - -#define HCI_SCK P2_0 -#define HCI_MOSI P2_1 -#define HCI_MISO P2_2 -#define HCI_CSN P2_3 -#define HCI_IRQ P2_4 -#define HCI_RST P2_5 - -#define TP1 P1_1 -#define TP2 P1_0 -#define TP3 P0_1 -#define TP4 P0_0 -#define TP5 P0_5 -#define TP6 P0_4 - -#endif /* _PIN_ALIASES_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinNames.h similarity index 86% rename from libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinNames.h index b172fc608b..5dab3cc304 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinNames.h @@ -115,7 +115,45 @@ typedef enum { AOUT_BO = (0xF << PORT_SHIFT) | 1, AOUT_CO = (0xF << PORT_SHIFT) | 2, AOUT_DO = (0xF << PORT_SHIFT) | 3, - + + LED_RED = P1_7, + LED_GREEN = P1_6, + LED_BLUE = P1_4, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // Push button + SW1 = P1_5, + + // UART Pins + USBTX = P1_3, + USBRX = P1_2, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + + I2C_SCL = P0_5, + I2C_SDA = P0_4, + + // BTLE Radio HCI + HCI_SCK = P2_0, + HCI_MOSI = P2_1, + HCI_MISO = P2_2, + HCI_CSN = P2_3, + HCI_IRQ = P2_4, + HCI_RST = P2_5, + + // Test points + TP1 = P1_1, + TP2 = P1_0, + TP3 = P0_1, + TP4 = P0_0, + TP5 = P0_5, + TP6 = P0_4, + // Not connected NC = (int)0xFFFFFFFF } PinName; @@ -127,7 +165,10 @@ typedef enum { PullDefault = PullUp } PinMode; -#include "PinAliases.h" +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; #ifdef __cplusplus } From 9fe3632b1728e394be00161791805e88418af4ef Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Thu, 9 Apr 2015 16:06:53 +0900 Subject: [PATCH 084/143] Add LPC11U68 support in Sleep test case - Add LPC11U68 target in MBED_4 test case - Add wakeup pin for LPC11U68 target and set PullUp mode --- libraries/tests/mbed/sleep/main.cpp | 5 +++++ workspace_tools/tests.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/libraries/tests/mbed/sleep/main.cpp b/libraries/tests/mbed/sleep/main.cpp index 77f25a7d19..ef8772da18 100644 --- a/libraries/tests/mbed/sleep/main.cpp +++ b/libraries/tests/mbed/sleep/main.cpp @@ -4,6 +4,8 @@ InterruptIn wkp(P2_10); #elif defined(TARGET_K22F) InterruptIn wkp(D0); +#elif defined(TARGET_LPC11U68) +InterruptIn wkp(P0_16); #else InterruptIn wkp(p14); #endif @@ -13,6 +15,9 @@ void flip() { } int main() { +#if defined(TARGET_LPC11U68) + wkp.mode(PullUp); +#endif wkp.rise(&flip); while (true) { diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index a2ccf52cb0..b52ad4c12e 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -368,7 +368,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "sleep"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "duration": 30, - "mcu": ["LPC1768", "LPC11U24", "LPC4088","LPC4088_DM","NRF51822"] + "mcu": ["LPC1768", "LPC11U24", "LPC4088","LPC4088_DM","NRF51822", "LPC11U68"] }, { "id": "MBED_5", "description": "PWM", From a70bdc5c0086a4fb1176038ab6b342f38541edb9 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 5 Apr 2015 00:11:13 +0200 Subject: [PATCH 085/143] [TARGET_STMF4] reorg hal for DISCO_F407VG Removing pin configuration from analogin_api, analogout_api and pwmout_api (hal function, used by every STM32F4 target) to the target specific files. --- libraries/mbed/common/pinmap_common.c | 20 ++ libraries/mbed/hal/pinmap.h | 2 + .../TARGET_DISCO_F407VG/PeripheralNames.h | 5 +- .../TARGET_DISCO_F407VG/PeripheralPins.c | 180 ++++++++++++------ .../TARGET_DISCO_F407VG/PinNames.h | 35 +--- .../TARGET_DISCO_F407VG/objects.h | 5 +- .../TARGET_STM/TARGET_STM32F4/analogin_api.c | 39 ++-- .../TARGET_STM/TARGET_STM32F4/analogout_api.c | 20 +- .../TARGET_STM/TARGET_STM32F4/pwmout_api.c | 64 ++----- libraries/tests/mbed/analog/main.cpp | 4 + libraries/tests/mbed/pwm/main.cpp | 9 + libraries/tests/mbed/pwm_led/pwm.cpp | 3 + workspace_tools/tests.py | 3 +- workspace_tools/toolchains/gcc.py | 2 +- 14 files changed, 222 insertions(+), 169 deletions(-) diff --git a/libraries/mbed/common/pinmap_common.c b/libraries/mbed/common/pinmap_common.c index 284268c7e7..736e8448fd 100644 --- a/libraries/mbed/common/pinmap_common.c +++ b/libraries/mbed/common/pinmap_common.c @@ -67,3 +67,23 @@ uint32_t pinmap_peripheral(PinName pin, const PinMap* map) { error("pinmap not found for peripheral"); return peripheral; } + +uint32_t pinmap_find_function(PinName pin, const PinMap* map) { + while (map->pin != NC) { + if (map->pin == pin) + return map->function; + map++; + } + return (uint32_t)NC; +} + +uint32_t pinmap_function(PinName pin, const PinMap* map) { + uint32_t function = (uint32_t)NC; + + if (pin == (PinName)NC) + return (uint32_t)NC; + function = pinmap_find_function(pin, map); + if ((uint32_t)NC == function) // no mapping available + error("pinmap not found for function"); + return function; +} \ No newline at end of file diff --git a/libraries/mbed/hal/pinmap.h b/libraries/mbed/hal/pinmap.h index 653d5fe9f3..a9cc92186b 100644 --- a/libraries/mbed/hal/pinmap.h +++ b/libraries/mbed/hal/pinmap.h @@ -32,9 +32,11 @@ void pin_function(PinName pin, int function); void pin_mode (PinName pin, PinMode mode); uint32_t pinmap_peripheral(PinName pin, const PinMap* map); +uint32_t pinmap_function(PinName pin, const PinMap* map); uint32_t pinmap_merge (uint32_t a, uint32_t b); void pinmap_pinout (PinName pin, const PinMap *map); uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map); +uint32_t pinmap_find_function(PinName pin, const PinMap* map); #ifdef __cplusplus } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralNames.h index ec3afd36cf..f2ad3ffd44 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralNames.h @@ -76,9 +76,12 @@ typedef enum { PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE } PWMName; #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c index a9681fff59..b02bd26ee4 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -62,8 +62,8 @@ const PinMap PinMap_ADC[] = { //*** DAC *** const PinMap PinMap_DAC[] = { - {PA_4, DAC_0, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT2 + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 {NC, NC, 0} }; @@ -71,12 +71,12 @@ const PinMap PinMap_DAC[] = { //*** I2C *** const PinMap PinMap_I2C_SDA[] = { - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_0 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_5 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_0 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_5 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, {NC, NC, 0} }; @@ -88,6 +88,7 @@ const PinMap PinMap_I2C_SCL[] = { {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PF_1 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PH_4 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7 , I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {NC, NC, 0} }; @@ -95,69 +96,126 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM3_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM3_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 {NC, NC, 0} }; //*** SERIAL *** const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h index be4907df97..fd47fd86c8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) -#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -219,32 +222,6 @@ typedef enum { PI_14 = 0x8E, PI_15 = 0x8F, - - // Arduino connector namings -/* - A0 = PA_0, - A1 = PA_1, - A2 = PA_4, - A3 = PB_0, - A4 = PC_1, - A5 = PC_0, - D0 = PA_3, - D1 = PA_2, - D2 = PA_10, - D3 = PB_3, - D4 = PB_5, - D5 = PB_4, - D6 = PB_10, - D7 = PA_8, - D8 = PA_9, - D9 = PC_7, - D10 = PB_6, - D11 = PA_7, - D12 = PA_6, - D13 = PA_5, - D14 = PB_9, - D15 = PB_8, -*/ // Generic signals namings LED1 = PD_13, LED2 = PD_12, diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h index 55364553be..4fad3e8a78 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h @@ -57,11 +57,12 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct dac_s { DACName dac; - PinName channel; + uint8_t channel; }; struct serial_s { @@ -99,6 +100,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c index 6750ad2751..a196a7086d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c @@ -45,6 +45,11 @@ void analogin_init(analogin_t *obj, PinName pin) obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); + // Get the functions (adc channel) from the pin and assign it to the object + uint32_t function = pinmap_function(pin, PinMap_ADC); + MBED_ASSERT(function != (uint32_t)NC); + obj->channel = STM_PIN_CHANNEL(function); + // Configure GPIO pinmap_pinout(pin, PinMap_ADC); @@ -87,53 +92,53 @@ static inline uint16_t adc_read(analogin_t *obj) sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; sConfig.Offset = 0; - switch (obj->pin) { - case PA_0: + switch (obj->channel) { + case 0: sConfig.Channel = ADC_CHANNEL_0; break; - case PA_1: + case 1: sConfig.Channel = ADC_CHANNEL_1; break; - case PA_2: + case 2: sConfig.Channel = ADC_CHANNEL_2; break; - case PA_3: + case 3: sConfig.Channel = ADC_CHANNEL_3; break; - case PA_4: + case 4: sConfig.Channel = ADC_CHANNEL_4; break; - case PA_5: + case 5: sConfig.Channel = ADC_CHANNEL_5; break; - case PA_6: + case 6: sConfig.Channel = ADC_CHANNEL_6; break; - case PA_7: + case 7: sConfig.Channel = ADC_CHANNEL_7; break; - case PB_0: + case 8: sConfig.Channel = ADC_CHANNEL_8; break; - case PB_1: + case 9: sConfig.Channel = ADC_CHANNEL_9; break; - case PC_0: + case 10: sConfig.Channel = ADC_CHANNEL_10; break; - case PC_1: + case 11: sConfig.Channel = ADC_CHANNEL_11; break; - case PC_2: + case 12: sConfig.Channel = ADC_CHANNEL_12; break; - case PC_3: + case 13: sConfig.Channel = ADC_CHANNEL_13; break; - case PC_4: + case 14: sConfig.Channel = ADC_CHANNEL_14; break; - case PC_5: + case 15: sConfig.Channel = ADC_CHANNEL_15; break; default: diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c index 6b9ff1311a..0bd8969647 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c @@ -47,6 +47,11 @@ void analogout_init(dac_t *obj, PinName pin) // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + // Get the functions (dac channel) from the pin and assign it to the object + uint32_t function = pinmap_function(pin, PinMap_DAC); + MBED_ASSERT(function != (uint32_t)NC); + // Save the channel for the write and read functions + obj->channel = STM_PIN_CHANNEL(function); if (obj->dac == (DACName)NC) { error("DAC pin mapping failed"); @@ -55,9 +60,6 @@ void analogout_init(dac_t *obj, PinName pin) // Configure GPIO pinmap_pinout(pin, PinMap_DAC); - // Save the channel for the write and read functions - obj->channel = pin; - __GPIOA_CLK_ENABLE(); __DAC_CLK_ENABLE(); @@ -72,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - if (obj->channel == PA_4) { + if (obj->channel == 1) { channel = DAC_CHANNEL_1; } else { channel = DAC_CHANNEL_2; @@ -100,22 +102,22 @@ static inline void dac_write(dac_t *obj, uint16_t value) { HAL_StatusTypeDef status = HAL_ERROR; - if (obj->channel == PA_4) { + if (obj->channel == 1) { status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - } else if (obj->channel == PA_5) { + } else if (obj->channel == 2) { status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); } if ( status != HAL_OK ) { - error("ADC pin mapping failed"); + error("DAC pin mapping failed"); } } static inline int dac_read(dac_t *obj) { - if (obj->channel == PA_4) { + if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); - } else if (obj->channel == PA_5) { + } else if (obj->channel == 2) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); } return 0; /* Just silented warning */ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c index 0165615344..2b90d7fb7b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c @@ -43,6 +43,12 @@ void pwmout_init(pwmout_t* obj, PinName pin) // Get the peripheral name from the pin and assign it to the object obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + // Get the functions (timer channel, (non)inverted) from the pin and assign it to the object + uint32_t function = pinmap_function(pin, PinMap_PWM); + MBED_ASSERT(function != (uint32_t)NC); + obj->channel = STM_PIN_CHANNEL(function); + obj->inverted = STM_PIN_INVERTED(function); + if (obj->pwm == (PWMName)NC) { error("PWM error: pinout mapping failed."); } @@ -52,9 +58,12 @@ void pwmout_init(pwmout_t* obj, PinName pin) if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE(); + if (obj->pwm == PWM_8) __TIM8_CLK_ENABLE(); if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE(); if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE(); if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE(); + if (obj->pwm == PWM_13) __TIM13_CLK_ENABLE(); + if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); // Configure GPIO pinmap_pinout(pin, PinMap_PWM); @@ -97,65 +106,22 @@ void pwmout_write(pwmout_t* obj, float value) sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - switch (obj->pin) { + complementary_channel = obj->inverted; + switch (obj->channel) { - // Channels 1 - case PA_0: - case PA_5: - case PA_6: - case PA_8: - case PA_15: - case PB_4: - case PB_6: - case PC_6: + case 1: channel = TIM_CHANNEL_1; break; - // Channels 1N - case PA_7: - case PB_13: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - - // Channels 2 - case PA_1: - case PA_9: - case PB_3: - case PB_5: - case PB_7: - case PC_7: + case 2: channel = TIM_CHANNEL_2; break; - // Channels 2N - case PB_0: - case PB_14: - channel = TIM_CHANNEL_2; - complementary_channel = 1; - break; - - // Channels 3 - case PA_2: - case PA_10: - case PB_8: - case PB_10: - case PC_8: + case 3: channel = TIM_CHANNEL_3; break; - // Channels 3N - case PB_1: - case PB_15: - channel = TIM_CHANNEL_3; - complementary_channel = 1; - break; - - // Channels 4 - case PA_3: - case PA_11: - case PB_9: - case PC_9: + case 4: channel = TIM_CHANNEL_4; break; diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 4be5fbf57a..7354ec025d 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -37,6 +37,10 @@ AnalogOut out(D12); //D12 is P0_12, the DAC output pin AnalogIn in(A0); AnalogOut out(A2); // DAC output +#elif defined(TARGET_DISCO_F407VG) +AnalogIn in(PC_5); +AnalogOut out(PA_4); + #else AnalogIn in(p17); AnalogOut out(p18); diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index 1f0b4bba62..27884678c8 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -94,6 +94,15 @@ int main() { printf("Initialize PWM on pin TP2 with duty cycle: %.2f\n", pwm_1.read()); printf("Initialize PWM on pin TP4 with duty cycle: %.2f\n", pwm_2.read()); +#elif defined(TARGET_DISCO_F407VG) + PwmOut pwm_1(PD_12); + PwmOut pwm_2(PD_13); + + pwm_1.write(0.75); + pwm_2.write(0.50); + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", pwm_1.read()); + printf("Initialize PWM on pin PD_13 with duty cycle: %.2f\n", pwm_2.read()); #else #error This test is not supported on this target. #endif diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp index 828a41cb78..c30dfc4fbd 100644 --- a/libraries/tests/mbed/pwm_led/pwm.cpp +++ b/libraries/tests/mbed/pwm_led/pwm.cpp @@ -25,6 +25,9 @@ #elif defined (TARGET_MAXWSNENV) #define TEST_LED LED_GREEN +#elif defined (TARGET_DISCO_F407VG) +#define TEST_LED LED1 + #else #error This test is not supported on this target. #endif diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index b52ad4c12e..33fc8640b6 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -138,7 +138,8 @@ TESTS = [ "peripherals": ["analog_loop"], "mcu": ["LPC1768", "LPC2368", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", - "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE"] + "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", + "DISCO_F407VG"] }, { "id": "MBED_A9", "description": "Serial Echo at 115200", diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index fa061220b7..c7d84cdebe 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H"]: + elif target.name in ["RZ_A1H", "DISCO_F407VG"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") From 22de60432abb3459ec0757915ec95705bcf56a1e Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 5 Apr 2015 01:08:23 +0200 Subject: [PATCH 086/143] [TARGET_STMF4] reorg hal for NUCLEO_F411RE same changes but for NUCLEO_F411RE as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG --- .../TARGET_NUCLEO_F411RE/PeripheralPins.c | 112 +++++++++--------- .../TARGET_NUCLEO_F411RE/PinNames.h | 3 + .../TARGET_NUCLEO_F411RE/objects.h | 3 + .../TARGET_STM/TARGET_STM32F4/pwmout_api.c | 6 + libraries/tests/mbed/pwm/main.cpp | 10 +- workspace_tools/tests.py | 2 +- workspace_tools/toolchains/gcc.py | 2 +- 7 files changed, 77 insertions(+), 61 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c index 1b6f1c0071..f1f50db2bd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -83,48 +83,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h index 6c82cf53b7..60718d7a8d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h index 2fbfffd863..d8b93568f7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h @@ -57,6 +57,7 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct serial_s { @@ -94,6 +95,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c index 2b90d7fb7b..767ec1297c 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c @@ -58,12 +58,18 @@ void pwmout_init(pwmout_t* obj, PinName pin) if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE(); +#if defined(TIM8_BASE) if (obj->pwm == PWM_8) __TIM8_CLK_ENABLE(); +#endif if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE(); if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE(); if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE(); +#if defined(TIM13_BASE) if (obj->pwm == PWM_13) __TIM13_CLK_ENABLE(); +#endif +#if defined(TIM14_BASE) if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); +#endif // Configure GPIO pinmap_pinout(pin, PinMap_PWM); diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index 27884678c8..702701c9eb 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -24,7 +24,7 @@ int main() { pwm.write(value); float result = floor(pwm.read() * 100 + 0.5) / 100; // round it to 0.xx - printf("%.2f\n", result); + printf("Initialize PWM on pin D9 with duty cycle: %.2f\n", result); notify_completion(result == value ? true : false); @@ -98,11 +98,15 @@ int main() { PwmOut pwm_1(PD_12); PwmOut pwm_2(PD_13); - pwm_1.write(0.75); + pwm_1.write(value); pwm_2.write(0.50); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx - printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", pwm_1.read()); + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); printf("Initialize PWM on pin PD_13 with duty cycle: %.2f\n", pwm_2.read()); + + notify_completion(result == value ? true : false); #else #error This test is not supported on this target. #endif diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 33fc8640b6..0ca65fa7bb 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -139,7 +139,7 @@ TESTS = [ "mcu": ["LPC1768", "LPC2368", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", - "DISCO_F407VG"] + "NUCLEO_F411RE","DISCO_F407VG"] }, { "id": "MBED_A9", "description": "Serial Echo at 115200", diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index c7d84cdebe..1f77809fcb 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H", "DISCO_F407VG"]: + elif target.name in ["RZ_A1H", "DISCO_F407VG", "NUCLEO_F411RE"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") From 34cfbedd6c9fe63a3aef43d03be3077901526936 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 5 Apr 2015 02:27:34 +0200 Subject: [PATCH 087/143] [TARGET_STMF4] reorg hal for DISCO_F429ZI same changes but for DISCO_F429ZI as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG --- .../TARGET_DISCO_F429ZI/PeripheralNames.h | 4 +- .../TARGET_DISCO_F429ZI/PeripheralPins.c | 186 +++++++++--------- .../TARGET_DISCO_F429ZI/PinNames.h | 4 + .../TARGET_DISCO_F429ZI/objects.h | 5 +- libraries/tests/mbed/analog/main.cpp | 4 + libraries/tests/mbed/pwm/main.cpp | 10 + workspace_tools/toolchains/gcc.py | 2 +- 7 files changed, 119 insertions(+), 96 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h index 9e31110885..0eaf47885e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h @@ -86,7 +86,9 @@ typedef enum { PWM_8 = (int)TIM8_BASE, PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE } PWMName; #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c index 2a7cf2a046..ee1dc97de0 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c @@ -39,30 +39,30 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 - {PF_3, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN9 - {PF_4, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN14 - {PF_5, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN15 - {PF_6, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 - {PF_8, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN6 - {PF_9, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN7 - {PF_10,ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN8 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 {NC, NC, 0} }; @@ -70,8 +70,8 @@ const PinMap PinMap_ADC[] = { //*** DAC *** const PinMap PinMap_DAC[] = { - {PA_4, DAC_0, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT2 + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 0, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT2 {NC, NC, 0} }; @@ -104,80 +104,80 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PA_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1N - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 -// {PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 -// {PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_15, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 -// {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 -// {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 -// {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PD_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PD_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 - {PD_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 + {PD_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_5, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PE_6, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PE_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PH_13, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1N - {PH_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N - {PH_15, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3N + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PI_2, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH4 - {PI_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1 - {PI_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2 - {PI_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h index d95d1a1cc9..7f4ff307f1 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h @@ -38,9 +38,13 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h index 82dcfc6868..f0b6d09b21 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h @@ -57,11 +57,12 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct dac_s { DACName dac; - PinName channel; + uint8_t channel; }; struct serial_s { @@ -99,6 +100,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 7354ec025d..c1b782d15b 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -41,6 +41,10 @@ AnalogOut out(A2); // DAC output AnalogIn in(PC_5); AnalogOut out(PA_4); +#elif defined(TARGET_DISCO_F429ZI) +AnalogIn in(PC_3); +AnalogOut out(PA_5); + #else AnalogIn in(p17); AnalogOut out(p18); diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index 702701c9eb..1836c12963 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -106,6 +106,16 @@ int main() { printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); printf("Initialize PWM on pin PD_13 with duty cycle: %.2f\n", pwm_2.read()); + notify_completion(result == value ? true : false); +#elif defined(TARGET_DISCO_F429ZI) + PwmOut pwm_1(PA_0); + + pwm_1.write(value); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + notify_completion(result == value ? true : false); #else #error This test is not supported on this target. diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index 1f77809fcb..4099cd463c 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H", "DISCO_F407VG", "NUCLEO_F411RE"]: + elif target.name in ["RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") From 879d971289ecdac4c35b2c276983f04366808dca Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 01:49:39 +0200 Subject: [PATCH 088/143] [TARGET_STMF4] reorg hal for NUCLEO_F401RE same changes but for NUCLEO_F401RE as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG --- .../TARGET_NUCLEO_F401RE/PeripheralPins.c | 112 +++++++++--------- .../TARGET_NUCLEO_F401RE/PinNames.h | 4 + .../TARGET_NUCLEO_F401RE/objects.h | 3 + workspace_tools/toolchains/gcc.py | 2 +- 4 files changed, 64 insertions(+), 57 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c index fe5dd323c5..2b164d7c1e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -81,48 +81,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h index 6c82cf53b7..c97b280041 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h @@ -38,9 +38,13 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h index 2fbfffd863..d8b93568f7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h @@ -57,6 +57,7 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct serial_s { @@ -94,6 +95,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index 4099cd463c..d8896a433c 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE"]: + elif target.name in ["RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F411RE"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") From 84c48c0f0b5d834148af6836607b3aca149d8951 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 15:50:25 +0200 Subject: [PATCH 089/143] [TARGET_STMF4] reorg hal for ARCH_MAX same changes but for ARCH_MAX as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG one bugfix for DISCO_F429 - wrong DAC channel numbers --- .../TARGET_ARCH_MAX/PeripheralNames.h | 5 +- .../TARGET_ARCH_MAX/PeripheralPins.c | 116 +++++++++--------- .../TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h | 3 + .../TARGET_STM32F4/TARGET_ARCH_MAX/objects.h | 5 +- .../TARGET_DISCO_F429ZI/PeripheralPins.c | 4 +- .../TARGET_DISCO_F429ZI/PinNames.h | 1 - libraries/tests/mbed/analog/main.cpp | 4 + .../tests/mbed/digitalin_digitalout/main.cpp | 3 +- libraries/tests/mbed/digitalinout/main.cpp | 3 +- libraries/tests/mbed/interruptin/main.cpp | 3 +- workspace_tools/toolchains/gcc.py | 2 +- 11 files changed, 82 insertions(+), 67 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralNames.h index fcf3e46345..5e743f5d56 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralNames.h @@ -76,9 +76,12 @@ typedef enum { PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE } PWMName; #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralPins.c index a9681fff59..0257dbe1be 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -62,8 +62,8 @@ const PinMap PinMap_ADC[] = { //*** DAC *** const PinMap PinMap_DAC[] = { - {PA_4, DAC_0, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT2 + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 {NC, NC, 0} }; @@ -95,48 +95,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h index 8158e678d4..7905be583d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h index 55364553be..4fad3e8a78 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h @@ -57,11 +57,12 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct dac_s { DACName dac; - PinName channel; + uint8_t channel; }; struct serial_s { @@ -99,6 +100,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c index ee1dc97de0..3b8ac54545 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c @@ -70,8 +70,8 @@ const PinMap PinMap_ADC[] = { //*** DAC *** const PinMap PinMap_DAC[] = { - {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 0, 0)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT2 + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h index 7f4ff307f1..e691488dc2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h @@ -42,7 +42,6 @@ extern "C" { #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) #define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) #define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index c1b782d15b..7af87699b0 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -37,6 +37,10 @@ AnalogOut out(D12); //D12 is P0_12, the DAC output pin AnalogIn in(A0); AnalogOut out(A2); // DAC output +#elif defined(TARGET_ARCH_MAX) +AnalogIn in(PA_0); +AnalogOut out(PA_4); + #elif defined(TARGET_DISCO_F407VG) AnalogIn in(PC_5); AnalogOut out(PA_4); diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index bd8894ced2..075744b2a1 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -26,7 +26,8 @@ DigitalIn in(D2); DigitalOut out(PC_7); DigitalIn in(PB_8); -#elif defined(TARGET_DISCO_F407VG) || \ +#elif defined(TARGET_ARCH_MAX) || \ + defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ defined(TARGET_DISCO_F401VC) DigitalOut out(PC_12); diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index d9d91a7364..fafb415474 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -26,7 +26,8 @@ DigitalInOut d2(D7); DigitalInOut d1(PC_7); DigitalInOut d2(PB_8); -#elif defined(TARGET_DISCO_F407VG) || \ +#elif defined(TARGET_ARCH_MAX) || \ + defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ defined(TARGET_DISCO_F401VC) DigitalInOut d1(PC_12); diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index 3a55c00d8d..610c07b07d 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -51,7 +51,8 @@ void in_handler() { #define PIN_IN PB_8 #define PIN_OUT PC_7 -#elif defined(TARGET_DISCO_F407VG) || \ +#elif defined(TARGET_ARCH_MAX) || \ + defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ defined(TARGET_DISCO_F401VC) #define PIN_OUT PC_12 diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index d8896a433c..34e0d61f87 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F411RE"]: + elif target.name in ["RZ_A1H", "ARCH_MAX", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F411RE"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") From 95e9aef2073b9d5871539c0bf54bda173c5d8b1b Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 20:45:46 +0200 Subject: [PATCH 090/143] [TARGET_STMF4] reorg hal for DISCO_F401VC same changes but for DISCO_F401VC as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG --- .../TARGET_DISCO_F401VC/PeripheralPins.c | 112 +++++++++--------- .../TARGET_DISCO_F401VC/PinNames.h | 3 + .../TARGET_DISCO_F401VC/objects.h | 3 + 3 files changed, 62 insertions(+), 56 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c index fe5dd323c5..e8f335d2b6 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -81,48 +81,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h index 0683efed7a..8e0affe222 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h index 2fbfffd863..d8b93568f7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h @@ -57,6 +57,7 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct serial_s { @@ -94,6 +95,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" From 410404d0b65b565c5383af9399eaa51dbf349d1c Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 22:29:05 +0200 Subject: [PATCH 091/143] [TARGET_STMF4] reorg hal for MTS_DRAGONFLY_F411RE same changes but for MTS_DRAGONFLY_F411RE as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG not tested because hardware not yet available --- .../PeripheralPins.c | 112 +++++++++--------- .../TARGET_MTS_DRAGONFLY_F411RE/PinNames.h | 3 + .../TARGET_MTS_DRAGONFLY_F411RE/objects.h | 3 + 3 files changed, 62 insertions(+), 56 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c index 8607395753..428ddc5046 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -83,48 +83,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h index f8a26e7584..57322789e6 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h index 2fbfffd863..d8b93568f7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h @@ -57,6 +57,7 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct serial_s { @@ -94,6 +95,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" From 2f2a885dad4535e1c43ad09ef2a6050c0c2613d5 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 22:49:15 +0200 Subject: [PATCH 092/143] [TARGET_STMF4] reorg hal for MTS_MDOT_F405RG same changes but for MTS_MDOT_F405RG as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG not tested because hardware not yet available --- .../TARGET_MTS_MDOT_F405RG/PeripheralNames.h | 4 +- .../TARGET_MTS_MDOT_F405RG/PeripheralPins.c | 138 +++++++++--------- .../TARGET_MTS_MDOT_F405RG/PinNames.h | 3 + .../TARGET_MTS_MDOT_F405RG/objects.h | 5 +- 4 files changed, 79 insertions(+), 71 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h index 9aa6a0694f..ab02b44b78 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h @@ -81,7 +81,9 @@ typedef enum { PWM_8 = (int)TIM8_BASE, PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE } PWMName; #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c index c0e74d63e4..54c96ffdd7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -62,8 +62,8 @@ const PinMap PinMap_ADC[] = { //*** DAC *** const PinMap PinMap_DAC[] = { - {PA_4, DAC_0, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF)}, // DAC_OUT2 + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 {NC, NC, 0} }; @@ -90,59 +90,59 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_5, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PA_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1N - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 -// {PB_0, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 -// {PB_1, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_14, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_15, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 -// {PC_6, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 -// {PC_7, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 -// {PC_8, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 -// {PC_9, PWM_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8)}, // TIM8_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h index c1b22d0da9..8fe270b12d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h index 82dcfc6868..f0b6d09b21 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h @@ -57,11 +57,12 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct dac_s { DACName dac; - PinName channel; + uint8_t channel; }; struct serial_s { @@ -99,6 +100,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" From 58f4519ca41fdaaf3d5d7ed9d988c97b1302a730 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 23:16:19 +0200 Subject: [PATCH 093/143] [TARGET_STMF4] reorg hal for MTS_MDOT_F411RE same changes but for MTS_MDOT_F411RE as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG not tested because hardware not yet available --- .../TARGET_MTS_MDOT_F411RE/PeripheralPins.c | 112 +++++++++--------- .../TARGET_MTS_MDOT_F411RE/PinNames.h | 3 + .../TARGET_MTS_MDOT_F411RE/objects.h | 3 + 3 files changed, 62 insertions(+), 56 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c index 1b6f1c0071..4d2118949d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c @@ -39,22 +39,22 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 {NC, NC, 0} }; @@ -83,48 +83,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h index fda0a86b8f..976952fedd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h index 2fbfffd863..d8b93568f7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h @@ -57,6 +57,7 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct serial_s { @@ -94,6 +95,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" From b25f943d5ff036254d0fb01d204166c56434646a Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 23:44:03 +0200 Subject: [PATCH 094/143] [TARGET_STMF4] reorg hal for UBLOX_C029 same changes but for UBLOX_C029 as in commit [TARGET_STMF4] reorg hal for DISCO_F407VG not tested because hardware not yet available --- .../TARGET_UBLOX_C029/PeripheralNames.h | 5 +- .../TARGET_UBLOX_C029/PeripheralPins.c | 128 +++++++++--------- .../TARGET_UBLOX_C029/PinNames.h | 5 + .../TARGET_UBLOX_C029/objects.h | 5 +- 4 files changed, 77 insertions(+), 66 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h index 47f03095d0..e0934553db 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h @@ -82,9 +82,12 @@ typedef enum { PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE } PWMName; #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c index 63720ea40b..c6a2e4079b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c @@ -39,31 +39,31 @@ //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {PF_6, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 - {PF_8, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN6 - {PF_9, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN7 - {PF_10,ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN8 - {PF_3, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN9 - {PF_4, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN14 - {PF_5, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN15 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 {NC, NC, 0} }; @@ -83,48 +83,48 @@ const PinMap PinMap_I2C_SCL[] = { // TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {NC, NC, 0} }; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h index 1e946564b8..ec006da5bb 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -38,9 +38,12 @@ extern "C" { // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM #define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -177,6 +180,8 @@ typedef enum { D14 = PF_0, // SDA D15 = PF_1, // SCL // Internal + LED1 = PE_0, // Red + LED2 = PB_6, // Green / shared with SW1 LED_RED = PE_0, // Red LED_GRE = PB_6, // Green / shared with SW1 LED_BLU = PB_8, // Blue diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h index 82dcfc6868..f0b6d09b21 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h @@ -57,11 +57,12 @@ struct port_s { struct analogin_s { ADCName adc; PinName pin; + uint8_t channel; }; struct dac_s { DACName dac; - PinName channel; + uint8_t channel; }; struct serial_s { @@ -99,6 +100,8 @@ struct pwmout_s { PinName pin; uint32_t period; uint32_t pulse; + uint8_t channel; + uint8_t inverted; }; #include "gpio_object.h" From dce050a915c764edc70ecf14b92efb97f48e6c39 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Mon, 6 Apr 2015 23:48:00 +0200 Subject: [PATCH 095/143] [TARGET_STMF4] reorg hal some test extensions --- libraries/tests/mbed/pwm/main.cpp | 40 +++++++++++++++++++++++++++++++ workspace_tools/tests.py | 2 +- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index 1836c12963..99bb908b24 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -116,6 +116,46 @@ int main() { printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + notify_completion(result == value ? true : false); +#elif defined(TARGET_MTS_MDOT_F405RG) + PwmOut pwm_1(PA_0); + + pwm_1.write(value); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + + notify_completion(result == value ? true : false); +#elif defined(TARGET_MTS_DRAGONFLY_F411RE) + PwmOut pwm_1(PA_0); + + pwm_1.write(value); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + + notify_completion(result == value ? true : false); +#elif defined(TARGET_MTS_MDOT_F411RE) + PwmOut pwm_1(PA_0); + + pwm_1.write(value); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + + notify_completion(result == value ? true : false); +#elif defined(TARGET_UBLOX_C029) + PwmOut pwm_1(PA_0); + + pwm_1.write(value); + + float result = floor(pwm_1.read() * 100 + 0.5) / 100; // round it to 0.xx + + printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); + notify_completion(result == value ? true : false); #else #error This test is not supported on this target. diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 0ca65fa7bb..34f9d0c7d8 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -139,7 +139,7 @@ TESTS = [ "mcu": ["LPC1768", "LPC2368", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", - "NUCLEO_F411RE","DISCO_F407VG"] + "NUCLEO_F411RE","DISCO_F407VG","ARCH_MAX"] }, { "id": "MBED_A9", "description": "Serial Echo at 115200", From de73e4574aca8e535a2efa83344918bb331856b8 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Thu, 9 Apr 2015 15:35:56 -0500 Subject: [PATCH 096/143] [MAXWSNENV] Fixing comments in startup file for ARM compiler. --- .../TOOLCHAIN_ARM_STD/startup_MAX32610.s | 191 +++++++++--------- 1 file changed, 95 insertions(+), 96 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s index 933e7871ce..e3c52cae9d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s @@ -1,35 +1,34 @@ -/******************************************************************************* - * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* - */ +;******************************************************************************* +; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* __initial_sp EQU 0x20008000 ; Top of RAM @@ -44,71 +43,71 @@ __initial_sp EQU 0x20008000 ; Top of RAM EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp /* Top of Stack */ - DCD Reset_Handler /* Reset Handler */ - DCD NMI_Handler /* NMI Handler */ - DCD HardFault_Handler /* Hard Fault Handler */ - DCD DefaultIRQ_Handler /* MPU Fault Handler */ - DCD DefaultIRQ_Handler /* Bus Fault Handler */ - DCD DefaultIRQ_Handler /* Usage Fault Handler */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD 0 /* Reserved */ - DCD DefaultIRQ_Handler /* SVCall Handler */ - DCD DebugMon_Handler /* Debug Monitor Handler */ - DCD 0 /* Reserved */ - DCD DefaultIRQ_Handler /* PendSV Handler */ - DCD SysTick_IRQHandler /* SysTick Handler */ +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD DefaultIRQ_Handler ; MPU Fault Handler + DCD DefaultIRQ_Handler ; Bus Fault Handler + DCD DefaultIRQ_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DefaultIRQ_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD DefaultIRQ_Handler ; PendSV Handler + DCD SysTick_IRQHandler ; SysTick Handler - /* Maxim 32610 Externals interrupts */ - DCD UART0_IRQHandler /* 16: 1 UART0 */ - DCD UART1_IRQHandler /* 17: 2 UART1 */ - DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ - DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ - DCD USB_IRQHandler /* 20: 5 USB */ - DCD PMU_IRQHandler /* 21: 6 DMA */ - DCD AFE_IRQHandler /* 22: 7 AFE */ - DCD MAA_IRQHandler /* 23: 8 MAA */ - DCD AES_IRQHandler /* 24: 9 AES */ - DCD SPI0_IRQHandler /* 25:10 SPI0 */ - DCD SPI1_IRQHandler /* 26:11 SPI1 */ - DCD SPI2_IRQHandler /* 27:12 SPI2 */ - DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ - DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ - DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ - DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ - DCD RSVD0_IRQHandler /* 32:17 RSVD */ - DCD RSVD1_IRQHandler /* 33:18 RSVD */ - DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ - DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ - DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ - DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ - DCD ADC_IRQHandler /* 38:23 ADC */ - DCD FLC_IRQHandler /* 39:24 Flash Controller */ - DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ - DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ - DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ - DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ - DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ - DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ - DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ - DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ - DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ - DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ - DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ - DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ - DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ - DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ - DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ - DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ - DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ - DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ - DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ - DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ - DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ - DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ - DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + ; Maxim 32610 Externals interrupts + DCD UART0_IRQHandler ; 16: 1 UART0 + DCD UART1_IRQHandler ; 17: 2 UART1 + DCD I2CM0_IRQHandler ; 18: 3 I2C Master 0 + DCD I2CS_IRQHandler ; 19: 4 I2C Slave + DCD USB_IRQHandler ; 20: 5 USB + DCD PMU_IRQHandler ; 21: 6 DMA + DCD AFE_IRQHandler ; 22: 7 AFE + DCD MAA_IRQHandler ; 23: 8 MAA + DCD AES_IRQHandler ; 24: 9 AES + DCD SPI0_IRQHandler ; 25:10 SPI0 + DCD SPI1_IRQHandler ; 26:11 SPI1 + DCD SPI2_IRQHandler ; 27:12 SPI2 + DCD TMR0_IRQHandler ; 28:13 Timer32-0 + DCD TMR1_IRQHandler ; 29:14 Timer32-1 + DCD TMR2_IRQHandler ; 30:15 Timer32-1 + DCD TMR3_IRQHandler ; 31:16 Timer32-2 + DCD RSVD0_IRQHandler ; 32:17 RSVD + DCD RSVD1_IRQHandler ; 33:18 RSVD + DCD DAC0_IRQHandler ; 34:19 DAC0 (12-bit DAC) + DCD DAC1_IRQHandler ; 35:20 DAC1 (12-bit DAC) + DCD DAC2_IRQHandler ; 36:21 DAC2 (8-bit DAC) + DCD DAC3_IRQHandler ; 37:22 DAC3 (8-bit DAC) + DCD ADC_IRQHandler ; 38:23 ADC + DCD FLC_IRQHandler ; 39:24 Flash Controller + DCD PWRMAN_IRQHandler ; 40:25 PWRMAN + DCD CLKMAN_IRQHandler ; 41:26 CLKMAN + DCD RTC0_IRQHandler ; 42:27 RTC INT0 + DCD RTC1_IRQHandler ; 43:28 RTC INT1 + DCD RTC2_IRQHandler ; 44:29 RTC INT2 + DCD RTC3_IRQHandler ; 45:30 RTC INT3 + DCD WDT0_IRQHandler ; 46:31 WATCHDOG0 + DCD WDT0_P_IRQHandler ; 47:32 WATCHDOG0 PRE-WINDOW + DCD WDT1_IRQHandler ; 48:33 WATCHDOG1 + DCD WDT1_P_IRQHandler ; 49:34 WATCHDOG1 PRE-WINDOW + DCD GPIO_P0_IRQHandler ; 50:35 GPIO Port 0 + DCD GPIO_P1_IRQHandler ; 51:36 GPIO Port 1 + DCD GPIO_P2_IRQHandler ; 52:37 GPIO Port 2 + DCD GPIO_P3_IRQHandler ; 53:38 GPIO Port 3 + DCD GPIO_P4_IRQHandler ; 54:39 GPIO Port 4 + DCD GPIO_P5_IRQHandler ; 55:40 GPIO Port 5 + DCD GPIO_P6_IRQHandler ; 56:41 GPIO Port 6 + DCD GPIO_P7_IRQHandler ; 57:42 GPIO Port 7 + DCD TMR16_0_IRQHandler ; 58:43 Timer16-s0 + DCD TMR16_1_IRQHandler ; 59:44 Timer16-s1 + DCD TMR16_2_IRQHandler ; 60:45 Timer16-s2 + DCD TMR16_3_IRQHandler ; 61:46 Timer16-s3 + DCD I2CM1_IRQHandler ; 62:47 I2C Master 1 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors From f211a680b460d3407ab3e5289a55760cda5cf039 Mon Sep 17 00:00:00 2001 From: Jun-Ru Chang Date: Fri, 10 Apr 2015 10:38:52 +0800 Subject: [PATCH 097/143] [RTOS] fix compilation warning pragma push/pop/Ospace are only supported by ARM compiler. Change predefined marco from __arm__ to __CC_ARM. Warning messages are shown as below. [Warning] rt_CMSIS.c@1867: 1866:0: warning: ignoring #pragma push [-Wunknown-pragmas] ignoring #pragma Ospace [-Wunknown-pragmas] [Warning] rt_CMSIS.c@1884: 1866:0: warning: ignoring #pragma push [-Wunknown-pragmas] ignoring #pragma pop [-Wunknown-pragmas] Change-Id: Ife657b710d694449b30dc4b3150cd49c883fc080 Signed-off-by: Jun-Ru Chang --- libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c | 4 ++-- libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c index 91a3584a33..8b7b1fad4e 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c @@ -2066,7 +2066,7 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } -#ifdef __arm__ +#ifdef __CC_ARM #pragma push #pragma Ospace #endif // __arm__ @@ -2084,6 +2084,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } -#ifdef __arm__ +#ifdef __CC_ARM #pragma pop #endif // __arm__ diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c index 13a23458af..3c05b4ed34 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c @@ -1862,7 +1862,7 @@ osStatus osMailPut (osMailQId queue_id, void *mail) { return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); } -#ifdef __arm__ +#ifdef __CC_ARM #pragma push #pragma Ospace #endif // __arm__ @@ -1880,6 +1880,6 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { return ret; } -#ifdef __arm__ +#ifdef __CC_ARM #pragma pop #endif // __arm__ From e54b32015d2413f502ddeb63f22871b24e415ad3 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 10 Apr 2015 18:11:16 -0500 Subject: [PATCH 098/143] Add GCC_CR to LPC824, fixes LPCXpresso exporter --- workspace_tools/build_release.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 9025434860..09ca8f3ebb 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -33,7 +33,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('LPC2368', ('ARM', 'GCC_ARM')), ('LPC812', ('uARM','IAR')), - ('LPC824', ('uARM', 'IAR')), + ('LPC824', ('uARM', 'IAR', 'GCC_CR')), ('SSCI824', ('uARM',)), ('LPC1347', ('ARM','IAR')), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), From 1793b6a80a27dcd7ec9b8c8c67469b654e98ccee Mon Sep 17 00:00:00 2001 From: julbouln Date: Sat, 11 Apr 2015 11:17:40 +0200 Subject: [PATCH 099/143] USBMIDI: Add SysEx support --- libraries/USBDevice/USBMIDI/MIDIMessage.h | 19 ++++- libraries/USBDevice/USBMIDI/USBMIDI.cpp | 90 +++++++++++++++++++++-- libraries/USBDevice/USBMIDI/USBMIDI.h | 5 +- 3 files changed, 104 insertions(+), 10 deletions(-) diff --git a/libraries/USBDevice/USBMIDI/MIDIMessage.h b/libraries/USBDevice/USBMIDI/MIDIMessage.h index 90f695039a..c0be0f869b 100644 --- a/libraries/USBDevice/USBMIDI/MIDIMessage.h +++ b/libraries/USBDevice/USBMIDI/MIDIMessage.h @@ -21,6 +21,8 @@ #include "mbed.h" +#define MAX_MIDI_MESSAGE_SIZE 256 // Max message size. SysEx can be up to 65536 but 256 should be fine for most usage + // MIDI Message Format // // [ msg(4) | channel(4) ] [ 0 | n(7) ] [ 0 | m(7) ] @@ -49,6 +51,16 @@ public: data[i] = buf[i]; } + // New constructor, buf is a true MIDI message (not USBMidi message) and buf_len true message length. + MIDIMessage(uint8_t *buf, int buf_len) { + length=buf_len+1; + // first byte keeped for retro-compatibility + data[0]=0; + + for (int i = 0; i < buf_len; i++) + data[i+1] = buf[i]; + } + // create messages /** Create a NoteOff message @@ -174,7 +186,8 @@ public: ProgramChangeType, ChannelAftertouchType, PitchWheelType, - AllNotesOffType + AllNotesOffType, + SysExType }; /** Read the message type @@ -196,6 +209,7 @@ public: case 0xC: return ProgramChangeType; case 0xD: return ChannelAftertouchType; case 0xE: return PitchWheelType; + case 0xF: return SysExType; default: return ErrorType; } } @@ -245,7 +259,8 @@ public: return p - 8192; // 0 - 16383, 8192 is center } - uint8_t data[4]; + uint8_t data[MAX_MIDI_MESSAGE_SIZE+1]; + uint8_t length=4; }; #endif diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/libraries/USBDevice/USBMIDI/USBMIDI.cpp index 048ab728bc..042f4f33d3 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.cpp +++ b/libraries/USBDevice/USBMIDI/USBMIDI.cpp @@ -25,8 +25,41 @@ USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_relea USBDevice::connect(); } +// write plain MIDIMessage that will be converted to USBMidi event packet void USBMIDI::write(MIDIMessage m) { - USBDevice::write(EPBULK_IN, m.data, 4, MAX_PACKET_SIZE_EPBULK); + // first byte keeped for retro-compatibility + for(int p=1; p < m.length; p+=3) { + uint8_t buf[4]; + // Midi message to USBMidi event packet + buf[0]=m.data[p] >> 4; + // SysEx + if(buf[0] == 0xF) { + if(p < m.length-1) { + // SysEx start or continue + buf[0]=0x4; + } else { + switch(m.length - p) { + case 1: + // SysEx end with one byte + buf[0]=0x5; + break; + case 2: + // SysEx end with two bytes + buf[0]=0x6; + break; + case 3: + // SysEx end with three bytes + buf[0]=0x7; + break; + } + } + } + buf[1]=m.data[p]; + buf[2]=m.data[p+1]; + buf[3]=m.data[p+2]; + + USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK); + } } @@ -34,16 +67,61 @@ void USBMIDI::attach(void (*fptr)(MIDIMessage)) { midi_evt = fptr; } - bool USBMIDI::EPBULK_OUT_callback() { uint8_t buf[64]; uint32_t len; readEP(EPBULK_OUT, buf, &len, 64); if (midi_evt != NULL) { - for (uint32_t i=0; i Date: Sat, 11 Apr 2015 11:22:29 +0200 Subject: [PATCH 100/143] USBMIDI: SysEx message create helper --- libraries/USBDevice/USBMIDI/MIDIMessage.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/libraries/USBDevice/USBMIDI/MIDIMessage.h b/libraries/USBDevice/USBMIDI/MIDIMessage.h index c0be0f869b..d1a2bc58e7 100644 --- a/libraries/USBDevice/USBMIDI/MIDIMessage.h +++ b/libraries/USBDevice/USBMIDI/MIDIMessage.h @@ -174,6 +174,16 @@ public: return ControlChange(123, 0, channel); } + /** Create a SysEx message + * @param data SysEx data (including 0xF0 .. 0xF7) + * @param len SysEx data length + * @returns A MIDIMessage + */ + static MIDIMessage SysEx(uint8_t *data, int len) { + MIDIMessage msg=MIDIMessage(data,len); + return msg; + } + // decode messages /** MIDI Message Types */ From d8049d58323c44f901e7361c787819f658137464 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Mon, 13 Apr 2015 17:13:02 +0900 Subject: [PATCH 101/143] [LPC824, SSCI824] Add GCC_ARM exporter support * Correct interrupt vector table for GCC_ARM startup * Add GCC_ARM build target for SSCI824 * Add GCC_ARM exporter template files * export_test has been passed * autometed test has been passed --- .../TOOLCHAIN_GCC_ARM/startup_LPC824.s | 28 ++- .../TOOLCHAIN_GCC_ARM/LPC824.ld | 152 ++++++++++++ .../TOOLCHAIN_GCC_ARM/startup_LPC824.s | 228 ++++++++++++++++++ workspace_tools/build_release.py | 4 +- workspace_tools/export/gcc_arm_lpc824.tmpl | 77 ++++++ workspace_tools/export/gcc_arm_ssci824.tmpl | 77 ++++++ workspace_tools/export/gccarm.py | 2 + workspace_tools/export_test.py | 6 +- workspace_tools/targets.py | 2 +- 9 files changed, 568 insertions(+), 8 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s create mode 100644 workspace_tools/export/gcc_arm_lpc824.tmpl create mode 100644 workspace_tools/export/gcc_arm_ssci824.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s index cb4f0b092e..c4273d680b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s @@ -98,16 +98,28 @@ __isr_vector: /* LPC824 interrupts */ .long SPI0_IRQHandler // SPI0 controller .long SPI1_IRQHandler // SPI1 controller + .long 0 // Reserved .long UART0_IRQHandler // UART0 .long UART1_IRQHandler // UART1 .long UART2_IRQHandler // UART2 - .long I2C_IRQHandler // I2C controller + .long 0 // Reserved + .long I2C1_IRQHandler // I2C ch1 controller + .long I2C0_IRQHandler // I2C ch0 controller .long SCT_IRQHandler // Smart Counter Timer .long MRT_IRQHandler // Multi-Rate Timer .long CMP_IRQHandler // Comparator .long WDT_IRQHandler // PIO1 (0:11) .long BOD_IRQHandler // Brown Out Detect + .long Flash_IRQHandler // Flash interrupt .long WKT_IRQHandler // Wakeup timer + .long ADC_SEQA_IRQHandler // ADC sequence A completion + .long ADC_SEQB_IRQHandler // ADC sequence B completion + .long ADC_THCMP_IRQHandler // ADC threshold compare + .long ADC_OVR_IRQHandler // ADC overrun + .long DMA_IRQHandler // DMA interrupt + .long I2C2_IRQHandler // I2C2 controller + .long I2C3_IRQHandler // I2C3 controller + .long 0 // Reserved .long PININT0_IRQHandler // PIO INT0 .long PININT1_IRQHandler // PIO INT1 .long PININT2_IRQHandler // PIO INT2 @@ -181,18 +193,28 @@ Reset_Handler: .weak \handler_name .set \handler_name, Default_Handler .endm + def_irq_default_handler SPI0_IRQHandler def_irq_default_handler SPI1_IRQHandler def_irq_default_handler UART0_IRQHandler def_irq_default_handler UART1_IRQHandler def_irq_default_handler UART2_IRQHandler - def_irq_default_handler I2C_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler I2C1_IRQHandler + def_irq_default_handler I2C2_IRQHandler + def_irq_default_handler I2C3_IRQHandler def_irq_default_handler SCT_IRQHandler def_irq_default_handler MRT_IRQHandler def_irq_default_handler CMP_IRQHandler def_irq_default_handler WDT_IRQHandler def_irq_default_handler BOD_IRQHandler + def_irq_default_handler Flash_IRQHandler def_irq_default_handler WKT_IRQHandler + def_irq_default_handler ADC_SEQA_IRQHandler + def_irq_default_handler ADC_SEQB_IRQHandler + def_irq_default_handler ADC_THCMP_IRQHandler + def_irq_default_handler ADC_OVR_IRQHandler + def_irq_default_handler DMA_IRQHandler def_irq_default_handler PININT0_IRQHandler def_irq_default_handler PININT1_IRQHandler def_irq_default_handler PININT2_IRQHandler @@ -200,7 +222,7 @@ Reset_Handler: def_irq_default_handler PININT4_IRQHandler def_irq_default_handler PININT5_IRQHandler def_irq_default_handler PININT6_IRQHandler - def_irq_default_handler PININT7_IRQHandler + def_irq_default_handler PININT7_IRQHandler .end diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld new file mode 100644 index 0000000000..be901736a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld @@ -0,0 +1,152 @@ +/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* Define each memory region */ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */ + RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */ + + +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text.Reset_Handler) + *(.text.SystemInit) + . = 0x200; + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s new file mode 100644 index 0000000000..c4273d680b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s @@ -0,0 +1,228 @@ +/* File: startup_ARMCM0.S + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.2 + * Date: 15 Nov 2011 + * + * Copyright (c) 2011, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv6-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x80 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x80 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + +/* LPC824 interrupts */ + .long SPI0_IRQHandler // SPI0 controller + .long SPI1_IRQHandler // SPI1 controller + .long 0 // Reserved + .long UART0_IRQHandler // UART0 + .long UART1_IRQHandler // UART1 + .long UART2_IRQHandler // UART2 + .long 0 // Reserved + .long I2C1_IRQHandler // I2C ch1 controller + .long I2C0_IRQHandler // I2C ch0 controller + .long SCT_IRQHandler // Smart Counter Timer + .long MRT_IRQHandler // Multi-Rate Timer + .long CMP_IRQHandler // Comparator + .long WDT_IRQHandler // PIO1 (0:11) + .long BOD_IRQHandler // Brown Out Detect + .long Flash_IRQHandler // Flash interrupt + .long WKT_IRQHandler // Wakeup timer + .long ADC_SEQA_IRQHandler // ADC sequence A completion + .long ADC_SEQB_IRQHandler // ADC sequence B completion + .long ADC_THCMP_IRQHandler // ADC threshold compare + .long ADC_OVR_IRQHandler // ADC overrun + .long DMA_IRQHandler // DMA interrupt + .long I2C2_IRQHandler // I2C2 controller + .long I2C3_IRQHandler // I2C3 controller + .long 0 // Reserved + .long PININT0_IRQHandler // PIO INT0 + .long PININT1_IRQHandler // PIO INT1 + .long PININT2_IRQHandler // PIO INT2 + .long PININT3_IRQHandler // PIO INT3 + .long PININT4_IRQHandler // PIO INT4 + .long PININT5_IRQHandler // PIO INT5 + .long PININT6_IRQHandler // PIO INT6 + .long PININT7_IRQHandler // PIO INT7 + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler SPI0_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler UART0_IRQHandler + def_irq_default_handler UART1_IRQHandler + def_irq_default_handler UART2_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler I2C1_IRQHandler + def_irq_default_handler I2C2_IRQHandler + def_irq_default_handler I2C3_IRQHandler + def_irq_default_handler SCT_IRQHandler + def_irq_default_handler MRT_IRQHandler + def_irq_default_handler CMP_IRQHandler + def_irq_default_handler WDT_IRQHandler + def_irq_default_handler BOD_IRQHandler + def_irq_default_handler Flash_IRQHandler + def_irq_default_handler WKT_IRQHandler + def_irq_default_handler ADC_SEQA_IRQHandler + def_irq_default_handler ADC_SEQB_IRQHandler + def_irq_default_handler ADC_THCMP_IRQHandler + def_irq_default_handler ADC_OVR_IRQHandler + def_irq_default_handler DMA_IRQHandler + def_irq_default_handler PININT0_IRQHandler + def_irq_default_handler PININT1_IRQHandler + def_irq_default_handler PININT2_IRQHandler + def_irq_default_handler PININT3_IRQHandler + def_irq_default_handler PININT4_IRQHandler + def_irq_default_handler PININT5_IRQHandler + def_irq_default_handler PININT6_IRQHandler + def_irq_default_handler PININT7_IRQHandler + + .end + diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 09ca8f3ebb..156a43021c 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -33,8 +33,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('LPC2368', ('ARM', 'GCC_ARM')), ('LPC812', ('uARM','IAR')), - ('LPC824', ('uARM', 'IAR', 'GCC_CR')), - ('SSCI824', ('uARM',)), + ('LPC824', ('uARM', 'GCC_ARM', 'IAR', 'GCC_CR')), + ('SSCI824', ('uARM','GCC_ARM')), ('LPC1347', ('ARM','IAR')), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC4088_DM', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), diff --git a/workspace_tools/export/gcc_arm_lpc824.tmpl b/workspace_tools/export/gcc_arm_lpc824.tmpl new file mode 100644 index 0000000000..6fffb9c742 --- /dev/null +++ b/workspace_tools/export/gcc_arm_lpc824.tmpl @@ -0,0 +1,77 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m0plus -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + @echo "" + @echo "*****" + @echo "***** You must modify vector checksum value in *.bin and *.hex files." + @echo "*****" + @echo "" + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gcc_arm_ssci824.tmpl b/workspace_tools/export/gcc_arm_ssci824.tmpl new file mode 100644 index 0000000000..6fffb9c742 --- /dev/null +++ b/workspace_tools/export/gcc_arm_ssci824.tmpl @@ -0,0 +1,77 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m0plus -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + @echo "" + @echo "*****" + @echo "***** You must modify vector checksum value in *.bin and *.hex files." + @echo "*****" + @echo "" + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 563158c495..3d0be4668f 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -40,6 +40,8 @@ class GccArm(Exporter): 'LPC11U35_401', 'LPC11U35_501', 'LPC11U37H_401', + 'LPC824', + 'SSCI824', 'STM32F407', 'DISCO_F100RB', 'DISCO_F051R8', diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index 021ad9c458..0f18fe7a79 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -156,6 +156,8 @@ if __name__ == '__main__': ('gcc_arm', 'LPC11U35_501'), ('gcc_arm', 'LPCCAPPUCCINO'), ('gcc_arm', 'LPC2368'), + ('gcc_arm', 'LPC824'), + ('gcc_arm', 'SSCI824'), ('gcc_arm', 'STM32F407'), ('gcc_arm', 'DISCO_F100RB'), @@ -194,8 +196,8 @@ if __name__ == '__main__': ('iar', 'MTS_MDOT_F405RG'), ('iar', 'MTS_MDOT_F411RE'), - - (None, None), + # Removed following item to avoid script error + #(None, None), ]: print '\n=== Exporting to "%s::%s" ===' % (toolchain, target) test_export(toolchain, target) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index facd822090..d3abcc4235 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -280,7 +280,7 @@ class SSCI824(LPCTarget): LPCTarget.__init__(self) self.core = "Cortex-M0+" self.extra_labels = ['NXP', 'LPC82X'] - self.supported_toolchains = ["uARM"] + self.supported_toolchains = ["uARM", "GCC_ARM"] self.default_toolchain = "uARM" self.is_disk_virtual = True From b8da610a78ee6fa0b39cf95de1380115b82f9db1 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 13 Apr 2015 16:13:52 +0200 Subject: [PATCH 102/143] Tools - build_release - return 1 if any build fails --- workspace_tools/build_release.py | 1 + 1 file changed, 1 insertion(+) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 09ca8f3ebb..f14575f8ee 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -126,3 +126,4 @@ if __name__ == '__main__': if failures: print "\n\nBuild failures:" print "\n".join([" * %s" % f for f in failures]) + sys.exit(1) From d65e7bfe3d2a2108722db1d7a79559d4ce779a2c Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Fri, 10 Apr 2015 08:36:24 -0500 Subject: [PATCH 103/143] Added copying of library files. --- workspace_tools/build_api.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 5e2c854045..9a4bf4e7f0 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -234,7 +234,7 @@ def build_mbed_libs(target, toolchain_name, options=None, verbose=False, clean=F # Target specific sources HAL_SRC = join(MBED_TARGETS_PATH, "hal") hal_implementation = toolchain.scan_resources(HAL_SRC) - toolchain.copy_files(hal_implementation.headers + hal_implementation.hex_files, BUILD_TARGET, HAL_SRC) + toolchain.copy_files(hal_implementation.headers + hal_implementation.hex_files + hal_implementation.libraries, BUILD_TARGET, HAL_SRC) incdirs = toolchain.scan_resources(BUILD_TARGET).inc_dirs objects = toolchain.compile_sources(hal_implementation, TMP_PATH, [MBED_LIBRARIES] + incdirs) From dc5fca2e21df28fa6b6f89f184a2e6b6464dc0f9 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 20 Mar 2015 11:17:53 -0500 Subject: [PATCH 104/143] added toolchain filter to build_release --- workspace_tools/build_release.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index f14575f8ee..0e85403bbb 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -98,6 +98,9 @@ if __name__ == '__main__': default=1, help="Number of concurrent jobs (default 1). Use 0 for auto based on host machine's number of CPUs") parser.add_option("-v", "--verbose", action="store_true", dest="verbose", default=False, help="Verbose diagnostic output") + parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma") + + options, args = parser.parse_args() start = time() failures = [] @@ -107,6 +110,12 @@ if __name__ == '__main__': toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),) else: toolchains = toolchain_list + + if options.toolchains: + print "Only building using the following toolchains: %s" % (options.toolchains) + toolchainSet = set(toolchains) + toolchains = toolchainSet and set((options.toolchains).split(',')) + for toolchain in toolchains: id = "%s::%s" % (target_name, toolchain) try: From f1c235b1d8baaa3fdd0d8d44e6d1fe6c0a8fd6af Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 27 Mar 2015 16:56:14 -0500 Subject: [PATCH 105/143] Added Jenkins build reporting option --- workspace_tools/build_release.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 0e85403bbb..49de1c1d9c 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -100,11 +100,14 @@ if __name__ == '__main__': default=False, help="Verbose diagnostic output") parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma") + parser.add_option("", "--report-jenkins", dest="report_jenkins_file", help="Output the build results to an xml file that is readable by Jenkins") + options, args = parser.parse_args() start = time() failures = [] successes = [] + build_report = [] for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD: if options.official_only: toolchains = (getattr(TARGET_MAP[target_name], 'default_toolchain', 'ARM'),) @@ -116,15 +119,23 @@ if __name__ == '__main__': toolchainSet = set(toolchains) toolchains = toolchainSet and set((options.toolchains).split(',')) + + cur_target_build_report = { "target": target_name, "successes": [], "failures": []} + for toolchain in toolchains: id = "%s::%s" % (target_name, toolchain) try: build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs) successes.append(id) + cur_target_build_report["successes"].append(toolchain) except Exception, e: failures.append(id) + cur_target_build_report["failures"].append(toolchain) print e + if len(toolchains) > 0: + build_report.append(cur_target_build_report) + # Write summary of the builds print "\n\nCompleted in: (%.2f)s" % (time() - start) From 1f6b56d060ff94269bc1839a102a0210e1cc2ed4 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 27 Mar 2015 18:55:50 -0500 Subject: [PATCH 106/143] Moved printing into build_api --- workspace_tools/build_api.py | 33 ++++++++++++++++++++++++++++++++ workspace_tools/build_release.py | 5 +++++ 2 files changed, 38 insertions(+) diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 9a4bf4e7f0..843f775ecc 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -529,3 +529,36 @@ def print_build_results(result_list, build_name): result += "\n".join([" * %s" % f for f in result_list]) result += "\n" return result + +def write_build_report(build_report, filename): + with open(filename, 'w+') as f: + f.write('
    \n') + f.write('\t\n') + + f.write('\t\t\n') + f.write('\t\t\t\n') + + for report in build_report: + f.write('\t\t\n') + + color = "#009933" + + if len(report["failures"]) > 0: + color = "#FF0000" + + target_cell = '\t\t\t\n') + + f.write('\t
    \n') + f.write('\t\t\t\n') + f.write('\t\t\t\n') + f.write('\t\t
    \n' % (report["target"], color) + f.write(target_cell) + + successes_cell = '\t\t\t\n' % ("\n".join(report["successes"])) + f.write(successes_cell) + + failures_cell = '\t\t\t\n' % ("\n".join(report["failures"])) + f.write(failures_cell) + + f.write('\t\t
    \n') + f.write('
    \n') diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 49de1c1d9c..1e132f50d2 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -24,6 +24,7 @@ ROOT = abspath(join(dirname(__file__), "..")) sys.path.insert(0, ROOT) from workspace_tools.build_api import build_mbed_libs +from workspace_tools.build_api import write_build_report from workspace_tools.targets import TARGET_MAP OFFICIAL_MBED_LIBRARY_BUILD = ( @@ -137,6 +138,10 @@ if __name__ == '__main__': build_report.append(cur_target_build_report) # Write summary of the builds + + if options.report_jenkins_file: + write_build_report(build_report, options.report_jenkins_file) + print "\n\nCompleted in: (%.2f)s" % (time() - start) if successes: From 8576f74b3c23ca27edbc9dc47a242901be574c49 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Tue, 31 Mar 2015 17:56:00 -0500 Subject: [PATCH 107/143] Changing Jenkins HTML build output --- workspace_tools/build_api.py | 89 +++++++++++++------ workspace_tools/build_release.py | 10 +-- .../library_build/build_report.html | 19 ++++ .../library_build/build_report_table.html | 10 +++ .../ci_templates/library_build/report.html | 9 ++ 5 files changed, 105 insertions(+), 32 deletions(-) create mode 100644 workspace_tools/ci_templates/library_build/build_report.html create mode 100644 workspace_tools/ci_templates/library_build/build_report_table.html create mode 100644 workspace_tools/ci_templates/library_build/report.html diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 843f775ecc..76875426f4 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -29,6 +29,8 @@ from workspace_tools.paths import MBED_TARGETS_PATH, MBED_LIBRARIES, MBED_API, M from workspace_tools.targets import TARGET_NAMES, TARGET_MAP from workspace_tools.libraries import Library from workspace_tools.toolchains import TOOLCHAIN_CLASSES +from jinja2 import FileSystemLoader +from jinja2.environment import Environment def build_project(src_path, build_path, target, toolchain_name, @@ -531,34 +533,67 @@ def print_build_results(result_list, build_name): return result def write_build_report(build_report, filename): - with open(filename, 'w+') as f: - f.write('
    \n') - f.write('\t\n') + build_report_failing = [] + build_report_passing = [] - f.write('\t\t\n') - f.write('\t\t\t\n') + for report in build_report: + if len(report["failing"]) > 0: + build_report_failing.append(report) + else: + build_report_passing.append(report) + + '''build_report_failing = [{ + "target": "K64F", + "passing": [ + { + "toolchain": "GCC_ARM" + }, + { + "toolchain": "ARM" + } + ], + "failing": [ + { + "toolchain": "GCC_CS" + }, + { + "toolchain": "IAR" + } + ] + }, + { + "target": "KL46Z", + "passing": [ + { + "toolchain": "GCC_ARM" + } + ], + "failing": [ + { + "toolchain": "ARM" + }, + { + "toolchain": "IAR" + } + ] + }] - for report in build_report: - f.write('\t\t\n') + build_report_passing = [{ + "target": "LPC1768", + "passing": [ + { + "toolchain": "GCC_ARM" + }, + { + "toolchain": "ARM" + } + ], + "failing": [] + }]''' - color = "#009933" + env = Environment(extensions=['jinja2.ext.with_']) + env.loader = FileSystemLoader('ci_templates/library_build') + template = env.get_template('report.html') - if len(report["failures"]) > 0: - color = "#FF0000" - - target_cell = '\t\t\t\n') - - f.write('\t
    \n') - f.write('\t\t\t\n') - f.write('\t\t\t\n') - f.write('\t\t
    \n' % (report["target"], color) - f.write(target_cell) - - successes_cell = '\t\t\t\n' % ("\n".join(report["successes"])) - f.write(successes_cell) - - failures_cell = '\t\t\t\n' % ("\n".join(report["failures"])) - f.write(failures_cell) - - f.write('\t\t
    \n') - f.write('
    \n') + with open(filename, 'w+') as f: + f.write(template.render(failing_builds=build_report_failing, passing_builds=build_report_passing)) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 1e132f50d2..a74177e37e 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -101,7 +101,7 @@ if __name__ == '__main__': default=False, help="Verbose diagnostic output") parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma") - parser.add_option("", "--report-jenkins", dest="report_jenkins_file", help="Output the build results to an xml file that is readable by Jenkins") + parser.add_option("", "--report-jenkins", dest="report_jenkins_file_name", help="Output the build results to an xml file that is readable by Jenkins") options, args = parser.parse_args() @@ -121,17 +121,17 @@ if __name__ == '__main__': toolchains = toolchainSet and set((options.toolchains).split(',')) - cur_target_build_report = { "target": target_name, "successes": [], "failures": []} + cur_target_build_report = { "target": target_name, "passing": [], "failing": []} for toolchain in toolchains: id = "%s::%s" % (target_name, toolchain) try: build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs) successes.append(id) - cur_target_build_report["successes"].append(toolchain) + cur_target_build_report["passing"].append({ "toolchain": toolchain }) except Exception, e: failures.append(id) - cur_target_build_report["failures"].append(toolchain) + cur_target_build_report["failing"].append({ "toolchain": toolchain }) print e if len(toolchains) > 0: @@ -140,7 +140,7 @@ if __name__ == '__main__': # Write summary of the builds if options.report_jenkins_file: - write_build_report(build_report, options.report_jenkins_file) + write_build_report(build_report, options.report_jenkins_file_name) print "\n\nCompleted in: (%.2f)s" % (time() - start) diff --git a/workspace_tools/ci_templates/library_build/build_report.html b/workspace_tools/ci_templates/library_build/build_report.html new file mode 100644 index 0000000000..b459478e42 --- /dev/null +++ b/workspace_tools/ci_templates/library_build/build_report.html @@ -0,0 +1,19 @@ +
    +

    + {% if report.failing|length > 0 %} + [FAIL] + {% else %} + [OK] + {% endif %} + + {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}}

    +

    Failing

    + {% with build = report.failing %} + {% include 'build_report_table.html' %} + {% endwith %} + +

    Passing

    + {% with build = report.passing %} + {% include 'build_report_table.html' %} + {% endwith %} +
    diff --git a/workspace_tools/ci_templates/library_build/build_report_table.html b/workspace_tools/ci_templates/library_build/build_report_table.html new file mode 100644 index 0000000000..26d87dfb17 --- /dev/null +++ b/workspace_tools/ci_templates/library_build/build_report_table.html @@ -0,0 +1,10 @@ + + + + + {% for run in build %} + + + + {% endfor %} +
    Toolchain
    {{run.toolchain}}
    diff --git a/workspace_tools/ci_templates/library_build/report.html b/workspace_tools/ci_templates/library_build/report.html new file mode 100644 index 0000000000..3fcfd73094 --- /dev/null +++ b/workspace_tools/ci_templates/library_build/report.html @@ -0,0 +1,9 @@ +

    Failing Builds

    +{% for report in failing_builds %} +{% include 'build_report.html' %} +{% endfor %} + +

    Passing Builds

    +{% for report in passing_builds %} +{% include 'build_report.html' %} +{% endfor %} From 4b0926fcdb65cf2d88fcc53736ded7b2c80e06ca Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Mon, 13 Apr 2015 17:04:57 -0500 Subject: [PATCH 108/143] Added report templates --- .../library_build/build_report.html | 37 +++++++------ .../ci_templates/library_build/report.html | 54 +++++++++++++++++++ 2 files changed, 76 insertions(+), 15 deletions(-) diff --git a/workspace_tools/ci_templates/library_build/build_report.html b/workspace_tools/ci_templates/library_build/build_report.html index b459478e42..f3be3f74aa 100644 --- a/workspace_tools/ci_templates/library_build/build_report.html +++ b/workspace_tools/ci_templates/library_build/build_report.html @@ -1,19 +1,26 @@ -     diff --git a/workspace_tools/ci_templates/library_build/report.html b/workspace_tools/ci_templates/library_build/report.html index a42c176cec..e32f30c604 100644 --- a/workspace_tools/ci_templates/library_build/report.html +++ b/workspace_tools/ci_templates/library_build/report.html @@ -1,63 +1,11 @@ -

    Failing Builds

    +

    {{failing_builds|length}} Failing Builds

    {% for report in failing_builds %} -{% include 'build_report.html' %} +{% include 'library_build/build_report.html' %} {% endfor %} -

    Passing Builds

    +

    {{passing_builds|length}} Passing Builds

    {% for report in passing_builds %} -{% include 'build_report.html' %} +{% include 'library_build/build_report.html' %} {% endfor %} - +{% include 'scripts.js' %} diff --git a/workspace_tools/ci_templates/scripts.js b/workspace_tools/ci_templates/scripts.js new file mode 100644 index 0000000000..28c0c59381 --- /dev/null +++ b/workspace_tools/ci_templates/scripts.js @@ -0,0 +1,53 @@ + diff --git a/workspace_tools/ci_templates/tests_build/build_report.html b/workspace_tools/ci_templates/tests_build/build_report.html new file mode 100644 index 0000000000..8b20d188cf --- /dev/null +++ b/workspace_tools/ci_templates/tests_build/build_report.html @@ -0,0 +1,26 @@ +
    +

    + + + {% if report.failing|length > 0 %} + [FAIL] + {% else %} + [PASS] + {% endif %} + + {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}} + +

    + +
    +

    Failing

    + {% with build = report.failing %} + {% include 'tests_build/build_report_table.html' %} + {% endwith %} + +

    Passing

    + {% with build = report.passing %} + {% include 'tests_build/build_report_table.html' %} + {% endwith %} +
    +
    diff --git a/workspace_tools/ci_templates/tests_build/build_report_table.html b/workspace_tools/ci_templates/tests_build/build_report_table.html new file mode 100644 index 0000000000..e7626b3670 --- /dev/null +++ b/workspace_tools/ci_templates/tests_build/build_report_table.html @@ -0,0 +1,12 @@ + + + + + + {% for run in build %} + + + + + {% endfor %} +
    ToolchainProject
    {{run.toolchain}}{{run.project}}
    diff --git a/workspace_tools/ci_templates/tests_build/report.html b/workspace_tools/ci_templates/tests_build/report.html new file mode 100644 index 0000000000..3f262556ef --- /dev/null +++ b/workspace_tools/ci_templates/tests_build/report.html @@ -0,0 +1,11 @@ +

    {{failing_builds|length}} Failing Builds

    +{% for report in failing_builds %} +{% include 'tests_build/build_report.html' %} +{% endfor %} + +

    {{passing_builds|length}} Passing Builds

    +{% for report in passing_builds %} +{% include 'tests_build/build_report.html' %} +{% endfor %} + +{% include 'scripts.js' %} diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index 1b01a1da00..cf51683afc 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -303,10 +303,10 @@ class SingleTestRunner(object): build_report[toolchain] = { "mbed_failure": False, "library_failure": False, - "library_build_successes": [], - "library_build_failures": [], - "test_build_successes": [], - "test_build_failures": [] + "library_build_passing": [], + "library_build_failing": [], + "test_build_passing": [], + "test_build_failing": [] } # print target, toolchain # Test suite properties returned to external tools like CI @@ -404,14 +404,17 @@ class SingleTestRunner(object): verbose=self.opts_verbose, clean=clean_mbed_libs_options, jobs=self.opts_jobs) + + build_report[toolchain]["library_build_passing"].append(lib_id) + except ToolException: print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id)) build_report[toolchain]["library_failure"] = True - build_report[toolchain]["library_build_failures"].append(lib_id) + build_report[toolchain]["library_build_failing"].append(lib_id) #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext continue - build_report[toolchain]["library_build_successes"].append(lib_id) + for test_id in valid_test_map_keys: @@ -437,27 +440,27 @@ class SingleTestRunner(object): project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None try: path = build_project(test.source_dir, - join(build_dir, test_id), - T, - toolchain, - test.dependencies, - options=build_project_options, - clean=clean_project_options, - verbose=self.opts_verbose, - name=project_name, - macros=MACROS, - inc_dirs=INC_DIRS, - jobs=self.opts_jobs) + join(build_dir, test_id), + T, + toolchain, + test.dependencies, + options=build_project_options, + clean=clean_project_options, + verbose=self.opts_verbose, + name=project_name, + macros=MACROS, + inc_dirs=INC_DIRS, + jobs=self.opts_jobs) + build_report[toolchain]["test_build_passing"].append(test_id) + except ToolException: project_name_str = project_name if project_name is not None else test_id print "DIS BE MAH ERRRRR: %s" % (str(ToolException)) print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) - build_report[toolchain]["test_build_failures"].append(test_id) + build_report[toolchain]["test_build_failing"].append(test_id) # return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext continue - build_report[toolchain]["test_build_successes"].append(test_id) - if self.opts_only_build_tests: # With this option we are skipping testing phase continue @@ -542,15 +545,13 @@ class SingleTestRunner(object): build_reports.append({ "target": target, "report": cur_build_report}) q.get() - print build_reports - build_report = [] for target_build_report in build_reports: cur_report = { "target": target_build_report["target"], - "successes": [], - "failures": [] + "passing": [], + "failing": [] } for toolchain in sorted(target_build_report["report"], key=target_build_report["report"].get): @@ -558,21 +559,34 @@ class SingleTestRunner(object): report = target_build_report["report"][toolchain] if report["mbed_failure"]: - cur_report["failures"].append("mbed::%s" % (toolchain)) - elif report["library_failure"]: - for library in report["library_build_failures"]: - cur_report["failures"].append("Library::%s::%s" % (library, toolchain)) + cur_report["failing"].append({ + "toolchain": toolchain, + "project": "mbed library" + }) else: - cur_report["successes"].append("All Libraries::%s" % (toolchain)) + for passing_library in report["library_build_failing"]: + cur_report["failing"].append({ + "toolchain": toolchain, + "project": "Library::%s" % (passing_library) + }) - if len(report["test_build_failures"]) > 0: - for successful_test in report["test_build_successes"]: - cur_report["successes"].append("Test::%s::%s" % (toolchain, successful_test)) + for failing_library in report["library_build_passing"]: + cur_report["passing"].append({ + "toolchain": toolchain, + "project": "Library::%s" % (failing_library) + }) - for failed_test in report["test_build_failures"]: - cur_report["failures"].append("Test::%s::%s" % (toolchain, failed_test)) - else: - cur_report["successes"].append("All Tests::%s" % (toolchain)) + for passing_test in report["test_build_passing"]: + cur_report["passing"].append({ + "toolchain": toolchain, + "project": "Test::%s" % (passing_test) + }) + + for failing_test in report["test_build_failing"]: + cur_report["failing"].append({ + "toolchain": toolchain, + "project": "Test::%s" % (failing_test) + }) build_report.append(cur_report) @@ -1427,7 +1441,7 @@ def singletest_in_cli_mode(single_test): report_exporter.report_to_file(test_summary_ext, single_test.opts_report_junit_file_name, test_suite_properties=test_suite_properties_ext) if single_test.opts_report_jenkins_file_name: # Export build results as Jenkins XML report ti sparate file - write_build_report(build_report, single_test.opts_report_jenkins_file_name) + write_build_report(build_report, 'tests_build/report.html', single_test.opts_report_jenkins_file_name) class TestLogger(): From 01ff0b32b3aec4de66e15548810906c724cd6396 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Wed, 1 Apr 2015 13:55:01 -0500 Subject: [PATCH 111/143] Removed comments --- workspace_tools/build_api.py | 49 ------------------------------------ 1 file changed, 49 deletions(-) diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 40e378ee9d..0acea152cf 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -542,55 +542,6 @@ def write_build_report(build_report, template_filename, filename): else: build_report_passing.append(report) - '''build_report_failing = [{ - "target": "K64F", - "passing": [ - { - "toolchain": "GCC_ARM" - }, - { - "toolchain": "ARM" - } - ], - "failing": [ - { - "toolchain": "GCC_CS" - }, - { - "toolchain": "IAR" - } - ] - }, - { - "target": "KL46Z", - "passing": [ - { - "toolchain": "GCC_ARM" - } - ], - "failing": [ - { - "toolchain": "ARM" - }, - { - "toolchain": "IAR" - } - ] - }] - - build_report_passing = [{ - "target": "LPC1768", - "passing": [ - { - "toolchain": "GCC_ARM" - }, - { - "toolchain": "ARM" - } - ], - "failing": [] - }]''' - env = Environment(extensions=['jinja2.ext.with_']) env.loader = FileSystemLoader('ci_templates') template = env.get_template(template_filename) From c71a082d2074cc4e1cf4596d146fff38066de0fb Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Wed, 8 Apr 2015 11:42:34 -0500 Subject: [PATCH 112/143] Added table styleing --- .../ci_templates/library_build/build_report_table.html | 2 +- .../ci_templates/tests_build/build_report_table.html | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/workspace_tools/ci_templates/library_build/build_report_table.html b/workspace_tools/ci_templates/library_build/build_report_table.html index 26d87dfb17..610f8851e9 100644 --- a/workspace_tools/ci_templates/library_build/build_report_table.html +++ b/workspace_tools/ci_templates/library_build/build_report_table.html @@ -1,4 +1,4 @@ - +
    diff --git a/workspace_tools/ci_templates/tests_build/build_report_table.html b/workspace_tools/ci_templates/tests_build/build_report_table.html index e7626b3670..79d41c1ab8 100644 --- a/workspace_tools/ci_templates/tests_build/build_report_table.html +++ b/workspace_tools/ci_templates/tests_build/build_report_table.html @@ -1,4 +1,4 @@ -
    Toolchain
    +
    From afb331dcff18a22f54b61e44bba61b6b2c824a8b Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Mon, 13 Apr 2015 16:43:10 -0500 Subject: [PATCH 113/143] Fixing arguments --- workspace_tools/build_release.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index a74177e37e..37a8bdcc35 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -139,8 +139,8 @@ if __name__ == '__main__': # Write summary of the builds - if options.report_jenkins_file: - write_build_report(build_report, options.report_jenkins_file_name) + if options.report_jenkins_file_name: + write_build_report(build_report, 'library_build/report.html', options.report_jenkins_file_name) print "\n\nCompleted in: (%.2f)s" % (time() - start) From 2198e68f76d9cfdf86b572faa943cda5b66af6b9 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Tue, 14 Apr 2015 13:09:09 +0200 Subject: [PATCH 114/143] mbed header file - mbed lib revision - 97 --- libraries/mbed/api/mbed.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h index 31d746f1e2..51b044d11e 100644 --- a/libraries/mbed/api/mbed.h +++ b/libraries/mbed/api/mbed.h @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 96 +#define MBED_LIBRARY_VERSION 97 #include "platform.h" From 5ada69b73d5a0554e035112894e2b4ec62433d41 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Thu, 9 Oct 2014 11:54:03 -0500 Subject: [PATCH 115/143] [MAX32600MBED] Adding MAX32600MBED platform. --- libraries/USBDevice/USBDevice/USBEndpoints.h | 2 + .../USBDevice/USBDevice/USBEndpoints_Maxim.h | 90 +++ .../USBDevice/USBDevice/USBHAL_Maxim.cpp | 473 +++++++++++++ .../TOOLCHAIN_ARM_STD/MAX32600.sct | 21 + .../TOOLCHAIN_ARM_STD/startup_MAX32600.s | 255 +++++++ .../TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp | 57 ++ .../TOOLCHAIN_GCC_ARM/max32600.ld | 182 +++++ .../TOOLCHAIN_GCC_ARM/startup_max32600.S | 262 +++++++ .../TOOLCHAIN_IAR/MAX32600.icf | 29 + .../TOOLCHAIN_IAR/startup_MAX32600.s | 383 ++++++++++ .../TARGET_Maxim/TARGET_MAX32600/adc_regs.h | 466 ++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/aes_regs.h | 159 +++++ .../TARGET_Maxim/TARGET_MAX32600/afe_regs.h | 626 ++++++++++++++++ .../TARGET_MAX32600/clkman_regs.h | 493 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/cmsis.h | 40 ++ .../TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c | 65 ++ .../TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32600/crc_regs.h | 89 +++ .../TARGET_Maxim/TARGET_MAX32600/dac_regs.h | 180 +++++ .../TARGET_Maxim/TARGET_MAX32600/flc_regs.h | 210 ++++++ .../TARGET_Maxim/TARGET_MAX32600/gpio_regs.h | 477 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h | 192 +++++ .../TARGET_Maxim/TARGET_MAX32600/icc_regs.h | 96 +++ .../TARGET_Maxim/TARGET_MAX32600/ioman_regs.h | 508 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/lcd_regs.h | 70 ++ .../TARGET_Maxim/TARGET_MAX32600/maa_regs.h | 124 ++++ .../TARGET_Maxim/TARGET_MAX32600/max32600.h | 666 ++++++++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/pmu_regs.h | 111 +++ .../TARGET_Maxim/TARGET_MAX32600/pt_regs.h | 175 +++++ .../TARGET_MAX32600/pwrman_regs.h | 386 ++++++++++ .../TARGET_MAX32600/pwrseq_regs.h | 299 ++++++++ .../TARGET_Maxim/TARGET_MAX32600/rtc_regs.h | 246 +++++++ .../TARGET_Maxim/TARGET_MAX32600/spi_regs.h | 215 ++++++ .../TARGET_MAX32600/system_max32600.c | 144 ++++ .../TARGET_MAX32600/system_max32600.h | 53 ++ .../TARGET_Maxim/TARGET_MAX32600/tmr_regs.h | 146 ++++ .../TARGET_Maxim/TARGET_MAX32600/tpu_regs.h | 108 +++ .../TARGET_Maxim/TARGET_MAX32600/trim_regs.h | 92 +++ .../TARGET_Maxim/TARGET_MAX32600/uart_regs.h | 175 +++++ .../TARGET_Maxim/TARGET_MAX32600/usb_regs.h | 480 +++++++++++++ .../TARGET_Maxim/TARGET_MAX32600/wdt_regs.h | 150 ++++ .../TARGET_MAX32600/PeripheralPins.c | 268 +++++++ .../TARGET_MAX32600/PeripheralPins.h | 65 ++ .../TARGET_Maxim/TARGET_MAX32600/PortNames.h | 55 ++ .../TARGET_MAX32600MBED/PeripheralNames.h | 86 +++ .../TARGET_MAX32600MBED/PinNames.h | 267 +++++++ .../TARGET_MAX32600MBED/low_level_init.c | 88 +++ .../TARGET_MAX32600/analogin_api.c | 147 ++++ .../TARGET_MAX32600/analogout_api.c | 212 ++++++ .../hal/TARGET_Maxim/TARGET_MAX32600/device.h | 72 ++ .../TARGET_Maxim/TARGET_MAX32600/gpio_api.c | 94 +++ .../TARGET_MAX32600/gpio_irq_api.c | 167 +++++ .../TARGET_MAX32600/gpio_object.h | 71 ++ .../TARGET_Maxim/TARGET_MAX32600/i2c_api.c | 405 +++++++++++ .../TARGET_Maxim/TARGET_MAX32600/objects.h | 118 ++++ .../hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c | 105 +++ .../TARGET_Maxim/TARGET_MAX32600/port_api.c | 97 +++ .../TARGET_Maxim/TARGET_MAX32600/pwmout_api.c | 234 ++++++ .../TARGET_Maxim/TARGET_MAX32600/rtc_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32600/serial_api.c | 355 ++++++++++ .../hal/TARGET_Maxim/TARGET_MAX32600/sleep.c | 169 +++++ .../TARGET_Maxim/TARGET_MAX32600/spi_api.c | 190 +++++ .../TARGET_Maxim/TARGET_MAX32600/us_ticker.c | 261 +++++++ .../rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 2 +- .../rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 6 +- libraries/tests/mbed/analog/main.cpp | 4 + .../tests/mbed/digitalin_digitalout/main.cpp | 4 + libraries/tests/mbed/digitalinout/main.cpp | 4 + libraries/tests/mbed/interruptin/main.cpp | 5 +- libraries/tests/mbed/portinout/main.cpp | 9 + libraries/tests/mbed/portout/main.cpp | 27 +- libraries/tests/mbed/portout_portin/main.cpp | 9 + libraries/tests/mbed/pwm/main.cpp | 9 + .../export/gcc_arm_max32600mbed.tmpl | 72 ++ workspace_tools/export/gccarm.py | 1 + workspace_tools/export_test.py | 1 + workspace_tools/targets.py | 10 + workspace_tools/tests.py | 20 +- 78 files changed, 12924 insertions(+), 23 deletions(-) create mode 100644 libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h create mode 100644 libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c create mode 100644 workspace_tools/export/gcc_arm_max32600mbed.tmpl diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index e7e78bf018..48950986ae 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -47,6 +47,8 @@ typedef enum { #include "USBEndpoints_STM32F4.h" #elif defined (TARGET_RZ_A1H) #include "USBEndpoints_RZ_A1H.h" +#elif defined(TARGET_Maxim) +#include "USBEndpoints_Maxim.h" #else #error "Unknown target type" #endif diff --git a/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h b/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h new file mode 100644 index 0000000000..5cd3905c9f --- /dev/null +++ b/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h @@ -0,0 +1,90 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#define NUMBER_OF_LOGICAL_ENDPOINTS (8) +#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2) + +#define DIR_OUT 0x00 +#define DIR_IN 0x01 +#define EP_NUM(ep) (ep >> 1) +#define IN_EP(ep) (ep & DIR_IN) +#define OUT_EP(ep) (!(ep & DIR_IN)) + +/* Define physical endpoint numbers */ + +/* Endpoint No. */ +/* ---------------- */ +#define EP0OUT ((0 << 1) | DIR_OUT) +#define EP0IN ((0 << 1) | DIR_IN) +#define EP1OUT ((1 << 1) | DIR_OUT) +#define EP1IN ((1 << 1) | DIR_IN) +#define EP2OUT ((2 << 1) | DIR_OUT) +#define EP2IN ((2 << 1) | DIR_IN) +#define EP3OUT ((3 << 1) | DIR_OUT) +#define EP3IN ((3 << 1) | DIR_IN) +#define EP4OUT ((4 << 1) | DIR_OUT) +#define EP4IN ((4 << 1) | DIR_IN) +#define EP5OUT ((5 << 1) | DIR_OUT) +#define EP5IN ((5 << 1) | DIR_IN) +#define EP6OUT ((6 << 1) | DIR_OUT) +#define EP6IN ((6 << 1) | DIR_IN) +#define EP7OUT ((7 << 1) | DIR_OUT) +#define EP7IN ((7 << 1) | DIR_IN) + +/* Maximum Packet sizes */ + +#define MAX_PACKET_SIZE_EP0 (64) +#define MAX_PACKET_SIZE_EP1 (64) +#define MAX_PACKET_SIZE_EP2 (64) +#define MAX_PACKET_SIZE_EP3 (64) +#define MAX_PACKET_SIZE_EP4 (64) +#define MAX_PACKET_SIZE_EP5 (64) +#define MAX_PACKET_SIZE_EP6 (64) +#define MAX_PACKET_SIZE_EP7 (64) + +/* Generic endpoints - intended to be portable accross devices */ +/* and be suitable for simple USB devices. */ + +/* Bulk endpoints */ +#define EPBULK_OUT (EP1OUT) +#define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP1_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback +/* Interrupt endpoints */ +#define EPINT_OUT (EP3OUT) +#define EPINT_IN (EP4IN) +#define EPINT_OUT_callback EP3_OUT_callback +#define EPINT_IN_callback EP4_IN_callback + +#define MAX_PACKET_SIZE_EPBULK (64) +#define MAX_PACKET_SIZE_EPINT (64) diff --git a/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp b/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp new file mode 100644 index 0000000000..13e193cd2c --- /dev/null +++ b/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp @@ -0,0 +1,473 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#if defined(TARGET_Maxim) + +#include "USBHAL.h" +#include "usb_regs.h" +#include "clkman_regs.h" + +#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR) + +USBHAL *USBHAL::instance; + +typedef struct { + volatile uint32_t buf0_desc; + volatile uint32_t buf0_address; + volatile uint32_t buf1_desc; + volatile uint32_t buf1_address; +} ep_buffer_t; + +typedef struct { + ep_buffer_t out_buffer; + ep_buffer_t in_buffer; +} ep0_buffer_t; + +typedef struct { + ep0_buffer_t ep0; + ep_buffer_t ep[MXC_USB_NUM_EP - 1]; +} ep_buffer_descriptor_t; + +// Static storage for endpoint buffer descriptor table. Must be 512 byte alligned for DMA. +#ifdef __IAR_SYSTEMS_ICC__ +#pragma data_alignment = 512 +#else +__attribute__ ((aligned (512))) +#endif +ep_buffer_descriptor_t ep_buffer_descriptor; + +// static storage for temporary data buffers. Must be 32 byte alligned. +#ifdef __IAR_SYSTEMS_ICC__ +#pragma data_alignment = 4 +#else +__attribute__ ((aligned (4))) +#endif +static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET]; + +// contorl packet state +static enum { + CTRL_NONE = 0, + CTRL_SETUP, + CTRL_OUT, + CTRL_IN, +} control_state; + +USBHAL::USBHAL(void) +{ + NVIC_DisableIRQ(USB_IRQn); + + // The PLL must be enabled for USB + MBED_ASSERT(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE); + + // Enable the USB clock + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N; + + // reset the device + MXC_USB->cn = 0; + MXC_USB->cn = 1; + MXC_USB->dev_inten = 0; + MXC_USB->dev_cn = 0; + MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST; + MXC_USB->dev_cn = 0; + + // fill in callback arrays + epCallback[EP0OUT] = NULL; + epCallback[EP0IN] = NULL; + epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback; + epCallback[EP1IN ] = &USBHAL::EP1_IN_callback; + epCallback[EP2OUT] = &USBHAL::EP2_OUT_callback; + epCallback[EP2IN ] = &USBHAL::EP2_IN_callback; + epCallback[EP3OUT] = &USBHAL::EP3_OUT_callback; + epCallback[EP3IN ] = &USBHAL::EP3_IN_callback; + epCallback[EP4OUT] = &USBHAL::EP4_OUT_callback; + epCallback[EP4IN ] = &USBHAL::EP4_IN_callback; + epCallback[EP5OUT] = &USBHAL::EP5_OUT_callback; + epCallback[EP5IN ] = &USBHAL::EP5_IN_callback; + epCallback[EP6OUT] = &USBHAL::EP6_OUT_callback; + epCallback[EP6IN ] = &USBHAL::EP6_IN_callback; + epCallback[EP7OUT] = &USBHAL::EP7_OUT_callback; + epCallback[EP7IN ] = &USBHAL::EP7_IN_callback; + + // clear driver state + control_state = CTRL_NONE; + + // set the descriptor location + MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor; + + // attach IRQ handler and enable interrupts + instance = this; + NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr); + NVIC_EnableIRQ(USB_IRQn); +} + +USBHAL::~USBHAL(void) +{ + MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST; + MXC_USB->dev_cn = 0; + MXC_USB->cn = 0; +} + +void USBHAL::connect(void) +{ + // enable interrupts + MXC_USB->dev_inten |= CONNECT_INTS; + + // allow interrupts on ep0 + MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN; + + // pullup enable + MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE); +} + +void USBHAL::disconnect(void) +{ + // disable interrupts + MXC_USB->dev_inten &= ~CONNECT_INTS; + + // disable pullup + MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT; +} + +void USBHAL::configureDevice(void) +{ + // do nothing +} + +void USBHAL::unconfigureDevice(void) +{ + // reset endpoints + for (int i = 0; i < MXC_USB_NUM_EP; i++) { + // Disable endpoint and clear the data toggle + MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR; + MXC_USB->ep[i] |= MXC_F_USB_EP_DT; + } +} + +void USBHAL::setAddress(uint8_t address) +{ + // do nothing +} + +void USBHAL::remoteWakeup(void) +{ + // do nothing +} + +static ep_buffer_t *get_desc(uint8_t endpoint) +{ + uint8_t epnum = EP_NUM(endpoint); + ep_buffer_t *desc; + + if (epnum == 0) { + if (IN_EP(endpoint)) { + desc = &ep_buffer_descriptor.ep0.in_buffer; + } else { + desc = &ep_buffer_descriptor.ep0.out_buffer; + } + } else { + desc = &ep_buffer_descriptor.ep[epnum - 1]; + } + + return desc; +} + +void USBHAL::EP0setup(uint8_t *buffer) +{ + memcpy(buffer, (void*)&MXC_USB->setup0, 8); // setup packet is fixed at 8 bytes +} + +void USBHAL::EP0read(void) +{ + if (control_state == CTRL_IN) { + // This is the status stage. ACK. + MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK; + control_state = CTRL_NONE; + return; + } + + control_state = CTRL_OUT; + + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); +} + +void USBHAL::EP0readStage(void) +{ + // do nothing +} + +uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) +{ + uint32_t size; + + if (MXC_USB->out_owner & 1) { + return 0; + } + + // get the packet length and contents + ep_buffer_t *desc = get_desc(EP0OUT); + size = desc->buf0_desc; + memcpy(buffer, aligned_buffer[0], size); + + return size; +} + +void USBHAL::EP0write(uint8_t *buffer, uint32_t size) +{ + if ((size == 0) && (control_state != CTRL_IN)) { + // This is a status stage ACK. Handle in hardware. + MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK; + control_state = CTRL_NONE; + return; + } + + control_state = CTRL_IN; + + endpointWrite(EP0IN, buffer, size); +} + +void USBHAL::EP0stall(void) +{ + stallEndpoint(0); +} + +EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) +{ + uint8_t epnum = EP_NUM(endpoint); + + if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) { + return EP_INVALID; + } + + if (maximumSize > MXC_USB_MAX_PACKET) { + return EP_INVALID; + } + + uint32_t mask = (1 << epnum); + if (MXC_USB->out_owner & mask) { + return EP_INVALID; + } + + ep_buffer_t *desc = get_desc(endpoint); + desc->buf0_desc = maximumSize; + desc->buf0_address = (uint32_t)aligned_buffer[epnum]; + + MXC_USB->out_owner = mask; + + return EP_PENDING; +} + +EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) +{ + if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) { + return EP_INVALID; + } + + uint32_t mask = (1 << EP_NUM(endpoint)); + if (MXC_USB->out_owner & mask) { + return EP_PENDING; + } + + // get the packet length and contents + ep_buffer_t *desc = get_desc(endpoint); + *bytesRead = desc->buf0_desc; + memcpy(data, aligned_buffer[EP_NUM(endpoint)], *bytesRead); + + return EP_COMPLETED; +} + +EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) +{ + uint8_t epnum = EP_NUM(endpoint); + + if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || OUT_EP(endpoint)) { + return EP_INVALID; + } + + if (size > MXC_USB_MAX_PACKET) { + return EP_INVALID; + } + + uint32_t mask = (1 << epnum); + if (MXC_USB->in_owner & mask) { + return EP_INVALID; + } + + memcpy(aligned_buffer[epnum], data, size); + + ep_buffer_t *desc = get_desc(endpoint); + desc->buf0_desc = size; + desc->buf0_address = (uint32_t)aligned_buffer[epnum]; + + // start the DMA + MXC_USB->in_owner = mask; + + return EP_PENDING; +} + +EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) +{ + uint32_t mask = (1 << EP_NUM(endpoint)); + if (MXC_USB->in_owner & mask) { + return EP_PENDING; + } + + return EP_COMPLETED; +} + +void USBHAL::stallEndpoint(uint8_t endpoint) +{ + uint8_t epnum = EP_NUM(endpoint); + + if (epnum == 0) { + MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL; + } + + MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL; +} + +void USBHAL::unstallEndpoint(uint8_t endpoint) +{ + MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL; +} + +bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) +{ + uint8_t epnum = EP_NUM(endpoint); + uint32_t ep_ctrl; + + if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) { + return false; + } + + if (IN_EP(endpoint)) { + ep_ctrl = (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS); + } else { + ep_ctrl = (MXC_S_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS); + } + + ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN); + + MXC_USB->ep[epnum] = ep_ctrl; + + return true; +} + +bool USBHAL::getEndpointStallState(unsigned char endpoint) +{ + return !!(MXC_USB->ep[endpoint] & MXC_F_USB_EP_STALL); +} + +void USBHAL::_usbisr(void) +{ + instance->usbisr(); +} + +void USBHAL::usbisr(void) +{ + // get and clear irqs + uint32_t irq_flags = MXC_USB->dev_intfl; + MXC_USB->dev_intfl = irq_flags; + + // process only enabled interrupts + irq_flags &= MXC_USB->dev_inten; + + // suspend + if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) { + suspendStateChanged(1); + } + + // bus reset + if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) { + + // reset endpoints + for (int i = 0; i < MXC_USB_NUM_EP; i++) { + // Disable endpoint and clear the data toggle + MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR; + MXC_USB->ep[i] |= MXC_F_USB_EP_DT; + } + + // clear driver state + control_state = CTRL_NONE; + + busReset(); + + // no need to process events after reset + return; + } + + // Setup packet + if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) { + control_state = CTRL_SETUP; + EP0setupCallback(); + } + + // IN packets + if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) { + // get and clear IN irqs + uint32_t in_irqs = MXC_USB->in_int; + MXC_USB->in_int = in_irqs; + + if (in_irqs & 1) { + EP0in(); + } + + for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) { + uint32_t irq_mask = (1 << epnum); + if (in_irqs & irq_mask) { + uint8_t endpoint = (epnum << 1) | DIR_IN; + (instance->*(epCallback[endpoint]))(); + } + } + } + + // OUT packets + if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) { + // get and clear OUT irqs + uint32_t out_irqs = MXC_USB->out_int; + MXC_USB->out_int = out_irqs; + + if (out_irqs & 1) { + EP0out(); + } + + for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) { + uint32_t irq_mask = (1 << epnum); + if (out_irqs & irq_mask) { + uint8_t endpoint = (epnum << 1) | DIR_OUT; + (instance->*(epCallback[endpoint]))(); + } + } + } +} + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct new file mode 100644 index 0000000000..cdc367ab99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct @@ -0,0 +1,21 @@ + +; MAX32600 +; 256KB FLASH (0x40000) @ 0x000000000 +; 2KB RAM (0x8000) @ 0x20000000 + + +; MAX32600: 256KB FLASH (0x40000) + 32KB RAM (0x8000) + +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment + RW_IRAM1 (0x20000000+0x140) (0x8000-0x140) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s new file mode 100644 index 0000000000..02ece3a3cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s @@ -0,0 +1,255 @@ +;******************************************************************************* +; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD DefaultIRQ_Handler ; MPU Fault Handler + DCD DefaultIRQ_Handler ; Bus Fault Handler + DCD DefaultIRQ_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DefaultIRQ_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD DefaultIRQ_Handler ; PendSV Handler + DCD SysTick_IRQHandler ; SysTick Handler + + ; Maxim 32600 Externals interrupts + DCD UART0_IRQHandler ; 16: 1 UART0 + DCD UART1_IRQHandler ; 17: 2 UART1 + DCD I2CM0_IRQHandler ; 18: 3 I2C Master 0 + DCD I2CS_IRQHandler ; 19: 4 I2C Slave + DCD USB_IRQHandler ; 20: 5 USB + DCD PMU_IRQHandler ; 21: 6 DMA + DCD AFE_IRQHandler ; 22: 7 AFE + DCD MAA_IRQHandler ; 23: 8 MAA + DCD AES_IRQHandler ; 24: 9 AES + DCD SPI0_IRQHandler ; 25:10 SPI0 + DCD SPI1_IRQHandler ; 26:11 SPI1 + DCD SPI2_IRQHandler ; 27:12 SPI2 + DCD TMR0_IRQHandler ; 28:13 Timer32-0 + DCD TMR1_IRQHandler ; 29:14 Timer32-1 + DCD TMR2_IRQHandler ; 30:15 Timer32-1 + DCD TMR3_IRQHandler ; 31:16 Timer32-2 + DCD RSVD0_IRQHandler ; 32:17 RSVD + DCD RSVD1_IRQHandler ; 33:18 RSVD + DCD DAC0_IRQHandler ; 34:19 DAC0 (12-bit DAC) + DCD DAC1_IRQHandler ; 35:20 DAC1 (12-bit DAC) + DCD DAC2_IRQHandler ; 36:21 DAC2 (8-bit DAC) + DCD DAC3_IRQHandler ; 37:22 DAC3 (8-bit DAC) + DCD ADC_IRQHandler ; 38:23 ADC + DCD FLC_IRQHandler ; 39:24 Flash Controller + DCD PWRMAN_IRQHandler ; 40:25 PWRMAN + DCD CLKMAN_IRQHandler ; 41:26 CLKMAN + DCD RTC0_IRQHandler ; 42:27 RTC INT0 + DCD RTC1_IRQHandler ; 43:28 RTC INT1 + DCD RTC2_IRQHandler ; 44:29 RTC INT2 + DCD RTC3_IRQHandler ; 45:30 RTC INT3 + DCD WDT0_IRQHandler ; 46:31 WATCHDOG0 + DCD WDT0_P_IRQHandler ; 47:32 WATCHDOG0 PRE-WINDOW + DCD WDT1_IRQHandler ; 48:33 WATCHDOG1 + DCD WDT1_P_IRQHandler ; 49:34 WATCHDOG1 PRE-WINDOW + DCD GPIO_P0_IRQHandler ; 50:35 GPIO Port 0 + DCD GPIO_P1_IRQHandler ; 51:36 GPIO Port 1 + DCD GPIO_P2_IRQHandler ; 52:37 GPIO Port 2 + DCD GPIO_P3_IRQHandler ; 53:38 GPIO Port 3 + DCD GPIO_P4_IRQHandler ; 54:39 GPIO Port 4 + DCD GPIO_P5_IRQHandler ; 55:40 GPIO Port 5 + DCD GPIO_P6_IRQHandler ; 56:41 GPIO Port 6 + DCD GPIO_P7_IRQHandler ; 57:42 GPIO Port 7 + DCD TMR16_0_IRQHandler ; 58:43 Timer16-s0 + DCD TMR16_1_IRQHandler ; 59:44 Timer16-s1 + DCD TMR16_2_IRQHandler ; 60:45 Timer16-s2 + DCD TMR16_3_IRQHandler ; 61:46 Timer16-s3 + DCD I2CM1_IRQHandler ; 62:47 I2C Master 1 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Handler + ENDP + +DefaultIRQ_Handler PROC + EXPORT DefaultIRQ_Handler [WEAK] + B DefaultIRQ_Handler + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B DebugMon_Handler + ENDP + +SysTick_IRQHandler PROC + EXPORT SysTick_IRQHandler [WEAK] + B SysTick_IRQHandler + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2CM0_IRQHandler [WEAK] + EXPORT I2CS_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT AFE_IRQHandler [WEAK] + EXPORT MAA_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT RSVD0_IRQHandler [WEAK] + EXPORT RSVD1_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FLC_IRQHandler [WEAK] + EXPORT PWRMAN_IRQHandler [WEAK] + EXPORT CLKMAN_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT RTC2_IRQHandler [WEAK] + EXPORT RTC3_IRQHandler [WEAK] + EXPORT WDT0_IRQHandler [WEAK] + EXPORT WDT0_P_IRQHandler [WEAK] + EXPORT WDT1_IRQHandler [WEAK] + EXPORT WDT1_P_IRQHandler [WEAK] + EXPORT GPIO_P0_IRQHandler [WEAK] + EXPORT GPIO_P1_IRQHandler [WEAK] + EXPORT GPIO_P2_IRQHandler [WEAK] + EXPORT GPIO_P3_IRQHandler [WEAK] + EXPORT GPIO_P4_IRQHandler [WEAK] + EXPORT GPIO_P5_IRQHandler [WEAK] + EXPORT GPIO_P6_IRQHandler [WEAK] + EXPORT GPIO_P7_IRQHandler [WEAK] + EXPORT TMR16_0_IRQHandler [WEAK] + EXPORT TMR16_1_IRQHandler [WEAK] + EXPORT TMR16_2_IRQHandler [WEAK] + EXPORT TMR16_3_IRQHandler [WEAK] + EXPORT I2CM1_IRQHandler [WEAK] + +UART0_IRQHandler +UART1_IRQHandler +I2CM0_IRQHandler +I2CS_IRQHandler +USB_IRQHandler +PMU_IRQHandler +AFE_IRQHandler +MAA_IRQHandler +AES_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +RSVD0_IRQHandler +RSVD1_IRQHandler +DAC0_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +DAC3_IRQHandler +ADC_IRQHandler +FLC_IRQHandler +PWRMAN_IRQHandler +CLKMAN_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +GPIO_P7_IRQHandler +TMR16_0_IRQHandler +TMR16_1_IRQHandler +TMR16_2_IRQHandler +TMR16_3_IRQHandler +I2CM1_IRQHandler + + B . + ENDP + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..90d1391ba3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld new file mode 100644 index 0000000000..2d5c3112e5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld @@ -0,0 +1,182 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +/****************************************************************************** + * + * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S new file mode 100644 index 0000000000..cda4da904b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + .syntax unified + .arch armv7-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Externals interrupts */ + .long UART0_IRQHandler /* 16: 1 UART0 */ + .long UART1_IRQHandler /* 17: 2 UART1 */ + .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + .long I2CS_IRQHandler /* 19: 4 I2C Slave */ + .long USB_IRQHandler /* 20: 5 USB */ + .long PMU_IRQHandler /* 21: 6 DMA */ + .long AFE_IRQHandler /* 22: 7 AFE */ + .long MAA_IRQHandler /* 23: 8 MAA */ + .long AES_IRQHandler /* 24: 9 AES */ + .long SPI0_IRQHandler /* 25:10 SPI0 */ + .long SPI1_IRQHandler /* 26:11 SPI1 */ + .long SPI2_IRQHandler /* 27:12 SPI2 */ + .long TMR0_IRQHandler /* 28:13 Timer32-0 */ + .long TMR1_IRQHandler /* 29:14 Timer32-1 */ + .long TMR2_IRQHandler /* 30:15 Timer32-1 */ + .long TMR3_IRQHandler /* 31:16 Timer32-2 */ + .long RSVD0_IRQHandler /* 32:17 RSVD */ + .long RSVD1_IRQHandler /* 33:18 RSVD */ + .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + .long ADC_IRQHandler /* 38:23 ADC */ + .long FLC_IRQHandler /* 39:24 Flash Controller */ + .long PWRMAN_IRQHandler /* 40:25 PWRMAN */ + .long CLKMAN_IRQHandler /* 41:26 CLKMAN */ + .long RTC0_IRQHandler /* 42:27 RTC INT0 */ + .long RTC1_IRQHandler /* 43:28 RTC INT1 */ + .long RTC2_IRQHandler /* 44:29 RTC INT2 */ + .long RTC3_IRQHandler /* 45:30 RTC INT3 */ + .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */ + def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */ + def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */ + def_irq_default_handler USB_IRQHandler /* 20: 5 USB */ + def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */ + def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */ + def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */ + def_irq_default_handler AES_IRQHandler /* 24: 9 AES */ + def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */ + def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */ + def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */ + def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */ + def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */ + def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */ + def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */ + def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */ + def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */ + def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */ + def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */ + def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */ + def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */ + def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */ + def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */ + def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */ + def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */ + def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf new file mode 100644 index 0000000000..2b90dc973d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf @@ -0,0 +1,29 @@ +/* [ROM] */ +define symbol __intvec_start__ = 0x0; +define symbol __region_ROM_start__ = 0x0; +define symbol __region_ROM_end__ = 0x0003FFFF; + +/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */ +define symbol __NVIC_start__ = 0x00000000; +define symbol __NVIC_end__ = 0x00000140; /* to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000000; +define symbol __region_RAM_end__ = 0x20007FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x800; +define symbol __size_heap__ = 0x800; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s new file mode 100644 index 0000000000..740a9150b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s @@ -0,0 +1,383 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) /* Top of Stack */ + DCD Reset_Handler /* Reset Handler */ + DCD NMI_Handler /* NMI Handler */ + DCD HardFault_Handler /* Hard Fault Handler */ + DCD DefaultIRQ_Handler /* MPU Fault Handler */ + DCD DefaultIRQ_Handler /* Bus Fault Handler */ + DCD DefaultIRQ_Handler /* Usage Fault Handler */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* SVCall Handler */ + DCD DebugMon_Handler /* Debug Monitor Handler */ + DCD 0 /* Reserved */ + DCD DefaultIRQ_Handler /* PendSV Handler */ + DCD SysTick_IRQHandler /* SysTick Handler */ + + /* Maxim 32600 Externals interrupts */ + DCD UART0_IRQHandler /* 16: 1 UART0 */ + DCD UART1_IRQHandler /* 17: 2 UART1 */ + DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */ + DCD I2CS_IRQHandler /* 19: 4 I2C Slave */ + DCD USB_IRQHandler /* 20: 5 USB */ + DCD PMU_IRQHandler /* 21: 6 DMA */ + DCD AFE_IRQHandler /* 22: 7 AFE */ + DCD MAA_IRQHandler /* 23: 8 MAA */ + DCD AES_IRQHandler /* 24: 9 AES */ + DCD SPI0_IRQHandler /* 25:10 SPI0 */ + DCD SPI1_IRQHandler /* 26:11 SPI1 */ + DCD SPI2_IRQHandler /* 27:12 SPI2 */ + DCD TMR0_IRQHandler /* 28:13 Timer32-0 */ + DCD TMR1_IRQHandler /* 29:14 Timer32-1 */ + DCD TMR2_IRQHandler /* 30:15 Timer32-1 */ + DCD TMR3_IRQHandler /* 31:16 Timer32-2 */ + DCD RSVD0_IRQHandler /* 32:17 RSVD */ + DCD RSVD1_IRQHandler /* 33:18 RSVD */ + DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */ + DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */ + DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */ + DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */ + DCD ADC_IRQHandler /* 38:23 ADC */ + DCD FLC_IRQHandler /* 39:24 Flash Controller */ + DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */ + DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */ + DCD RTC0_IRQHandler /* 42:27 RTC INT0 */ + DCD RTC1_IRQHandler /* 43:28 RTC INT1 */ + DCD RTC2_IRQHandler /* 44:29 RTC INT2 */ + DCD RTC3_IRQHandler /* 45:30 RTC INT3 */ + DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */ + DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */ + DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */ + DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */ + DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */ + DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */ + DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */ + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK DefaultIRQ_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DefaultIRQ_Handler + B DefaultIRQ_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK SysTick_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_IRQHandler + B SysTick_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK I2CM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM0_IRQHandler + B I2CM0_IRQHandler + + PUBWEAK I2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CS_IRQHandler + B I2CS_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PMU_IRQHandler + B PMU_IRQHandler + + PUBWEAK AFE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AFE_IRQHandler + B AFE_IRQHandler + + PUBWEAK MAA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MAA_IRQHandler + B MAA_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK RSVD0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD0_IRQHandler + B RSVD0_IRQHandler + + PUBWEAK RSVD1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSVD1_IRQHandler + B RSVD1_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FLC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK PWRMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWRMAN_IRQHandler + B PWRMAN_IRQHandler + + PUBWEAK CLKMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLKMAN_IRQHandler + B CLKMAN_IRQHandler + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B RTC0_IRQHandler + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B RTC1_IRQHandler + + PUBWEAK RTC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC2_IRQHandler + B RTC2_IRQHandler + + PUBWEAK RTC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC3_IRQHandler + B RTC3_IRQHandler + + PUBWEAK WDT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK WDT0_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_P_IRQHandler + B WDT0_P_IRQHandler + + PUBWEAK WDT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_IRQHandler + B WDT1_IRQHandler + + PUBWEAK WDT1_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_P_IRQHandler + B WDT1_P_IRQHandler + + PUBWEAK GPIO_P0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P0_IRQHandler + B GPIO_P0_IRQHandler + + PUBWEAK GPIO_P1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P1_IRQHandler + B GPIO_P1_IRQHandler + + PUBWEAK GPIO_P2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P2_IRQHandler + B GPIO_P2_IRQHandler + + PUBWEAK GPIO_P3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P3_IRQHandler + B GPIO_P3_IRQHandler + + PUBWEAK GPIO_P4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P4_IRQHandler + B GPIO_P4_IRQHandler + + PUBWEAK GPIO_P5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P5_IRQHandler + B GPIO_P5_IRQHandler + + PUBWEAK GPIO_P6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P6_IRQHandler + B GPIO_P6_IRQHandler + + PUBWEAK GPIO_P7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P7_IRQHandler + B GPIO_P7_IRQHandler + + PUBWEAK TMR16_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_0_IRQHandler + B TMR16_0_IRQHandler + + PUBWEAK TMR16_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_1_IRQHandler + B TMR16_1_IRQHandler + + PUBWEAK TMR16_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_2_IRQHandler + B TMR16_2_IRQHandler + + PUBWEAK TMR16_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_3_IRQHandler + B TMR16_3_IRQHandler + + PUBWEAK I2CM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM1_IRQHandler + B I2CM1_IRQHandler + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h new file mode 100644 index 0000000000..4e4d5299c2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h @@ -0,0 +1,466 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ADC_REGS_H +#define _MXC_ADC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file adc_regs.h + * @addtogroup adc ADC + * @{ + */ + +/** + * @brief Defines ADC Modes. + */ +typedef enum { + /** Single Mode Full Rate */ + MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0, + /** Single Mode Low Power */ + MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1, + /** Continuous Mode Full Rate */ + MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2, + /** Continuous Mode Low Power */ + MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3, + /** Single Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8, + /** Single Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9, + /** Continuous Mode Full Rate with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10, + /** Continuous Mode Low Power with Scan Enabled */ + MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11 +} mxc_adc_mode_t; + +/** + * @brief Defines ADC Range Control. + */ +typedef enum { + /** Bi-polar Operation (-Vref/2 -> Vref/2) */ + MXC_E_ADC_RANGE_HALF = 0, + /** Bi-polar Operation (-Vref -> Vref) */ + MXC_E_ADC_RANGE_FULL +} mxc_adc_range_t; + +/** + * @brief Defines ADC Bipolar operation. + */ +typedef enum { + /** Uni-polar operation (0 -> Vref) */ + MXC_E_ADC_BI_POL_UNIPOLAR = 0, + /** Bi-polar operation see ADC Range Control */ + MXC_E_ADC_BI_POL_BIPOLAR +} mxc_adc_bi_pol_t; + +/** + * @brief Defines Decimation Filter Modes. + */ +typedef enum { + /** Decimation Filter ByPassed */ + MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0, + /** Output Average Only*/ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT, + /** Output Average and Raw Data (Test Mode Only) */ + MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW +} mxc_adc_avg_mode_t; + +/** + * @brief Defines ADC StartMode Modes. + */ +typedef enum { + /** StarMode via Software */ + MXC_E_ADC_STRT_MODE_SOFTWARE = 0, + /** StarMode via PulseTrain */ + MXC_E_ADC_STRT_MODE_PULSETRAIN +} mxc_adc_strt_mode_t; + +/** + * @brief Defines Mux Channel Select for the Positive Input to the ADC. + */ +typedef enum { + /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0, + /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1, + /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2, + /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3, + /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4, + /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5, + /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6, + /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7, + /** Single Mode Input AIN8+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8, + /** Single Mode Input AIN9+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9, + /** Single Mode Input AIN10+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10, + /** Single Mode Input AIN11+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11, + /** Single Mode Input AIN12+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12, + /** Single Mode Input AIN13+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13, + /** Single Mode Input AIN14+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14, + /** Single Mode Input AIN15+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15, + /** Positive Input VSSADC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16, + /** Positive Input TMON_R */ + MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17, + /** Positive Input VDDA/4 */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18, + /** Positive Input PWRMAN_TST */ + MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19, + /** Positive Input Ain0Div */ + MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20, + /** Positive Input OpAmp OUTA */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32, + /** Positive Input OpAmp OUTB */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33, + /** Positive Input OpAmp OUTC */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34, + /** Positive Input OpAmp OUTD */ + MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35, + /** Positive INA+ */ + MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36, + /** Positive SNO_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37, + /** Positive SCM_or */ + MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38, + /** Positive TPROBE_sense */ + MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48, + /** Positive VREFDAC */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49, + /** Positive VREFADJ */ + MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50, + /** Positive Vdd3xtal */ + MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51 +} mxc_adc_pga_mux_ch_sel_t; + +/** + * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC. + */ +typedef enum { + /** Differential Mode Disabled */ + MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0, + /** Differential Mode Enabled */ + MXC_E_ADC_PGA_MUX_DIFF_ENABLE +} mxc_adc_pga_mux_diff_t; + +/** + * @brief Defines the PGA Gain Options. + */ +typedef enum { + /** PGA Gain = 1 */ + MXC_E_ADC_PGA_GAIN_1 = 0, + /** PGA Gain = 2 */ + MXC_E_ADC_PGA_GAIN_2, + /** PGA Gain = 4 */ + MXC_E_ADC_PGA_GAIN_4, + /** PGA Gain = 8 */ + MXC_E_ADC_PGA_GAIN_8, +} mxc_adc_pga_gain_t; + +/** + * @brief Defines the Switch Control Mode. + */ +typedef enum { + /** Switch Control Mode = Software */ + MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0, + /** Switch Control Mode = Pulse Train */ + MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN +} mxc_adc_spst_sw_ctrl_t; + +/** + * @brief Defines the number of channels to scan when Scan Mode is enabled. + */ +typedef enum { + /** Number of Channels to Scan = 1 */ + MXC_E_ADC_SCAN_CNT_1 = 0, + /** Number of Channels to Scan = 2 */ + MXC_E_ADC_SCAN_CNT_2, + /** Number of Channels to Scan = 3 */ + MXC_E_ADC_SCAN_CNT_3, + /** Number of Channels to Scan = 4 */ + MXC_E_ADC_SCAN_CNT_4, + /** Number of Channels to Scan = 5 */ + MXC_E_ADC_SCAN_CNT_5, + /** Number of Channels to Scan = 6 */ + MXC_E_ADC_SCAN_CNT_6, + /** Number of Channels to Scan = 7 */ + MXC_E_ADC_SCAN_CNT_7, + /** Number of Channels to Scan = 8 */ + MXC_E_ADC_SCAN_CNT_8, +} mxc_adc_scan_cnt_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */ + __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */ + __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */ + __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */ + __IO uint32_t limit; /* 0x0010 ADC Limit Settings */ + __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */ + __IO uint32_t out; /* 0x0018 ADC Output Register */ +} mxc_adc_regs_t; + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */ + __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */ + __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */ + __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */ + __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */ +} mxc_adccfg_regs_t; + +typedef struct { + __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */ +} mxc_adc_fifo_regs_t; + +/* + Register offsets for module ADC, ADCCFG, ADC_FIFO +*/ +#define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL) +#define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL) +#define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL) +#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL) +#define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL) + +#define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL) +#define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL) +#define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL) +#define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL) +#define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL) +#define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module ADC. +*/ +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0 +#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS)) +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5 +#define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6 +#define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS)) +#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7 +#define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8 +#define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS)) +#define MXC_F_ADC_CTRL0_ADC_DV_POS 9 +#define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS)) +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10 +#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11 +#define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12 +#define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13 +#define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14 +#define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS)) +#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15 +#define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18 +#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS)) +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19 +#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS)) +#define MXC_F_ADC_CTRL0_AVG_MODE_POS 20 +#define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS)) +#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22 +#define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS)) +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24 +#define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS)) +#define MXC_F_ADC_CTRL0_ADC_MODE_POS 28 +#define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS)) + +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0 +#define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS)) +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6 +#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8 +#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13 +#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14 +#define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15 +#define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS)) +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20 +#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS)) +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24 +#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS)) + +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS)) +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS)) + +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0 +#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4 +#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8 +#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12 +#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS)) +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16 +#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS)) + +#define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0 +#define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS)) +#define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16 +#define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS)) + +#define MXC_F_ADC_INTR_FIFO_AF_POS 6 +#define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7 +#define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IF_POS 8 +#define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IF_POS 9 +#define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS)) +#define MXC_F_ADC_INTR_DONE_IF_POS 10 +#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11 +#define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12 +#define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13 +#define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14 +#define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15 +#define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS)) +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16 +#define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17 +#define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18 +#define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19 +#define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS)) +#define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23 +#define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS)) +#define MXC_F_ADC_INTR_HI_RNG_IE_POS 24 +#define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS)) +#define MXC_F_ADC_INTR_LO_RNG_IE_POS 25 +#define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS)) +#define MXC_F_ADC_INTR_DONE_IE_POS 26 +#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27 +#define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28 +#define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29 +#define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30 +#define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS)) +#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31 +#define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS)) + +#define MXC_F_ADC_OUT_DATA_REG_POS 0 +#define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS)) + +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16 +#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS)) + +#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0 +#define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8 +#define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16 +#define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS)) +#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24 +#define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS)) + +#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0 +#define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8 +#define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16 +#define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS)) +#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24 +#define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS)) + +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 +#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 +#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 +#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) +#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 +#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) +#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 +#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) + +#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 +#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 +#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) +#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 +#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _MXC_ADC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h new file mode 100644 index 0000000000..cf9995be40 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AES_REGS_H_ +#define _MXC_AES_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file aes_regs.h + * @addtogroup aes AES + * @{ + */ + +/** + * @brief Settings for AES_CTRL.CRYPT_MODE + */ +typedef enum { + MXC_E_AES_CTRL_ENCRYPT_MODE = 0, + MXC_E_AES_CTRL_DECRYPT_MODE = 1 +} mxc_aes_ctrl_crypt_mode_t; + +/** + * @brief Settings for AES_CTRL.EXP_KEY_MODE + */ +typedef enum { + MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0, + MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1 +} mxc_aes_ctrl_exp_key_mode_t; + +/** + * @brief Settings for AES_CTRL.KEY_SIZE + */ +typedef enum { + MXC_E_AES_CTRL_KEY_SIZE_128 = 0, + MXC_E_AES_CTRL_KEY_SIZE_192 = 1, + MXC_E_AES_CTRL_KEY_SIZE_256 = 2 +} mxc_aes_ctrl_key_size_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 AES Control and Status */ + __I uint32_t rsv004; /* 0x0004 */ + __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */ +} mxc_aes_regs_t; + +/* Offset Register Description + ====== =========================================================== */ +typedef struct { + __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */ + __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */ + __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */ + __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */ +} mxc_aes_mem_regs_t; + +/* + Register offsets for module AES. +*/ +#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) +#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) +#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) +#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) +#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) +#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) +#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) +#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) +#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) +#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) +#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) +#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) +#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) +#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) +#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) +#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) +#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) +#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) + +#define MXC_F_AES_CTRL_START_POS 0 +#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) +#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 +#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 +#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_F_AES_CTRL_INTEN_POS 5 +#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) +#define MXC_F_AES_CTRL_INTFL_POS 6 +#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) + +#define MXC_V_AES_CTRL_ENCRYPT_MODE 0 +#define MXC_V_AES_CTRL_DECRYPT_MODE 1 +#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) +#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) + +#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0 +#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1 +#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) +#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) + +#define MXC_V_AES_CTRL_KEY_SIZE_128 0 +#define MXC_V_AES_CTRL_KEY_SIZE_192 1 +#define MXC_V_AES_CTRL_KEY_SIZE_256 2 +#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) +#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AES_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h new file mode 100644 index 0000000000..31a3f7cb80 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h @@ -0,0 +1,626 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_AFE_REGS_H +#define _MXC_AFE_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file afe_regs.h + * @addtogroup afe AFE + * @{ + */ + +/** + * @brief Defines Configure Options for the LED Ports. + */ +typedef enum { + /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0, + /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */ + MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D, + /** Disable LED Sink Port 0,Disable LED Sink Port 1 */ + MXC_E_AFE_LED_CFG_PORT_DISABLED, +} mxc_afe_led_cfg_port_t; + +/** + * @brief Setup of Wake Up Detector for LPCs. + */ +typedef enum { + /** IDLE */ + MXC_E_AFE_EN_WUD_COMP_IDLE = 0, + /** Activate WUD for falling edges */ + MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2, + /** Activate WUD for rising edges */ + MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3 +} mxc_afe_en_wud_comp_t; + +/** + * @brief LPC InMode. + */ +typedef enum { + /** InMode: both Nch and Pch */ + MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0, + /** InMode: only Nch */ + MXC_E_AFE_IN_MODE_COMP_NCH, + /** InMode: only Pch */ + MXC_E_AFE_IN_MODE_COMP_PCH, +} mxc_afe_in_mode_comp_t; + +/** + * @brief LPC Bias. + */ +typedef enum { + /** BIAS 0.52uA Delay 4.0us */ + MXC_E_AFE_BIAS_MODE_COMP_0 = 0, + /** BIAS 1.4uA Delay 1.7us */ + MXC_E_AFE_BIAS_MODE_COMP_1, + /** BIAS 2.8uA Delay 1.1us */ + MXC_E_AFE_BIAS_MODE_COMP_2, + /** BIAS 5.1uA Delay 0.7us */ + MXC_E_AFE_BIAS_MODE_COMP_3 +} mxc_afe_bias_mode_comp_t; + +/** + * @brief TMON Current Value. + */ +typedef enum { + /** TMON Current 4uA */ + MXC_E_AFE_TMON_CURRENT_VAL_0 = 0, + /** TMON Current 60uA */ + MXC_E_AFE_TMON_CURRENT_VAL_1, + /** TMON Current 64uA */ + MXC_E_AFE_TMON_CURRENT_VAL_2, + /** TMON Current 120uA */ + MXC_E_AFE_TMON_CURRENT_VAL_3 +} mxc_afe_tmon_current_t; + +/** + * @brief REFADC and REFDAC Voltage Select. + */ +typedef enum { + /** Voltage Reference = 1.024 V */ + MXC_E_AFE_REF_VOLT_SEL_1024 = 0, + /** Voltage Reference = 1.5 V */ + MXC_E_AFE_REF_VOLT_SEL_1500, + /** Voltage Reference = 2.048 V */ + MXC_E_AFE_REF_VOLT_SEL_2048, + /** Voltage Reference = 2.5 V */ + MXC_E_AFE_REF_VOLT_SEL_2500 +} mxc_afe_ref_volt_sel_t; + +/** + * @brief Selection for DAC VOltage Reference, REFADC or REFDAC. + */ +typedef enum { + /** DAC Voltage Reference = REFADC */ + MXC_E_AFE_DAC_REF_REFADC = 0, + /** DAC Voltage Reference = REFDAC */ + MXC_E_AFE_DAC_REF_REFDAC +} mxc_afe_dac_ref_t; + +/** + * @brief Selection for LPC Hysteresis. + */ +typedef enum { + /** LPC Hysteresis = 0 mV */ + MXC_E_AFE_HYST_COMP_0 = 0, + /** LPC Hysteresis = 7.5 mV */ + MXC_E_AFE_HYST_COMP_1, + /** LPC Hysteresis = 15 mV */ + MXC_E_AFE_HYST_COMP_2, + /** LPC Hysteresis = 30 mV */ + MXC_E_AFE_HYST_COMP_3 +} mxc_afe_hyst_comp_t; + +/** + * @brief Selection for MUX for SCM_or_sel. + */ +typedef enum { + /** SCM_or = HIZ */ + MXC_E_AFE_SCM_OR_SEL_HIZ = 0, + /** SCM_or = SCM0 */ + MXC_E_AFE_SCM_OR_SEL_SCM0, + /** SCM_or = SCM1 */ + MXC_E_AFE_SCM_OR_SEL_SCM1, + /** SCM_or = SCM2 */ + MXC_E_AFE_SCM_OR_SEL_SCM2, + /** SCM_or = SCM3 */ + MXC_E_AFE_SCM_OR_SEL_SCM3 +} mxc_afe_scm_or_sel_t; + +/** + * @brief Selection for MUX for SNO_or_sel. + */ +typedef enum { + /** SNO_or = HIZ */ + MXC_E_AFE_SNO_OR_SEL_HIZ = 0, + /** SNO_or = SNO0 */ + MXC_E_AFE_SNO_OR_SEL_SNO0, + /** SNO_or = SNO1 */ + MXC_E_AFE_SNO_OR_SEL_SNO1, + /** SNO_or = SNO2 */ + MXC_E_AFE_SNO_OR_SEL_SNO2, + /** SNO_or = SNO3 */ + MXC_E_AFE_SNO_OR_SEL_SNO3 +} mxc_afe_sno_or_sel_t; + +/** + * @brief Selection for MUX DACx_sel. + */ +typedef enum { + /** dacx = DACOP */ + MXC_E_AFE_DACX_SEL_P = 0, + /** dacx = DACON */ + MXC_E_AFE_DACX_SEL_N +} mxc_afe_dacx_sel_t; + +/** + * @brief Selection for state of Switch. + */ +typedef enum { + /** Switch is OPEN */ + MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0, + /** Switch is CLOSED */ + MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE +} mxc_afe_close_spst_t; + +/** + * @brief Switch to Connect Positive Pad to GND. + */ +typedef enum { + /** Positive Pad GND Switch OPEN */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0, + /** Positive Pad GND Switch CLOSED */ + MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED +} mxc_afe_gnd_sel_opamp_t; + +/** + * @brief MUX Selection for OpPsel. + */ +typedef enum { + /** OpPsel = INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0, + /** OpPsel = DAC_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR, + /** OpPsel = SNO_or */ + MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR, + /** OpPsel = DAC_or also output on INx+ */ + MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS +} mxc_afe_p_in_sel_opamp_t; + +/** + * @brief MUX Selection for OpNsel. + */ +typedef enum { + /** OpNsel = INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0, + /** OpNsel = OUTx */ + MXC_E_AFE_N_IN_SEL_OPAMP_OUT, + /** OpNsel = SCM_or */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR, + /**OpNsel = SCM_or also output on INx- */ + MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS, +} mxc_afe_n_in_sel_opamp_t; + +/** + * @brief MUX Selection for DAC_sel. + */ +typedef enum { + /** DAC_or = DAC0 */ + MXC_E_AFE_DAC_SEL_DAC0 = 0, + /** DAC_or = DAC1 */ + MXC_E_AFE_DAC_SEL_DAC1, + /** DAC_or = DAC2P */ + MXC_E_AFE_DAC_SEL_DAC2P, + /** DAC_or = DAC3P */ + MXC_E_AFE_DAC_SEL_DAC3P +} mxc_afe_dac_sel_t; + +/** + * @brief MUX Selection for NPAD_sel. + */ +typedef enum { + /** NPAD_Sel = HIZ */ + MXC_E_AFE_NPAD_SEL_HIZ = 0, + /** NPAD_Sel = LED Observe Port */ + MXC_E_AFE_NPAD_SEL_LED_OBS_PORT, + /** NPAD_Sel = DAC_or */ + MXC_E_AFE_NPAD_SEL_DAC_OR, + /** NPAD_Sel = DAC_or and LED Observe Port */ + MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT +} mxc_afe_npad_sel_t; + +/** + * @brief MUX Selection for CmpPSel. + */ +typedef enum { + /** CmpPSel = INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0, + /** CmpPSel = SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_SCM, + /** CmpPSel = dac1 */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1, + /** CmpPSel = DAC3P */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P, + /** CmpPSel = LED Observe Port */ + MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT, + /** CmpPSel = dac1 also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS, + /** CmpPSel = DAC3P also output on INx+ */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS, + /** CmpPSel = dac1 also output on SCM */ + MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM +} mxc_afe_pos_in_sel_comp_t; + +/** + * @brief MUX Selection for CmpNSel. + */ +typedef enum { + /** CmpNSel = INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0, + /** CmpNSel = SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_SNO, + /** CmpNSel = dac0 */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0, + /** CmpNSel = DAC2P */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P, + /** CmpNSel = LED Observation Port */ + MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT, + /** CmpNSel = dac0 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS, + /** CmpNSel = DAC2 also output on INx- */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS, + /** CmpNSel = DAC2 also output on SNO */ + MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO +} mxc_afe_neg_in_sel_comp_t; + +/* Offset Register Description + ====== ==================================================== */ +typedef struct { + __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */ + __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */ + __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */ + __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */ + __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */ + __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */ +} mxc_afe_regs_t; + +/* + Register offsets for module AFE. +*/ +#define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL) +#define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL) +#define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL) +#define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL) +#define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL) + +/* + Field positions and masks for module AFE. +*/ +#define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0 +#define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1 +#define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2 +#define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3 +#define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4 +#define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5 +#define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6 +#define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7 +#define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8 +#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9 +#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10 +#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11 +#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12 +#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13 +#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14 +#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15 +#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16 +#define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17 +#define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18 +#define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19 +#define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20 +#define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21 +#define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22 +#define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23 +#define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS)) +#define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24 +#define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25 +#define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26 +#define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27 +#define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28 +#define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29 +#define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30 +#define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS)) +#define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31 +#define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS)) + +#define MXC_F_AFE_CTRL0_LED_CFG_POS 0 +#define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7 +#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS)) +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14 +#define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22 +#define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS)) +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30 +#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS)) + +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS)) +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1 +#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3 +#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4 +#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS)) +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5 +#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6 +#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8 +#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_SEL_POS 10 +#define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11 +#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12 +#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13 +#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14 +#define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15 +#define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS)) +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16 +#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18 +#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS)) +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20 +#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS)) +#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23 +#define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS)) +#define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25 +#define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS)) +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30 +#define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS)) + +#define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0 +#define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2 +#define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4 +#define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6 +#define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8 +#define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9 +#define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10 +#define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS)) +#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11 +#define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12 +#define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13 +#define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14 +#define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS)) +#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15 +#define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16 +#define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17 +#define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18 +#define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS)) +#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19 +#define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS)) +#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20 +#define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23 +#define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26 +#define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS)) +#define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27 +#define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS)) + +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15 +#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19 +#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20 +#define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21 +#define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22 +#define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS)) +#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23 +#define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27 +#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS)) +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31 +#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS)) + +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6 +#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS)) +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14 +#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16 +#define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18 +#define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20 +#define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22 +#define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24 +#define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26 +#define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28 +#define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS)) +#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30 +#define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS)) + +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9 +#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS)) +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21 +#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP0_POS 24 +#define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP1_POS 25 +#define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP2_POS 26 +#define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS)) +#define MXC_F_AFE_CTRL5_OP_CMP3_POS 27 +#define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_AFE_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h new file mode 100644 index 0000000000..28a258b999 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CLKMAN_REGS_H_ +#define _MXC_CLKMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file clkman_regs.h + * @addtogroup clkman CLKMAN + * @{ + */ + +/** + * @brief Defines clock input selections for the phase locked loop. + */ +typedef enum { + /** Input select for high frequency crystal oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0, + /** Input select for 24MHz ring oscillator */ + MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO, +} mxc_clkman_pll_input_select_t; + +/** + * @brief Defines clock input frequency for the phase locked loop. + */ +typedef enum { + /** Input frequency of 24MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0, + /** Input frequency of 12MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ, + /** Input frequency of 8MHz */ + MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ, +} mxc_clkman_pll_divisor_select_t; + +/** + * @brief Defines terminal count for PLL stable. + */ +typedef enum { + /** Clock stable after 2^8 = 256 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0, + /** Clock stable after 2^9 = 512 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS, + /** Clock stable after 2^10 = 1024 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS, + /** Clock stable after 2^11 = 2048 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS, + /** Clock stable after 2^12 = 4096 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS, + /** Clock stable after 2^13 = 8192 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS, + /** Clock stable after 2^14 = 16384 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS, + /** Clock stable after 2^15 = 32768 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS, + /** Clock stable after 2^16 = 65536 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS, + /** Clock stable after 2^17 = 131072 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS, + /** Clock stable after 2^18 = 262144 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS, + /** Clock stable after 2^19 = 524288 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS, + /** Clock stable after 2^20 = 1048576 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS, + /** Clock stable after 2^21 = 2097152 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS, + /** Clock stable after 2^22 = 4194304 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS, + /** Clock stable after 2^23 = 8388608 clock cycles */ + MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS +} mxc_clkman_stability_count_t; + +/** + * @brief Defines clock source selections for system clock. + */ +typedef enum { + /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX, + /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */ + MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 +} mxc_clkman_system_source_select_t; + +/** + * @brief Defines clock source selections for analog to digital converter clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO, +} mxc_clkman_adc_source_select_t; + +/** + * @brief Defines clock source selections for watchdog timer clock. + */ +typedef enum { + /** Clock select for system clock frequency */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0, + /** Clock select for 8MHz phase locked loop output */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC, + /** Clock select for high frequency crystal oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO, + /** Clock select for 24MHz ring oscillator */ + MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO, +} mxc_clkman_wdt_source_select_t; + +/** + * @brief Defines clock scales for various clocks. + */ +typedef enum { + /** Clock disabled */ + MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0, + /** Clock enabled */ + MXC_E_CLKMAN_CLK_SCALE_ENABLED, + /** Clock scale for dividing by 2 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_2, + /** Clock scale for dividing by 4 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_4, + /** Clock scale for dividing by 8 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_8, + /** Clock scale for dividing by 16 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_16, + /** Clock scale for dividing by 32 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_32, + /** Clock scale for dividing by 64 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_64, + /** Clock scale for dividing by 128 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_128, + /** Clock scale for dividing by 256 */ + MXC_E_CLKMAN_CLK_SCALE_DIV_256 +} mxc_clkman_clk_scale_t; + +/** + * @brief Defines Setting of the Clock Gates . + */ +typedef enum { + /** Clock Gater is Off */ + MXC_E_CLKMAN_CLK_GATE_OFF = 0, + /** Clock Gater is Dynamic */ + MXC_E_CLKMAN_CLK_GATE_DYNAMIC, + /** Clock Gater is On */ + MXC_E_CLKMAN_CLK_GATE_ON +} mxc_clkman_clk_gate_t; + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */ + __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */ + __IO uint32_t intfl; /* 0x0008 Interrupt Flags */ + __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */ + __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */ + __I uint32_t rsv0014[4]; /* 0x0014 */ + __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */ + __I uint32_t rsv0028[6]; /* 0x0028 */ + __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */ + __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */ + __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */ + __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */ + __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */ + __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */ + __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */ + __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */ + __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */ + __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */ + __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */ + __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */ + __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */ + __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */ + __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */ + __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */ + __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */ + __I uint32_t rsv0088[30]; /* 0x0088 */ + __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */ + __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */ + __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */ + __I uint32_t rsv010C[13]; /* 0x010C */ + __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */ + __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */ + __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */ +} mxc_clkman_regs_t; + +/* + Register offsets for module CLKMAN. +*/ +#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) +#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) +#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) +#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL) +#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) +#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) +#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) + +/* + Field positions and masks for module CLKMAN. +*/ +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9 +#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20 +#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS)) +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28 +#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1 +#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3 +#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4 +#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9 +#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12 +#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21 +#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS)) +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24 +#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) + +#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0 +#define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1 +#define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS)) +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2 +#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) + +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 +#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) + +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 +#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 +#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30 +#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS)) + +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS)) +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6 +#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CLKMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h new file mode 100644 index 0000000000..cce733185e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max32600.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c new file mode 100644 index 0000000000..3694273047 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis_nvic.h" + +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD) +__attribute__((aligned(256))) +#endif +#if defined(TOOLCHAIN_IAR) +#pragma data_alignment=256 +#endif +static void (*ramVectorTable[MXC_IRQ_COUNT])(void); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR != (uint32_t)ramVectorTable) { + uint32_t *old_vectors = (uint32_t*)SCB->VTOR; + vectors = (uint32_t*)ramVectorTable; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)ramVectorTable; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h new file mode 100644 index 0000000000..d3e5447614 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS MXC_IRQ_COUNT +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif /* MBED_CMSIS_NVIC_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h new file mode 100644 index 0000000000..6acec11048 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h @@ -0,0 +1,89 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_CRC_REGS_H_ +#define _MXC_CRC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file crc_regs.h + * @addtogroup crc CRC + * @{ + */ + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */ + __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */ + __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */ +} mxc_crc_regs_t; + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t value16[512]; /* 0x0000 Write Next CRC-16 Data Value / Read CRC-16 Result Value */ + __IO uint32_t value32[512]; /* 0x0800 Write Next CRC-32 Data Value / Read CRC-32 Result Value */ +} mxc_crc_data_regs_t; + +/* + Register offsets for module CRC. +*/ +#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) +#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) +#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) +#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) +#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module CRC. +*/ +#define MXC_F_CRC_RESEED_CRC16_POS 0 +#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) +#define MXC_F_CRC_RESEED_CRC32_POS 1 +#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_CRC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h new file mode 100644 index 0000000000..2f0f4bd8c5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h @@ -0,0 +1,180 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_DAC_REGS_H +#define _MXC_DAC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file dac_regs.h + * @addtogroup dac DAC + * @{ + */ + +/** + * @brief Defines the DAC Operational Modes. + */ +typedef enum { + /** DAC OpMode FIFO */ + MXC_E_DAC_OP_MODE_FIFO = 0, + /** DAC OpMode Sample Count */ + MXC_E_DAC_OP_MODE_DACSMPLCNT, + /** DAC OpMode DAC_REG Control */ + MXC_E_DAC_OP_MODE_DAC_REG, + /** DAC OpMode Continuous */ + MXC_E_DAC_OP_MODE_CONTINUOUS +} mxc_dac_op_mode_t; + +/** + * @brief Defines the DAC Interpolation Options. + */ +typedef enum { + /** DAC Interpolation is Disabled */ + MXC_E_DAC_INTERP_MODE_DISABLED = 0, + /** DAC Interpolation 2:1 */ + MXC_E_DAC_INTERP_MODE_2_TO_1, + /** DAC Interpolation 4:1 */ + MXC_E_DAC_INTERP_MODE_4_TO_1, + /** DAC Interpolation 8:1 */ + MXC_E_DAC_INTERP_MODE_8_TO_1 +} mxc_dac_interp_mode_t; + +/** + * @brief Defines the DAC Start Modes. + */ +typedef enum { + /** Start on FIFO Not Empty */ + MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0, + /** Start on ADC generated Start Strobe */ + MXC_E_DAC_START_MODE_ADC_STROBE, + /** Start on DAC generated Start Strobe */ + MXC_E_DAC_START_MODE_DAC_STROBE +} mxc_dac_start_mode_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */ + __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */ + __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */ + __IO uint32_t reg; /* 0x000C DAC Data Register */ + __IO uint32_t trm; /* 0x0010 DAC Trim Register */ +} mxc_dac_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + union { + __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */ + __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */ + }; +} mxc_dac_fifo_t; + +/* + Register offsets for module DAC12. +*/ +#define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL) +#define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL) +#define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL) +#define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL) + +/* + Field positions and masks for module DAC. +*/ +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0 +#define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS)) +#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6 +#define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7 +#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS)) +#define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8 +#define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS)) +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12 +#define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS)) +#define MXC_F_DAC_CTRL0_START_MODE_POS 16 +#define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS)) +#define MXC_F_DAC_CTRL0_CPU_START_POS 20 +#define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS)) +#define MXC_F_DAC_CTRL0_OP_MODE_POS 24 +#define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26 +#define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS)) +#define MXC_F_DAC_CTRL0_POWER_ON_POS 28 +#define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS)) +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29 +#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS)) +#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30 +#define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS)) +#define MXC_F_DAC_CTRL0_RESET_POS 31 +#define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS)) + +#define MXC_F_DAC_RATE_RATE_CNT_POS 0 +#define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS)) +#define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16 +#define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS)) + +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS)) +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16 +#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17 +#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18 +#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS)) +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28 +#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS)) +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29 +#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _DAC12_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h new file mode 100644 index 0000000000..864c8c9b97 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h @@ -0,0 +1,210 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_FLC_REGS_H +#define _MXC_FLC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file flc_regs.h + * @addtogroup flc FLC + * @{ + */ +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t faddr; /* 0x0000 Flash Operation Address */ + __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */ + __IO uint32_t ctrl; /* 0x0008 Flash Control Register */ + __I uint32_t rsv000C[6]; /* 0x000C */ + __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */ + __I uint32_t rsv0028[2]; /* 0x0028 */ + __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */ + __I uint32_t rsv0034[7]; /* 0x0034 */ + __IO uint32_t perform; /* 0x0050 Flash Performance Settings */ + __I uint32_t rsv0054[11]; /* 0x0054 */ + __IO uint32_t status; /* 0x0080 Security Status Flags */ + __I uint32_t rsv0084; /* 0x0084 */ + __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */ + __I uint32_t rsv008C[4]; /* 0x008C */ + __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */ + __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */ + __I uint32_t rsv0104[15]; /* 0x0104 */ + __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */ + __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */ + __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */ + __I uint32_t rsv014C; /* 0x014C */ + __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */ + __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */ + __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */ + __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */ + __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */ + __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */ + __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */ + __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */ +} mxc_flc_regs_t; + +/* + Register offsets for module FLC. +*/ +#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) +#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) +#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) +#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) +#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) +#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) +#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) +#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) +#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) +#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) +#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) +#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) +#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL) +#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL) +#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL) +#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL) +#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL) +#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL) +#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL) +#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL) + +#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) +#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) + +#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) + +/* + Field positions and masks for module FLC. +*/ +#define MXC_F_FLC_FADDR_FADDR_POS 0 +#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) + +#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0 +#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) + +#define MXC_F_FLC_CTRL_WRITE_POS 0 +#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) +#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 +#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) +#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 +#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 +#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) +#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 +#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) +#define MXC_F_FLC_CTRL_PENDING_POS 24 +#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 +#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 +#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) +#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 +#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) + +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9 +#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS)) +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10 +#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS)) + +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 +#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) +#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 +#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) + +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS)) +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1 +#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS)) +#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 +#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) + +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 +#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 +#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) +#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31 +#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) + +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 +#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 +#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 +#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) + +#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 +#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 +#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) + +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) + +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 +#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 +#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 +#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 +#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_FLC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h new file mode 100644 index 0000000000..8a8122d8cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h @@ -0,0 +1,477 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_GPIO_REGS_H_ +#define _MXC_GPIO_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file gpio_regs.h + * @addtogroup gpio GPIO + * @{ + */ + +/* Offset Register Description + ============= ========================================== */ +typedef struct { + __I uint32_t rsv000[16]; /* 0x0000-0x003C */ + + __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */ + __I uint32_t rsv060[8]; /* 0x0060-0x007C */ + + __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */ + __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */ + + __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */ + __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */ + + __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */ + __I uint32_t rsv120[8]; /* 0x0120-0x013C */ + + __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */ + __I uint32_t rsv160[8]; /* 0x0160-0x017C */ + + __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */ + __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */ + + __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */ + __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */ + + __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */ + __I uint32_t rsv220[8]; /* 0x0220-0x023C */ + + __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */ +} mxc_gpio_regs_t; + +/* + Register offsets for module GPIO. +*/ +#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) +#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) +#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) +#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) +#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) +#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) +#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) +#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) +#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) +#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) +#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) +#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) +#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) +#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) +#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) +#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) +#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) +#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) +#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) +#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) +#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) +#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) +#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) +#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) +#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) +#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) +#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) +#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) +#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) +#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) +#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) +#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) +#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) + + +/* + Field positions and masks for module GPIO. +*/ +#define MXC_F_GPIO_FREE_PIN0_POS 0 +#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_F_GPIO_FREE_PIN1_POS 1 +#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_F_GPIO_FREE_PIN2_POS 2 +#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_F_GPIO_FREE_PIN3_POS 3 +#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_F_GPIO_FREE_PIN4_POS 4 +#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_F_GPIO_FREE_PIN5_POS 5 +#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_F_GPIO_FREE_PIN6_POS 6 +#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_F_GPIO_FREE_PIN7_POS 7 +#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 +#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 +#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 +#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 +#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 +#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 +#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 +#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) +#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 +#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) + +#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 +#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 +#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 +#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 +#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 +#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 +#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 +#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) +#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 +#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) + +#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 +#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) +#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 +#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) +#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 +#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) +#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 +#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) +#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 +#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) +#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 +#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) +#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 +#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) +#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 +#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) + +#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 +#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) +#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 +#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) +#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 +#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) +#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 +#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) +#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 +#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) +#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 +#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) +#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 +#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) +#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 +#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) + +#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 +#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) +#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 +#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) +#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 +#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) +#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 +#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) +#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 +#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) +#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 +#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) +#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 +#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) +#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 +#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) + +#define MXC_F_GPIO_INTFL_PIN0_POS 0 +#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) +#define MXC_F_GPIO_INTFL_PIN1_POS 1 +#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) +#define MXC_F_GPIO_INTFL_PIN2_POS 2 +#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) +#define MXC_F_GPIO_INTFL_PIN3_POS 3 +#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) +#define MXC_F_GPIO_INTFL_PIN4_POS 4 +#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) +#define MXC_F_GPIO_INTFL_PIN5_POS 5 +#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) +#define MXC_F_GPIO_INTFL_PIN6_POS 6 +#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) +#define MXC_F_GPIO_INTFL_PIN7_POS 7 +#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) + +#define MXC_F_GPIO_INTEN_PIN0_POS 0 +#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) +#define MXC_F_GPIO_INTEN_PIN1_POS 1 +#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) +#define MXC_F_GPIO_INTEN_PIN2_POS 2 +#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) +#define MXC_F_GPIO_INTEN_PIN3_POS 3 +#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) +#define MXC_F_GPIO_INTEN_PIN4_POS 4 +#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) +#define MXC_F_GPIO_INTEN_PIN5_POS 5 +#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) +#define MXC_F_GPIO_INTEN_PIN6_POS 6 +#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) +#define MXC_F_GPIO_INTEN_PIN7_POS 7 +#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) + + +/* + Field values and shifted values for module GPIO. +*/ +#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) +#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) + +#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) +#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) + +#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) +#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) + +#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) +#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) + +#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) +#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) + +#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) +#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) + +#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) +#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) + +#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL)) +#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL)) + +#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) +#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) + +#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) +#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) +#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) + +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS)) + +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS)) +#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS)) + +#define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL)) +#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) +#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) +#define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL)) +#define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL)) +#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_GPIO_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h new file mode 100644 index 0000000000..173d3107a3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h @@ -0,0 +1,192 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_I2CM_REGS_H_ +#define _MXC_I2CM_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file i2cm_regs.h + * @addtogroup i2cm I2CM + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */ + __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */ + __I uint32_t rsv0008; /* 0x0008 */ + __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */ + __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */ + __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */ + __IO uint32_t intfl; /* 0x0018 Interrupt Flags */ + __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */ + __I uint32_t rsv0020[2]; /* 0x0020 */ + __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */ +} mxc_i2cm_regs_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */ + __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */ +} mxc_i2cm_fifo_regs_t; + +/* + Register offsets for module I2CM. +*/ +#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL) +#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) +#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) +#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) +#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) +#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) +#define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL) + +#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module I2CM. +*/ +#define MXC_S_I2CM_TRANS_TAG_START 0x000 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 +#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 +#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 +#define MXC_S_I2CM_TRANS_TAG_STOP 0x700 +#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 +#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 + +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0 +#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8 +#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)) +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20 +#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS)) + +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 +#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 +#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) + +#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 +#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 +#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 +#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) + +#define MXC_F_I2CM_TRANS_TX_START_POS 0 +#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 +#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) +#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 +#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) +#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 +#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 +#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 +#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) + +#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 +#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) +#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 +#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 +#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) +#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 +#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 +#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) +#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 +#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 +#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 +#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6 +#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 +#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 +#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 +#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) + +#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 +#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 +#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 +#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 +#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) +#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 +#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h new file mode 100644 index 0000000000..c8407a843c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_ICC_REGS_H_ +#define _MXC_ICC_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file icc_regs.h + * @addtogroup icc ICC + * @{ + */ + +/* Offset Register Description + ====== =================================================== */ +typedef struct { + __IO uint32_t id; /* 0x0000 Device ID Register */ + __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */ + __I uint32_t rsv0008[62]; /* 0x0008 */ + __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */ + __I uint32_t rsv0104[383]; /* 0x0104 */ + __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */ +} mxc_icc_regs_t; + +/* + Register offsets for module ICC. +*/ +#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) +#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) +#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) +#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) + +/* + Field positions and masks for module ICC. +*/ +#define MXC_F_ICC_ID_RTL_VERSION_POS 0 +#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) +#define MXC_F_ICC_ID_PART_NUM_POS 6 +#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) +#define MXC_F_ICC_ID_CACHE_ID_POS 10 +#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) + +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 +#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 +#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) + +#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 +#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) +#define MXC_F_ICC_CTRL_STAT_READY_POS 16 +#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_ICC_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h new file mode 100644 index 0000000000..930a181595 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h @@ -0,0 +1,508 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_IOMAN_REGS_H_ +#define _MXC_IOMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file ioman_regs.h + * @addtogroup ioman IO MUX Manager + * @{ + */ + +typedef enum { + /** Pin Mapping 'A' */ + MXC_E_IOMAN_MAPPING_A = 0, + /** Pin Mapping 'B' */ + MXC_E_IOMAN_MAPPING_B, + /** Pin Mapping 'C' */ + MXC_E_IOMAN_MAPPING_C, + /** Pin Mapping 'D' */ + MXC_E_IOMAN_MAPPING_D, + /** Pin Mapping 'E' */ + MXC_E_IOMAN_MAPPING_E, + /** Pin Mapping 'F' */ + MXC_E_IOMAN_MAPPING_F, + /** Pin Mapping 'G' */ + MXC_E_IOMAN_MAPPING_G, + /** Pin Mapping 'H' */ + MXC_E_IOMAN_MAPPING_H, +} ioman_mapping_t; + +/* Offset Register Description + ====== ========================================== */ +typedef struct { + __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */ + __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */ + __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */ + __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */ + __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */ + __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */ + __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */ + __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */ + __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */ + __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */ + __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */ + __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */ + __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */ + __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */ + __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */ + __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */ + __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */ + __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */ + __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */ + __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */ + __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */ + __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */ + __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */ + __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */ + __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */ + __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */ + __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */ + __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */ + __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */ + __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */ + __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */ + __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */ + __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */ + __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */ + __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */ + __IO uint32_t padx_control; /* 0x008C PADX Control */ +} mxc_ioman_regs_t; + + +/* + Register offsets for module IOMAN. +*/ +#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) +#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) +#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) +#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) +#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) +#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) +#define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL) +#define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL) +#define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL) +#define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL) +#define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL) +#define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL) +#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL) +#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL) +#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL) +#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL) +#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL) +#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL) +#define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL) +#define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL) +#define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL) +#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL) +#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL) +#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL) +#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL) +#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL) +#define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL) + + +/* + Field positions and masks for module IOMAN. +*/ +#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS)) + +#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0 +#define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8 +#define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16 +#define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS)) +#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24 +#define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS)) + +#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0 +#define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8 +#define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16 +#define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS)) +#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24 +#define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS)) + +#define MXC_F_IOMAN_SPI_MAPPING_POS 0 +#define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS)) +#define MXC_F_IOMAN_SPI_CORE_IO_POS 4 +#define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS)) +#define MXC_F_IOMAN_SPI_SS0_IO_POS 8 +#define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS)) +#define MXC_F_IOMAN_SPI_SS1_IO_POS 9 +#define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS)) +#define MXC_F_IOMAN_SPI_SS2_IO_POS 10 +#define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS)) +#define MXC_F_IOMAN_SPI_SS3_IO_POS 11 +#define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS)) +#define MXC_F_IOMAN_SPI_SS4_IO_POS 12 +#define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS)) +#define MXC_F_IOMAN_SPI_SR0_IO_POS 16 +#define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS)) +#define MXC_F_IOMAN_SPI_SR1_IO_POS 17 +#define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS)) +#define MXC_F_IOMAN_SPI_QUAD_IO_POS 20 +#define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS)) +#define MXC_F_IOMAN_SPI_FAST_MODE_POS 24 +#define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS)) + +#define MXC_F_IOMAN_UART_MAPPING_POS 0 +#define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS)) +#define MXC_F_IOMAN_UART_CORE_IO_POS 4 +#define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS)) +#define MXC_F_IOMAN_UART_CTS_IO_POS 5 +#define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS)) +#define MXC_F_IOMAN_UART_RTS_IO_POS 6 +#define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS)) + +#define MXC_F_IOMAN_I2CM_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS)) +#define MXC_F_IOMAN_I2CM_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS)) + +#define MXC_F_IOMAN_I2CS_MAPPING_POS 0 +#define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS)) +#define MXC_F_IOMAN_I2CS_CORE_IO_POS 4 +#define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0 +#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31 +#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS)) + +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS)) +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7 +#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS)) + +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7 +#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS)) + +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS)) +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28 +#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS)) + +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS)) +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10 +#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_IOMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h new file mode 100644 index 0000000000..db8223fdf8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_LCD_REGS_H +#define _MXC_LCD_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file lcd_regs.h + * @addtogroup lcd LCD + * @{ + */ + +#define MXC_LCD_ADDRESS_SEGS 21 + +/* Offset Register Description + ====== ======================================================= */ +typedef struct { + __IO uint32_t lcfg; /* 0x0000 */ + __IO uint32_t lcra; /* 0x0004 */ + __IO uint32_t lpcf; /* 0x0008 LCD Port Configuration Register */ + __IO uint32_t lcaddr; /* 0x000C */ + __IO uint32_t lcdata; /* 0x0010 LCD Memory Data Read / Write */ + __IO uint32_t lpwrctrl; /* 0x0014 LCD Power Control */ +} mxc_lcd_regs_t; + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _MXC_LCD_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h new file mode 100644 index 0000000000..e8c80c712b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h @@ -0,0 +1,124 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_MAA_REGS_H_ +#define _MXC_MAA_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file maa_regs.h + * @addtogroup maa MAA + * @{ + */ + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */ + __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */ +} mxc_maa_regs_t; + +/* Offset Register Description + ====== ========================================================== */ +typedef struct { + __IO uint32_t seg0[16]; /* 0x0000 [64 bytes] MAA Memory Segment 0 */ + __IO uint32_t seg1[16]; /* 0x0040 [64 bytes] MAA Memory Segment 1 */ + __IO uint32_t seg2[16]; /* 0x0080 [64 bytes] MAA Memory Segment 2 */ + __IO uint32_t seg3[16]; /* 0x00C0 [64 bytes] MAA Memory Segment 3 */ + __IO uint32_t seg4[16]; /* 0x0100 [64 bytes] MAA Memory Segment 4 */ + __IO uint32_t seg5[16]; /* 0x0140 [64 bytes] MAA Memory Segment 5 */ +} mxc_maa_mem_regs_t; + +/* + Register offsets for module MAA. +*/ +#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) +#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) +#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000040UL) +#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000080UL) +#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x000000C0UL) +#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000100UL) +#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000140UL) + +/* + Field positions and masks for module MAA. +*/ +#define MXC_F_MAA_CTRL_START_POS 0 +#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) +#define MXC_F_MAA_CTRL_OPSEL_POS 1 +#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) +#define MXC_F_MAA_CTRL_OCALC_POS 4 +#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) +#define MXC_F_MAA_CTRL_INTEN_POS 5 +#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) +#define MXC_F_MAA_CTRL_IF_DONE_POS 6 +#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) +#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 +#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) +#define MXC_F_MAA_CTRL_OFS_A_POS 8 +#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) +#define MXC_F_MAA_CTRL_OFS_B_POS 10 +#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) +#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 +#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) +#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 +#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) +#define MXC_F_MAA_CTRL_SEG_A_POS 16 +#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) +#define MXC_F_MAA_CTRL_SEG_B_POS 20 +#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) +#define MXC_F_MAA_CTRL_SEG_RES_POS 24 +#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) +#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 +#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) + +#define MXC_F_MAA_MAWS_MODLEN_POS 0 +#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) +#define MXC_F_MAA_MAWS_BYTESWAP_POS 16 +#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_MAA_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h new file mode 100644 index 0000000000..5b50a7aabe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h @@ -0,0 +1,666 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MAX32600_H_ +#define _MAX32600_H_ + +#include + +typedef enum IRQn_Type { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Externals interrupts */ + UART0_IRQn = 0, /* 16:01 UART0 */ + UART1_IRQn, /* 17: 2 UART1 */ + I2CM0_IRQn, /* 18: 3 I2C Master 0 */ + I2CS_IRQn, /* 19: 4 I2C Slave */ + USB_IRQn, /* 20: 5 USB */ + PMU_IRQn, /* 21: 6 DMA */ + AFE_IRQn, /* 22: 7 AFE */ + MAA_IRQn, /* 23: 8 MAA */ + AES_IRQn, /* 24: 9 AES */ + SPI0_IRQn, /* 25:10 SPI0 */ + SPI1_IRQn, /* 26:11 SPI1 */ + SPI2_IRQn, /* 27:12 SPI2 */ + TMR0_IRQn, /* 28:13 Timer32-0 */ + TMR1_IRQn, /* 29:14 Timer32-1 */ + TMR2_IRQn, /* 30:15 Timer32-1 */ + TMR3_IRQn, /* 31:16 Timer32-2 */ + RSVD0_IRQn, /* 32:17 RSVD */ + RSVD1_IRQn, /* 33:18 RSVD */ + DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */ + DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */ + DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */ + DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */ + ADC_IRQn, /* 38:23 ADC */ + FLC_IRQn, /* 39:24 Flash Controller */ + PWRMAN_IRQn, /* 40:25 PWRMAN */ + CLKMAN_IRQn, /* 41:26 CLKMAN */ + RTC0_IRQn, /* 42:27 RTC INT0 */ + RTC1_IRQn, /* 43:28 RTC INT1 */ + RTC2_IRQn, /* 44:29 RTC INT2 */ + RTC3_IRQn, /* 45:30 RTC INT3 */ + WDT0_IRQn, /* 46:31 WATCHDOG0 */ + WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */ + WDT1_IRQn, /* 48:33 WATCHDOG1 */ + WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */ + GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */ + GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */ + GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */ + GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */ + GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */ + GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */ + GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */ + GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */ + TMR16_0_IRQn, /* 58:43 Timer16-s0 */ + TMR16_1_IRQn, /* 59:44 Timer16-s1 */ + TMR16_2_IRQn, /* 60:45 Timer16-s2 */ + TMR16_3_IRQn, /* 61:46 Timer16-s3 */ + I2CM1_IRQn, /* 62:47 I2C Master 1 */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ + +#include /* Processor and core peripherals */ +#include "system_max32600.h" /* System Header */ + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_SYS_MEM_BASE 0x20000000UL + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/*******************************************************************************/ +/* General Purpose I/O Ports (GPIO) */ + +#define MXC_BASE_GPIO ((uint32_t)0x40000000UL) +#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) +#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL) + +#define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn) + + +/*******************************************************************************/ +/* Pulse Train Generation */ + +#define MXC_CFG_PT_INSTANCES (13) + +#define MXC_BASE_PTG ((uint32_t)0x40001000UL) +#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) +#define MXC_BASE_PT ((uint32_t)0x40001008UL) +#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT) +#define MXC_BASE_PT0 ((uint32_t)0x40001008UL) +#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) +#define MXC_BASE_PT1 ((uint32_t)0x40001010UL) +#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) +#define MXC_BASE_PT2 ((uint32_t)0x40001018UL) +#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) +#define MXC_BASE_PT3 ((uint32_t)0x40001020UL) +#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) +#define MXC_BASE_PT4 ((uint32_t)0x40001028UL) +#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) +#define MXC_BASE_PT5 ((uint32_t)0x40001030UL) +#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) +#define MXC_BASE_PT6 ((uint32_t)0x40001038UL) +#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) +#define MXC_BASE_PT7 ((uint32_t)0x40001040UL) +#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) +#define MXC_BASE_PT8 ((uint32_t)0x40001048UL) +#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) +#define MXC_BASE_PT9 ((uint32_t)0x40001050UL) +#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) +#define MXC_BASE_PT10 ((uint32_t)0x40001058UL) +#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) +#define MXC_BASE_PT11 ((uint32_t)0x40001060UL) +#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) + +/* PT12, PT13, PT14 are not used */ + +/*******************************************************************************/ +/* CRC-16/CRC-32 Engine */ + +#define MXC_BASE_CRC ((uint32_t)0x40010000UL) +#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC) + +#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL) +#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) + +/*******************************************************************************/ +/* Trust Protection Unit (TPU) */ + +#define MXC_BASE_TPU ((uint32_t)0x40011000UL) +#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) + +#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL) +#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) + +/*******************************************************************************/ +/* AES Cryptographic Engine */ + +#define MXC_BASE_AES ((uint32_t)0x40011400UL) +#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) + +#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL) +#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) + + +/*******************************************************************************/ +/* MAA Cryptographic Engine */ + +#define MXC_BASE_MAA ((uint32_t)0x40011800UL) +#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) + +#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL) +#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) + +/*******************************************************************************/ +/* 32-Bit PWM Timer/Counter */ + +#define MXC_CFG_TMR_INSTANCES (4) + +#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL) +#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0) + +#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL) +#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1) + +#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL) +#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2) + +#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL) +#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL) +#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3) + + +#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : 0) + +#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR16_0_IRQn : \ + (i) == 5 ? TMR16_1_IRQn : \ + (i) == 6 ? TMR16_2_IRQn : \ + (i) == 7 ? TMR16_3_IRQn : 0) + +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : 0) + +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : 0) +/*******************************************************************************/ +/* Watchdog Timer */ + +#define MXC_CFG_WDT_INSTANCES (2) + +#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL) +#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) + +#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL) +#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL) +#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) + +#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \ + (i) == 1 ? WDT1_IRQn : 0) + +#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \ + (i) == 1 ? WDT1_P_IRQn : 0) + +#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ + (i) == 1 ? MXC_BASE_WDT1 : 0) + +#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ + (i) == 1 ? MXC_WDT1 : 0) + +/*******************************************************************************/ +/* SPI Interface */ + +#define MXC_CFG_SPI_INSTANCES (3) +#define MXC_CFG_SPI_FIFO_DEPTH (16) + +#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL) +#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) + +#define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL) +#define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO) +#define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL) +#define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO) + +#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL) +#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) + +#define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL) +#define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO) +#define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL) +#define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO) + +#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL) +#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) + +#define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL) +#define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO) +#define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL) +#define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO) + + +#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \ + (i) == 1 ? SPI1_IRQn : \ + (i) == 2 ? SPI2_IRQn : 0) + +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ + (i) == 1 ? MXC_BASE_SPI1 : \ + (i) == 2 ? MXC_BASE_SPI2 : 0) + +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ + (i) == 1 ? MXC_SPI1 : \ + (i) == 2 ? MXC_SPI2 : 0) + +#define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \ + (i) == 1 ? MXC_SPI1_RXFIFO : \ + (i) == 2 ? MXC_SPI2_RXFIFO : 0) + +#define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \ + (i) == 1 ? MXC_SPI1_TXFIFO : \ + (i) == 2 ? MXC_SPI2_TXFIFO : 0) + +#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0) +#define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12) + + +/*******************************************************************************/ +/* UART Interface */ + +#define MXC_CFG_UART_INSTANCES (2) + +#define MXC_BASE_UART0 ((uint32_t)0x40038000UL) +#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL) +#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) + +#define MXC_BASE_UART1 ((uint32_t)0x40039000UL) +#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL) +#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) + + +#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : 0) + +#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0) +#define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12) + + +/*******************************************************************************/ +/* I2C Master Interface */ + +#define MXC_CFG_I2CM_INSTANCES (2) + +#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL) +#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL) +#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) +#define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL) +#define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL) + +#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL) +#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL) +#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) +#define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL) +#define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL) + +#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \ + (i) == 1 ? I2CM1_IRQn : 0) + +#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ + (i) == 1 ? MXC_BASE_I2CM1 : 0) + +#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ + (i) == 1 ? MXC_I2CM1 : 0) + +#define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0) + +#define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \ + (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0) + +#define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0) +#define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13) + + +/*******************************************************************************/ +/* I2C Slave Interface */ + +#define MXC_CFG_I2CS_INSTANCES (1) + +#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL) +#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL) +#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0) + +#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL) +#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0) + + + +/*******************************************************************************/ +/* DACs */ + +#define MXC_CFG_DAC_INSTANCES (4) +#define MXC_CFG_DAC_FIFO_DEPTH (32) + +#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL) +#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0) +#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL) +#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO) +#define MXC_DAC0_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL) +#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1) +#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL) +#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO) +#define MXC_DAC1_WIDTH ((uint8_t)(2)) + +#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL) +#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2) +#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL) +#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO) +#define MXC_DAC2_WIDTH ((uint8_t)(1)) + +#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL) +#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3) +#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL) +#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO) +#define MXC_DAC3_WIDTH ((uint8_t)(1)) + + +#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \ + (i) == 1 ? DAC1_IRQn : \ + (i) == 2 ? DAC2_IRQn : \ + (i) == 3 ? DAC3_IRQn : 0) + + +#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \ + i == 1 ? MXC_BASE_DAC1 : \ + i == 2 ? MXC_BASE_DAC2 : \ + i == 3 ? MXC_BASE_DAC3 : 0) + +#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \ + i == 1 ? MXC_BASE_DAC1_FIFO : \ + i == 2 ? MXC_BASE_DAC2_FIFO : \ + i == 3 ? MXC_BASE_DAC3_FIFO : 0) + +#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \ + i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \ + i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \ + i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0) + +#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \ + i == 1 ? MXC_DAC1 : \ + i == 2 ? MXC_DAC2 : \ + i == 3 ? MXC_DAC3 : 0) + +#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \ + i == 1 ? MXC_DAC1_WIDTH : \ + i == 2 ? MXC_DAC2_WIDTH : \ + i == 3 ? MXC_DAC3_WIDTH : 0) + + +/*******************************************************************************/ +/* Analog Front End */ + +#define MXC_BASE_AFE ((uint32_t)0x4005401CUL) +#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE) + + + +/*******************************************************************************/ +/* ADC */ + +#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32)) + +#define MXC_BASE_ADC ((uint32_t)0x40054000UL) +#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) + +#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL) +#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG) + +#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL) +#define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO) + + + +/*******************************************************************************/ +/* LCD */ +#define MXC_BASE_LCD ((uint32_t)0x40060000) +#define MXC_LCD ((mxc_lcd_regs_t *)MXC_BASE_LCD) + +/*******************************************************************************/ +/* Peripheral Management Unit (PMU) - formerly DMA Controller */ + +#define MXC_CFG_PMU_CHANNELS (6) + +#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL) +#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) +#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL) +#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) +#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL) +#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) +#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL) +#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) +#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL) +#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) +#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL) +#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) + +#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL) +#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL) +/*******************************************************************************/ + +typedef enum { + PMU_IRQ_DAC0_FIFO_AE, + PMU_IRQ_DAC1_FIFO_AE, + PMU_IRQ_DAC2_FIFO_AE, + PMU_IRQ_DAC3_FIFO_AE, + PMU_IRQ_DAC0_DONE, + PMU_IRQ_DAC1_DONE, + PMU_IRQ_DAC2_DONE, + PMU_IRQ_DAC3_DONE, + PMU_IRQ_ADC_FIFO_AF, + PMU_IRQ_ADC_DONE, + PMU_IRQ_I2C_MST0_DONE, + PMU_IRQ_I2C_MST1_DONE, + PMU_IRQ_SPI0_RSLTS_DONE, + PMU_IRQ_SPI1_RSLTS_DONE, + PMU_IRQ_SPI2_RSLTS_DONE, + PMU_IRQ_MAA_DONE, + PMU_IRQ_SPI0_TX_FIFO_AE, + PMU_IRQ_SPI0_RSLTS_FIFO_AF, + PMU_IRQ_SPI1_TX_FIFO_AE, + PMU_IRQ_SPI1_RSLTS_FIFO_AF, + PMU_IRQ_SPI2_TX_FIFO_AE, + PMU_IRQ_SPI3_RSLTS_FIFO_AF, + PMU_IRQ_I2C_MST0_TRANS_FIFO, + PMU_IRQ_I2C_MST0_RSLT_FIFO, + PMU_IRQ_I2C_MST1_TRANS_FIFO, + PMU_IRQ_I2C_MST2_RSLT_FIFO, + PMU_IRQ_I2C_SLV_TRANS_FIFO, + PMU_IRQ_I2C_SLV_RSLT_FIFO, + PMU_IRQ_UART0_TX_FIFO, + PMU_IRQ_UART0_RX_FIFO, + PMU_IRQ_UART1_TX_FIFO, + PMU_IRQ_UART1_RX_FIFO, + PMU_IRQ_SPI0_EXCP, + PMU_IRQ_SPI1_EXCP, + PMU_IRQ_SPI2_EXCP, + PMU_IRQ_RSVD0, + PMU_IRQ_I2C_MST0_EXCP, + PMU_IRQ_I2C_MST1_EXCP, + PMU_IRQ_I2C_SLV_EXCP, + PMU_IRQ_RSVD1, + PMU_IRQ_GPIO0, + PMU_IRQ_GPIO1, + PMU_IRQ_GPIO2, + PMU_IRQ_GPIO3, + PMU_IRQ_GPIO4, + PMU_IRQ_GPIO5, + PMU_IRQ_GPIO6, + PMU_IRQ_GPIO7, + PMU_IRQ_GPIO8, + PMU_IRQ_AFE_COMP_NMI, + PMU_IRQ_AES_ENGINE, +} pmu_int_mask_t; + +/*******************************************************************************/ +/* USB */ + +#define MXC_BASE_USB ((uint32_t)0x4010C000UL) +#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) + +#define MXC_USB_MAX_PACKET (64) +#define MXC_USB_NUM_EP (8) + + +/*******************************************************************************/ +/* Instruction Cache Controller */ + +#define MXC_BASE_ICC ((uint32_t)0x40080000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) + +/* System Manager */ + +#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL) + +/*******************************************************************************/ +/* Clock Manager */ + +#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL) +#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) + + +/*******************************************************************************/ +/* Power Manager */ + +#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL) +#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) + +/*******************************************************************************/ +/* I/O Manager */ + +#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL) +#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) + + +/*******************************************************************************/ +/* RTC: Timer/Alarms */ + +#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL) +#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) + +#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \ + i == 1 ? RTC1_IRQn : \ + i == 2 ? RTC2_IRQn : \ + i == 3 ? RTC3_IRQn : 0) + +#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL) +#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) +/*******************************************************************************/ +/* RTC: Power Sequencer */ + +#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) + +/*******************************************************************************/ +/* Trim Shadow Registers */ + +#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL) +#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM) + +/*******************************************************************************/ +/* Flash Memory Controller / Security */ + +#define MXC_BASE_FLC ((uint32_t)0x400F0000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) +#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL) +#define MXC_FLC_PAGE_SIZE_SHIFT 11 +#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) +#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT + +/*******************************************************************************/ + +#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) + +/*******************************************************************************/ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0 +#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1 +#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +/*******************************************************************************/ + +#endif /* _MAX32600_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h new file mode 100644 index 0000000000..e36b9b04e6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PMU_REGS_H_ +#define _MXC_PMU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pmu_regs.h + * @addtogroup pmu PMU + * @{ + */ + +/* Offset Register Description + ====== ======================================================== */ +typedef struct { + __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */ + __IO uint32_t cfg; /* 0x0004 Channel Configuration */ + __IO uint32_t loop; /* 0x0008 Channel Loop Counters */ + __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */ + __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */ + __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */ + __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */ + __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */ +} mxc_pmu_regs_t; + +/* + Register offsets for module PMU. +*/ +#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) +#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) +#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) +#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL) +#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL) +#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL) +#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL) +#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL) + +/* + Field positions and masks for module PMU. +*/ +#define MXC_F_PMU_CFG_ENABLE_POS 0 +#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) +#define MXC_F_PMU_CFG_LL_STOPPED_POS 2 +#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) +#define MXC_F_PMU_CFG_MANUAL_POS 3 +#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) +#define MXC_F_PMU_CFG_BUS_ERROR_POS 4 +#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) +#define MXC_F_PMU_CFG_TO_STAT_POS 6 +#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) +#define MXC_F_PMU_CFG_TO_SEL_POS 11 +#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) +#define MXC_F_PMU_CFG_PS_SEL_POS 14 +#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) +#define MXC_F_PMU_CFG_INTERRUPT_POS 16 +#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) +#define MXC_F_PMU_CFG_INT_EN_POS 17 +#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) +#define MXC_F_PMU_CFG_BURST_SIZE_POS 24 +#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) + +#define MXC_F_PMU_LOOP_COUNTER_0_POS 0 +#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) +#define MXC_F_PMU_LOOP_COUNTER_1_POS 16 +#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PMU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h new file mode 100644 index 0000000000..53936e390f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PT_REGS_H_ +#define _MXC_PT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pt_regs.h + * @addtogroup pt PT + * @{ + */ + +typedef struct { + __IO uint32_t ctrl; + __IO uint32_t resync; +} mxc_ptg_regs_t; + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */ + __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ +} mxc_pt_regs_t; + +/* + Register offsets for module PT. +*/ +#define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) +#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) +#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) + + +/* + Field positions and masks for module PT. +*/ +#define MXC_F_PT_CTRL_ENABLE_ALL_POS 1 +#define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS)) + +#define MXC_F_PT_RESYNC_PT0_POS 0 +#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) +#define MXC_F_PT_RESYNC_PT1_POS 1 +#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) +#define MXC_F_PT_RESYNC_PT2_POS 2 +#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) +#define MXC_F_PT_RESYNC_PT3_POS 3 +#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) +#define MXC_F_PT_RESYNC_PT4_POS 4 +#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) +#define MXC_F_PT_RESYNC_PT5_POS 5 +#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) +#define MXC_F_PT_RESYNC_PT6_POS 6 +#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) +#define MXC_F_PT_RESYNC_PT7_POS 7 +#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) + +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) +#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 +#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +/* + Field values and shifted values for module PT. +*/ +#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL)) +#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL)) + +#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) +#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PT_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h new file mode 100644 index 0000000000..cc717dd659 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRMAN_REGS_H_ +#define _MXC_PWRMAN_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrman_regs.h + * @addtogroup pwrman PWRMAN + * @{ + */ + +/** + * @brief Defines PAD Modes for Wake Up Detection. + */ +typedef enum { + /** WUD Mode for Selected PAD = Clear/Activate */ + MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, + /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ + MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, + /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ + MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, + /** WUD Mode for Selected PAD = No pad state change */ + MXC_E_PWRMAN_PAD_MODE_NONE +} mxc_pwrman_pad_mode_t; + +/* Offset Register Description + ====== =========================================== */ +typedef struct { + __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ + __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ + __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ + __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ + __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ + __I uint32_t rsv001C[5]; /* 0x001C */ + + __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */ + __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */ + __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */ + __IO uint32_t base_part_num; /* 0x003C Base Part Number */ + __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ + __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ + __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ +} mxc_pwrman_regs_t; + +/* + Register offsets for module PWRMAN. +*/ +#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) +#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) +#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) +#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL) +#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL) +#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) +#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) +#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) +#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) +#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) + +/* + Field positions and masks for module PWRMAN. +*/ +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 +#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 +#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 +#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 +#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 +#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18 +#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19 +#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20 +#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 +#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 +#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 +#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) + +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0 +#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 +#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3 +#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS)) +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4 +#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) + +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 +#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 +#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) + +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS)) +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31 +#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS)) + +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 +#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28 +#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS)) + +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 +#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) + +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 +#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) + +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25 +#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRMAN_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h new file mode 100644 index 0000000000..506b11bda1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h @@ -0,0 +1,299 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_PWRSEQ_REGS_H +#define _MXC_PWRSEQ_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file pwrseq_regs.h + * @addtogroup pwrseq PWRSEQ + * @{ + */ + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ + __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ + __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ + __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ + __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */ + __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ + __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ + __I uint32_t rsv001C; /* 0x001C */ + __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ + __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ +} mxc_pwrseq_regs_t; + + +/* + Register offsets for module PWRSEQ. +*/ +#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) +#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) +#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) +#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) +#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) +#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) +#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) +#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) +#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) + + +/* + Field positions and masks for module PWRSEQ. +*/ +#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 +#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 +#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 +#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4 +#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6 +#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 +#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 +#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 +#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14 +#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16 +#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18 +#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS)) +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19 +#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS)) + +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0 +#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9 +#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10 +#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13 +#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS)) +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14 +#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS)) + +#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0 +#define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5 +#define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10 +#define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15 +#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20 +#define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS)) +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25 +#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS)) + +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3 +#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5 +#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10 +#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13 +#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15 +#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16 +#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS)) +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17 +#define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS)) + +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 +#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 +#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2 +#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 +#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4 +#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5 +#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS)) +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6 +#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS)) + +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS)) +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15 +#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS)) + +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 +#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) + +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 +#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS)) + +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16 +#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS)) +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21 +#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_PWRSEQ_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h new file mode 100644 index 0000000000..3c947b028f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h @@ -0,0 +1,246 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_RTC_REGS_H +#define _MXC_RTC_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file rtc_regs.h + * @addtogroup rtc RTCTMR + * @{ + */ + +/** + * @brief Defines clock divider for 4096Hz input clock. + */ +typedef enum { + /** (4kHz) divide input clock by 2^0 = 1 */ + MXC_E_RTC_PRESCALE_DIV_2_0 = 0, + /** (2kHz) divide input clock by 2^1 = 2 */ + MXC_E_RTC_PRESCALE_DIV_2_1, + /** (1kHz) divide input clock by 2^2 = 4 */ + MXC_E_RTC_PRESCALE_DIV_2_2, + /** (512Hz) divide input clock by 2^3 = 8 */ + MXC_E_RTC_PRESCALE_DIV_2_3, + /** (256Hz) divide input clock by 2^4 = 16 */ + MXC_E_RTC_PRESCALE_DIV_2_4, + /** (128Hz) divide input clock by 2^5 = 32 */ + MXC_E_RTC_PRESCALE_DIV_2_5, + /** (64Hz) divide input clock by 2^6 = 64 */ + MXC_E_RTC_PRESCALE_DIV_2_6, + /** (32Hz) divide input clock by 2^7 = 128 */ + MXC_E_RTC_PRESCALE_DIV_2_7, + /** (16Hz) divide input clock by 2^8 = 256 */ + MXC_E_RTC_PRESCALE_DIV_2_8, + /** (8Hz) divide input clock by 2^9 = 512 */ + MXC_E_RTC_PRESCALE_DIV_2_9, + /** (4Hz) divide input clock by 2^10 = 1024 */ + MXC_E_RTC_PRESCALE_DIV_2_10, + /** (2Hz) divide input clock by 2^11 = 2048 */ + MXC_E_RTC_PRESCALE_DIV_2_11, + /** (1Hz) divide input clock by 2^12 = 4096 */ + MXC_E_RTC_PRESCALE_DIV_2_12, +} mxc_rtc_prescale_t; + +/* Offset Register Description + ====== ========================================= */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */ + __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */ + __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */ + __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */ + __I uint32_t rsv0014; /* 0x0014 */ + __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */ + __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */ + __I uint32_t rsv0020; /* 0x0020 */ + __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */ + __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */ + __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */ +} mxc_rtctmr_regs_t; + +/* + Register offsets for module RTCTMR. +*/ +#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) +#define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL) +#define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL) +#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) +#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) +#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) +#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) +#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) +#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) + +/* + Field positions and masks for module RTCTMR. +*/ +#define MXC_F_RTC_CTRL_ENABLE_POS 0 +#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) +#define MXC_F_RTC_CTRL_CLEAR_POS 1 +#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) +#define MXC_F_RTC_CTRL_PENDING_POS 2 +#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 +#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 +#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) +#define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16 +#define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 +#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 +#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 +#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20 +#define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21 +#define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 +#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 +#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 +#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 +#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 +#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) + +#define MXC_F_RTC_FLAGS_COMP0_POS 0 +#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) +#define MXC_F_RTC_FLAGS_COMP1_POS 1 +#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) +#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 +#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) +#define MXC_F_RTC_FLAGS_TRIM_POS 4 +#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 +#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 +#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 +#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 +#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 +#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 +#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) + +#define MXC_F_RTC_INTEN_COMP0_POS 0 +#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) +#define MXC_F_RTC_INTEN_COMP1_POS 1 +#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) +#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 +#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) +#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 +#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) +#define MXC_F_RTC_INTEN_TRIM_POS 4 +#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) + +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0 +#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS)) + +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0 +#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS)) + +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 +#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 +#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 +#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) + +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 +#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18 +#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS)) + +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 +#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) + +#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 +#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 +#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) +#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 +#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) + +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0 +#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS)) + +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 +#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 +#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) + +/* Offset Register Description + ====== ===================================================================== */ +typedef struct { + __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */ + __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */ + __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */ + __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */ +} mxc_rtccfg_regs_t; + +/* + Register offsets for module RTCCFG. +*/ +#define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL) +#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) +#define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_RTC_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h new file mode 100644 index 0000000000..645178ca37 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h @@ -0,0 +1,215 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_SPI_REGS_H +#define _MXC_SPI_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file spi_regs.h + * @addtogroup spi SPI + * @{ + */ + +/* Offset Register Description + ====== ============================================ */ +typedef struct { + __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */ + __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */ + __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */ + __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */ + __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */ + __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */ + __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */ + __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */ +} mxc_spi_regs_t; + +/** + * @brief TX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __O uint8_t txfifo_8; + __O uint16_t txfifo_16; + __O uint32_t txfifo_32; + }; +} mxc_spi_txfifo_regs_t; + +/** + * @brief RX FIFO register. Can do 8, 16, or 32 bit access. + */ +typedef struct { + union { + __I uint8_t rxfifo_8; + __I uint16_t rxfifo_16; + __I uint32_t rxfifo_32; + }; +} mxc_spi_rxfifo_regs_t; + +/* + Register offsets for module SPI. +*/ +#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) +#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) +#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) +#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) +#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) +#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL) +#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL) + +#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) +#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) + +/* + Field positions and masks for module SPI. +*/ +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0 +#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS)) +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3 +#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4 +#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS)) +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6 +#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8 +#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12 +#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16 +#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18 +#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS)) +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24 +#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS)) + +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0 +#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS)) +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8 +#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS)) + +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0 +#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1 +#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2 +#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS)) +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3 +#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4 +#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5 +#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6 +#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS)) +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16 +#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8 +#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24 +#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS)) + +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 +#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS)) +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1 +#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 +#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) + +#define MXC_F_SPI_INTFL_TX_STALLED_POS 0 +#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS)) +#define MXC_F_SPI_INTFL_RX_STALLED_POS 1 +#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS)) +#define MXC_F_SPI_INTFL_TX_READY_POS 2 +#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS)) +#define MXC_F_SPI_INTFL_RX_DONE_POS 3 +#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS)) +#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_INTEN_TX_STALLED_POS 0 +#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS)) +#define MXC_F_SPI_INTEN_RX_STALLED_POS 1 +#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS)) +#define MXC_F_SPI_INTEN_TX_READY_POS 2 +#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS)) +#define MXC_F_SPI_INTEN_RX_DONE_POS 3 +#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS)) +#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4 +#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS)) +#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5 +#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS)) + +#define MXC_F_SPI_FIFO_DIR_POS 0 +#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS)) +#define MXC_F_SPI_FIFO_UNIT_POS 2 +#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS)) +#define MXC_F_SPI_FIFO_SIZE_POS 4 +#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS)) +#define MXC_F_SPI_FIFO_WIDTH_POS 9 +#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS)) +#define MXC_F_SPI_FIFO_ALT_POS 11 +#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS)) +#define MXC_F_SPI_FIFO_FLOW_POS 12 +#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS)) +#define MXC_F_SPI_FIFO_DASS_POS 13 +#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_SPI_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c new file mode 100644 index 0000000000..539f7ac5f4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c @@ -0,0 +1,144 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "max32600.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "ioman_regs.h" +#include "trim_regs.h" +#include "flc_regs.h" +#include "pwrseq_regs.h" +#include "dac_regs.h" +#include "icc_regs.h" + +/* Application developer should override where necessary with different external HFX source */ +#ifndef __SYSTEM_HFX +#define __SYSTEM_HFX 8000000 +#endif + +uint32_t SystemCoreClock = 24000000; + +void SystemCoreClockUpdate(void) +{ + switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8: + SystemCoreClock = 3000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO: + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2: + SystemCoreClock = 24000000; + break; + case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX: + SystemCoreClock = __SYSTEM_HFX; + break; + } + + uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system; + if (shift) { + SystemCoreClock = SystemCoreClock >> (shift - 1); + } +} + +/* power seq registers */ +static void set_pwr_regs(void) +{ + uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff; + uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff; + dac2trim = dac2trim + MXC_TRIM->trim_reg_36; + dac3trim = dac3trim + MXC_TRIM->trim_reg_37; + MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13; + MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14; + MXC_DAC0->trm = MXC_TRIM->trim_reg_34; + MXC_DAC1->trm = MXC_TRIM->trim_reg_35; + MXC_DAC2->reg = dac2trim; + MXC_DAC3->reg = dac3trim; +} + +void ICC_Enable(void) +{ + /* clock gater must be 'on' not 'dynamic' for cache control */ + uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; + + + /* invalidate, wait, enable */ + MXC_ICC->invdt_all = 0xFFFF; + while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); + MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; + + /* must invalidate a second time for proper use */ + MXC_ICC->invdt_all = 1; + + /* clock gater 'dynamic' safe again */ + temp = MXC_CLKMAN->clk_gate_ctrl0; + temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; + temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); + MXC_CLKMAN->clk_gate_ctrl0 = temp; +} + +// This function to be implemented by the hal +extern void low_level_init(); + +void SystemInit(void) +{ + set_pwr_regs(); + + // enable instruction cache + ICC_Enable(); + + low_level_init(); + + // Clear IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE); + + // Set WUD Clear + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR); + + // Set IO Active + MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE | + MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED); + + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN; + + // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep + MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; + + SystemCoreClockUpdate(); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h new file mode 100644 index 0000000000..9bbd239f13 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef SYSTEM_MAX32600_H_ +#define SYSTEM_MAX32600_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit (void); + +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_MAX32600_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h new file mode 100644 index 0000000000..1803814ee5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TMR_REGS_H +#define _MXC_TMR_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tmr_regs.h + * @addtogroup tmr TMR + * @{ + */ + +/** + * @brief Defines timer modes for 16 and 32-bit timers + */ +typedef enum { + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_ONE_SHOT = 0, + /** 32-bit or 16-bit timer one-shot mode */ + MXC_E_TMR_MODE_CONTINUOUS, + /** 32-bit timer counter mode */ + MXC_E_TMR_MODE_COUNTER, + /** 32-bit timer pulse width modulation mode */ + MXC_E_TMR_MODE_PWM, + /** 32-bit timer capture mode */ + MXC_E_TMR_MODE_CAPTURE, + /** 32-bit timer compare mode */ + MXC_E_TMR_MODE_COMPARE, + /** 32-bit timer gated mode */ + MXC_E_TMR_MODE_GATED, + /** 32-bit timer measure mode */ + MXC_E_TMR_MODE_MEASURE +} mxc_tmr_mode_t; + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Timer Control Register */ + __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */ + __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */ + __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */ + __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */ + __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */ + __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */ + __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */ + __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */ + __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */ +} mxc_tmr_regs_t; + +/* + Register offsets for module TMR. +*/ +#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) +#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) +#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) +#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) +#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) +#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) +#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) +#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) + +/* + Field positions and masks for module TMR. +*/ +#define MXC_F_TMR_CTRL_MODE_POS 0 +#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) +#define MXC_F_TMR_CTRL_TMR2X16_POS 3 +#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) +#define MXC_F_TMR_CTRL_PRESCALE_POS 4 +#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) +#define MXC_F_TMR_CTRL_POLARITY_POS 8 +#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) +#define MXC_F_TMR_CTRL_ENABLE0_POS 12 +#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) +#define MXC_F_TMR_CTRL_ENABLE1_POS 13 +#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) + +#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) + +#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 +#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) + +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 +#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) + +#define MXC_F_TMR_INTFL_TIMER0_POS 0 +#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) +#define MXC_F_TMR_INTFL_TIMER1_POS 1 +#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) + +#define MXC_F_TMR_INTEN_TIMER0_POS 0 +#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) +#define MXC_F_TMR_INTEN_TIMER1_POS 1 +#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TMR_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h new file mode 100644 index 0000000000..1a0c8f49b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TPU_REGS_H_ +#define _MXC_TPU_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file tpu_regs.h + * @addtogroup tpu TPU + * @{ + */ + +/* Offset Register Description + ====== ================================================== */ +typedef struct { + __I uint32_t rsv0000; /* 0x0000 Reserved */ + __I uint32_t rsv0004; /* 0x0004 Reserved - PUF Control (Deprecated) */ + __I uint32_t rsv0008; /* 0x0008 Reserved - PUF Output (Deprecated) */ + __I uint32_t rsv000C[125]; /* 0x000C */ + __IO uint32_t prng_user_entropy; /* 0x0200 PRNG User Entropy Value */ + __IO uint32_t prng_rnd_num; /* 0x0204 PRNG Random Number Output */ +} mxc_tpu_regs_t; + +/* Offset Register Description + ====== ================================================= */ +typedef struct { + __IO uint32_t status; /* 0x0000 Dynamic Tamper Sensor Status */ + __IO uint32_t ctrl0; /* 0x0004 Dynamic Tamper Sensor Control 0 */ + __IO uint32_t ctrl1; /* 0x0008 Dynamic Tamper Sensor Control 1 */ + __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 0 */ + __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 0 */ +} mxc_tpu_tsr_regs_t; + +/* + Register offsets for module TPU. +*/ +#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000200UL) +#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000204UL) +#define MXC_R_TPU_TSR_OFFS_STATUS ((uint32_t)0x00000000UL) +#define MXC_R_TPU_TSR_OFFS_CTRL0 ((uint32_t)0x00000004UL) +#define MXC_R_TPU_TSR_OFFS_CTRL1 ((uint32_t)0x00000008UL) +#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL) +#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL) +#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL) +#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL) + + +/* + Field positions and masks for module TPU. +*/ +#define MXC_F_TPU_CTRL0_ERR_THR_POS 0 +#define MXC_F_TPU_CTRL0_ERR_THR ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS)) +#define MXC_F_TPU_CTRL0_OUT_FREQ_POS 5 +#define MXC_F_TPU_CTRL0_OUT_FREQ ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS)) +#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS 8 +#define MXC_F_TPU_CTRL0_CLOCK_DIV ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS)) +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS 14 +#define MXC_F_TPU_CTRL0_RTC_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS)) +#define MXC_F_TPU_CTRL0_LOCK_POS 15 +#define MXC_F_TPU_CTRL0_LOCK ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_TPU_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h new file mode 100644 index 0000000000..2c6ecac55c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h @@ -0,0 +1,92 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_TRIM_REGS_H +#define _MXC_TRIM_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef struct { + __IO uint32_t trim_reg_00; + __IO uint32_t trim_reg_01; + __IO uint32_t trim_reg_02; + __IO uint32_t trim_reg_03; + __IO uint32_t trim_reg_04; + __IO uint32_t trim_reg_05; + __IO uint32_t trim_reg_06; + __IO uint32_t trim_reg_07; + __IO uint32_t trim_reg_08; + __IO uint32_t trim_reg_09; + __IO uint32_t trim_reg_10; + __IO uint32_t trim_reg_11; + __IO uint32_t trim_reg_12; + __IO uint32_t trim_reg_13; + __IO uint32_t trim_reg_14; + __IO uint32_t trim_reg_15; + __IO uint32_t trim_reg_16; + __IO uint32_t trim_reg_17; + __IO uint32_t trim_reg_18; + __IO uint32_t trim_reg_19; + __IO uint32_t trim_reg_20; + __IO uint32_t trim_reg_21; + __IO uint32_t trim_reg_22; + __IO uint32_t trim_reg_23; + __IO uint32_t trim_reg_24; + __IO uint32_t trim_reg_25; + __IO uint32_t trim_reg_26; + __IO uint32_t trim_reg_27; + __IO uint32_t trim_reg_28; + __IO uint32_t trim_reg_29; + __IO uint32_t trim_reg_30; + __IO uint32_t trim_reg_31; + __IO uint32_t trim_reg_32; + __IO uint32_t trim_reg_33; + __IO uint32_t trim_reg_34; + __IO uint32_t trim_reg_35; + __IO uint32_t trim_reg_36; + __IO uint32_t trim_reg_37; + __IO uint32_t trim_reg_38; + __IO uint32_t trim_reg_39; + __IO uint32_t trim_reg_40; + __IO uint32_t trim_reg_41; +} mxc_ftr_regs_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_TRIM_REGS_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h new file mode 100644 index 0000000000..49fbe5d967 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h @@ -0,0 +1,175 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_UART_REGS_H_ +#define _MXC_UART_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file uart_regs.h + * @addtogroup uart UART + * @{ + */ + +/* Offset Register Description + ====== ============================================== */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 UART Control Register */ + __IO uint32_t status; /* 0x0004 UART Status Register */ + __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ + __IO uint32_t intfl; /* 0x000C Interrupt Flags */ + __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */ + __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */ + __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */ + __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */ + __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */ +} mxc_uart_regs_t; + + +/* + Register offsets for module UART. +*/ +#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL) +#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL) +#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL) +#define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL) +#define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL) +#define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL) +#define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL) +#define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL) + +/* + Field positions and masks for module UART. +*/ +#define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0 +#define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS)) +#define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4 +#define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS)) +#define MXC_F_UART_CTRL_PARITY_MODE_POS 5 +#define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS)) +#define MXC_F_UART_CTRL_PARITY_BIAS_POS 6 +#define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS)) +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8 +#define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9 +#define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS)) +#define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10 +#define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS)) +#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12 +#define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS)) +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13 +#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS)) +#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14 +#define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS)) + +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4 +#define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5 +#define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6 +#define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7 +#define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS)) +#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8 +#define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS)) +#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12 +#define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS)) + +#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTEN_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS)) +#define MXC_F_UART_INTEN_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS)) +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0 +#define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS)) +#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1 +#define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS)) +#define MXC_F_UART_INTFL_CTS_CHANGE_POS 2 +#define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS)) +#define MXC_F_UART_INTFL_RX_OVERRUN_POS 3 +#define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS)) +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4 +#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS)) +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5 +#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS)) +#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6 +#define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS)) + +#define MXC_F_UART_BAUD_INT_FBAUD_POS 0 +#define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS)) + +#define MXC_F_UART_BAUD_DIV_128_DIV_POS 0 +#define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS)) + +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0 +#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS)) + +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0 +#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS)) +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1 +#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS)) + +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0 +#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS)) +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8 +#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_UART_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h new file mode 100644 index 0000000000..6f2b9b8e03 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h @@ -0,0 +1,480 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_USB_REGS_H_ +#define _MXC_USB_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file usb_regs.h + * @addtogroup usb USB + * @{ + */ + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t cn; /* 0x0000 USB Control Register */ + __I uint32_t rsv0004[127]; /* 0x0004 */ + __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ + __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ + __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ + __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ + __I uint32_t rsv0210[4]; /* 0x0210 */ + __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ + __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ + __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ + __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ + __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ + __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ + __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ + __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ + __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ + __I uint32_t rsv0244[7]; /* 0x0244 */ + __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ + __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ + __I uint32_t rsv0268[6]; /* 0x0268 */ + __IO uint32_t ep[MXC_USB_NUM_EP]; /* 0x0280 USB Endpoint Control Registers */ +} mxc_usb_regs_t; + + +/* + Register offsets for module USB. +*/ +#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) +#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) +#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) +#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) +#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) +#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) +#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) +#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) +#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) +#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) +#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) +#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) +#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) +#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) +#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) +#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) +#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) +#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) +#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) +#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) +#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) +#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) +#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) +#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) + + +/* + Field positions and masks for module USB. +*/ +#define MXC_F_USB_CN_USB_EN_POS 0 +#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) + +#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 +#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) + +#define MXC_F_USB_DEV_CN_SIGRWU_POS 2 +#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) +#define MXC_F_USB_DEV_CN_CONNECT_POS 3 +#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) +#define MXC_F_USB_DEV_CN_ULPM_POS 4 +#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) +#define MXC_F_USB_DEV_CN_URST_POS 5 +#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) +#define MXC_F_USB_DEV_CN_VBGATE_POS 6 +#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) +#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 +#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) + +#define MXC_F_USB_DEV_INTFL_DPACT_POS 0 +#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) +#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTFL_BACT_POS 2 +#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_POS 3 +#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) +#define MXC_F_USB_DEV_INTFL_SUSP_POS 4 +#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) +#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_POS 6 +#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) +#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTFL_SETUP_POS 8 +#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) +#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) +#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) +#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 +#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) + +#define MXC_F_USB_DEV_INTEN_DPACT_POS 0 +#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) +#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 +#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) +#define MXC_F_USB_DEV_INTEN_BACT_POS 2 +#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_POS 3 +#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) +#define MXC_F_USB_DEV_INTEN_SUSP_POS 4 +#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) +#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 +#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_VBUS_POS 6 +#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) +#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 +#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) +#define MXC_F_USB_DEV_INTEN_SETUP_POS 8 +#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) +#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 +#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) +#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 +#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) +#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 +#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) +#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 +#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) +#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 +#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) + +#define MXC_F_USB_EP_BASE_EP_BASE_POS 9 +#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) + +#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 +#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) +#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 +#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) + +#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 +#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 +#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) + +#define MXC_F_USB_IN_INT_INBAV0_POS 0 +#define MXC_F_USB_IN_INT_INBAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS)) +#define MXC_F_USB_IN_INT_INBAV1_POS 1 +#define MXC_F_USB_IN_INT_INBAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS)) +#define MXC_F_USB_IN_INT_INBAV2_POS 2 +#define MXC_F_USB_IN_INT_INBAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS)) +#define MXC_F_USB_IN_INT_INBAV3_POS 3 +#define MXC_F_USB_IN_INT_INBAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS)) +#define MXC_F_USB_IN_INT_INBAV4_POS 4 +#define MXC_F_USB_IN_INT_INBAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS)) +#define MXC_F_USB_IN_INT_INBAV5_POS 5 +#define MXC_F_USB_IN_INT_INBAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS)) +#define MXC_F_USB_IN_INT_INBAV6_POS 6 +#define MXC_F_USB_IN_INT_INBAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS)) +#define MXC_F_USB_IN_INT_INBAV7_POS 7 +#define MXC_F_USB_IN_INT_INBAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS)) + +#define MXC_F_USB_OUT_INT_OUTDAV0_POS 0 +#define MXC_F_USB_OUT_INT_OUTDAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV1_POS 1 +#define MXC_F_USB_OUT_INT_OUTDAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV2_POS 2 +#define MXC_F_USB_OUT_INT_OUTDAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV3_POS 3 +#define MXC_F_USB_OUT_INT_OUTDAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV4_POS 4 +#define MXC_F_USB_OUT_INT_OUTDAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV5_POS 5 +#define MXC_F_USB_OUT_INT_OUTDAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV6_POS 6 +#define MXC_F_USB_OUT_INT_OUTDAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS)) +#define MXC_F_USB_OUT_INT_OUTDAV7_POS 7 +#define MXC_F_USB_OUT_INT_OUTDAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS)) + +#define MXC_F_USB_NAK_INT_NAK0_POS 0 +#define MXC_F_USB_NAK_INT_NAK0 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS)) +#define MXC_F_USB_NAK_INT_NAK1_POS 1 +#define MXC_F_USB_NAK_INT_NAK1 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS)) +#define MXC_F_USB_NAK_INT_NAK2_POS 2 +#define MXC_F_USB_NAK_INT_NAK2 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS)) +#define MXC_F_USB_NAK_INT_NAK3_POS 3 +#define MXC_F_USB_NAK_INT_NAK3 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS)) +#define MXC_F_USB_NAK_INT_NAK4_POS 4 +#define MXC_F_USB_NAK_INT_NAK4 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS)) +#define MXC_F_USB_NAK_INT_NAK5_POS 5 +#define MXC_F_USB_NAK_INT_NAK5 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS)) +#define MXC_F_USB_NAK_INT_NAK6_POS 6 +#define MXC_F_USB_NAK_INT_NAK6 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS)) +#define MXC_F_USB_NAK_INT_NAK7_POS 7 +#define MXC_F_USB_NAK_INT_NAK7 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS)) + +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS 0 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS 1 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS 2 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS 3 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS 4 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS 5 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS 6 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS)) +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS 7 +#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS)) + +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS 0 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS 1 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS 2 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS 3 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS 4 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS 5 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS 6 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS)) +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS 7 +#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS)) + +#define MXC_F_USB_SETUP0_BYTE0_POS 0 +#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) +#define MXC_F_USB_SETUP0_BYTE1_POS 8 +#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) +#define MXC_F_USB_SETUP0_BYTE2_POS 16 +#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) +#define MXC_F_USB_SETUP0_BYTE3_POS 24 +#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) + +#define MXC_F_USB_SETUP1_BYTE4_POS 0 +#define MXC_F_USB_SETUP1_BYTE4 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS)) +#define MXC_F_USB_SETUP1_BYTE5_POS 8 +#define MXC_F_USB_SETUP1_BYTE5 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS)) +#define MXC_F_USB_SETUP1_BYTE6_POS 16 +#define MXC_F_USB_SETUP1_BYTE6 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS)) +#define MXC_F_USB_SETUP1_BYTE7_POS 24 +#define MXC_F_USB_SETUP1_BYTE7 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS)) + +#define MXC_F_USB_EP0_EP_DIR_POS 0 +#define MXC_F_USB_EP0_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS)) +#define MXC_F_USB_EP0_EP_BUF2_POS 3 +#define MXC_F_USB_EP0_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS)) +#define MXC_F_USB_EP0_EP_INT_EN_POS 4 +#define MXC_F_USB_EP0_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS)) +#define MXC_F_USB_EP0_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP0_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS)) +#define MXC_F_USB_EP0_EP_DT_POS 6 +#define MXC_F_USB_EP0_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS)) +#define MXC_F_USB_EP0_EP_STALL_POS 8 +#define MXC_F_USB_EP0_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP0_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS)) +#define MXC_F_USB_EP0_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP0_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP1_EP_DIR_POS 0 +#define MXC_F_USB_EP1_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS)) +#define MXC_F_USB_EP1_EP_BUF2_POS 3 +#define MXC_F_USB_EP1_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS)) +#define MXC_F_USB_EP1_EP_INT_EN_POS 4 +#define MXC_F_USB_EP1_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS)) +#define MXC_F_USB_EP1_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP1_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS)) +#define MXC_F_USB_EP1_EP_DT_POS 6 +#define MXC_F_USB_EP1_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS)) +#define MXC_F_USB_EP1_EP_STALL_POS 8 +#define MXC_F_USB_EP1_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP1_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS)) +#define MXC_F_USB_EP1_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP1_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP2_EP_DIR_POS 0 +#define MXC_F_USB_EP2_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS)) +#define MXC_F_USB_EP2_EP_BUF2_POS 3 +#define MXC_F_USB_EP2_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS)) +#define MXC_F_USB_EP2_EP_INT_EN_POS 4 +#define MXC_F_USB_EP2_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS)) +#define MXC_F_USB_EP2_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP2_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS)) +#define MXC_F_USB_EP2_EP_DT_POS 6 +#define MXC_F_USB_EP2_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS)) +#define MXC_F_USB_EP2_EP_STALL_POS 8 +#define MXC_F_USB_EP2_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP2_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS)) +#define MXC_F_USB_EP2_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP2_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP3_EP_DIR_POS 0 +#define MXC_F_USB_EP3_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS)) +#define MXC_F_USB_EP3_EP_BUF2_POS 3 +#define MXC_F_USB_EP3_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS)) +#define MXC_F_USB_EP3_EP_INT_EN_POS 4 +#define MXC_F_USB_EP3_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS)) +#define MXC_F_USB_EP3_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP3_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS)) +#define MXC_F_USB_EP3_EP_DT_POS 6 +#define MXC_F_USB_EP3_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS)) +#define MXC_F_USB_EP3_EP_STALL_POS 8 +#define MXC_F_USB_EP3_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP3_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS)) +#define MXC_F_USB_EP3_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP3_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP4_EP_DIR_POS 0 +#define MXC_F_USB_EP4_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS)) +#define MXC_F_USB_EP4_EP_BUF2_POS 3 +#define MXC_F_USB_EP4_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS)) +#define MXC_F_USB_EP4_EP_INT_EN_POS 4 +#define MXC_F_USB_EP4_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS)) +#define MXC_F_USB_EP4_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP4_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS)) +#define MXC_F_USB_EP4_EP_DT_POS 6 +#define MXC_F_USB_EP4_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS)) +#define MXC_F_USB_EP4_EP_STALL_POS 8 +#define MXC_F_USB_EP4_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP4_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS)) +#define MXC_F_USB_EP4_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP4_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP5_EP_DIR_POS 0 +#define MXC_F_USB_EP5_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS)) +#define MXC_F_USB_EP5_EP_BUF2_POS 3 +#define MXC_F_USB_EP5_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS)) +#define MXC_F_USB_EP5_EP_INT_EN_POS 4 +#define MXC_F_USB_EP5_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS)) +#define MXC_F_USB_EP5_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP5_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS)) +#define MXC_F_USB_EP5_EP_DT_POS 6 +#define MXC_F_USB_EP5_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS)) +#define MXC_F_USB_EP5_EP_STALL_POS 8 +#define MXC_F_USB_EP5_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP5_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS)) +#define MXC_F_USB_EP5_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP5_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP6_EP_DIR_POS 0 +#define MXC_F_USB_EP6_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS)) +#define MXC_F_USB_EP6_EP_BUF2_POS 3 +#define MXC_F_USB_EP6_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS)) +#define MXC_F_USB_EP6_EP_INT_EN_POS 4 +#define MXC_F_USB_EP6_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS)) +#define MXC_F_USB_EP6_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP6_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS)) +#define MXC_F_USB_EP6_EP_DT_POS 6 +#define MXC_F_USB_EP6_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS)) +#define MXC_F_USB_EP6_EP_STALL_POS 8 +#define MXC_F_USB_EP6_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP6_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS)) +#define MXC_F_USB_EP6_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP6_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP7_EP_DIR_POS 0 +#define MXC_F_USB_EP7_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS)) +#define MXC_F_USB_EP7_EP_BUF2_POS 3 +#define MXC_F_USB_EP7_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS)) +#define MXC_F_USB_EP7_EP_INT_EN_POS 4 +#define MXC_F_USB_EP7_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS)) +#define MXC_F_USB_EP7_EP_NAK_EN_POS 5 +#define MXC_F_USB_EP7_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS)) +#define MXC_F_USB_EP7_EP_DT_POS 6 +#define MXC_F_USB_EP7_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS)) +#define MXC_F_USB_EP7_EP_STALL_POS 8 +#define MXC_F_USB_EP7_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_STALL_POS 9 +#define MXC_F_USB_EP7_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS)) +#define MXC_F_USB_EP7_EP_ST_ACK_POS 10 +#define MXC_F_USB_EP7_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS)) + +#define MXC_F_USB_EP_DIR_POS (0) +#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS)) + +#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL) +#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL) +#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL) +#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL) + +#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS) +#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS) + +#define MXC_F_USB_EP_BUF2_POS (3) +#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS)) +#define MXC_F_USB_EP_INTEN_POS (4) +#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INTEN_POS)) +#define MXC_F_USB_EP_NAK_EN_POS (5) +#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS)) +#define MXC_F_USB_EP_DT_POS (6) +#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS)) +#define MXC_F_USB_EP_STALL_POS (8) +#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS)) +#define MXC_F_USB_EP_ST_STALL_POS (9) +#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS)) +#define MXC_F_USB_EP_ST_ACK_POS (10) +#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_USB_REGS_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h new file mode 100644 index 0000000000..906e801460 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef _MXC_WDT_REGS_H_ +#define _MXC_WDT_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @file wdt_regs.h + * @addtogroup wdt WDT + * @{ + */ + +/** + * @brief Defines watchdog timer periods + */ +typedef enum { + /** 2^31 cycle period */ + MXC_E_WDT_PERIOD_2_31_CLKS = 0, + /** 2^30 cycle period */ + MXC_E_WDT_PERIOD_2_30_CLKS, + /** 2^29 cycle period */ + MXC_E_WDT_PERIOD_2_29_CLKS, + /** 2^28 cycle period */ + MXC_E_WDT_PERIOD_2_28_CLKS, + /** 2^27 cycle period */ + MXC_E_WDT_PERIOD_2_27_CLKS, + /** 2^26 cycle period */ + MXC_E_WDT_PERIOD_2_26_CLKS, + /** 2^25 cycle period */ + MXC_E_WDT_PERIOD_2_25_CLKS, + /** 2^24 cycle period */ + MXC_E_WDT_PERIOD_2_24_CLKS, + /** 2^23 cycle period */ + MXC_E_WDT_PERIOD_2_23_CLKS, + /** 2^22 cycle period */ + MXC_E_WDT_PERIOD_2_22_CLKS, + /** 2^21 cycle period */ + MXC_E_WDT_PERIOD_2_21_CLKS, + /** 2^20 cycle period */ + MXC_E_WDT_PERIOD_2_20_CLKS, + /** 2^19 cycle period */ + MXC_E_WDT_PERIOD_2_19_CLKS, + /** 2^18 cycle period */ + MXC_E_WDT_PERIOD_2_18_CLKS, + /** 2^17 cycle period */ + MXC_E_WDT_PERIOD_2_17_CLKS, + /** 2^16 cycle period */ + MXC_E_WDT_PERIOD_2_16_CLKS, +} mxc_wdt_period_t; + +/* Offset Register Description + ====== ================================================ */ +typedef struct { + __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */ + __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */ + __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */ + __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */ + __I uint32_t rsv0010; /* 0x0010 */ + __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */ +} mxc_wdt_regs_t; + +/* + Register offsets for module WDT. +*/ +#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) +#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) +#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL) +#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL) +#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) + +#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24) +#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42) + + +/* + Field positions and masks for module WDT. +*/ +#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 +#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) +#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 +#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) +#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 +#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) +#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 +#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) +#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 +#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) + +#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 +#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) +#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 +#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) +#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 +#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) + +#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 +#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) +#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 +#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) +#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 +#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) + +#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 +#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +#endif /* _MXC_WDT_REGS_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c new file mode 100644 index 0000000000..f32942d57f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c @@ -0,0 +1,268 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "device.h" +#include "PeripheralPins.h" +#include "ioman_regs.h" + +/* + * To select a peripheral function on Maxim microcontrollers, multiple + * configurations must be made. The mbed PinMap structure only includes one + * data member to hold this information. To extend the configuration storage, + * the "function" data member is used as a pointer to a pin_function_t + * structure. This structure is defined in objects.h. The definitions below + * include the creation of the pin_function_t structures and the assignment of + * the pointers to the "function" data members. + */ + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + { P2_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P2_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P2_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_I2C_SCL[] = { + { P2_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P2_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P2_3, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, + { NC, NC, 0 } +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P7_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P7_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RX[] = { + { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P7_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P7_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_CTS[] = { + { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P1_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P7_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P7_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) }, + { NC, NC, 0 } +}; + +const PinMap PinMap_UART_RTS[] = { + { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P1_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P7_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P7_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) }, + { NC, NC, 0 } +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P0_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P1_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P0_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P1_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P0_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P1_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { P6_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) }, + { NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { +#if (defined(EM9301_CSN) && (EM9301_CSN == P0_3)) + { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) }, +#else + { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, +#endif + { P0_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P1_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P2_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, +#if (defined(EM9301_CSN) && (EM9301_CSN == P2_3)) + { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) }, +#else + { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, +#endif + { P6_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { P6_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) }, + { NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3}, + {P0_1, PWM_0, 3}, {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, + {P0_2, PWM_1, 2}, {P0_2, PWM_2, 1}, {P0_2, PWM_5, 3}, + {P0_3, PWM_1, 3}, {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, + {P0_4, PWM_2, 2}, {P0_4, PWM_4, 1}, {P0_4, PWM_6, 3}, + {P0_5, PWM_2, 3}, {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, + {P0_6, PWM_3, 2}, {P0_6, PWM_6, 1}, {P0_6, PWM_7, 3}, + {P0_7, PWM_3, 3}, {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, + + {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3}, + {P1_1, PWM_0, 3}, {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, + {P1_2, PWM_1, 2}, {P1_2, PWM_2, 1}, {P1_2, PWM_5, 3}, + {P1_3, PWM_1, 3}, {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, + {P1_4, PWM_2, 2}, {P1_4, PWM_4, 1}, {P1_4, PWM_6, 3}, + {P1_5, PWM_2, 3}, {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, + {P1_6, PWM_3, 2}, {P1_6, PWM_6, 1}, {P1_6, PWM_7, 3}, + {P1_7, PWM_3, 3}, {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, + + {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3}, + {P2_1, PWM_0, 3}, {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, + {P2_2, PWM_1, 2}, {P2_2, PWM_2, 1}, {P2_2, PWM_5, 3}, + {P2_3, PWM_1, 3}, {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, + {P2_4, PWM_2, 2}, {P2_4, PWM_4, 1}, {P2_4, PWM_6, 3}, + {P2_5, PWM_2, 3}, {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, + {P2_6, PWM_3, 2}, {P2_6, PWM_6, 1}, {P2_6, PWM_7, 3}, + {P2_7, PWM_3, 3}, {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, + + {P6_0, PWM_0, 1}, {P6_0, PWM_0, 2}, {P6_0, PWM_4, 3}, + {P6_1, PWM_0, 3}, {P6_1, PWM_1, 1}, {P6_1, PWM_4, 2}, + {P6_2, PWM_1, 2}, {P6_2, PWM_2, 1}, {P6_2, PWM_5, 3}, + {P6_3, PWM_1, 3}, {P6_3, PWM_3, 1}, {P6_3, PWM_5, 2}, + {P6_4, PWM_2, 2}, {P6_4, PWM_4, 1}, {P6_4, PWM_6, 3}, + {P6_5, PWM_2, 3}, {P6_5, PWM_5, 1}, {P6_5, PWM_6, 2}, + {P6_6, PWM_3, 2}, {P6_6, PWM_6, 1}, {P6_6, PWM_7, 3}, + {P6_7, PWM_3, 3}, {P6_7, PWM_7, 1}, {P6_7, PWM_7, 2}, + + {P7_0, PWM_0, 1}, {P7_0, PWM_0, 2}, {P7_0, PWM_4, 3}, + {P7_1, PWM_0, 3}, {P7_1, PWM_1, 1}, {P7_1, PWM_4, 2}, + {P7_2, PWM_1, 2}, {P7_2, PWM_2, 1}, {P7_2, PWM_5, 3}, + {P7_3, PWM_1, 3}, {P7_3, PWM_3, 1}, {P7_3, PWM_5, 2}, + {P7_4, PWM_2, 2}, {P7_4, PWM_4, 1}, {P7_4, PWM_6, 3}, + {P7_5, PWM_2, 3}, {P7_5, PWM_5, 1}, {P7_5, PWM_6, 2}, + {P7_6, PWM_3, 2}, {P7_6, PWM_6, 1}, {P7_6, PWM_7, 3}, + {P7_7, PWM_3, 3}, {P7_7, PWM_7, 1}, {P7_7, PWM_7, 2}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {AIN_0P, ADC, 0}, + {AIN_1P, ADC, 0}, + {AIN_2P, ADC, 0}, + {AIN_3P, ADC, 0}, + {AIN_4P, ADC, 0}, + {AIN_5P, ADC, 0}, + {AIN_6P, ADC, 0}, + {AIN_7P, ADC, 0}, + + {AIN_0N, ADC, 0}, + {AIN_1N, ADC, 0}, + {AIN_2N, ADC, 0}, + {AIN_3N, ADC, 0}, + {AIN_4N, ADC, 0}, + {AIN_5N, ADC, 0}, + {AIN_6N, ADC, 0}, + {AIN_7N, ADC, 0}, + + {AIN_0D, ADC, 1}, + {AIN_1D, ADC, 1}, + {AIN_2D, ADC, 1}, + {AIN_3D, ADC, 1}, + {AIN_4D, ADC, 1}, + {AIN_5D, ADC, 1}, + {AIN_6D, ADC, 1}, + {AIN_7D, ADC, 1}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {AOUT_AO, DAC0, 0}, + {AOUT_BO, DAC1, 0}, + {AOUT_CO, DAC2, 0}, + {AOUT_DO, DAC3, 0}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h new file mode 100644 index 0000000000..c06ab368b6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h new file mode 100644 index 0000000000..3327949078 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h @@ -0,0 +1,55 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h new file mode 100644 index 0000000000..150331bae2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1, + STDIO_UART = UART_1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPI0, + SPI_1 = MXC_BASE_SPI1, + SPI_2 = MXC_BASE_SPI2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +typedef enum { + DAC0 = MXC_BASE_DAC0, + DAC1 = MXC_BASE_DAC1, + DAC2 = MXC_BASE_DAC2, + DAC3 = MXC_BASE_DAC3, +} DACName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h new file mode 100644 index 0000000000..ae9cf84df7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h @@ -0,0 +1,267 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = MXC_V_GPIO_OUT_MODE_HIGH_Z, + PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +typedef enum { + P0_0 = (0 << PORT_SHIFT) | 0, + P0_1 = (0 << PORT_SHIFT) | 1, + P0_2 = (0 << PORT_SHIFT) | 2, + P0_3 = (0 << PORT_SHIFT) | 3, + P0_4 = (0 << PORT_SHIFT) | 4, + P0_5 = (0 << PORT_SHIFT) | 5, + P0_6 = (0 << PORT_SHIFT) | 6, + P0_7 = (0 << PORT_SHIFT) | 7, + + P1_0 = (1 << PORT_SHIFT) | 0, + P1_1 = (1 << PORT_SHIFT) | 1, + P1_2 = (1 << PORT_SHIFT) | 2, + P1_3 = (1 << PORT_SHIFT) | 3, + P1_4 = (1 << PORT_SHIFT) | 4, + P1_5 = (1 << PORT_SHIFT) | 5, + P1_6 = (1 << PORT_SHIFT) | 6, + P1_7 = (1 << PORT_SHIFT) | 7, + + P2_0 = (2 << PORT_SHIFT) | 0, + P2_1 = (2 << PORT_SHIFT) | 1, + P2_2 = (2 << PORT_SHIFT) | 2, + P2_3 = (2 << PORT_SHIFT) | 3, + P2_4 = (2 << PORT_SHIFT) | 4, + P2_5 = (2 << PORT_SHIFT) | 5, + P2_6 = (2 << PORT_SHIFT) | 6, + P2_7 = (2 << PORT_SHIFT) | 7, + + P3_0 = (3 << PORT_SHIFT) | 0, + P3_1 = (3 << PORT_SHIFT) | 1, + P3_2 = (3 << PORT_SHIFT) | 2, + P3_3 = (3 << PORT_SHIFT) | 3, + P3_4 = (3 << PORT_SHIFT) | 4, + P3_5 = (3 << PORT_SHIFT) | 5, + P3_6 = (3 << PORT_SHIFT) | 6, + P3_7 = (3 << PORT_SHIFT) | 7, + + P4_0 = (4 << PORT_SHIFT) | 0, + P4_1 = (4 << PORT_SHIFT) | 1, + P4_2 = (4 << PORT_SHIFT) | 2, + P4_3 = (4 << PORT_SHIFT) | 3, + P4_4 = (4 << PORT_SHIFT) | 4, + P4_5 = (4 << PORT_SHIFT) | 5, + P4_6 = (4 << PORT_SHIFT) | 6, + P4_7 = (4 << PORT_SHIFT) | 7, + + P5_0 = (5 << PORT_SHIFT) | 0, + P5_1 = (5 << PORT_SHIFT) | 1, + P5_2 = (5 << PORT_SHIFT) | 2, + P5_3 = (5 << PORT_SHIFT) | 3, + P5_4 = (5 << PORT_SHIFT) | 4, + P5_5 = (5 << PORT_SHIFT) | 5, + P5_6 = (5 << PORT_SHIFT) | 6, + P5_7 = (5 << PORT_SHIFT) | 7, + + P6_0 = (6 << PORT_SHIFT) | 0, + P6_1 = (6 << PORT_SHIFT) | 1, + P6_2 = (6 << PORT_SHIFT) | 2, + P6_3 = (6 << PORT_SHIFT) | 3, + P6_4 = (6 << PORT_SHIFT) | 4, + P6_5 = (6 << PORT_SHIFT) | 5, + P6_6 = (6 << PORT_SHIFT) | 6, + P6_7 = (6 << PORT_SHIFT) | 7, + + P7_0 = (7 << PORT_SHIFT) | 0, + P7_1 = (7 << PORT_SHIFT) | 1, + P7_2 = (7 << PORT_SHIFT) | 2, + P7_3 = (7 << PORT_SHIFT) | 3, + P7_4 = (7 << PORT_SHIFT) | 4, + P7_5 = (7 << PORT_SHIFT) | 5, + P7_6 = (7 << PORT_SHIFT) | 6, + P7_7 = (7 << PORT_SHIFT) | 7, + + // Analog ADC pins + AIN_0P = (0xA << PORT_SHIFT) | 0, + AIN_1P = (0xA << PORT_SHIFT) | 1, + AIN_2P = (0xA << PORT_SHIFT) | 2, + AIN_3P = (0xA << PORT_SHIFT) | 3, + AIN_4P = (0xA << PORT_SHIFT) | 4, + AIN_5P = (0xA << PORT_SHIFT) | 5, + AIN_6P = (0xA << PORT_SHIFT) | 6, + AIN_7P = (0xA << PORT_SHIFT) | 7, + + AIN_0N = (0xB << PORT_SHIFT) | 0, + AIN_1N = (0xB << PORT_SHIFT) | 1, + AIN_2N = (0xB << PORT_SHIFT) | 2, + AIN_3N = (0xB << PORT_SHIFT) | 3, + AIN_4N = (0xB << PORT_SHIFT) | 4, + AIN_5N = (0xB << PORT_SHIFT) | 5, + AIN_6N = (0xB << PORT_SHIFT) | 6, + AIN_7N = (0xB << PORT_SHIFT) | 7, + + // Analog differential ADC + AIN_0D = (0xC << PORT_SHIFT) | 0, + AIN_1D = (0xC << PORT_SHIFT) | 1, + AIN_2D = (0xC << PORT_SHIFT) | 2, + AIN_3D = (0xC << PORT_SHIFT) | 3, + AIN_4D = (0xC << PORT_SHIFT) | 4, + AIN_5D = (0xC << PORT_SHIFT) | 5, + AIN_6D = (0xC << PORT_SHIFT) | 6, + AIN_7D = (0xC << PORT_SHIFT) | 7, + + // OPAMP Positive supply pins + AOUT_AP = (0xD << PORT_SHIFT) | 0, + AOUT_BP = (0xD << PORT_SHIFT) | 1, + AOUT_CP = (0xD << PORT_SHIFT) | 2, + AOUT_DP = (0xD << PORT_SHIFT) | 3, + + // OPAMP Negative supply pins + AOUT_AN = (0xE << PORT_SHIFT) | 0, + AOUT_BN = (0xE << PORT_SHIFT) | 1, + AOUT_CN = (0xE << PORT_SHIFT) | 2, + AOUT_DN = (0xE << PORT_SHIFT) | 3, + + // DAC Output pins + AOUT_AO = (0xF << PORT_SHIFT) | 0, + AOUT_BO = (0xF << PORT_SHIFT) | 1, + AOUT_CO = (0xF << PORT_SHIFT) | 2, + AOUT_DO = (0xF << PORT_SHIFT) | 3, + + LED_GREEN = P7_4, + LED_RED = P7_0, + LED_YELLOW = P6_6, + LED_BLUE = P7_6, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_YELLOW, + + // Push button + SW2 = P6_4, + SW3 = P6_5, + + // UART pins + USBTX = P7_3, + USBRX = P7_2, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + + // I2C pins + I2C0_SCL = P2_4, + I2C0_SDA = P2_5, + + I2C1_SCL = P2_7, + I2C1_SDA = P2_6, + + // UART pins + UART0_RX = P1_0, + UART0_TX = P1_1, + UART0_CTS = P1_2, + UART0_RTS = P1_3, + + UART1_RX = P1_2, + UART1_TX = P1_3, + UART1_CTS = P2_6, + UART1_RTS = P2_7, + + // SPI pins + SPI0_SCK = P6_0, + SPI0_MOSI = P6_1, + SPI0_MISO = P6_2, + SPI0_SS = P6_3, + + SPI2_SCK = P2_0, + SPI2_MOSI = P2_1, + SPI2_MISO = P2_2, + SPI2_SS = P2_3, + + // Arduino Headers + D0 = P1_0, + D1 = P1_1, + D2 = P1_2, + D3 = P1_3, + D4 = P1_4, + D5 = P1_5, + D6 = P1_6, + D7 = P1_7, + D8 = P2_5, + D9 = P2_4, + D10 = P2_3, + D11 = P2_1, + D12 = P2_2, + D13 = P2_0, + D14 = P2_6, + D15 = P2_7, + A0 = AIN_0P, + A1 = AIN_1P, + A2 = AIN_2P, + A3 = AIN_3P, + A4 = AIN_4P, + A5 = AIN_5P, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c new file mode 100644 index 0000000000..0130c5f0a3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c @@ -0,0 +1,88 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "cmsis.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +/* Application developer should override where necessary with different external HFX source */ +#ifndef __SYSTEM_HFX +#define __SYSTEM_HFX 24000000 +#endif + +//****************************************************************************** +// This function will get called early in system initialization +void low_level_init(void) +{ + /* wait for the RO to stabilize */ + while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_RING_STABLE)); + + /* Configure and enable the oscillator */ + if (!(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE)) { + + MXC_CLKMAN->clk_config = (0x4 << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS); + + /* Enable the external crystal */ + MXC_CLKMAN->clk_config |= MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE; + } + + /* Wait for external crystal to stabilize */ + for (volatile int waitcnt = 0; waitcnt < 0x4000; waitcnt++); // 0x4000 ~10ms 0x10000 ~35ms, 0x20000 ~75ms + + /* Configure the PLL */ + uint32_t clk_config = MXC_CLKMAN->clk_config; + clk_config = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT) | (MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS); + +#if (__SYSTEM_HFX == 8000000) + clk_config = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS); +#elif (__SYSTEM_HFX == 12000000) + clk_config = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS); +#elif (__SYSTEM_HFX == 24000000) + clk_config = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS); +#else +#error Invalid __SYSTEM_HFX setting +#endif + + clk_config |= MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE; + clk_config &= ~MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS; + clk_config = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT) | (MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS); + MXC_CLKMAN->clk_config = clk_config; + + /* Enable the PLL and wait for stable */ + MXC_CLKMAN->clk_config |= (MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE | MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N); + while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_PLL_STABLE)); + + /* Switch to the PLL */ + MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) | + ((MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)); +} \ No newline at end of file diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c new file mode 100644 index 0000000000..e7d89bb6f2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogin_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +#define PGA_TRK_CNT 0x1F +#define ADC_ACT_CNT 0x1 +#define ADC_PGA_CNT 0x1 +#define ADC_ACQ_CNT 0x1 +#define ADC_SLP_CNT 0x1 + +//****************************************************************************** +void analogin_init(analogin_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC); + + // Set the object pointer + obj->adc = MXC_ADC; + obj->adccfg = MXC_ADCCFG; + obj->adc_fifo = MXC_ADC_FIFO; + obj->adc_pin = pin; + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup and hold window + MXC_SET_FIELD(&obj->adc->tg_ctrl0, MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT, PGA_TRK_CNT); + + // Setup sampling count and timing + MXC_SET_FIELD(&obj->adc->tg_ctrl1, (MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT | + MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT | MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT), + ((ADC_PGA_CNT << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS) | + (ADC_ACQ_CNT << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS) | + (ADC_SLP_CNT << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS) | + (MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT))); +} + +//****************************************************************************** +float analogin_read(analogin_t *obj) +{ + // Convert integer to float + return (((float)analogin_read_u16(obj)/(float)0xFFFF)); +} + +//****************************************************************************** +uint16_t analogin_read_u16(analogin_t *obj) +{ + // Set the pin to take readings from + unsigned mux_pos; + unsigned diff = 0; + if(obj->adc_pin >> PORT_SHIFT == 0xB) { + mux_pos = (obj->adc_pin & 0xF) + 8; + } else { + mux_pos = (obj->adc_pin & 0xF); + } + + if(obj->adc_pin >> PORT_SHIFT == 0xC) { + diff = 1; + mux_pos = (obj->adc_pin & 0xF) + 8; + } + + // Reset the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_RST; + + // Enable the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN; + + // Setup the ADC clock + MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE | + MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL), + ((MXC_E_ADC_MODE_SMPLCNT_FULL_RATE << MXC_F_ADC_CTRL0_ADC_MODE_POS) | + (MXC_E_ADC_AVG_MODE_FILTER_OUTPUT << MXC_F_ADC_CTRL0_AVG_MODE_POS) | + (0x2 << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS) | + MXC_F_ADC_CTRL0_ADC_CLK_EN)); + + // Setup the input multiplexor + MXC_SET_FIELD(&obj->adc->pga_ctrl, (MXC_F_ADC_PGA_CTRL_MUX_CH_SEL | + MXC_F_ADC_PGA_CTRL_MUX_DIFF | MXC_F_ADC_PGA_CTRL_PGA_GAIN), + ((mux_pos << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS) | + (diff << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))); + + // Setup voltage reference + MXC_SET_FIELD(&MXC_AFE->ctrl1, MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL, + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Clear the done bit + obj->adc->intr = MXC_F_ADC_INTR_DONE_IF; + + // Take one sample + obj->adc->tg_ctrl0 |= (1 << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS); + + // Set the start bit to take the sample + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_START; + + // Wait for the conversion to complete + while(!(obj->adc->intr & MXC_F_ADC_INTR_DONE_IF)) {} + + // Get sample from the fifo + uint16_t sample = (uint16_t)(obj->adc->out & 0xFFFF); + + // Disable ADC + obj->adc->ctrl0 &= ~MXC_F_ADC_CTRL0_CPU_ADC_EN; + + return (sample - 1); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c new file mode 100644 index 0000000000..c17b06e8b5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c @@ -0,0 +1,212 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "analogout_api.h" +#include "clkman_regs.h" +#include "pwrman_regs.h" +#include "afe_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void analogout_init(dac_t *obj, PinName pin) +{ + // Make sure pin is an analog pin we can use for ADC + DACName dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT((DACName)dac != (DACName)NC); + + // Set the object pointer + obj->dac = ((mxc_dac_regs_t*)MXC_DAC_GET_DAC((pin & 0x3))); + obj->dac_fifo = ((mxc_dac_fifo_t*)MXC_DAC_GET_FIFO((pin & 0x3))); + obj->index = (pin & 0x3); + + // Set the ADC clock to the system clock frequency + MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT, + (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << + MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))); + + + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_14_dac0 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP0; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_A | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS) | + (0x0 << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP0); + break; + case 1: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_15_dac1 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP1; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_B | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS) | + (0x1 << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP1); + + break; + case 2: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_16_dac2 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP2; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_C | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS) | + (0x2 << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP2); + break; + case 3: + // Enable DAC clock + MXC_CLKMAN->clk_ctrl_17_dac3 = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable OPAMP + MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP3; + + // Set the positive and negative inputs + MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_D | + MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3), + ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS) | + (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS) | + (0x3 << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))); + + // Enable N and P channel inputs + MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 | + MXC_F_AFE_CTRL3_EN_NCH_OPAMP3); + break; + } + + // Enable AFE power + MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; + + // Setup internal voltage references + MXC_SET_FIELD(&MXC_AFE->ctrl1, (MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL | MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL), + (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | + (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); + + // Disable interpolation + obj->dac->ctrl0 &= MXC_F_DAC_CTRL0_INTERP_MODE; +} + +//****************************************************************************** +void analogout_write(dac_t *obj, float value) +{ + analogout_write_u16(obj, (uint16_t)((value/1.0) * 0xFFFF)); +} + +//****************************************************************************** +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Enable the OPAMP + // Setup the OPAMP in follower mode + switch(obj->index) { + case 0: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP0; + break; + case 1: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP1; + break; + case 2: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP2; + break; + case 3: + MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP3; + break; + } + + // Output 1 sample with minimal delay + obj->dac->rate |= 0x1; + + // Set the start mode to output once data is in the FIFO + obj->dac->ctrl0 &= ~(MXC_F_DAC_CTRL0_START_MODE | MXC_F_DAC_CTRL0_OP_MODE); + + // Enable the DAC + obj->dac->ctrl0 |= (MXC_F_DAC_CTRL0_POWER_MODE_2 | + MXC_F_DAC_CTRL0_POWER_MODE_1_0 | MXC_F_DAC_CTRL0_POWER_ON | + MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START); + + if(obj->index < 2) { + obj->out = (value); + obj->dac_fifo->output_16 = (obj->out); + + } else { + // Convert 16 bits to 8 bits + obj->out = (value >> 8); + obj->dac_fifo->output_8 = (obj->out); + } +} + +//****************************************************************************** +float analogout_read(dac_t *obj) +{ + return (((float)analogout_read_u16(obj) / (float)0xFFFF) * 1.5); +} + +//****************************************************************************** +uint16_t analogout_read_u16(dac_t *obj) +{ + if(obj->index < 2) { + // Convert 12 bits to 16 bits + return (obj->out << 4); + } else { + // Convert 8 bits to 16 bits + return (obj->out << 8); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h new file mode 100644 index 0000000000..59ff712fe9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_SPI 1 + +#define DEVICE_I2C 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_ANALOGIN 1 + +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_RTC 1 + +#define DEVICE_SLEEP 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#define DEVICE_CAN 0 +#define DEVICE_ETHERNET 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c new file mode 100644 index 0000000000..2b1c1986ec --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +uint32_t gpio_set(PinName name) +{ + MBED_ASSERT(name != (PinName)NC); + pin_function(name, 0); + return 1 << PINNAME_TO_PIN(name); +} + +void gpio_init(gpio_t *obj, PinName name) +{ + obj->name = name; + if (name == (PinName)NC) { + return; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin); + obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin); + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->name, mode); +} + +void pin_dir(PinName name, PinDirection direction) +{ + MBED_ASSERT(name != (PinName)NC); + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Set function */ + MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin)); + + /* Normal input is always enabled */ + MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin)); + + /* Set requested output mode */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + out_mode &= ~(0xF << (4 * pin)); + out_mode |= (direction << (4 * pin)); + MXC_GPIO->out_mode[port] = out_mode; +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + pin_dir(obj->name, direction); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c new file mode 100644 index 0000000000..d592319f86 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c @@ -0,0 +1,167 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define NUM_PORTS 8 +#define NUM_PINS_PER_PORT 8 + +static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}}; +static gpio_irq_handler irq_handler; + +static void handle_irq(unsigned int port) +{ + uint32_t intfl, in_val; + uint32_t mask; + unsigned int pin; + + /* Read pin state */ + in_val = MXC_GPIO->in_val[port]; + + /* Read interrupts */ + intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; + + mask = 1; + + for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) { + if (intfl & mask) { + if (ids[port][pin]) { + if (in_val & mask) { + irq_handler(ids[port][pin], IRQ_RISE); + } else { + irq_handler(ids[port][pin], IRQ_FALL); + } + } + MXC_GPIO->intfl[port] = mask; /* clear interrupt */ + } + mask <<= 1; + } +} + +void gpio_irq_0(void) { handle_irq(0); } +void gpio_irq_1(void) { handle_irq(1); } +void gpio_irq_2(void) { handle_irq(2); } +void gpio_irq_3(void) { handle_irq(3); } +void gpio_irq_4(void) { handle_irq(4); } +void gpio_irq_5(void) { handle_irq(5); } +void gpio_irq_6(void) { handle_irq(6); } +void gpio_irq_7(void) { handle_irq(7); } + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +{ + if (name == NC) + return -1; + + uint8_t port = PINNAME_TO_PORT(name); + uint8_t pin = PINNAME_TO_PIN(name); + + if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) { + return 1; + } + + obj->port = port; + obj->pin = pin; + + irq_handler = handler; + + ids[port][pin] = id; + + /* register handlers */ + NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); + NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); + NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); + NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3); + NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4); + NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5); + NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6); + NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7); + + /* disable the interrupt locally */ + MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); + + /* clear a pending request */ + MXC_GPIO->intfl[port] = 1 << pin; + + /* enable the requested interrupt */ + MXC_GPIO->inten[port] |= (1 << pin); + NVIC_EnableIRQ(GPIO_P0_IRQn + port); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + /* disable interrupt */ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); + MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4)); + + ids[obj->port][obj->pin] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; + uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3; /* only supporting edge interrupts */ + + uint32_t new_mode = curr_mode; + if (event == IRQ_FALL) { + if (enable) { + new_mode |= 0x1; + } else { + new_mode &= ~0x1; + } + } else if (event == IRQ_RISE) { + if (enable) { + new_mode |= 0x2; + } else { + new_mode &= ~0x2; + } + } + + int_mode &= ~(0xF << (obj->pin*4)); + int_mode |= (new_mode << (obj->pin*4)); + MXC_GPIO->int_mode[obj->port] = int_mode; +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] |= (1 << obj->pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h new file mode 100644 index 0000000000..0c064f9068 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h @@ -0,0 +1,71 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName name; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->name != (PinName)NC); + *obj->reg_out = !!value; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->name != (PinName)NC); + return *obj->reg_in; +} + +void pin_dir(PinName name, PinDirection direction); + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->name != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c new file mode 100644 index 0000000000..cb986662db --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c @@ -0,0 +1,405 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "i2cm_regs.h" +#include "clkman_regs.h" +#include "ioman_regs.h" +#include "PeripheralPins.h" + +#define I2C_SLAVE_ADDR_READ_BIT 0x0001 + +#ifndef MXC_I2CM_TX_TIMEOUT +#define MXC_I2CM_TX_TIMEOUT 0x5000 +#endif + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 +#endif + +typedef enum { + /** 100KHz */ + MXC_E_I2CM_SPEED_100KHZ = 0, + /** 400KHz */ + MXC_E_I2CM_SPEED_400KHZ, + /** 1MHz */ + MXC_E_I2CM_SPEED_1MHZ +} i2cm_speed_t; + +/* Clock divider lookup table */ +static const uint32_t clk_div_table[3][8] = { + /* MXC_E_I2CM_SPEED_100KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_400KHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, + /* MXC_E_I2CM_SPEED_1MHZ */ + { + /* 0: */ 0, /* not supported */ + /* 1: */ 0, /* not supported */ + /* 2: */ 0, /* not supported */ + /* 3: */ 0, /* not supported */ + /* 4: */ 0, /* not supported */ + /* 5: */ 0, /* not supported */ + /* 6: */ 0, /* not supported */ + /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)), + }, +}; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c != NC); + + obj->i2c = i2c; + obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c)); + obj->start_pending = 0; + obj->stop_pending = 0; + + // configure the pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // enable the clock + MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // reset module + i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + i2c->ctrl = 0; + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + // set timeout to 255 ms and turn on the auto-stop option + i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN; + + // enable tx_fifo and rx_fifo + i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + // compute clock array index + int clki = ((SystemCoreClock + 1500000) / 3000000) - 1; + + // get clock divider settings from lookup table + if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki]; + } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) { + obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki]; + } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) { + obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki]; + } +} + +static int write_tx_fifo(i2c_t *obj, const uint16_t data) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while (*obj->txfifo) { + uint32_t intfl = obj->i2c->intfl; + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + return I2C_ERROR_NO_SLAVE; + } + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + return I2C_ERROR_BUS_BUSY; + } + timeout--; + } + *obj->txfifo = data; + + return 0; +} + +static int wait_tx_in_progress(i2c_t *obj) +{ + int timeout = MXC_I2CM_TX_TIMEOUT; + + while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout); + + uint32_t intfl = obj->i2c->intfl; + + if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) { + i2c_reset(obj); + return I2C_ERROR_NO_SLAVE; + } + + if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) { + i2c_reset(obj); + return I2C_ERROR_BUS_BUSY; + } + + return 0; +} + +int i2c_start(i2c_t *obj) +{ + obj->start_pending = 1; + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + obj->start_pending = 0; + write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP); + + return wait_tx_in_progress(obj); +} + +void i2c_reset(i2c_t *obj) +{ + obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN; + obj->i2c->intfl = 0x3FF; // clear all interrupts + obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN; + obj->start_pending = 0; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (obj->start_pending) { + obj->start_pending = 0; + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START; + } else { + data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK; + } + + if ((err = write_tx_fifo(obj, data)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + return 0; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + uint16_t fifo_value; + int err; + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + if (last) { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK; + } else { + fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT; + } + + if ((err = write_tx_fifo(obj, fifo_value)) != 0) { + return err; + } + + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + int timeout = MXC_I2CM_RX_TIMEOUT; + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + break; + } + } + + if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) { + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + return *obj->rxfifo; + } + + return -1; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int err, retval = 0; + int i; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // write the address to the fifo + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write) + return err; + } + obj->start_pending = 0; + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + // load as much of the cmd into the FIFO as possible + for (i = 0; i < length; i++) { + if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK) + retval = (retval ? retval : err); + break; + } + } + + if (stop) { + obj->stop_pending = 0; + if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + retval = (retval ? retval : err); + } + + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + int timeout = MXC_I2CM_TX_TIMEOUT; + // Wait for TX fifo to be empty + while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {} + } + + if (retval == 0) { + return length; + } + + return retval; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int err, retval = 0; + int i = length; + int timeout; + + if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + return 0; + } + + // clear all interrupts + obj->i2c->intfl = 0x3FF; + + // start + addr (read) + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) { + goto read_done; + } + obj->start_pending = 0; + + while (i > 256) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) { + goto read_done; + } + i -= 256; + } + + if (i > 1) { + if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) { + goto read_done; + } + } + + // start the transaction + obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START; + + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte + goto read_done; + } + + if (stop) { + if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + i = 0; + while (i < length) { + while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) && + (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) { + if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) { + retval = -3; + goto read_done; + } + } + + timeout = MXC_I2CM_RX_TIMEOUT; + + obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY; + + uint16_t temp = *obj->rxfifo; + + if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) { + continue; + } + data[i++] = (uint8_t) temp; + } + +read_done: + + if (stop) { + obj->stop_pending = 0; + if ((err = wait_tx_in_progress(obj)) != 0) { + retval = (retval ? retval : err); + } + } else { + obj->stop_pending = 1; + } + + if (retval == 0) { + return length; + } + + return retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h new file mode 100644 index 0000000000..442ab5e248 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "gpio_regs.h" +#include "uart_regs.h" +#include "i2cm_regs.h" +#include "spi_regs.h" +#include "pt_regs.h" +#include "adc_regs.h" +#include "dac_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + PortName port; + uint32_t mask; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; +}; + +struct gpio_irq_s { + uint8_t port; + uint8_t pin; +}; + +struct serial_s { + int index; + mxc_uart_regs_t *uart; +}; + +struct i2c_s { + int index; + mxc_i2cm_regs_t *i2c; + volatile uint16_t *txfifo; + volatile uint16_t *rxfifo; + int start_pending; + int stop_pending; +}; + +struct spi_s { + int index; + mxc_spi_regs_t *spi; + mxc_spi_rxfifo_regs_t *rxfifo; + mxc_spi_txfifo_regs_t *txfifo; +}; + +struct pwmout_s { + mxc_pt_regs_t *pwm; + int period; + int pulse_width; +}; + +struct analogin_s { + mxc_adc_regs_t *adc; + mxc_adccfg_regs_t *adccfg; + mxc_adc_fifo_regs_t * adc_fifo; + PinName adc_pin; +}; + +struct dac_s { + int index; + uint16_t out; + mxc_dac_regs_t *dac; + mxc_dac_fifo_t * dac_fifo; +}; + +typedef struct { + volatile uint32_t *reg_req; + volatile uint32_t *reg_ack; + uint32_t req_val; + uint32_t ack_mask; +} pin_function_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c new file mode 100644 index 0000000000..099c77a307 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "objects.h" +#include "gpio_regs.h" +#include "ioman_regs.h" + +void pin_function(PinName name, int function) +{ + MBED_ASSERT(name != (PinName)NC); + + if ((function >= 0) && (function <= 0xF)) { + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4)); + MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4)); + } else { + /* Assume this is a pointer to a pin function object */ + pin_function_t *obj = (pin_function_t*)function; + + if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) { + /* Request pin mapping */ + *obj->reg_req |= obj->req_val; + + /* Check for acknowledgment */ + MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val); + } + } +} + +void pin_mode(PinName name, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + /* Must set mode while retaining direction */ + + /* Get the current direction */ + uint32_t out_mode = MXC_GPIO->out_mode[port]; + uint32_t curr_mode = (out_mode >> (pin*4)) & 0xF; + PinDirection dir = PIN_OUTPUT; + if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z)) { + dir = PIN_INPUT; + } + + /* Set mode based on current direction */ + uint32_t new_mode; + if (dir == PIN_OUTPUT) { + // PullUp = not valid, + // OpenDrain = MXC_V_GPIO_OUT_MODE_OD, + // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL, + if (mode == OpenDrain) { + new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE; + } + } else { + // PullUp = MXC_V_GPIO_OUT_MODE_HIZPU, + // OpenDrain = not valid, + // PullNone = MXC_V_GPIO_OUT_MODE_HIZ, + if (mode == PullUp) { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP; + } else { + new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z; + } + } + + /* Set new mode */ + out_mode &= ~(0xF << (pin*4)); + out_mode |= (new_mode << (pin*4)); + MXC_GPIO->out_mode[port] = out_mode; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c new file mode 100644 index 0000000000..f8b7e0884c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c @@ -0,0 +1,97 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_regs.h" +#include "clkman_regs.h" + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->reg_out = &MXC_GPIO->out_val[port]; + obj->reg_in = &MXC_GPIO->in_val[port]; + + /* Ensure that the GPIO clock is enabled */ + if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) { + MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + } + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i)); + pin_dir(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + // The mode is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), dir); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + return (*obj->reg_in & obj->mask); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c new file mode 100644 index 0000000000..1a412248de --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c @@ -0,0 +1,234 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "cmsis.h" +#include "pwmout_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +//****************************************************************************** +void pwmout_init(pwmout_t* obj, PinName pin) +{ + // Make sure the pin is free for GPIO use + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT); + MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin)); + + int i = 0; + PinMap pwm = PinMap_PWM[0]; + + // Check if there is a pulse train already active on this port + int pin_func = (MXC_GPIO->func_sel[port] & (0xF << (port_pin*4))) >> (port_pin*4); + if((pin_func > 0) && (pin_func < 4)) { + // Search through PinMap_PWM to find the active PT + while(pwm.pin != (PinName)NC) { + if((pwm.pin == pin) && (pwm.function == pin_func)) { + break; + } + pwm = PinMap_PWM[++i]; + } + + } else { + // Search through PinMap_PWM to find an available PT + int i = 0; + while(pwm.pin != (PinName)NC && (i > -1)) { + pwm = PinMap_PWM[i++]; + if(pwm.pin == pin) { + // Check each instance of PT + while(1) { + // Check to see if this PT instance is already in use + if((((mxc_pt_regs_t*)pwm.peripheral)->rate_length & + MXC_F_PT_RATE_LENGTH_MODE)) { + i = -1; + break; + } + + // If all instances are in use, overwrite the last + pwm = PinMap_PWM[++i]; + if(pwm.pin != pin) { + pwm = PinMap_PWM[--i]; + i = -1; + break; + } + + } + } + } + } + + // Make sure we found an available PWM generator + MBED_ASSERT(pwm.pin != (PinName)NC); + + // Disable all pwm output + MXC_PTG->ctrl = 0; + + // Enable the clock + MXC_CLKMAN->clk_ctrl_2_pt = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Set the drive mode to normal + MXC_SET_FIELD(&MXC_GPIO->out_mode[port], (0x7 << (port_pin*4)), (MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << (port_pin*4))); + + // Set the obj pointer to the propper PWM instance + obj->pwm = (mxc_pt_regs_t*)pwm.peripheral; + + // Initialize object period and pulse width + obj->period = -1; + obj->pulse_width = -1; + + // Disable the output + obj->pwm->train = 0x0; + obj->pwm->rate_length = 0x0; + + // Configure the pin + pin_mode(pin, (PinMode)PullNone); + pin_function(pin, pwm.function); + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_us(obj, 20000); + pwmout_write (obj, 0); + + // Enable the global pwm + MXC_PTG->ctrl = MXC_F_PT_CTRL_ENABLE_ALL; +} + +//****************************************************************************** +void pwmout_free(pwmout_t* obj) +{ + // Set the registers to the reset value + obj->pwm->train = 0; + obj->pwm->rate_length = 0x08000000; +} + +//****************************************************************************** +static void pwmout_update(pwmout_t* obj) +{ + // Calculate and set the divider ratio + int div = (obj->period * (SystemCoreClock/1000000))/32; + if (div < 2){ + div = 2; + } + MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); + + // Change the duty cycle to adjust the pulse width + obj->pwm->train = (0xFFFFFFFF << (32-((32*obj->pulse_width)/obj->period))); +} + + +//****************************************************************************** +void pwmout_write(pwmout_t* obj, float percent) +{ + // Saturate percent if outside of range + if(percent < 0.0) { + percent = 0.0; + } else if(percent > 1.0) { + percent = 1.0; + } + + // Resize the pulse width to set the duty cycle + pwmout_pulsewidth_us(obj, (int)(percent*obj->period)); +} + +//****************************************************************************** +float pwmout_read(pwmout_t* obj) +{ + // Check for when pulsewidth or period equals 0 + if((obj->pulse_width == 0) || (obj->period == 0)){ + return 0; + } + + // Return the duty cycle + return ((float)obj->pulse_width / (float)obj->period); +} + +//****************************************************************************** +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_period_us(pwmout_t* obj, int us) +{ + // Check the range of the period + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Set pulse width to half the period if uninitialized + if(obj->pulse_width == -1){ + obj->pulse_width = us/2; + } + + // Save the period + obj->period = us; + + // Update the registers + pwmout_update(obj); +} + +//****************************************************************************** +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0)); +} + +//****************************************************************************** +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms*1000); +} + +//****************************************************************************** +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + // Check the range of the pulsewidth + MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32))); + + // Initialize period to double the pulsewidth if uninitialized + if(obj->period == -1){ + obj->period = 2*us; + } + + // Save the pulsewidth + obj->pulse_width = us; + + // Update the register + pwmout_update(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c new file mode 100644 index 0000000000..033420d4ad --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "rtc_api.h" +#include "cmsis.h" +#include "rtc_regs.h" +#include "pwrseq_regs.h" +#include "clkman_regs.h" + +static int rtc_inited = 0; +static volatile uint32_t overflow_cnt = 0; +static uint32_t overflow_alarm = 0; + +//****************************************************************************** +static void overflow_handler(void) +{ + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; + overflow_cnt++; + + if (overflow_cnt == overflow_alarm) { + // Enable the comparator interrupt for the alarm + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } +} + +//****************************************************************************** +static void alarm_handler(void) +{ + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; +} + +//****************************************************************************** +void rtc_init(void) +{ + if(rtc_inited) { + return; + } + rtc_inited = 1; + + // Enable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED; + + // Enable the clock to the RTC + MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; + + // Set the divider from the 4kHz clock + MXC_RTCTMR->prescale = MXC_E_RTC_PRESCALE_DIV_2_0; + + // Enable the overflow interrupt + MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW; + + // Prepare interrupt handlers + NVIC_SetVector(RTC0_IRQn, (uint32_t)alarm_handler); + NVIC_EnableIRQ(RTC0_IRQn); + NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler); + NVIC_EnableIRQ(RTC3_IRQn); + + // Enable the RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; +} + +//****************************************************************************** +void rtc_free(void) +{ + if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) { + // Clear and disable RTC + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR; + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; + + // Wait for pending transactions + while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + } + + // Disable the clock to the RTC + MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); + + // Disable the clock to the synchronizer + MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED; +} + +//****************************************************************************** +int rtc_isenabled(void) +{ + return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE); +} + +//****************************************************************************** +time_t rtc_read(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + return (timer_cnt >> shift_amt) + (ovf_cnt_1 << (32 - shift_amt)); +} + +//****************************************************************************** +uint64_t rtc_read_us(void) +{ + unsigned int shift_amt; + uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt; + uint64_t currentUs; + + // Account for a change in the default prescaler + shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Ensure coherency between overflow_cnt and timer + do { + ovf_cnt_1 = overflow_cnt; + timer_cnt = MXC_RTCTMR->timer; + ovf_cnt_2 = overflow_cnt; + } while (ovf_cnt_1 != ovf_cnt_2); + + currentUs = (((uint64_t)timer_cnt * 1000000) >> shift_amt) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - shift_amt)); + + return currentUs; +} + +//****************************************************************************** +void rtc_write(time_t t) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating + MXC_RTCTMR->timer = t << shift_amt; + overflow_cnt = t >> (32 - shift_amt); + MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating +} + +//****************************************************************************** +void rtc_set_wakeup(uint64_t wakeupUs) +{ + // Account for a change in the default prescaler + unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale; + + // Disable the alarm while it is prepared + MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0; + MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt + + overflow_alarm = (wakeupUs >> (32 - shift_amt)) / 1000000; + + if (overflow_alarm == overflow_cnt) { + MXC_RTCTMR->comp[0] = (wakeupUs << shift_amt) / 1000000; + MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; + } + + // Enable wakeup from RTC + MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER | MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c new file mode 100644 index 0000000000..34fc49ce8a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c @@ -0,0 +1,355 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "serial_api.h" +#include "uart_regs.h" +#include "PeripheralPins.h" + +#define UART_NUM 2 +#define DEFAULT_BAUD 9600 +#define DEFAULT_STOP 1 +#define DEFAULT_PARITY ParityNone + +#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \ + MXC_F_UART_INTFL_RX_PARITY_ERROR | \ + MXC_F_UART_INTFL_RX_OVERRUN) + +// Variables for managing the stdio UART +int stdio_uart_inited; +serial_t stdio_uart; + +// Variables for interrupt driven +static uart_irq_handler irq_handler; +static uint32_t serial_irq_ids[UART_NUM]; + +//****************************************************************************** +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine which uart is associated with each pin + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + // Make sure that both pins are pointing to the same uart + MBED_ASSERT(uart != (UARTName)NC); + + // Set the obj pointer to the proper uart + obj->uart = (mxc_uart_regs_t*)uart; + + // Set the uart index + obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart); + + // Configure the pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // Flush the RX and TX FIFOs, clear the settings + obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH); + + // Disable interrupts + obj->uart->inten = 0; + obj->uart->intfl = 0; + + // Configure to default settings + serial_baud(obj, DEFAULT_BAUD); + serial_format(obj, 8, ParityNone, 1); + + // Manage stdio UART + if(uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +//****************************************************************************** +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t idiv = 0, ddiv = 0, div = 0; + + // Calculate the integer and decimal portions + div = SystemCoreClock / ((baudrate / 100) * 128); + idiv = (div / 100); + ddiv = (div - idiv * 100) * 128 / 100; + + obj->uart->baud_int = idiv; + obj->uart->baud_div_128 = ddiv; + + // Enable the baud clock + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + +//****************************************************************************** +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + + // Check the validity of the inputs + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || + (parity == ParityEven) || (parity == ParityForced1) || + (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + // Adjust the stop and data bits + stop_bits -= 1; + data_bits -= 5; + + // Adjust the parity setting + int paren = 0, mode = 0; + switch (parity) { + case ParityNone: + paren = 0; + mode = 0; + break; + case ParityOdd : + paren = 1; + mode = 0; + break; + case ParityEven: + paren = 1; + mode = 1; + break; + case ParityForced1: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + case ParityForced0: + // Hardware does not support forced parity + MBED_ASSERT(0); + break; + default: + paren = 1; + mode = 0; + break; + } + + obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) | + (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) | + (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) | + (mode << MXC_F_UART_CTRL_PARITY_MODE_POS)); +} + +//****************************************************************************** +void uart_handler(mxc_uart_regs_t* uart, int id) +{ + // Check for errors or RX Threshold + if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) { + irq_handler(serial_irq_ids[id], RxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS); + } + + // Check for TX Threshold + if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) { + irq_handler(serial_irq_ids[id], TxIrq); + uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY); + } +} + +void uart0_handler(void) +{ + uart_handler(MXC_UART0, 0); +} +void uart1_handler(void) +{ + uart_handler(MXC_UART1, 1); +} + +//****************************************************************************** +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +//****************************************************************************** +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if(obj->index == 0) { + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + } else { + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + } + + if(irq == RxIrq) { + // Set the RX FIFO Threshold to 1 + obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD; + obj->uart->ctrl |= 0x1; + // Enable RX FIFO Threshold Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | + UART_ERRORS); + } + + } else if (irq == TxIrq) { + // Enable TX Almost empty Interrupt + if(enable) { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } else { + // Clear pending interrupts + obj->uart->intfl = 0; + obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY; + } + + } else { + MBED_ASSERT(0); + } +} + + +//****************************************************************************** +int serial_getc(serial_t *obj) +{ + int c; + + // Wait for data to be available + while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {} + c = obj->uart->tx_rx_fifo & 0xFF; + + // Echo characters for stdio + if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { + obj->uart->tx_rx_fifo = c; + } + + return c; +} + +//****************************************************************************** +void serial_putc(serial_t *obj, int c) +{ + // Append a carriage return for stdio + if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = '\r'; + } + + // Wait for TXFIFO to not be full + while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} + obj->uart->tx_rx_fifo = c; + +} + +//****************************************************************************** +int serial_readable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY)); +} + +//****************************************************************************** +int serial_writable(serial_t *obj) +{ + return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL)); +} + +//****************************************************************************** +void serial_clear(serial_t *obj) +{ + // Clear the rx and tx fifos + obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH ); +} + + +//****************************************************************************** +void serial_break_set(serial_t *obj) +{ + // Make sure that nothing is being sent + while(obj->uart->status & MXC_F_UART_STATUS_RX_BUSY) {} + + // Disable the clock to pause any transmission + obj->uart->ctrl &= ~MXC_F_UART_CTRL_BAUD_CLK_EN ; +} + +//****************************************************************************** +void serial_break_clear(serial_t *obj) +{ + obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN; +} + + +//****************************************************************************** +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + + +//****************************************************************************** +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + if(FlowControlNone == type) { + // Disable hardware flow control + obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN); + return; + } + + // Check to see if we can use HW flow control + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_cts != (UARTName)NC); + + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + } + + if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) { + // Make sure pin is in the PinMap + MBED_ASSERT(uart_rts != (UARTName)NC); + + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + } + + if(FlowControlRTSCTS == type){ + // Make sure that the pins are pointing to the same UART + MBED_ASSERT(uart != (UARTName)NC); + } + + // Enable hardware flow control + obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN; +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c new file mode 100644 index 0000000000..3eb9154f03 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c @@ -0,0 +1,169 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "sleep_api.h" +#include "us_ticker_api.h" +#include "cmsis.h" +#include "pwrman_regs.h" +#include "pwrseq_regs.h" +#include "ioman_regs.h" +#include "rtc_regs.h" + +#define MIN_DEEP_SLEEP_US 500 + +uint64_t rtc_read_us(void); +void rtc_set_wakeup(uint64_t wakeupUs); +void us_ticker_deinit(void); +void us_ticker_set(timestamp_t timestamp); + +static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART; + +// Normal wait mode +void sleep(void) +{ + // Normal sleep mode for ARM core + SCB->SCR = 0; + + __DSB(); + __WFI(); +} + +// Work-around for issue of clearing power sequencer I/O flag +static void clearAllGPIOWUD(void) +{ + uint32_t wud_req0 = MXC_IOMAN->wud_req0; + uint32_t wud_req1 = MXC_IOMAN->wud_req1; + + // I/O must be a wakeup detect to clear + MXC_IOMAN->wud_req0 = 0xffffffff; + MXC_IOMAN->wud_req1 = 0xffffffff; + + // Clear all WUDs + MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL; + MXC_PWRMAN->wud_pulse0 = 1; + + // Restore WUD requests + MXC_IOMAN->wud_req0 = wud_req0; + MXC_IOMAN->wud_req1 = wud_req1; +} + +// Low-power stop mode +void deepsleep(void) +{ + uint64_t sleepStartRtcUs; + uint32_t sleepStartTickerUs; + int32_t sleepDurationUs; + uint64_t sleepEndRtcUs; + uint64_t elapsedUs; + + __disable_irq(); + + // Wait for all STDIO characters to be sent. The UART clock will stop. + while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY); + + // Record the current times + sleepStartRtcUs = rtc_read_us(); + sleepStartTickerUs = us_ticker_read(); + + // Get the next mbed timer expiration + timestamp_t next_event = 0; + us_ticker_get_next_timestamp(&next_event); + sleepDurationUs = next_event - sleepStartTickerUs; + + if (sleepDurationUs < MIN_DEEP_SLEEP_US) { + /* The next wakeup is too soon. */ + __enable_irq(); + return; + } + + // Disable the us_ticker. It won't be clocked in DeepSleep + us_ticker_deinit(); + + // Prepare to wakeup from the RTC + rtc_set_wakeup(sleepStartRtcUs + sleepDurationUs); + + // Prepare for LP1 + uint32_t reg0 = MXC_PWRSEQ->reg0; + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode + if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run + reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode + } else { + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode + } + reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode + reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1 + reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag + MXC_PWRSEQ->reg0 = reg0; + + MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS); + + // Deep sleep for ARM core + SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; + + // clear latches for wakeup detect + MXC_PWRSEQ->flags = MXC_PWRSEQ->flags; + if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) { + // attempt work-around for I/O flag clearing issue + clearAllGPIOWUD(); + MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP; + } + + // Wait for pending RTC transaction + while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING); + + // Ensure that the event register is clear + __SEV(); // set event + __WFE(); // clear event + + // Enter LP1 + __WFE(); + // Woke up from LP1 + + // The RTC timer does not update until the next tick + uint64_t tempUs = rtc_read_us(); + do { + sleepEndRtcUs = rtc_read_us(); + } while(sleepEndRtcUs == tempUs); + + // Get the elapsed time from the RTC. Wakeup could have been from some other event. + elapsedUs = sleepEndRtcUs - sleepStartRtcUs; + + // Update the us_ticker. It was not clocked during DeepSleep + us_ticker_init(); + us_ticker_set(sleepStartTickerUs + elapsedUs); + us_ticker_get_next_timestamp(&next_event); + us_ticker_set_interrupt(next_event); + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c new file mode 100644 index 0000000000..0dda7cdd0c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c @@ -0,0 +1,190 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "spi_api.h" +#include "pinmap.h" +#include "ioman_regs.h" +#include "clkman_regs.h" +#include "PeripheralPins.h" + +#define DEFAULT_CHAR 8 +#define DEFAULT_MODE 0 +#define DEFAULT_FREQ 1000000 + +// Formatting settings +static int spi_bits; + +//****************************************************************************** +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Make sure pins are pointing to the same SPI instance + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl; + + // Give the application the option to manually control Slave Select + if((SPIName)spi_ssel != (SPIName)NC) { + spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + } else { + spi_cntl = spi_sclk; + } + + SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((SPIName)spi != (SPIName)NC); + + // Set the obj pointer to the proper SPI Instance + obj->spi = (mxc_spi_regs_t*)spi; + + // Set the SPI index and FIFOs + obj->index = MXC_SPI_BASE_TO_INSTANCE(obj->spi); + obj->rxfifo = MXC_SPI_GET_RXFIFO(obj->index); + obj->txfifo = MXC_SPI_GET_TXFIFO(obj->index); + + // Configure the pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + // Enable SPI and FIFOs + obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN | + MXC_F_SPI_GEN_CTRL_TX_FIFO_EN | + MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ); + + // Give instance the default settings + spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0); + spi_frequency(obj, DEFAULT_FREQ); +} + +//****************************************************************************** +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Check the validity of the inputs + MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3))); + + // Only supports master mode + MBED_ASSERT(!slave); + + // Save formatting data + spi_bits = bits; + + // Set the mode + obj->spi->mstr_cfg &= ~(MXC_F_SPI_MSTR_CFG_SPI_MODE); + obj->spi->mstr_cfg |= (mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS); +} + +//****************************************************************************** +void spi_frequency(spi_t *obj, int hz) +{ + // Maximum frequency is half the system frequency + MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2)); + unsigned clocks = ((SystemCoreClock/2)/(hz)); + + // Figure out the divider ratio + int clk_div = 1; + while(clk_div < 10) { + if(clocks < 0x10) { + break; + } + clk_div++; + clocks = clocks >> 1; + } + + // Turn on the SPI clock + if(obj->index == 0) { + MXC_CLKMAN->clk_ctrl_3_spi0 = clk_div; + } else if(obj->index == 1) { + MXC_CLKMAN->clk_ctrl_4_spi1 = clk_div; + } else if(obj->index == 2) { + MXC_CLKMAN->clk_ctrl_5_spi2 = clk_div; + } else { + MBED_ASSERT(0); + } + + // Set the number of clocks to hold sclk high and low + MXC_SET_FIELD(&obj->spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK), + ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))); +} + +//****************************************************************************** +int spi_master_write(spi_t *obj, int value) +{ + int bits = spi_bits; + if(spi_bits == 32) { + bits = 0; + } + // Create the header + uint16_t header = ((0x3 << MXC_F_SPI_FIFO_DIR_POS ) | // TX and RX + (0x0 << MXC_F_SPI_FIFO_UNIT_POS) | // Send bits + (bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units + (0x1 << MXC_F_SPI_FIFO_DASS_POS)); // Deassert SS + + // Send the message header + obj->txfifo->txfifo_16 = header; + + // Send the data + if(spi_bits < 17) { + obj->txfifo->txfifo_16 = (uint16_t)value; + } else { + obj->txfifo->txfifo_32 = (uint32_t)value; + } + + // Get the data + bits = spi_bits; + int result = 0; + int i = 0; + while(bits > 0) { + // Wait for data + while(((obj->spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) + >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1) {} + + result |= (obj->rxfifo->rxfifo_8 << (i++*8)); + bits-=8; + } + + return result; +} + +//****************************************************************************** +int spi_busy(spi_t *obj) +{ + return !(obj->spi->intfl & MXC_F_SPI_INTFL_TX_READY); +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c new file mode 100644 index 0000000000..b129ae5b69 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c @@ -0,0 +1,261 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_error.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "tmr_regs.h" + +#define US_TIMER MXC_TMR0 +#define US_TIMER_IRQn TMR0_IRQn + +static int us_ticker_inited = 0; +static uint32_t ticks_per_us; +static uint32_t tick_win; +static volatile uint64_t current_cnt; // Hold the current ticks +static volatile uint64_t event_cnt; // Holds the value of the next event + +#define ticks_to_us(ticks) ((ticks) / ticks_per_us); +#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) + +//****************************************************************************** +static inline void inc_current_cnt(uint32_t inc) { + + // Overflow the ticker when the us ticker overflows + current_cnt += inc; + if(current_cnt > MAX_TICK_VAL) { + current_cnt -= (MAX_TICK_VAL + 1); + } +} + +//****************************************************************************** +static inline int event_passed(uint64_t current, uint64_t event) { + + // Determine if the event has already happened. + // If the event is behind the current ticker, within a window, + // then the event has already happened. + if(((current < tick_win) && ((event < current) || + (event > (MAX_TICK_VAL - (tick_win - current))))) || + ((event < current) && (event > (current - tick_win)))) { + return 1; + } + + return 0; +} + +//****************************************************************************** +static inline uint64_t event_diff(uint64_t current, uint64_t event) { + + // Check to see if the ticker will overflow before the event + if(current <= event) { + return (event - current); + } + + return ((MAX_TICK_VAL - current) + event); +} + +//****************************************************************************** +static void tmr_handler(void) +{ + uint32_t term_cnt32 = US_TIMER->term_cnt32; + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + + inc_current_cnt(term_cnt32); + + if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { + // the timestamp has expired + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } else { + + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + + // Since the timer keeps counting after the terminal value is reached, it is possible that the new + // terminal value is in the past. + if (US_TIMER->term_cnt32 < US_TIMER->count32) { + // the timestamp has expired + US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + event_cnt = -1; // reset to max value + us_ticker_irq_handler(); + } + } + } +} + +//****************************************************************************** +void us_ticker_init(void) +{ + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + current_cnt = 0; + event_cnt = -1; // initialize to max value + + if (SystemCoreClock <= 1000000) { + error("us_ticker cannot operate at this SystemCoreClock"); + return; + } + + // Configure timer for 32-bit continuous mode with /1 prescaler + US_TIMER->ctrl = MXC_E_TMR_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS | (0 << MXC_F_TMR_CTRL_PRESCALE_POS); + ticks_per_us = SystemCoreClock / 1000000; + + // Set the tick window to 10ms + tick_win = SystemCoreClock/100; + + // Set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->pwm_cap32 = 0xFFFFFFFF; + US_TIMER->count32 = 0; + + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear pending interrupts + + NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler); + NVIC_EnableIRQ(US_TIMER_IRQn); + + US_TIMER->inten |= MXC_F_TMR_INTEN_TIMER0; // enable interrupts + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_deinit(void) +{ + US_TIMER->ctrl = 0; // disable timer + US_TIMER->inten = 0; // disable interrupts + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupts + us_ticker_inited = 0; +} + +//****************************************************************************** +uint32_t us_ticker_read(void) +{ + uint64_t current_cnt1, current_cnt2; + uint32_t term_cnt, tmr_cnt; + int intfl1, intfl2; + + if (!us_ticker_inited) + us_ticker_init(); + + // Ensure coherency between current_cnt and US_TIMER->count32 + do { + current_cnt1 = current_cnt; + intfl1 = US_TIMER->intfl; + term_cnt = US_TIMER->term_cnt32; + tmr_cnt = US_TIMER->count32; + intfl2 = US_TIMER->intfl; + current_cnt2 = current_cnt; + } while ((current_cnt1 != current_cnt2) || (intfl1 != intfl2)); + + if (intfl1) { + current_cnt1 += term_cnt; + } + + current_cnt1 += tmr_cnt; + + return (current_cnt1 / ticks_per_us); +} + +//****************************************************************************** +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Note: interrupts are disabled before this function is called. + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + + if (US_TIMER->intfl) { + US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt + NVIC_ClearPendingIRQ(US_TIMER_IRQn); + inc_current_cnt(US_TIMER->term_cnt32); + } + + // add and reset the current count value + inc_current_cnt(US_TIMER->count32); + US_TIMER->count32 = 0; + + // add the number of cycles that the timer is disabled here for + inc_current_cnt(200); + + event_cnt = (uint64_t)timestamp * ticks_per_us; + + // Check to see if the event has already passed + if (!event_passed(current_cnt, event_cnt)) { + uint64_t diff = event_diff(current_cnt, event_cnt); + if (diff < (uint64_t)0xFFFFFFFF) { + // the event occurs before the next overflow + US_TIMER->term_cnt32 = diff; + } else { + // the event occurs after the next overflow + US_TIMER->term_cnt32 = 0xFFFFFFFF; // set to max + } + } else { + // the requested timestamp occurs in the past + // set the timer up to immediately expire + US_TIMER->term_cnt32 = 1; + } + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer +} + +//****************************************************************************** +void us_ticker_disable_interrupt(void) +{ + // There are no more events, set timer overflow to the max + US_TIMER->term_cnt32 = 0xFFFFFFFF; +} + +//****************************************************************************** +void us_ticker_clear_interrupt(void) +{ + // cleared in the local handler +} + +//****************************************************************************** +void us_ticker_set(timestamp_t timestamp) +{ + US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer + current_cnt = (uint64_t)timestamp * ticks_per_us; + US_TIMER->count32 = 0; + US_TIMER->term_cnt32 = 0xFFFFFFFF; + US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer + + if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) { + // The next timestamp has elapsed. Trigger the interrupt to handle it. + NVIC_SetPendingIRQ(US_TIMER_IRQn); + } +} diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index 530046c741..23d72be0ee 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -301,7 +301,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_STM32F303RE) #define INITIAL_SP (0x20010000UL) -#elif defined(TARGET_MAX32610) +#elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600) #define INITIAL_SP (0x20008000UL) #else diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 0b836cd419..f6c5de83c5 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -51,7 +51,7 @@ #ifndef OS_TASKCNT # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -67,7 +67,7 @@ #ifndef OS_SCHEDULERSTKSIZE # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -168,7 +168,7 @@ #elif defined(TARGET_STM32F401VC) # define OS_CLOCK 84000000 -#elif defined(TARGET_MAX32610) +#elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600) # define OS_CLOCK 24000000 # else diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 7af87699b0..88f65ef042 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -49,6 +49,10 @@ AnalogOut out(PA_4); AnalogIn in(PC_3); AnalogOut out(PA_5); +#elif defined(TARGET_MAX32600MBED) +AnalogIn in(AIN_7P); +AnalogOut out(AOUT_DO); + #else AnalogIn in(p17); AnalogOut out(p18); diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index 075744b2a1..08fc12b784 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -41,6 +41,10 @@ DigitalIn in(D0); DigitalOut out(TP3); DigitalIn in(TP4); +#elif defined(TARGET_MAX32600MBED) +DigitalOut out(P1_0); +DigitalIn in(P4_7); + #else DigitalOut out(p5); DigitalIn in(p25); diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index fafb415474..9335651769 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -41,6 +41,10 @@ DigitalInOut d2(D7); DigitalInOut d1(TP3); DigitalInOut d2(TP4); +#elif defined(TARGET_MAX32600MBED) +DigitalInOut d1(P1_0); +DigitalInOut d2(P4_7); + #else DigitalInOut d1(p5); DigitalInOut d2(p25); diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index 610c07b07d..53da68f5b6 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -62,7 +62,6 @@ void in_handler() { #define PIN_OUT D1 #define PIN_IN D5 - #elif defined(TARGET_FF_ARDUINO) #define PIN_OUT D0 #define PIN_IN D7 @@ -71,6 +70,10 @@ void in_handler() { #define PIN_OUT P0_0 #define PIN_IN P0_1 +#elif defined(TARGET_MAX32600MBED) +#define PIN_OUT P1_0 +#define PIN_IN P4_7 + #else #define PIN_IN (p5) #define PIN_OUT (p25) diff --git a/libraries/tests/mbed/portinout/main.cpp b/libraries/tests/mbed/portinout/main.cpp index 1a30f42561..22f2c66b3b 100644 --- a/libraries/tests/mbed/portinout/main.cpp +++ b/libraries/tests/mbed/portinout/main.cpp @@ -72,6 +72,15 @@ #define P2_2 (1 << 1) #define PORT_2 Port1 +#elif defined(TARGET_MAX32600MBED) +#define P1_1 (1 << 0) // P1_0 +#define P1_2 (1 << 1) // P1_1 +#define PORT_1 Port1 + +#define P2_1 (1 << 7) // P4_7 +#define P2_2 (1 << 6) // P4_6 +#define PORT_2 Port4 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp index 3c30032493..cf8f4d2ba6 100644 --- a/libraries/tests/mbed/portout/main.cpp +++ b/libraries/tests/mbed/portout/main.cpp @@ -1,20 +1,29 @@ #include "mbed.h" # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) -# define LED1 (1 << 18) // P1.18 -# define LED2 (1 << 20) // P1.20 -# define LED3 (1 << 21) // P1.21 -# define LED4 (1 << 23) // P1.23 +# define LED_PORT Port1 +# define LED1 (1 << 18) // P1.18 +# define LED2 (1 << 20) // P1.20 +# define LED3 (1 << 21) // P1.21 +# define LED4 (1 << 23) // P1.23 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC1114) -# define LED1 (1 << 8) // P1.8 -# define LED2 (1 << 9) // P1.9 -# define LED3 (1 << 10) // P1.10 -# define LED4 (1 << 11) // P1.11 +# define LED_PORT Port1 +# define LED1 (1 << 8) // P1.8 +# define LED2 (1 << 9) // P1.9 +# define LED3 (1 << 10) // P1.10 +# define LED4 (1 << 11) // P1.11 # elif defined(TARGET_MAXWSNENV) +# define LED_PORT Port1 # define LED1 (1 << 4) // P1.4 # define LED2 (1 << 6) // P1.6 # define LED3 (1 << 7) // P1.7 # define LED4 0 +# elif defined(TARGET_MAX32600MBED) +# define LED_PORT Port7 +# define LED1 (1 << 0) // P7.0 +# define LED2 (1 << 6) // P7.6 +# define LED3 (1 << 4) // P7.4 +# define LED4 0 # endif #define LED_MASK (LED1|LED2|LED3|LED4) @@ -26,7 +35,7 @@ int mask[4] = { (LED3 | LED4) }; -PortOut ledport(Port1, LED_MASK); +PortOut ledport(LED_PORT, LED_MASK); int main() { while (1) { diff --git a/libraries/tests/mbed/portout_portin/main.cpp b/libraries/tests/mbed/portout_portin/main.cpp index 222c3c414a..6fb02990e6 100644 --- a/libraries/tests/mbed/portout_portin/main.cpp +++ b/libraries/tests/mbed/portout_portin/main.cpp @@ -72,6 +72,15 @@ #define P2_2 (1 << 1) #define PORT_2 Port1 +#elif defined(TARGET_MAX32600MBED) +#define P1_1 (1 << 0) // P1_0 +#define P1_2 (1 << 1) // P1_1 +#define PORT_1 Port1 + +#define P2_1 (1 << 7) // P4_7 +#define P2_2 (1 << 6) // P4_6 +#define PORT_2 Port4 + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index 99bb908b24..b7b3550098 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -157,6 +157,15 @@ int main() { printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result); notify_completion(result == value ? true : false); +#elif defined(TARGET_MAX32600MBED) + PwmOut pwm_1(P1_2); + PwmOut pwm_2(P1_3); + + pwm_1.write(0.75); + pwm_2.write(0.50); + + printf("Initialize PWM on pin P1.2 with duty cycle: %.2f\n", pwm_1.read()); + printf("Initialize PWM on pin P1.3 with duty cycle: %.2f\n", pwm_2.read()); #else #error This test is not supported on this target. #endif diff --git a/workspace_tools/export/gcc_arm_max32600mbed.tmpl b/workspace_tools/export/gcc_arm_max32600mbed.tmpl new file mode 100644 index 0000000000..68a5847a58 --- /dev/null +++ b/workspace_tools/export/gcc_arm_max32600mbed.tmpl @@ -0,0 +1,72 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m3 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 563158c495..6922b55455 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -71,6 +71,7 @@ class GccArm(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L073RZ', 'DISCO_F334C8', + 'MAX32600MBED', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'NUCLEO_L152RE', diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index 021ad9c458..9271a1ebb1 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -168,6 +168,7 @@ if __name__ == '__main__': ('gcc_arm', 'NUCLEO_F411RE'), ('gcc_arm', 'DISCO_F429ZI'), ('gcc_arm', 'NUCLEO_F334R8'), + ('gcc_arm', 'MAX32600MBED'), ('gcc_arm', 'MTS_MDOT_F405RG'), ('gcc_arm', 'MTS_MDOT_F411RE'), ('gcc_arm', 'RZ_A1H'), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index facd822090..597fc72e81 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1113,6 +1113,15 @@ class MAXWSNENV(Target): self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"] self.default_toolchain = "ARM" +class MAX32600MBED(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['Maxim', 'MAX32600'] + self.macros = ['__SYSTEM_HFX=24000000'] + self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"] + self.default_toolchain = "ARM" + # Get a single instance for each target TARGETS = [ @@ -1224,6 +1233,7 @@ TARGETS = [ ### Maxim Integrated ### MAXWSNENV(), + MAX32600MBED(), ] # Map each target name to its unique instance diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 34f9d0c7d8..55c326cae2 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -48,6 +48,7 @@ Wiring: * KL25Z: (PTA5<-> PTC6) * NUCLEO_F103RB: (PC_6 <-> PB_8) * MAXWSNENV: (TP3 <-> TP4) + * MAX32600MBED: (P1_0 <-> P4_7) * port_loop (Port(In|Out|InOut)): * Arduino headers: (D0 <-> D7), (D1 <-> D6) @@ -55,6 +56,7 @@ Wiring: * KL25Z: (PTA5 <-> PTC6), (PTA4 <-> PTC5) * NUCLEO_F103RB: (PC_6 <-> PB_8), (PC_5 <-> PB_9) * MAXWSNENV: (TP1 <-> TP3), (TP2 <-> TP4) + * MAX32600MBED: (P1_0 <-> P4_7), (P1_1 <-> P4_6) * analog_loop (AnalogIn, AnalogOut): * Arduino headers: (A0 <-> A5) @@ -139,7 +141,7 @@ TESTS = [ "mcu": ["LPC1768", "LPC2368", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", - "NUCLEO_F411RE","DISCO_F407VG","ARCH_MAX"] + "NUCLEO_F411RE", "DISCO_F407VG", "ARCH_MAX", "MAX32600MBED"] }, { "id": "MBED_A9", "description": "Serial Echo at 115200", @@ -616,7 +618,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -629,7 +631,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -642,7 +644,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -654,7 +656,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -666,7 +668,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -678,7 +680,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_7", "description": "Timer", @@ -692,7 +694,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -704,7 +706,7 @@ TESTS = [ "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV"], + "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED"], }, { "id": "RTOS_9", "description": "SD File write-read", From a14683a62a4127fa7ec2eafc21eab5e8f60a91a0 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Tue, 14 Apr 2015 10:07:21 -0500 Subject: [PATCH 116/143] [MAXWSNENV] Adjusting hal analog. --- .../hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c | 13 ++++++++----- .../TARGET_Maxim/TARGET_MAX32610/analogout_api.c | 3 +-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c index 2d64a187e0..e7d89bb6f2 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c @@ -38,11 +38,11 @@ #include "afe_regs.h" #include "PeripheralPins.h" -#define PGA_TRK_CNT 0x8 +#define PGA_TRK_CNT 0x1F #define ADC_ACT_CNT 0x1 #define ADC_PGA_CNT 0x1 #define ADC_ACQ_CNT 0x1 -#define ADC_SLP_CNT 0x0 +#define ADC_SLP_CNT 0x1 //****************************************************************************** void analogin_init(analogin_t *obj, PinName pin) @@ -100,6 +100,12 @@ uint16_t analogin_read_u16(analogin_t *obj) mux_pos = (obj->adc_pin & 0xF) + 8; } + // Reset the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_RST; + + // Enable the ADC + obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN; + // Setup the ADC clock MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE | MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL), @@ -119,9 +125,6 @@ uint16_t analogin_read_u16(analogin_t *obj) (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP | (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))); - // Enable the ADC - obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN; - // Clear the done bit obj->adc->intr = MXC_F_ADC_INTR_DONE_IF; diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c index 00ca4e9936..c17b06e8b5 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c @@ -183,8 +183,7 @@ void analogout_write_u16(dac_t *obj, uint16_t value) MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START); if(obj->index < 2) { - // Convert 16 bits to 12 bits - obj->out = (value >> 4); + obj->out = (value); obj->dac_fifo->output_16 = (obj->out); } else { From 5eb4894e7145a9ea49016a587eb70e1bac10671c Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Tue, 14 Apr 2015 13:39:29 -0500 Subject: [PATCH 117/143] Added skipped mbed library build reporting and removed unnecessary print --- workspace_tools/build_release.py | 20 +++++++++++++++---- .../library_build/build_report.html | 7 ++++++- .../tests_build/build_report.html | 7 ++++++- workspace_tools/test_api.py | 1 - 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 37a8bdcc35..3acaaf1d53 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -108,6 +108,7 @@ if __name__ == '__main__': start = time() failures = [] successes = [] + skips = [] build_report = [] for target_name, toolchain_list in OFFICIAL_MBED_LIBRARY_BUILD: if options.official_only: @@ -121,14 +122,21 @@ if __name__ == '__main__': toolchains = toolchainSet and set((options.toolchains).split(',')) - cur_target_build_report = { "target": target_name, "passing": [], "failing": []} + cur_target_build_report = { "target": target_name, "passing": [], "failing": [], "skipped": []} for toolchain in toolchains: id = "%s::%s" % (target_name, toolchain) try: - build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs) - successes.append(id) - cur_target_build_report["passing"].append({ "toolchain": toolchain }) + built_mbed_lib = build_mbed_libs(TARGET_MAP[target_name], toolchain, verbose=options.verbose, jobs=options.jobs) + + if built_mbed_lib: + successes.append(id) + cur_target_build_report["passing"].append({ "toolchain": toolchain }) + else: + skips.append(id) + cur_target_build_report["skipped"].append({ "toolchain": toolchain }) + + except Exception, e: failures.append(id) cur_target_build_report["failing"].append({ "toolchain": toolchain }) @@ -148,6 +156,10 @@ if __name__ == '__main__': print "\n\nBuild successes:" print "\n".join([" * %s" % s for s in successes]) + if skips: + print "\n\nBuild skips:" + print "\n".join([" * %s" % s for s in skips]) + if failures: print "\n\nBuild failures:" print "\n".join([" * %s" % f for f in failures]) diff --git a/workspace_tools/ci_templates/library_build/build_report.html b/workspace_tools/ci_templates/library_build/build_report.html index 24283125a3..1b2b693884 100644 --- a/workspace_tools/ci_templates/library_build/build_report.html +++ b/workspace_tools/ci_templates/library_build/build_report.html @@ -8,7 +8,7 @@ [PASS] {% endif %} - {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}} + {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}}, Skipped: {{report.skipped|length}} @@ -22,5 +22,10 @@ {% with build = report.passing %} {% include 'library_build/build_report_table.html' %} {% endwith %} + +

    Skipped

    + {% with build = report.skipped %} + {% include 'library_build/build_report_table.html' %} + {% endwith %} diff --git a/workspace_tools/ci_templates/tests_build/build_report.html b/workspace_tools/ci_templates/tests_build/build_report.html index 8b20d188cf..1e2ae7d5c9 100644 --- a/workspace_tools/ci_templates/tests_build/build_report.html +++ b/workspace_tools/ci_templates/tests_build/build_report.html @@ -8,7 +8,7 @@ [PASS] {% endif %} - {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}} + {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}}, Skipped: {{report.skipped|length}} @@ -22,5 +22,10 @@ {% with build = report.passing %} {% include 'tests_build/build_report_table.html' %} {% endwith %} + +

    Skipped

    + {% with build = report.skipped %} + {% include 'tests_build/build_report_table.html' %} + {% endwith %} diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index cf51683afc..f29fdd65e4 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -455,7 +455,6 @@ class SingleTestRunner(object): except ToolException: project_name_str = project_name if project_name is not None else test_id - print "DIS BE MAH ERRRRR: %s" % (str(ToolException)) print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) build_report[toolchain]["test_build_failing"].append(test_id) # return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext From 8dab8c4751106afd950e9b8b47af73b835987944 Mon Sep 17 00:00:00 2001 From: julbouln Date: Tue, 14 Apr 2015 20:57:56 +0200 Subject: [PATCH 118/143] Added USBMIDI tests + bugfix MIDI OUT --- libraries/USBDevice/USBMIDI/USBMIDI.cpp | 16 ++++-- libraries/tests/usb/device/midi/main.cpp | 63 +++++++++++++++++++++ workspace_tools/host_tests/midi.py | 72 ++++++++++++++++++++++++ 3 files changed, 147 insertions(+), 4 deletions(-) create mode 100644 workspace_tools/host_tests/midi.py diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/libraries/USBDevice/USBMIDI/USBMIDI.cpp index 042f4f33d3..a46f9ae77d 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.cpp +++ b/libraries/USBDevice/USBMIDI/USBMIDI.cpp @@ -31,10 +31,10 @@ void USBMIDI::write(MIDIMessage m) { for(int p=1; p < m.length; p+=3) { uint8_t buf[4]; // Midi message to USBMidi event packet - buf[0]=m.data[p] >> 4; + buf[0]=m.data[1] >> 4; // SysEx if(buf[0] == 0xF) { - if(p < m.length-1) { + if((m.length - p) > 3) { // SysEx start or continue buf[0]=0x4; } else { @@ -55,8 +55,16 @@ void USBMIDI::write(MIDIMessage m) { } } buf[1]=m.data[p]; - buf[2]=m.data[p+1]; - buf[3]=m.data[p+2]; + + if(p+1 < m.length) + buf[2]=m.data[p+1]; + else + buf[2]=0; + + if(p+2 < m.length) + buf[3]=m.data[p+2]; + else + buf[3]=0; USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK); } diff --git a/libraries/tests/usb/device/midi/main.cpp b/libraries/tests/usb/device/midi/main.cpp index 6160215c30..b0a6cd381e 100644 --- a/libraries/tests/usb/device/midi/main.cpp +++ b/libraries/tests/usb/device/midi/main.cpp @@ -4,7 +4,70 @@ USBMIDI midi; Serial pc(USBTX, USBRX); +// MIDI IN +void transmitMessage(MIDIMessage msg) { + switch (msg.type()) { + case MIDIMessage::NoteOnType: + wait(0.1); + midi.write(MIDIMessage::NoteOn(msg.key())); + break; + case MIDIMessage::NoteOffType: + wait(0.1); + midi.write(MIDIMessage::NoteOff(msg.key())); + break; + case MIDIMessage::ProgramChangeType: + wait(0.1); + midi.write(MIDIMessage::ProgramChange(msg.program())); + break; + case MIDIMessage::SysExType: + wait(0.1); + unsigned char tmp[64]; + for(int i=0;i Date: Wed, 15 Apr 2015 09:11:39 -0400 Subject: [PATCH 119/143] Replaced SPI pin definitions for K64F in SD tests The old pin definitions were all for Port D pins, which are incorrect. These improper pin mappings caused all tests to fail. Pin definitions were replaced with the definitions as stated here - http://developer.mbed.org/media/uploads/sam_grove/xk64f_sensors.jpg.pagespeed.ic.RCpM8talCK.webp Tests now pass on the K64F Sch Rev D1 --- libraries/tests/mbed/sd/main.cpp | 2 +- libraries/tests/mbed/sd_perf_fatfs/main.cpp | 2 +- libraries/tests/mbed/sd_perf_fhandle/main.cpp | 2 +- libraries/tests/mbed/sd_perf_stdio/main.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/tests/mbed/sd/main.cpp b/libraries/tests/mbed/sd/main.cpp index eb23347c99..2d1b5a19cf 100644 --- a/libraries/tests/mbed/sd/main.cpp +++ b/libraries/tests/mbed/sd/main.cpp @@ -9,7 +9,7 @@ SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); #elif defined(TARGET_K64F) -SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); +SDFileSystem sd(PTE3, PTE1, PTE2, PTE4, "sd"); #elif defined(TARGET_K22F) SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); diff --git a/libraries/tests/mbed/sd_perf_fatfs/main.cpp b/libraries/tests/mbed/sd_perf_fatfs/main.cpp index 5b5e83b953..6e95fec97a 100644 --- a/libraries/tests/mbed/sd_perf_fatfs/main.cpp +++ b/libraries/tests/mbed/sd_perf_fatfs/main.cpp @@ -11,7 +11,7 @@ SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); #elif defined(TARGET_K64F) -SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); +SDFileSystem sd(PTE3, PTE1, PTE2, PTE4, "sd"); #elif defined(TARGET_K22F) SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); diff --git a/libraries/tests/mbed/sd_perf_fhandle/main.cpp b/libraries/tests/mbed/sd_perf_fhandle/main.cpp index 5d16b71b4d..209c948145 100644 --- a/libraries/tests/mbed/sd_perf_fhandle/main.cpp +++ b/libraries/tests/mbed/sd_perf_fhandle/main.cpp @@ -11,7 +11,7 @@ SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); #elif defined(TARGET_K64F) -SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); +SDFileSystem sd(PTE3, PTE1, PTE2, PTE4, "sd"); #elif defined(TARGET_K22F) SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); diff --git a/libraries/tests/mbed/sd_perf_stdio/main.cpp b/libraries/tests/mbed/sd_perf_stdio/main.cpp index c7ee9f35a0..46c14bcb66 100644 --- a/libraries/tests/mbed/sd_perf_stdio/main.cpp +++ b/libraries/tests/mbed/sd_perf_stdio/main.cpp @@ -11,7 +11,7 @@ SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); #elif defined(TARGET_K64F) -SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd"); +SDFileSystem sd(PTE3, PTE1, PTE2, PTE4, "sd"); #elif defined(TARGET_K22F) SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd"); From 250ce08712cabb52d7136bb4dfd3e0db6a83782f Mon Sep 17 00:00:00 2001 From: porkybrain Date: Wed, 15 Apr 2015 17:07:40 +0200 Subject: [PATCH 120/143] Changed CircBuffer to take its size as a template parameters. This results in smaller code size and less ram usage because the optimizer knows the size at compile time and it does not need to be stored in ram. It should also be faster because there is no indirection to the heap. I have not tested this code! --- libraries/USBDevice/USBSerial/CircBuffer.h | 21 +++++---------------- libraries/USBDevice/USBSerial/USBSerial.h | 4 ++-- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/libraries/USBDevice/USBSerial/CircBuffer.h b/libraries/USBDevice/USBSerial/CircBuffer.h index 78d5eecc6c..b784a72019 100644 --- a/libraries/USBDevice/USBSerial/CircBuffer.h +++ b/libraries/USBDevice/USBSerial/CircBuffer.h @@ -19,20 +19,9 @@ #ifndef CIRCBUFFER_H #define CIRCBUFFER_H -template +template class CircBuffer { public: - CircBuffer(int length) { - write = 0; - read = 0; - size = length + 1; - buf = (T *)malloc(size * sizeof(T)); - }; - - ~CircBuffer() { - free(buf); - } - bool isFull() { return ((write + 1) % size == read); }; @@ -64,10 +53,10 @@ public: }; private: - volatile uint16_t write; - volatile uint16_t read; - uint16_t size; - T * buf; + volatile uint16_t write{0}; //in case older compilers are targeted this should be done in a constructor + volatile uint16_t read{0}; + static constexpr int size{Size+1}; + T buf[Size]; }; #endif diff --git a/libraries/USBDevice/USBSerial/USBSerial.h b/libraries/USBDevice/USBSerial/USBSerial.h index e83aea6b18..164cf9bc7d 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.h +++ b/libraries/USBDevice/USBSerial/USBSerial.h @@ -56,7 +56,7 @@ public: * @param connect_blocking define if the connection must be blocked if USB not plugged in * */ - USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking), buf(128){ + USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking){ settingsChangedCallback = 0; }; @@ -154,7 +154,7 @@ protected: private: FunctionPointer rx; - CircBuffer buf; + CircBuffer buf; void (*settingsChangedCallback)(int baud, int bits, int parity, int stop); }; From e34e16d31183128f2869d24a66fcb9e133e4febc Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Thu, 16 Apr 2015 13:27:49 +0100 Subject: [PATCH 121/143] Fixed interrupt handler in serial_api.c for the Nordic NRF51. The last byte sent in a sequence would not correctly clear the interrupt flag. --- .../TARGET_MCU_NRF51822/serial_api.c | 41 ++++++++++++++----- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c index 8e3e8c34c7..4cf1819f60 100755 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c @@ -76,7 +76,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart->TXD = 0; obj->index = 0; - + obj->uart->PSELRTS = RTS_PIN_NUMBER; obj->uart->PSELTXD = tx; //TX_PIN_NUMBER; obj->uart->PSELCTS = CTS_PIN_NUMBER; @@ -162,14 +162,20 @@ extern "C" { #endif void UART0_IRQHandler() { - uint32_t irtype = 0; + if((NRF_UART0->INTENSET & UART_INTENSET_TXDRDY_Msk) && NRF_UART0->EVENTS_TXDRDY) + { + uart_irq(1, 0); - if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) { - irtype = 1; - } else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) { - irtype = 2; + /* Explicitly clear TX flag to prevent interrupt from firing + immediately after returning from ISR. This ensures that the + last interrupt in a transmission sequence is correcly handled. + */ + NRF_UART0->EVENTS_TXDRDY = 0; + } + else if((NRF_UART0->INTENSET & UART_INTENSET_RXDRDY_Msk) && NRF_UART0->EVENTS_RXDRDY) + { + uart_irq(2, 0); } - uart_irq(irtype, 0); } #ifdef __cplusplus @@ -239,11 +245,24 @@ int serial_getc(serial_t *obj) void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)) { - } + /* In interrupt mode, send character immediately. Otherwise, block until + UART is ready to receive next character before sending. - obj->uart->EVENTS_TXDRDY = 0; - obj->uart->TXD = (uint8_t)c; + The TXDRDY flag is cleared in interrupt handler to ensure that it is + cleared even if there are no more characters to send. + */ + if (NRF_UART0->INTENSET & UART_INTENSET_TXDRDY_Msk) + { + obj->uart->TXD = (uint8_t)c; + } + else + { + while (!serial_writable(obj)) { + } + + obj->uart->EVENTS_TXDRDY = 0; + obj->uart->TXD = (uint8_t)c; + } } int serial_readable(serial_t *obj) From cad87d11d4beb8d1b81f9d63cf86bbe9478d42d3 Mon Sep 17 00:00:00 2001 From: porkybrain Date: Thu, 16 Apr 2015 15:57:30 +0200 Subject: [PATCH 122/143] moved initialization into constructor for compatibility with c++03 --- libraries/USBDevice/USBSerial/CircBuffer.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/libraries/USBDevice/USBSerial/CircBuffer.h b/libraries/USBDevice/USBSerial/CircBuffer.h index b784a72019..f581f9d2df 100644 --- a/libraries/USBDevice/USBSerial/CircBuffer.h +++ b/libraries/USBDevice/USBSerial/CircBuffer.h @@ -22,6 +22,7 @@ template class CircBuffer { public: + CircBuffer():write(0), read(0){} bool isFull() { return ((write + 1) % size == read); }; @@ -53,9 +54,9 @@ public: }; private: - volatile uint16_t write{0}; //in case older compilers are targeted this should be done in a constructor - volatile uint16_t read{0}; - static constexpr int size{Size+1}; + volatile uint16_t write; + volatile uint16_t read; + static const int size = Size+1; T buf[Size]; }; From c48e5ea445697afb23a1e83a92aae940e00b10fe Mon Sep 17 00:00:00 2001 From: Odin Holmes Date: Thu, 16 Apr 2015 17:39:18 +0200 Subject: [PATCH 123/143] Update CircBuffer.h --- libraries/USBDevice/USBSerial/CircBuffer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBDevice/USBSerial/CircBuffer.h b/libraries/USBDevice/USBSerial/CircBuffer.h index f581f9d2df..ea46bdfe6f 100644 --- a/libraries/USBDevice/USBSerial/CircBuffer.h +++ b/libraries/USBDevice/USBSerial/CircBuffer.h @@ -56,7 +56,7 @@ public: private: volatile uint16_t write; volatile uint16_t read; - static const int size = Size+1; + static const int size = Size+1; //a modern optimizer should be able to remove this so it uses no ram. T buf[Size]; }; From 72d62f783b162d69d116c001a9ca9750dbaa6d61 Mon Sep 17 00:00:00 2001 From: bsilvereagle Date: Thu, 16 Apr 2015 11:47:51 -0400 Subject: [PATCH 124/143] Mentioned the Contributor Agreement in Contributing.md --- CONTRIBUTING.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 5a588ed021..353cd58c0f 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -10,6 +10,8 @@ You can for example read more in our ```docs``` section in [mbedmicro/mbed/doc]( # How to contribute We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things. +Before a pull request will be merged, the [mbed Contributor Agreement](http://developer.mbed.org/contributor_agreement/) must be signed. + You can pick up existing [mbed GitHub Issue](https://github.com/mbedmicro/mbed/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality. # Enhancements vs Bugs From 2044135c1964265b26291c8e37ed5c56f35beb69 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Thu, 9 Apr 2015 12:55:08 -0500 Subject: [PATCH 125/143] Adding export support for MAXWSNENV and MAX32600MBED. --- .../TARGET_MAX32600/system_max32600.c | 2 +- .../TARGET_MAX32610/system_max32610.c | 2 +- .../TARGET_MAX32600MBED/low_level_init.c | 2 +- .../TARGET_MAX32600/gpio_irq_api.c | 2 +- .../TARGET_Maxim/TARGET_MAX32600/us_ticker.c | 6 +- .../TARGET_MAX32610/gpio_irq_api.c | 2 +- .../TARGET_Maxim/TARGET_MAX32610/us_ticker.c | 6 +- workspace_tools/export/gcc_arm_maxwsnenv.tmpl | 72 + workspace_tools/export/gccarm.py | 1 + workspace_tools/export/iar.py | 2 + .../export/iar_max32600mbed.ewd.tmpl | 1370 +++++++++++++++++ .../export/iar_max32600mbed.ewp.tmpl | 957 ++++++++++++ workspace_tools/export/iar_maxwsnenv.ewd.tmpl | 1370 +++++++++++++++++ workspace_tools/export/iar_maxwsnenv.ewp.tmpl | 957 ++++++++++++ workspace_tools/export/uvision4.py | 4 +- .../export/uvision4_max32600mbed.uvopt.tmpl | 177 +++ .../export/uvision4_max32600mbed.uvproj.tmpl | 420 +++++ .../export/uvision4_maxwsnenv.uvopt.tmpl | 177 +++ .../export/uvision4_maxwsnenv.uvproj.tmpl | 420 +++++ workspace_tools/export_test.py | 6 + 20 files changed, 5943 insertions(+), 12 deletions(-) create mode 100644 workspace_tools/export/gcc_arm_maxwsnenv.tmpl create mode 100644 workspace_tools/export/iar_max32600mbed.ewd.tmpl create mode 100644 workspace_tools/export/iar_max32600mbed.ewp.tmpl create mode 100644 workspace_tools/export/iar_maxwsnenv.ewd.tmpl create mode 100644 workspace_tools/export/iar_maxwsnenv.ewp.tmpl create mode 100644 workspace_tools/export/uvision4_max32600mbed.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_max32600mbed.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_maxwsnenv.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_maxwsnenv.uvproj.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c index 539f7ac5f4..5357f31b37 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c @@ -109,7 +109,7 @@ void ICC_Enable(void) } // This function to be implemented by the hal -extern void low_level_init(); +extern void low_level_init(void); void SystemInit(void) { diff --git a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c index 36a77b601d..6915b24338 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c +++ b/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c @@ -109,7 +109,7 @@ void ICC_Enable(void) } // This function to be implemented by the hal -extern void low_level_init(); +extern void low_level_init(void); void SystemInit(void) { diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c index 0130c5f0a3..66dc6462eb 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c @@ -85,4 +85,4 @@ void low_level_init(void) /* Switch to the PLL */ MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) | ((MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)); -} \ No newline at end of file +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c index d592319f86..f629079567 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c @@ -117,7 +117,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 /* enable the requested interrupt */ MXC_GPIO->inten[port] |= (1 << pin); - NVIC_EnableIRQ(GPIO_P0_IRQn + port); + NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port)); return 0; } diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c index b129ae5b69..17690d5da4 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c @@ -96,7 +96,7 @@ static void tmr_handler(void) if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { // the timestamp has expired - event_cnt = -1; // reset to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value us_ticker_irq_handler(); } else { @@ -112,7 +112,7 @@ static void tmr_handler(void) US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt NVIC_ClearPendingIRQ(US_TIMER_IRQn); - event_cnt = -1; // reset to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value us_ticker_irq_handler(); } } @@ -127,7 +127,7 @@ void us_ticker_init(void) us_ticker_inited = 1; current_cnt = 0; - event_cnt = -1; // initialize to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value if (SystemCoreClock <= 1000000) { error("us_ticker cannot operate at this SystemCoreClock"); diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c index 4e153cd01a..083f064d9a 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c @@ -118,7 +118,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 /* enable the requested interrupt */ MXC_GPIO->inten[port] |= (1 << pin); - NVIC_EnableIRQ(GPIO_P0_IRQn + port); + NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port)); return 0; } diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c index b129ae5b69..17690d5da4 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c @@ -96,7 +96,7 @@ static void tmr_handler(void) if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) { // the timestamp has expired - event_cnt = -1; // reset to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value us_ticker_irq_handler(); } else { @@ -112,7 +112,7 @@ static void tmr_handler(void) US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1); // clear interrupt NVIC_ClearPendingIRQ(US_TIMER_IRQn); - event_cnt = -1; // reset to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value us_ticker_irq_handler(); } } @@ -127,7 +127,7 @@ void us_ticker_init(void) us_ticker_inited = 1; current_cnt = 0; - event_cnt = -1; // initialize to max value + event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value if (SystemCoreClock <= 1000000) { error("us_ticker cannot operate at this SystemCoreClock"); diff --git a/workspace_tools/export/gcc_arm_maxwsnenv.tmpl b/workspace_tools/export/gcc_arm_maxwsnenv.tmpl new file mode 100644 index 0000000000..68a5847a58 --- /dev/null +++ b/workspace_tools/export/gcc_arm_maxwsnenv.tmpl @@ -0,0 +1,72 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m3 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index a0e642dde6..a803e1451b 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -74,6 +74,7 @@ class GccArm(Exporter): 'NUCLEO_L073RZ', 'DISCO_F334C8', 'MAX32600MBED', + 'MAXWSNENV', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'NUCLEO_L152RE', diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index d13cdc9473..a0ca0afcd6 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -60,6 +60,8 @@ class IAREmbeddedWorkbench(Exporter): 'NUCLEO_L073RZ', 'NUCLEO_L152RE', #'STM32F407', Fails to build same for GCC + 'MAXWSNENV', + 'MAX32600MBED', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MTS_DRAGONFLY_F411RE', diff --git a/workspace_tools/export/iar_max32600mbed.ewd.tmpl b/workspace_tools/export/iar_max32600mbed.ewd.tmpl new file mode 100644 index 0000000000..c99d125078 --- /dev/null +++ b/workspace_tools/export/iar_max32600mbed.ewd.tmpl @@ -0,0 +1,1370 @@ + + + + 2 + + debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/workspace_tools/export/iar_max32600mbed.ewp.tmpl b/workspace_tools/export/iar_max32600mbed.ewp.tmpl new file mode 100644 index 0000000000..be7d8093e3 --- /dev/null +++ b/workspace_tools/export/iar_max32600mbed.ewp.tmpl @@ -0,0 +1,957 @@ + + + + 2 + + debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {{source_files}} + diff --git a/workspace_tools/export/iar_maxwsnenv.ewd.tmpl b/workspace_tools/export/iar_maxwsnenv.ewd.tmpl new file mode 100644 index 0000000000..c99d125078 --- /dev/null +++ b/workspace_tools/export/iar_maxwsnenv.ewd.tmpl @@ -0,0 +1,1370 @@ + + + + 2 + + debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/workspace_tools/export/iar_maxwsnenv.ewp.tmpl b/workspace_tools/export/iar_maxwsnenv.ewp.tmpl new file mode 100644 index 0000000000..be7d8093e3 --- /dev/null +++ b/workspace_tools/export/iar_maxwsnenv.ewp.tmpl @@ -0,0 +1,957 @@ + + + + 2 + + debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {{source_files}} + diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 1ea95a91e2..1f1c053829 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -72,7 +72,9 @@ class Uvision4(Exporter): 'NRF51_DONGLE', 'SEEED_TINY_BLE', 'LPC11U37H_401', - 'DELTA_DFCM_NNN40', + 'DELTA_DFCM_NNN40', + 'MAXWSNENV', + 'MAX32600MBED', ] USING_MICROLIB = [ diff --git a/workspace_tools/export/uvision4_max32600mbed.uvopt.tmpl b/workspace_tools/export/uvision4_max32600mbed.uvopt.tmpl new file mode 100644 index 0000000000..2f5a7b5fa0 --- /dev/null +++ b/workspace_tools/export/uvision4_max32600mbed.uvopt.tmpl @@ -0,0 +1,177 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + MAX32600MBED + 0x4 + ARM-ADS + + 24000000 + + + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 13 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +     diff --git a/workspace_tools/export/uvision4_max32600mbed.uvproj.tmpl b/workspace_tools/export/uvision4_max32600mbed.uvproj.tmpl new file mode 100644 index 0000000000..638f80a2a1 --- /dev/null +++ b/workspace_tools/export/uvision4_max32600mbed.uvproj.tmpl @@ -0,0 +1,420 @@ + + + + 1.1 + +
    ###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
    + + + + MAX32600MBED + 0x4 + ARM-ADS + + + MAX32600 + Maxim Integrated + IRAM(0x20000000, 0x8000) IROM(0, 0x40000) CLOCK(24000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_max32600.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + + + + + + + + + + + + + + + + + + + + + 0 + 0 + 1 + 1 + + + 0 + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +     diff --git a/workspace_tools/export/uvision4_maxwsnenv.uvopt.tmpl b/workspace_tools/export/uvision4_maxwsnenv.uvopt.tmpl new file mode 100644 index 0000000000..9b10a4f775 --- /dev/null +++ b/workspace_tools/export/uvision4_maxwsnenv.uvopt.tmpl @@ -0,0 +1,177 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + MAXWSNENV + 0x4 + ARM-ADS + + 24000000 + + + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 13 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +     diff --git a/workspace_tools/export/uvision4_maxwsnenv.uvproj.tmpl b/workspace_tools/export/uvision4_maxwsnenv.uvproj.tmpl new file mode 100644 index 0000000000..8566a7ee91 --- /dev/null +++ b/workspace_tools/export/uvision4_maxwsnenv.uvproj.tmpl @@ -0,0 +1,420 @@ + + + + 1.1 + +
    ###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
    + + + + MAXWSNENV + 0x4 + ARM-ADS + + + MAX32610 + Maxim Integrated + IRAM(0x20000000, 0x8000) IROM(0, 0x40000) CLOCK(24000000) CPUTYPE("Cortex-M3") + + + + + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_max32610.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + + + + + + + + + + + + + + + + + + + + + 0 + 0 + 1 + 1 + + + 0 + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +     diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index 0066d12b23..188811b89b 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -132,6 +132,8 @@ if __name__ == '__main__': ('uvision', 'NUCLEO_L073RZ'), ('uvision', 'NUCLEO_L152RE'), ('uvision', 'MTS_MDOT_F405RG'), + ('uvision', 'MAXWSNENV'), + ('uvision', 'MAX32600MBED'), ('lpcxpresso', 'LPC1768'), ('lpcxpresso', 'LPC4088'), @@ -174,6 +176,8 @@ if __name__ == '__main__': ('gcc_arm', 'MTS_MDOT_F405RG'), ('gcc_arm', 'MTS_MDOT_F411RE'), ('gcc_arm', 'RZ_A1H'), + ('gcc_arm', 'MAXWSNENV'), + ('gcc_arm', 'MAX32600MBED'), ('ds5_5', 'LPC1768'), ('ds5_5', 'LPC11U24'), @@ -196,6 +200,8 @@ if __name__ == '__main__': ('iar', 'STM32F407'), ('iar', 'MTS_MDOT_F405RG'), ('iar', 'MTS_MDOT_F411RE'), + ('iar', 'MAXWSNENV'), + ('iar', 'MAX32600MBED'), # Removed following item to avoid script error #(None, None), From 478aa7ef33942eff6bac60ad033b8add2e773c6b Mon Sep 17 00:00:00 2001 From: porkybrain Date: Fri, 17 Apr 2015 01:56:35 +0200 Subject: [PATCH 126/143] free memory afer disabling the usb ISR solves race condition which could corrupt the heap. (issue #1049) --- libraries/USBDevice/USBMSD/USBMSD.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBDevice/USBMSD/USBMSD.cpp b/libraries/USBDevice/USBMSD/USBMSD.cpp index f2b6e3d791..ee5ad24733 100644 --- a/libraries/USBDevice/USBMSD/USBMSD.cpp +++ b/libraries/USBDevice/USBMSD/USBMSD.cpp @@ -135,10 +135,10 @@ bool USBMSD::connect(bool blocking) { } void USBMSD::disconnect() { + USBDevice::disconnect(); //De-allocate MSD page size: free(page); page = NULL; - USBDevice::disconnect(); } void USBMSD::reset() { From e753aa2d9ef632e8ebf9e56eca7f56dcd464d779 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Fri, 17 Apr 2015 15:39:15 +0900 Subject: [PATCH 127/143] [NXP's HAL] Fix PwmOut period using SCT * Some targets which use SCT timer for PwmOut have a bug which PWM signal does not come out when period set more than 65536us. (issue #1050) * Fix SCT counter mode from 16-bit Low to 32-bit Unified mode * Fix wrong cast size (uint64_t) for 32-bit register * Some TABs convert to white spaces * Affected with LPC812, LPC824, LPC1549 and LPC11U68 --- .../TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c | 11 +++-- .../TARGET_NXP/TARGET_LPC15XX/pwmout_api.c | 43 +++++++++---------- .../hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c | 31 ++++++------- .../hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 13 +++--- 4 files changed, 48 insertions(+), 50 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c index d23a98b07f..71f9aaa41b 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c @@ -77,9 +77,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pinmap_pinout(pin, PinMap_PWM); LPC_SCT0_Type* pwm = obj->pwm; - // Two 16-bit counters, autolimit - pwm->CONFIG &= ~(0x1); - pwm->CONFIG |= (1 << 17); + // Unified 32-bit counter, autolimit + pwm->CONFIG |= ((0x3 << 17) | 0x01); // halt and clear the counter pwm->CTRL |= (1 << 2) | (1 << 3); @@ -170,8 +169,8 @@ void pwmout_period_us(pwmout_t* obj, int us) { uint32_t t_off = obj->pwm->MATCHREL0; uint32_t t_on = obj->pwm->MATCHREL1; float v = (float)t_on/(float)t_off; - obj->pwm->MATCHREL0 = (uint64_t)us; - obj->pwm->MATCHREL1 = (uint64_t)((float)us * (float)v); + obj->pwm->MATCHREL0 = (uint32_t)us; + obj->pwm->MATCHREL1 = (uint32_t)((float)us * (float)v); } void pwmout_pulsewidth(pwmout_t* obj, float seconds) { @@ -183,7 +182,7 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { } void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - obj->pwm->MATCHREL1 = (uint64_t)us; + obj->pwm->MATCHREL1 = (uint32_t)us; } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c index 0f32764d01..8a17f4be48 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c @@ -59,33 +59,32 @@ void pwmout_init(pwmout_t* obj, PinName pin) { LPC_SYSCON->PRESETCTRL1 &= ~(1 << (obj->pwm_ch + 2)); switch(obj->pwm_ch) { - case 0: + case 0: // SCT0_OUT0 LPC_SWM->PINASSIGN[7] &= ~0x0000FF00; LPC_SWM->PINASSIGN[7] |= (pin << 8); - break; - case 1: + break; + case 1: // SCT1_OUT0 LPC_SWM->PINASSIGN[8] &= ~0x000000FF; LPC_SWM->PINASSIGN[8] |= (pin); - break; - case 2: + break; + case 2: // SCT2_OUT0 LPC_SWM->PINASSIGN[8] &= ~0xFF000000; LPC_SWM->PINASSIGN[8] |= (pin << 24); - break; - case 3: + break; + case 3: // SCT3_OUT0 LPC_SWM->PINASSIGN[9] &= ~0x00FF0000; LPC_SWM->PINASSIGN[9] |= (pin << 16); - break; - default: - break; + break; + default: + break; } - // Two 16-bit counters, autolimit - pwm->CONFIG &= ~(0x1); - pwm->CONFIG |= (1 << 17); + // Unified 32-bit counter, autolimit + pwm->CONFIG |= ((0x3 << 17) | 0x01); // halt and clear the counter pwm->CTRL |= (1 << 2) | (1 << 3); @@ -101,10 +100,10 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwm->OUT0_SET = (1 << 0); // event 0 pwm->OUT0_CLR = (1 << 1); // event 1 - pwm->EV0_CTRL = (1 << 12); - pwm->EV0_STATE = 0xFFFFFFFF; - pwm->EV1_CTRL = (1 << 12) | (1 << 0); - pwm->EV1_STATE = 0xFFFFFFFF; + pwm->EV0_CTRL = (1 << 12); + pwm->EV0_STATE = 0xFFFFFFFF; + pwm->EV1_CTRL = (1 << 12) | (1 << 0); + pwm->EV1_STATE = 0xFFFFFFFF; // unhalt the counter: // - clearing bit 2 of the CTRL register @@ -135,7 +134,7 @@ void pwmout_write(pwmout_t* obj, float value) { float pwmout_read(pwmout_t* obj) { uint32_t t_off = obj->pwm->MATCHREL0; uint32_t t_on = obj->pwm->MATCHREL1; - float v = (float)t_on/(float)t_off; + float v = (float)t_on/(float)t_off; return (v > 1.0f) ? (1.0f) : (v); } @@ -152,9 +151,9 @@ void pwmout_period_us(pwmout_t* obj, int us) { LPC_SCT0_Type* pwm = obj->pwm; uint32_t t_off = pwm->MATCHREL0; uint32_t t_on = pwm->MATCHREL1; - float v = (float)t_on/(float)t_off; - pwm->MATCHREL0 = (uint64_t)us; - pwm->MATCHREL1 = (uint64_t)((float)us * (float)v); + float v = (float)t_on/(float)t_off; + pwm->MATCHREL0 = (uint32_t)us; + pwm->MATCHREL1 = (uint32_t)((float)us * (float)v); } void pwmout_pulsewidth(pwmout_t* obj, float seconds) { @@ -166,6 +165,6 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { } void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - obj->pwm->MATCHREL1 = (uint64_t)us; + obj->pwm->MATCHREL1 = (uint32_t)us; } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c index 7866df5629..393d51981a 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c @@ -72,22 +72,23 @@ void pwmout_init(pwmout_t* obj, PinName pin) { LPC_SYSCON->PRESETCTRL |= (1 << 8); // Two 16-bit counters, autolimit (ie reset on Match_0) - pwm->CONFIG &= ~(0x1); - pwm->CONFIG |= (1 << 17); + //pwm->CONFIG &= ~(0x1); + //pwm->CONFIG |= (1 << 17); + pwm->CONFIG |= ((0x3 << 17) | 0x01); // halt and clear the counter - pwm->CTRL_L |= (1 << 2) | (1 << 3); + pwm->CTRL_U |= (1 << 2) | (1 << 3); // System Clock (30 Mhz) -> Prescaler -> us_ticker (1 MHz) - pwm->CTRL_L &= ~(0x7F << 5); - pwm->CTRL_L |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5); + pwm->CTRL_U &= ~(0x7F << 5); + pwm->CTRL_U |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5); pwm->EVENT[0].CTRL = (1 << 12) | 0; // Event_0 on Match_0 pwm->EVENT[0].STATE = 0xFFFFFFFF; // All states // unhalt the counter: // - clearing bit 2 of the CTRL register - pwm->CTRL_L &= ~(1 << 2); + pwm->CTRL_U &= ~(1 << 2); // Not using IRQs //NVIC_SetVector(PWM_IRQn, (uint32_t)pwm_irq_handler); @@ -154,20 +155,20 @@ void pwmout_write(pwmout_t* obj, float value) { } // Match_0 is PWM period. Compute new endtime of pulse for current channel - uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].L) * value); - obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = t_off; // New endtime + uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].U) * value); + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = t_off; // New endtime } // Get dutycycle (0.0 .. 1.0) float pwmout_read(pwmout_t* obj) { - uint32_t t_period = obj->pwm->MATCHREL[0].L; + uint32_t t_period = obj->pwm->MATCHREL[0].U; //Sanity check if (t_period == 0) { return 0.0; }; - uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L; + uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U; float v = (float)t_off/(float)t_period; //Sanity check return (v > 1.0f) ? (1.0f) : (v); @@ -186,8 +187,8 @@ void pwmout_period_ms(pwmout_t* obj, int ms) { // Set the PWM period, keeping the duty cycle the same (for this channel only!). void pwmout_period_us(pwmout_t* obj, int us) { - uint32_t t_period = obj->pwm->MATCHREL[0].L; // Current PWM period - obj->pwm->MATCHREL[0].L = (uint64_t)us; // New PWM period + uint32_t t_period = obj->pwm->MATCHREL[0].U; // Current PWM period + obj->pwm->MATCHREL[0].U = (uint32_t)us; // New PWM period //Keep the dutycycle for the new PWM period //Should really do this for all active channels!! @@ -199,9 +200,9 @@ void pwmout_period_us(pwmout_t* obj, int us) { // obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = 0; // New endtime for this channel } else { - uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L; + uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U; float v = (float)t_off/(float)t_period; - obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = (uint64_t)((float)us * (float)v); // New endtime for this channel + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = (uint32_t)((float)us * (float)v); // New endtime for this channel } } @@ -220,7 +221,7 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms){ void pwmout_pulsewidth_us(pwmout_t* obj, int us) { //Should add Sanity check to make sure pulsewidth < period! - obj->pwm->MATCHREL[(obj->pwm_ch) + 1].L = (uint64_t)us; // New endtime for this channel + obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = (uint32_t)us; // New endtime for this channel } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c index dcfd96656c..05c5113e46 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c @@ -48,7 +48,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) obj->pwm = (LPC_SCT_Type*)LPC_SCT; obj->pwm_ch = sct_n; - LPC_SCT_Type* pwm = obj->pwm; + LPC_SCT_Type* pwm = obj->pwm; // Enable the SCT clock LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); @@ -81,9 +81,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) break; } - // Two 16-bit counters, autolimit - pwm->CONFIG &= ~(0x1); - pwm->CONFIG |= (1 << 17); + // Unified 32-bit counter, autolimit + pwm->CONFIG |= ((0x3 << 17) | 0x01); // halt and clear the counter pwm->CTRL |= (1 << 2) | (1 << 3); @@ -151,8 +150,8 @@ void pwmout_period_us(pwmout_t* obj, int us) uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0]; uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1]; float v = (float)t_on/(float)t_off; - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint64_t)us; - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint64_t)((float)us * (float)v); + obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us; + obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)((float)us * (float)v); } void pwmout_pulsewidth(pwmout_t* obj, float seconds) @@ -167,7 +166,7 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint64_t)us; + obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us; } #endif From 2f4d6683827c192cab49f004223f9e42da5a3a89 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Tue, 14 Apr 2015 13:45:56 -0500 Subject: [PATCH 128/143] Renamed Jenkins specific options to general "Build" options --- .travis.yml | 7 ++++--- workspace_tools/build_release.py | 6 +++--- workspace_tools/singletest.py | 2 +- workspace_tools/test_api.py | 16 ++++++++-------- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/.travis.yml b/.travis.yml index 4f4d70d811..a26edf15aa 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,8 +1,9 @@ ---- -python: +--- +python: - "2.7" script: "python workspace_tools/build_travis.py" install: - "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null" - sudo pip install colorama - - sudo pip install prettytable \ No newline at end of file + - sudo pip install prettytable + - sudo pip install jinja2 diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 3acaaf1d53..b5d79a0886 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -101,7 +101,7 @@ if __name__ == '__main__': default=False, help="Verbose diagnostic output") parser.add_option("-t", "--toolchains", dest="toolchains", help="Use toolchains names separated by comma") - parser.add_option("", "--report-jenkins", dest="report_jenkins_file_name", help="Output the build results to an xml file that is readable by Jenkins") + parser.add_option("", "--report-build", dest="report_build_file_name", help="Output the build results to an html file") options, args = parser.parse_args() @@ -147,8 +147,8 @@ if __name__ == '__main__': # Write summary of the builds - if options.report_jenkins_file_name: - write_build_report(build_report, 'library_build/report.html', options.report_jenkins_file_name) + if options.report_build_file_name: + write_build_report(build_report, 'library_build/report.html', options.report_build_file_name) print "\n\nCompleted in: (%.2f)s" % (time() - start) diff --git a/workspace_tools/singletest.py b/workspace_tools/singletest.py index b88215a977..e1ee3a449f 100644 --- a/workspace_tools/singletest.py +++ b/workspace_tools/singletest.py @@ -209,7 +209,7 @@ if __name__ == '__main__': _opts_log_file_name=opts.log_file_name, _opts_report_html_file_name=opts.report_html_file_name, _opts_report_junit_file_name=opts.report_junit_file_name, - _opts_report_jenkins_file_name=opts.report_jenkins_file_name, + _opts_report_build_file_name=opts.report_build_file_name, _test_spec=test_spec, _opts_goanna_for_mbed_sdk=opts.goanna_for_mbed_sdk, _opts_goanna_for_tests=opts.goanna_for_tests, diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index f29fdd65e4..bca2da5270 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -154,7 +154,7 @@ class SingleTestRunner(object): _opts_log_file_name=None, _opts_report_html_file_name=None, _opts_report_junit_file_name=None, - _opts_report_jenkins_file_name=None, + _opts_report_build_file_name=None, _test_spec={}, _opts_goanna_for_mbed_sdk=None, _opts_goanna_for_tests=None, @@ -207,7 +207,7 @@ class SingleTestRunner(object): self.opts_log_file_name = _opts_log_file_name self.opts_report_html_file_name = _opts_report_html_file_name self.opts_report_junit_file_name = _opts_report_junit_file_name - self.opts_report_jenkins_file_name = _opts_report_jenkins_file_name + self.opts_report_build_file_name = _opts_report_build_file_name self.opts_goanna_for_mbed_sdk = _opts_goanna_for_mbed_sdk self.opts_goanna_for_tests = _opts_goanna_for_tests self.opts_shuffle_test_order = _opts_shuffle_test_order @@ -1438,9 +1438,9 @@ def singletest_in_cli_mode(single_test): # Export results in form of JUnit XML report to separate file report_exporter = ReportExporter(ResultExporterType.JUNIT) report_exporter.report_to_file(test_summary_ext, single_test.opts_report_junit_file_name, test_suite_properties=test_suite_properties_ext) - if single_test.opts_report_jenkins_file_name: - # Export build results as Jenkins XML report ti sparate file - write_build_report(build_report, 'tests_build/report.html', single_test.opts_report_jenkins_file_name) + if single_test.opts_report_build_file_name: + # Export build results as html report to sparate file + write_build_report(build_report, 'tests_build/report.html', single_test.opts_report_build_file_name) class TestLogger(): @@ -1811,9 +1811,9 @@ def get_default_test_options_parser(): dest='report_junit_file_name', help='You can log test suite results in form of JUnit compliant XML report') - parser.add_option("", "--report-jenkins", - dest="report_jenkins_file_name", - help="Output the build results to an xml file that is readable by Jenkins") + parser.add_option("", "--report-build", + dest="report_build_file_name", + help="Output the build results to an html file") parser.add_option('', '--verbose-skipped', dest='verbose_skipped_tests', From 8348517bbba5964b8addec295478a5652940fbc0 Mon Sep 17 00:00:00 2001 From: Christoph Plank Date: Sun, 22 Mar 2015 00:15:27 +0100 Subject: [PATCH 129/143] Fixed section names in linker script for TEENSY3_1 when using GCC_ARM --- .../TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld index 71925fc817..3a40be8642 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld @@ -42,10 +42,11 @@ SECTIONS { .isr_vector : { - __vector_table = .; - KEEP(*(.vector_table)) + . = 0; + __isr_vector = .; + KEEP(*(.isr_vector)) *(.text.Reset_Handler) - *(.text.System_Init) + *(.text.SystemInit) . = ALIGN(4); } > VECTORS From e66f9ff0aadd4cbf49eb735fc4cb166fcc0ea577 Mon Sep 17 00:00:00 2001 From: Christoph Plank Date: Sun, 22 Mar 2015 00:16:51 +0100 Subject: [PATCH 130/143] Call SystemInit before loading the .data section for TEENSY3.1 when using GCC_ARM This is needed because it seems the watchdog otherwise resets the board before SystemInit is reached even though I'm not sure why the watchdog timer expires so early. --- .../TOOLCHAIN_GCC_ARM/startup_MK20DX256.s | 9 +++++++-- .../TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s index c2eaa33f46..e54559a4dc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s @@ -192,6 +192,13 @@ __isr_vector: .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: +/* + * Call SystemInit before loading the .data section to prevent the watchdog + * from resetting the board. + */ + ldr r0, =SystemInit + blx r0 + /* Loop to copy data from read only memory to RAM. The ranges * of copy from/to are specified by following symbols evaluated in * linker script. @@ -212,8 +219,6 @@ Reset_Handler: .Lflash_to_ram_loop_end: - ldr r0, =SystemInit - blx r0 ldr r0, =_start bx r0 .pool diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c index 4b45c719f0..4f34cc76c1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c @@ -100,6 +100,8 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit (void) { + /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */ + #if (DISABLE_WDOG) /* Disable the WDOG module */ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ From bd1bfb5c4b539160e5a85a97c4c65031268cdbb9 Mon Sep 17 00:00:00 2001 From: Christoph Plank Date: Sat, 18 Apr 2015 16:32:59 +0200 Subject: [PATCH 131/143] Fixed RTOS support for Cortex-M4 without FPU --- .../TARGET_M4/TOOLCHAIN_GCC/HAL_CM4.s | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M4/TOOLCHAIN_GCC/HAL_CM4.s b/libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M4/TOOLCHAIN_GCC/HAL_CM4.s index cebb80e8e8..ce3242bcbb 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M4/TOOLCHAIN_GCC/HAL_CM4.s +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M4/TOOLCHAIN_GCC/HAL_CM4.s @@ -210,8 +210,12 @@ SVC_Handler_Veneer: CBZ R1,SVC_Next /* Runtask deleted? */ TST LR,#0x10 /* is it extended frame? */ + #ifdef __FPU_PRESENT ITTE EQ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */ + #else + ITE EQ + #endif MOVEQ R0,#0x01 /* os_tsk->stack_frame val */ MOVNE R0,#0x00 STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */ @@ -229,8 +233,12 @@ SVC_Next: LDMIA R12!,{R4-R11} /* Restore New Context */ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */ CMP R0,#0 /* Basic/Extended Stack Frame */ + #ifdef __FPU_PRESENT ITTE NE VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */ + #else + ITE NE + #endif MVNNE LR,#~0xFFFFFFED /* set EXC_RETURN value */ MVNEQ LR,#~0xFFFFFFFD MSR PSP,R12 /* Write PSP */ @@ -303,8 +311,12 @@ Sys_Switch: MRS R12,PSP /* Read PSP */ TST LR,#0x10 /* is it extended frame? */ + #ifdef __FPU_PRESENT ITTE EQ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */ + #else + ITE EQ + #endif MOVEQ R0,#0x01 /* os_tsk->stack_frame val */ MOVNE R0,#0x00 STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */ @@ -321,8 +333,12 @@ Sys_Switch: LDMIA R12!,{R4-R11} /* Restore New Context */ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */ CMP R0,#0 /* Basic/Extended Stack Frame */ + #ifdef __FPU_PRESENT ITTE NE VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */ + #else + ITE NE + #endif MVNNE LR,#~0xFFFFFFED /* set EXC_RETURN value */ MVNEQ LR,#~0xFFFFFFFD MSR PSP,R12 /* Write PSP */ From 82b7d9d3f7e5b80f4f7e1542158c7017c459edba Mon Sep 17 00:00:00 2001 From: Christoph Plank Date: Sat, 18 Apr 2015 16:33:20 +0200 Subject: [PATCH 132/143] Added RTOS support for TEENSY3_1 target --- libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 3 +++ libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index 23d72be0ee..62bc31ce27 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -304,6 +304,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600) #define INITIAL_SP (0x20008000UL) +#elif defined(TARGET_TEENSY3_1) +#define INITIAL_SP (0x20008000UL) + #else #error "no target defined" diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index f6c5de83c5..af69c9cde9 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -51,7 +51,7 @@ #ifndef OS_TASKCNT # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -67,7 +67,7 @@ #ifndef OS_SCHEDULERSTKSIZE # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -119,7 +119,7 @@ # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) # define OS_CLOCK 96000000 -# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE) +# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE) || defined(TARGET_TEENSY3_1) # define OS_CLOCK 72000000 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) \ From 5b74eed7da7af522dd384280bff8d54bc0c9622d Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Mon, 20 Apr 2015 14:34:47 +0900 Subject: [PATCH 133/143] [USBMIDI] Fix compile error * Member variables in USBMIDIMessage and USBMIDI class wrongly initialized in class declaration * Add member initialization in constructor --- libraries/USBDevice/USBMIDI/MIDIMessage.h | 6 +++--- libraries/USBDevice/USBMIDI/USBMIDI.cpp | 4 +++- libraries/USBDevice/USBMIDI/USBMIDI.h | 4 ++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/libraries/USBDevice/USBMIDI/MIDIMessage.h b/libraries/USBDevice/USBMIDI/MIDIMessage.h index d1a2bc58e7..9cfcf13635 100644 --- a/libraries/USBDevice/USBMIDI/MIDIMessage.h +++ b/libraries/USBDevice/USBMIDI/MIDIMessage.h @@ -44,9 +44,9 @@ /** A MIDI message container */ class MIDIMessage { public: - MIDIMessage() {} + MIDIMessage() : length(4) {} - MIDIMessage(uint8_t *buf) { + MIDIMessage(uint8_t *buf) : length(4) { for (int i = 0; i < 4; i++) data[i] = buf[i]; } @@ -270,7 +270,7 @@ public: } uint8_t data[MAX_MIDI_MESSAGE_SIZE+1]; - uint8_t length=4; + uint8_t length; }; #endif diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/libraries/USBDevice/USBMIDI/USBMIDI.cpp index a46f9ae77d..084574a790 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.cpp +++ b/libraries/USBDevice/USBMIDI/USBMIDI.cpp @@ -20,7 +20,9 @@ #include "USBMIDI.h" -USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) { +USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release) + : USBDevice(vendor_id, product_id, product_release), cur_data(0), data_end(true) +{ midi_evt = NULL; USBDevice::connect(); } diff --git a/libraries/USBDevice/USBMIDI/USBMIDI.h b/libraries/USBDevice/USBMIDI/USBMIDI.h index a7818dd8ce..cc5be5b7d8 100644 --- a/libraries/USBDevice/USBMIDI/USBMIDI.h +++ b/libraries/USBDevice/USBMIDI/USBMIDI.h @@ -103,8 +103,8 @@ protected: private: uint8_t data[MAX_MIDI_MESSAGE_SIZE+1]; - uint8_t cur_data=0; - bool data_end = true; + uint8_t cur_data; + bool data_end; void (*midi_evt)(MIDIMessage); }; From c3da63092360d95a0402955c008b033eb0e28e4e Mon Sep 17 00:00:00 2001 From: Rohit Grover Date: Mon, 30 Mar 2015 08:24:03 +0100 Subject: [PATCH 134/143] attempt at upgrading to v8.0 of the SDK --- .../TARGET_MCU_NORDIC_16K/nRF51822.sct | 7 +- .../TARGET_MCU_NORDIC_32K/nRF51822.sct | 7 +- .../TARGET_MCU_NORDIC_16K/NRF51822.ld | 2 +- .../TARGET_MCU_NORDIC_32K/NRF51822.ld | 2 +- .../components/libraries/crc16/crc16.h | 13 +- .../components/libraries/util/app_error.h | 8 + .../components/libraries/util/app_util.h | 2 + .../s110_nrf51822_7.1.0_API/doc/ble_api.dox | 1334 ---- .../s110_nrf51822_7.1.0_API/include/ble.h | 419 -- .../s110_nrf51822_7.1.0_API/include/ble_err.h | 54 - .../s110_nrf51822_7.1.0_API/include/ble_gap.h | 1035 --- .../include/ble_gatt.h | 171 - .../include/ble_gattc.h | 406 -- .../include/ble_gatts.h | 566 -- .../s110_nrf51822_7.1.0_API/include/ble_hci.h | 96 - .../include/ble_l2cap.h | 144 - .../include/ble_ranges.h | 89 - .../include/ble_types.h | 169 - .../include/nrf_error.h | 51 - .../include/nrf_error_sdm.h | 33 - .../include/nrf_error_soc.h | 49 - .../s110_nrf51822_7.1.0_API/include/nrf_mbr.h | 155 - .../s110_nrf51822_7.1.0_API/include/nrf_sdm.h | 167 - .../s110_nrf51822_7.1.0_API/include/nrf_soc.h | 958 --- .../s110_nrf51822_7.1.0_API/include/nrf_svc.h | 33 - .../include/softdevice_assert.h | 46 - .../s110_nrf51822_7.1.0_licence_agreement.pdf | Bin 5553 -> 0 bytes .../s110_nrf51822_7.1.0_readme.txt | 16 - .../s110_nrf51822_7.1.0_releasenotes.pdf | Bin 41671 -> 0 bytes .../s110_nrf51822_7.1.0_softdevice.hex | 5280 --------------- .../s110_nrf51822_8.0.0_softdevice.hex | 5649 +++++++++++++++++ workspace_tools/targets.py | 16 +- 32 files changed, 5681 insertions(+), 11296 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/doc/ble_api.dox delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_err.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gap.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatt.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gattc.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatts.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_hci.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_l2cap.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_ranges.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_types.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_sdm.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_soc.h delete mode 100755 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_mbr.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_sdm.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_soc.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_svc.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/softdevice_assert.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_licence_agreement.pdf delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_readme.txt delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_releasenotes.pdf delete mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_softdevice.hex create mode 100644 libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct index bccc79bda6..62638400f2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct @@ -12,8 +12,8 @@ ; ;WITH SOFTDEVICE: -LR_IROM1 0x16000 0x002A000 { - ER_IROM1 0x16000 0x002A000 { +LR_IROM1 0x18000 0x0028000 { + ER_IROM1 0x18000 0x0028000 { *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) @@ -22,6 +22,3 @@ LR_IROM1 0x16000 0x002A000 { .ANY (+RW +ZI) } } - - - diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct index 20a31ef141..6dd0642fd1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct @@ -12,8 +12,8 @@ ; ;WITH SOFTDEVICE: -LR_IROM1 0x16000 0x002A000 { - ER_IROM1 0x16000 0x002A000 { +LR_IROM1 0x18000 0x0028000 { + ER_IROM1 0x18000 0x0028000 { *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) @@ -22,6 +22,3 @@ LR_IROM1 0x16000 0x002A000 { .ANY (+RW +ZI) } } - - - diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld index 43e0ac80da..cb472e5640 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld @@ -2,7 +2,7 @@ MEMORY { - FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000 + FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000 RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 } diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld index db71363817..812a86d4e3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld @@ -2,7 +2,7 @@ MEMORY { - FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000 + FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000 RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x6000 } diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h index e4e82ceed3..57f6251354 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h @@ -9,7 +9,7 @@ * the file. * */ - + /** @file * * @defgroup crc_compute CRC compute @@ -18,7 +18,7 @@ * * @brief This module implements the CRC-16 calculation in the blocks. */ - + #ifndef CRC16_H__ #define CRC16_H__ @@ -30,13 +30,13 @@ extern "C" { /**@brief Function for calculating CRC-16 in blocks. * - * Feed each consecutive data block into this function, along with the current value of p_crc as - * returned by the previous call of this function. The first call of this function should pass NULL + * Feed each consecutive data block into this function, along with the current value of p_crc as + * returned by the previous call of this function. The first call of this function should pass NULL * as the initial value of the crc in p_crc. * * @param[in] p_data The input data block for computation. * @param[in] size The size of the input data block in bytes. - * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. + * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. * * @return The updated CRC-16 value, based on the input supplied. */ @@ -46,7 +46,6 @@ uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p } #endif - #endif // CRC16_H__ - + /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h index 616634c887..2711170419 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h @@ -26,6 +26,10 @@ #include #include "nrf_error.h" +#ifdef __cplusplus +extern "C" { +#endif + /**@brief Function for error handling, which is called when an error has occurred. * * @param[in] error_code Error code supplied to the handler. @@ -34,6 +38,10 @@ */ void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); +#ifdef __cplusplus +} +#endif + /**@brief Macro for calling error handler function. * * @param[in] ERR_CODE Error code supplied to the error handler. diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h index c4b1022eb1..7b0ef5a06a 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h @@ -50,6 +50,8 @@ enum #if defined(__GNUC__) #define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1] +#elif defined(__ICCARM__) +#define STATIC_ASSERT(EXPR) extern char static_assert_failed[(EXPR) ? 1 : -1] #else #define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1] #endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/doc/ble_api.dox b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/doc/ble_api.dox deleted file mode 100644 index 9adbffe39a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/doc/ble_api.dox +++ /dev/null @@ -1,1334 +0,0 @@ -/** - * @addtogroup BLE_COMMON - * @{ - * @defgroup BLE_COMMON_MSC Message Sequence Charts - * @{ - * @defgroup BLE_COMMON_IRQ_EVT_MSC Interrupt-driven Event Retrieval - * @msc - * hscale = "1.5"; - * APP,SD; - * |||; - * APP=>SD [label = "sd_softdevice_enable(clock, assertion_handler);"]; - * APP<SD [label = "sd_nvic_EnableIRQ(SD_EVENT_IRQn)"]; - * APP<APP [label = "SD_EVENT_IRQHandler()"]; - * APP=>SD [label = "sd_ble_evt_get(buffer);"]; - * APP<SD [label = "sd_softdevice_enable(clock, assertion_handler);"]; - * APP<SD [label = "sd_app_evt_wait(void);"]; - * APP rbox APP [label="App Thread Mode blocked, CPU in low power mode"]; - * |||; - * ...; - * |||; - * SD rbox SD [label="Event Available for the App"]; - * APP<SD [label = "sd_ble_evt_get(buffer);"]; - * APP<SD [label = "sd_app_evt_wait(void);"]; - * APP rbox APP [label="App Thread Mode blocked, CPU in low power mode"]; - * |||; - * ...; - * |||; - * SD rbox SD [label="Event Available for the App"]; - * APP<SD [label = "sd_ble_evt_get(buffer);"]; - * APP<SD [label = "sd_app_evt_wait(void);"]; - * APP rbox APP [label="App Thread Mode blocked, CPU in low power mode"]; - * |||; - * ...; - * |||; - * @endmsc - * - * @defgroup BLE_COMMON_APP_BUFF_MSC App Buffer Management - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP=>SD [label = "sd_ble_tx_buffer_count_get();"]; - * APP<SD [label = "sd_ble_gattc_write(handle, value)"]; - * APP<PEER [label = "ATT Write Command", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_TX_COMPLETE {1}"]; - * APP rbox APP [label="available += 1"]; - * |||; - * ...; - * |||; - * APP=>SD [label = "sd_ble_gatts_hvx(NOTIFICATION, app_value)"]; - * APP<PEER [label = "ATT Handle Value Notification", textcolor="#000080", linecolor="#000080"]; - * APP=>SD [label = "sd_ble_gatts_hvx(NOTIFICATION, app_value)"]; - * APP<PEER [label = "ATT Handle Value Notification", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_TX_COMPLETE {2}"]; - * APP rbox APP [label="available += 2"]; - * |||; - * ...; - * |||; - * APP rbox PEER [label="Terminate Connection"]; - * |||; - * APP rbox APP [label="available = N"]; - * |||; - * @endmsc - * @} - * @} - */ - -/** - * @addtogroup BLE_GAP - * @{ - * @defgroup BLE_GAP_MSC Message Sequence Charts - * @{ - * @defgroup BLE_GAP_ADV_MSC GAP Advertisement - * @msc - * hscale = "1.5"; - * APP,SD,SCANNERS; - * |||; - * APP=>SD [label = "sd_ble_gap_address_set(addr)"]; - * APP<SD [label = "sd_ble_gap_adv_data_set(adv, sr)"]; - * APP<SD [label = "sd_ble_gap_adv_start(params)"]; - * APP<SCANNERS [label = "ADV packet", textcolor="#000080", linecolor="#000080"]; - * SD->SCANNERS [label = "ADV packet", textcolor="#000080", linecolor="#000080"]; - * SD->SCANNERS [label = "ADV packet", textcolor="#000080", linecolor="#000080"]; - * ...; - * SD->SCANNERS [label = "ADV packet", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #1 App Stops Advertisement "]; - * APP=>SD [label = "sd_ble_gap_adv_stop()"]; - * APP<CENTRAL [label = "Connection Establishment", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONNECTED"]; - * |||; - * --- [label = " Variant #1 Local Disconnection "]; - * APP=>SD [label = "sd_ble_gap_disconnect(reason)"]; - * APP<CENTRAL [label = "Connection Termination", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_DISCONNECTED {reason}"]; - * |||; - * --- [label = " Variant #2 Remote Disconnection "]; - * SD<:CENTRAL [label = "Connection Termination", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_DISCONNECTED {reason}"]; - * @endmsc - * - * @defgroup BLE_GAP_CPU_MSC GAP Connection Parameter Update - * @msc - * hscale = "1.5"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established with conn. params. CP#1"]; - * |||; - * APP=>SD [label = "sd_ble_gap_conn_param_update(CP#2)"]; - * APP<CENTRAL [label = "L2CAP CPU Request", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #1 Central Accepts "]; - * |||; - * SD<:CENTRAL [label = "L2CAP CPU Response: Accepted", textcolor="#000080", linecolor="#000080"]; - * |||; - * SD<:CENTRAL [label = "Connection Update", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_PARAM_UPDATE {CP#2}"]; - * |||; - * --- [label = " Variant #2 Central Rejects "]; - * |||; - * SD<:CENTRAL [label = "L2CAP CPU Response: Rejected", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_PARAM_UPDATE {CP#1}"]; - * --- [label = " Variant #3 Central Ignores "]; - * |||; - * ...; - * |||; - * SD box SD [label="Timeout"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_PARAM_UPDATE {CP#1}"]; - * @endmsc - * - * @defgroup BLE_GAP_RSSI_MSC GAP RSSI - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gap_rssi_start()"]; - * APP<SD [label = "sd_ble_gap_rssi_stop()"]; - * APP<SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: no_bond, no_mitm, no_io_caps)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 2", textbgcolor="#7f7fff"]; - * |||; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {SUCCESS}"]; - * APP rbox CENTRAL [label = "Encrypted with STK"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_SEC_UPDATE {ENC_NO_MITM}"]; - * @endmsc - * - * @defgroup BLE_GAP_BONDING_JW_MSC GAP Bonding: Just Works - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST {central_params: bond, no_mitm, no_io_caps}"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: bond, no_mitm, no_io_caps)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 2", textbgcolor="#7f7fff"]; - * |||; - * APP rbox CENTRAL [label = "Encrypted with STK"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_SEC_UPDATE {ENC_NO_MITM}"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 3", textbgcolor="#7f7fff"]; - * |||; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {SUCCESS, periph_keys}"]; - * APP rbox APP [label = "Store Peripheral Keys"]; - * @endmsc - * - * @defgroup BLE_GAP_BONDING_PK_PERIPH_MSC GAP Bonding: Passkey Entry, Peripheral displays - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST {central_params: bond, mitm, keyboard}"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: bond, mitm, display)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_PASSKEY_DISPLAY {passkey}"]; - * APP rbox APP [label="Passkey displayed to the user"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 2", textbgcolor="#7f7fff"]; - * |||; - * APP rbox CENTRAL [label = "Encrypted with STK"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_SEC_UPDATE {ENC_MITM}"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 3", textbgcolor="#7f7fff"]; - * |||; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {SUCCESS, periph_keys}"]; - * APP rbox APP [label = "Store Peripheral Keys"]; - * @endmsc - * - * @defgroup BLE_GAP_BONDING_PK_CENTRAL_OOB_MSC GAP Bonding: Passkey Entry (Central display) or OOB MSC - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST {central_params: bond, mitm, display}"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: bond, mitm, keyboard)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_KEY_REQUEST {type}"]; - * APP rbox APP [label="User enters Passkey or data received Out Of Band"]; - * APP=>SD [label = "sd_ble_gap_auth_key_reply(passkey or OOB)"]; - * APP<SD [label = "sd_ble_opt_set(opt_id = BLE_GAP_OPT_PASSKEY, p_opt->p_passkey=passkey)"]; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST {central_params: bond, mitm, keyboard}"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: bond, mitm, io_caps = display)"]; - * - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_PASSKEY_DISPLAY {passkey}"]; - * APP rbox APP [label="Passkey displayed to the user"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 2", textbgcolor="#7f7fff"]; - * |||; - * APP rbox CENTRAL [label = "Encrypted with STK"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_SEC_UPDATE {ENC_MITM}"]; - * |||; - * SD abox CENTRAL [label="SMP Pairing Phase 3", textbgcolor="#7f7fff"]; - * |||; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {SUCCESS, periph_keys}"]; - * APP rbox APP [label = "Store Peripheral Keys"]; - * @endmsc - * - * @defgroup BLE_GAP_SEC_MSC GAP Security Establishment using stored keys - * @msc - * hscale = "1.5"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "LL Encryption Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_INFO_REQUEST {addr, div}"]; - * |||; - * --- [label = " Variant #1 App Replies with Keys "]; - * |||; - * APP rbox APP [label = "Load Peripheral Keys"]; - * APP=>SD [label = "sd_ble_gap_sec_info_reply(div, LTK)"]; - * APP<CENTRAL [label = "LL Encryption Response", textcolor="#000080", linecolor="#000080"]; - * APP rbox CENTRAL [label = "Encrypted with LTK"]; - * APP<<=SD [label = "BLE_GAP_EVT_CONN_SEC_UPDATE"]; - * |||; - * --- [label = " Variant #2 App Replies without Keys "]; - * |||; - * APP=>SD [label = "sd_ble_gap_sec_info_reply(NULL)"]; - * APP<CENTRAL [label = "LL Reject Ind: Pin or Key Missing", textcolor="#000080", linecolor="#000080"]; - * APP rbox CENTRAL [label = "Link Not Encrypted"]; - * @endmsc - * - * @defgroup BLE_GAP_PERIPH_SEC_MSC GAP Peripheral Initiated Security Establishment - * @msc - * hscale = "1.5"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gap_authenticate(params)"]; - * APP<CENTRAL [label = "SMP Security Request", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #1 Central initiates Security Establishment "]; - * |||; - * APP rbox CENTRAL [label="Encryption or Pairing/Bonding initiated by Central"]; - * |||; - * --- [label = " Variant #2 Central ignores "]; - * |||; - * ...; - * |||; - * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT"]; - * |||; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_KS_OUT_OF_RANGE_MSC GAP Failed Pairing: Keysize out of supported range - * This occurs if the min key size offered by the peer is above 16, or max key size below 7. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: Invalid params, error_src: local}"]; - * SD:>CENTRAL [label = "SMP Pairing failed", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_KS_TOO_SMALL_MSC GAP Failed Pairing: Keysize too small - * This occurs if the max key size offered by the peer is below the min key size specified by - * the app. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * SD<:CENTRAL [label = "SMP Pairing Confirm", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: Enc key size, error_src: local}"]; - * SD:>CENTRAL [label = "SMP Pairing failed", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_APP_ERROR_MSC GAP Failed Pairing: Pairing aborted by the application - * When the application detects that the pairing should not be performed, for example an - * insufficient IO combination, it can use sd_ble_gap_sec_params_reply() to send - * SMP Pairing failed to the peer. - * - * When the stack handles the response from the application it will also validate - * the passkey (SMP_STC_PASSKEY_ENTRY_FAILED). If any error is detected it will be - * reported when sd_ble_gap_sec_params_reply() is called. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST"]; - * SD abox APP [label="Stack looks for errors", textbgcolor="#7f7fff"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply()"]; - * APP<CENTRAL [label = "SMP Pairing failed", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: , error_src: local}"]; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_CONFIRM_FAIL_MSC GAP Failed Pairing: Confirm failed - * This occurs if the random value doesn't match, usually because the user entered a wrong pin - * or out of band data was missing. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST {central_params: mitm, display}"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS, periph_params: mitm, keyboard)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * SD<:CENTRAL [label = "SMP Pairing Confirm", textcolor="#000080", linecolor="#000080"]; - * SD:>CENTRAL [label = "SMP Pairing Confirm", textcolor="#000080", linecolor="#000080"]; - * SD<:CENTRAL [label = "SMP Pairing Random", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: Confirm value, error_src: local}"]; - * SD:>CENTRAL [label = "SMP Pairing failed", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_REMOTE_PAIRING_FAIL_MSC GAP Failed Pairing: Pairing failed from master - * SMP Pairing Failed may be sent from the master at various times. The application should - * prepare for this and gracefully handle the event. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * SD<:CENTRAL [label = "SMP Pairing Failed", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: , error_src: remote}"]; - * @endmsc - * - * @defgroup BLE_GAP_PAIRING_TIMEOUT_MSC GAP Failed Pairing: Timeout - * This occurs if the central device doesn't continue the pairing sequence within 30 seconds. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * SD<:CENTRAL [label = "SMP Pairing Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GAP_EVT_SEC_PARAMS_REQUEST"]; - * APP=>SD [label = "sd_ble_gap_sec_params_reply(SUCCESS)"]; - * APP<CENTRAL [label = "SMP Pairing Response", textcolor="#000080", linecolor="#000080"]; - * --- [ label = "Wait 30 sec" ]; - * APP<<=SD [label = "BLE_GAP_EVT_AUTH_STATUS {auth_status: Timeout, error_src: local}"]; - - * @endmsc - * - * @defgroup BLE_GAP_SECURITY_TIMEOUT_MSC GAP Authenticate request: Timeout - * This occurs if the central device doesn't continue the pairing sequence after - * the security procedure timeout. - * @msc - * hscale = "2"; - * APP,SD,CENTRAL; - * |||; - * APP rbox CENTRAL [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gap_authenticate(..., ble_gap_sec_params_t*)"]; - * APP<CENTRAL [label = "Security Request", textcolor="#000080", linecolor="#000080"]; - --- [ label = "After req_timeout (in ble_gap_sec_params_t)" ]; - * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {error_src: BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST}"]; - * @endmsc - * - * @} - * @} - */ - -/** - * @addtogroup BLE_GATTC - * @{ - * @defgroup BLE_GATTC_MSC Message Sequence Charts - * @{ - * @defgroup BLE_GATTC_PRIM_SRVC_DISC_MSC GATTC Primary Service Discovery - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * --- [label = " Variant #1 Discover All Services "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle, NULL)"]; - * APP<PEER [label = "ATT Read By Group Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Group Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {SUCCESS, services}"]; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle + N, NULL)"]; - * APP<PEER [label = "ATT Read By Group Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Group Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {SUCCESS, services}"]; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle + N + M, NULL)"]; - * APP<PEER [label = "ATT Read By Group Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {ATTRIBUTE_NOT_FOUND}"]; - * |||; - * --- [label = " Variant #2 Discover a Specific Service "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle, uuid)"]; - * APP<PEER [label = "ATT Find By Type Value Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Find By Type Value Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {SUCCESS, services}"]; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle + N, uuid)"]; - * APP<PEER [label = "ATT Find By Type Value Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Find By Type Value Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {SUCCESS, services}"]; - * APP=>SD [label = "sd_ble_gattc_primary_services_discover(handle + N + M, uuid)"]; - * APP<PEER [label = "ATT Find By Type Value Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP {ATTRIBUTE_NOT_FOUND}"]; - * @endmsc - * - * @defgroup BLE_GATTC_REL_DISC_MSC GATTC Relationship Discovery - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gattc_relationships_discover(handle_range)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_REL_DISC_RSP {SUCCESS, includes}"]; - * APP=>SD [label = "sd_ble_gattc_relationships_discover(handle_range + N)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_REL_DISC_RSP {SUCCESS, includes}"]; - * APP=>SD [label = "sd_ble_gattc_relationships_discover(handle_range + N + M)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_REL_DISC_RSP {ATTRIBUTE_NOT_FOUND}"]; - * @endmsc - * - * @defgroup BLE_GATTC_CHAR_DISC_MSC GATTC Characteristic Discovery - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gattc_characteristics_discover(handle_range)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_DISC_RSP {SUCCESS, chars}"]; - * APP=>SD [label = "sd_ble_gattc_characteristics_discover(handle_range + N)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_DISC_RSP {SUCCESS, chars}"]; - * APP=>SD [label = "sd_ble_gattc_characteristics_discover(handle_range + N + M)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_DISC_RSP {ATTRIBUTE_NOT_FOUND}"]; - * @endmsc - * - * @defgroup BLE_GATTC_DESC_DISC_MSC GATTC Descriptor Discovery - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gattc_descriptors_discover(handle_range)"]; - * APP<PEER [label = "ATT Find Information Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Find Information Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_DESC_DISC_RSP {SUCCESS, descs}"]; - * APP=>SD [label = "sd_ble_gattc_descriptors_discover(handle_range + N)"]; - * APP<PEER [label = "ATT Find Information Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Find Information Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_DESC_DISC_RSP {SUCCESS, descs}"]; - * APP=>SD [label = "sd_ble_gattc_descriptors_discover(handle_range + N + M)"]; - * APP<PEER [label = "ATT Find Information Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_DESC_DISC_RSP {ATTRIBUTE_NOT_FOUND}"]; - * @endmsc - * - * @defgroup BLE_GATTC_READ_UUID_MSC GATTC Read Characteristic Value by UUID - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP=>SD [label = "sd_ble_gattc_char_value_by_uuid_read(uuid, handle_range)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP {SUCCESS, char_values}"]; - * APP=>SD [label = "sd_ble_gattc_char_value_by_uuid_read(uuid, handle_range + N)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read By Type Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP {SUCCESS, char_values}"]; - * APP=>SD [label = "sd_ble_gattc_char_value_by_uuid_read(uuid, handle_range + N + M)"]; - * APP<PEER [label = "ATT Read By Type Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Attribute Not Found", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP {ATTRIBUTE_NOT_FOUND}"]; - * @endmsc - * - * @defgroup BLE_GATTC_VALUE_READ_MSC GATTC Characteristic or Descriptor Value Read - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * --- [label = " Variant #1 offset == 0 "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_read(handle, 0)"]; - * APP<PEER [label = "ATT Read Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_READ_RSP {SUCCESS, value}"]; - * |||; - * --- [label = " Variant #2 offset != 0 "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_read(handle, offset)"]; - * APP<PEER [label = "ATT Read Blob Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read Blob Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_READ_RSP {SUCCESS, value}"]; - * APP=>SD [label = "sd_ble_gattc_read(handle, offset + N)"]; - * APP<PEER [label = "ATT Read Blob Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read Blob Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_READ_RSP {SUCCESS, value}"]; - * APP=>SD [label = "sd_ble_gattc_read(handle, offset + N + M + 1)"]; - * APP<PEER [label = "ATT Read Blob Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Invalid Offset", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_READ_RSP {INVALID_OFFSET}"]; - * @endmsc - * - * @defgroup BLE_GATTC_READ_MULT_MSC GATTC Read Multiple Characteristic Values - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * --- [label = " Variant #1 Successful request "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_char_values_read(handles)"]; - * APP<PEER [label = "ATT Read Multiple Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Read Multiple Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_VALS_READ_RSP {SUCCESS, char_values}"]; - * |||; - * --- [label = " Variant #2 Failing request (invalid handle) "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_char_values_read(handles)"]; - * APP<PEER [label = "ATT Read Multiple Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Error Response: Invalid Handle", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_CHAR_VALS_READ_RSP {INVALID_HANDLE, error_handle=}"]; - * @endmsc - * - * @defgroup BLE_GATTC_VALUE_WRITE_MSC GATTC Characteristic or Descriptor Value Write - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * --- [label = " Variant #1 write_op == BLE_GATT_OP_WRITE_CMD "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_write(handle, value)"]; - * APP<PEER [label = "ATT Write Command", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_TX_COMPLETE"]; - * |||; - * --- [label = " Variant #2 write_op == BLE_GATT_OP_WRITE_REQ "]; - * |||; - * APP=>SD [label = "sd_ble_gattc_write(handle, value)"]; - * APP<PEER [label = "ATT Write Request", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_WRITE_RSP {SUCCESS}"]; - * @endmsc - * - * @defgroup BLE_GATTC_HVI_MSC GATTC Handle Value Indication - * GATTC Handle Value Indication MSC - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD<:PEER [label = "ATT Handle Value Indication", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_HVX {INDICATION, data}"]; - * APP=>SD [label = "sd_ble_gattc_hv_confirm(handle)"]; - * APP<PEER [label = "ATT Handle Value Confirmation", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTC_HVN_MSC GATTC Handle Value Notification - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD<:PEER [label = "ATT Handle Value Notification", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTC_EVT_HVX {NOTIFICATION, data}"]; - * @endmsc - * - * @defgroup BLE_GATTC_TIMEOUT_MSC GATTC Timeout - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox PEER [label="Any GATTC API used"]; - * SD:>PEER [label = "ATT Packet", textcolor="#000080", linecolor="#000080"]; - * APP note PEER [label = "No Response from Peer"]; - * |||; - * ...; - * |||; - * SD box SD [label="Timeout"]; - * APP<<=SD [label = "BLE_GATTC_EVT_TIMEOUT {source}"]; - * APP rbox PEER [label="No additional ATT Traffic Allowed", textbgcolour="#ff7f7f"]; - * APP=>SD [label = "Any API call"]; - * APP<SD [label = "sd_ble_gatts_service_add(uuid#1)"]; - * APP<SD [label = "sd_ble_gatts_characteristic_add(handle_srvc#1, char_md, value)"]; - * APP<SD [label = "sd_ble_gatts_descriptor_add(handle_char#1, value)"]; - * APP<SD [label = "sd_ble_gatts_descriptor_add(handle_char#1, value)"]; - * APP<SD [label = "sd_ble_gatts_characteristic_add(handle_srvc#1, char_md, value)"]; - * APP<SD [label = "sd_ble_gatts_descriptor_add(handle_char#2, value)"]; - * APP<SD [label = "sd_ble_gatts_service_add(uuid#2)"]; - * APP<SD [label = "sd_ble_gatts_include_add(handle_srvc#2, handle_srvc#1)"]; - * APP<PEER [label = "ATT Read Response", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_WRITE_REQ_NO_AUTH_MSC GATTS Write Request without Authorization - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD<:PEER [label = "ATT Write Request", textcolor="#000080", linecolor="#000080"]; - * SD:>PEER [label = "ATT Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_WRITE {WRITE_REQ, data}"]; - * @endmsc - * - * @defgroup BLE_GATTS_WRITE_CMD_NO_AUTH_MSC GATTS Write Command with or without Authorization - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD<:PEER [label = "ATT Write Command", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_WRITE {WRITE_CMD, data}"]; - * @endmsc - * - * @defgroup BLE_GATTS_READ_REQ_AUTH_MSC GATTS Read Request with Authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * SD<:PEER [label = "ATT Read Request", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {READ, current_value}"]; - * --- [label = " Variant #1 App Authorizes "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(SUCCESS, app_value)"]; - * APP<PEER [label = "ATT Read Response {app_value}", textcolor="#000080", linecolor="#000080"]; - * --- [label = " Variant #2 App Disallows "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(READ_NOT_PERMITTED)"]; - * APP<PEER [label = "ATT Error Response", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_WRITE_REQ_AUTH_MSC GATTS Write Request with Authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * SD<:PEER [label = "ATT Write Request {peer_data}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, peer_value}"]; - * --- [label = " Variant #1 App Authorizes "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(SUCCESS)"]; - * APP<PEER [label = "ATT Write Response", textcolor="#000080", linecolor="#000080"]; - * --- [label = " Variant #2 App Disallows "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE_NOT_PERMITTED)"]; - * APP<PEER [label = "ATT Error Response", textcolor="#000080", linecolor="#000080"]; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * @endmsc - * - * @defgroup BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC GATTS Queued Writes: Stack handled, no attributes require authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_REQUEST {BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES}"]; - * APP=>SD [label = "sd_ble_user_mem_reply {user_mem_block}"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #1 Attribute Values validation passed "]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: peer_value_2"]; - * APP<<=SD [label = "BLE_GATTS_EVT_WRITE {EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="App parses the memory it provided"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * --- [label = " Variant #2 Attribute Values validation failed "]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Error Response {Invalid Value Length / Offset}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * --- [label = " Variant #3 Peer cancels operation "]; - * SD<:PEER [label = "ATT Execute Write Request {CANCEL}", textcolor="#000080", linecolor="#000080"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * @endmsc - * - * @defgroup BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC GATTS Queued Writes: Stack handled, one or more attributes require authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_REQUEST {BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES}"]; - * APP=>SD [label = "sd_ble_user_mem_reply {user_mem_block}"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_2, offset_2, peer_value_2}"]; - * |||; - * --- [label = " Variant #1 App Authorizes both Prepare Write and Execute Write"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="App parses the memory it provided"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: peer_value_2"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * --- [label = " Variant #2 App Disallows Prepare Write and Authorizes Execute Write "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, INSUF_AUTHORIZATION)"]; - * SD:>PEER [label = "ATT Error Response {Insufficient Authorization}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="App parses the memory it provided"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * --- [label = " Variant #3 App Authorizes Prepare Write and Disallows Execute Write "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="App parses the memory it provided"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, APP_ERROR_CODE)"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Error Response {APP_ERROR_CODE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * @endmsc - * - * @defgroup BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC GATTS Queued Writes: App handled, no attributes require authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_REQUEST {BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES}"]; - * APP=>SD [label = "sd_ble_user_mem_reply {NULL}"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_1, offset_1, peer_value_1}"]; - * APP rbox APP [label="App queues {handle_1, offset_1, peer_value_1}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_2, offset_2, peer_value_2}"]; - * APP rbox APP [label="App queues {handle_2, offset_2, peer_value_2}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * |||; - * --- [label = " Variant #1 Attribute values in stack memory (VLOC_STACK), attribute values validation passed "]; - * APP=>SD [label = "sd_ble_gatts_value_set {handle_1, offset_1, peer_value_1}"]; - * APP<SD [label = "sd_ble_gatts_value_set {handle_2, offset_2, peer_value_2}"]; - * APP<SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #2 Attribute values in user memory (VLOC_USER), attribute values validation passed "]; - * APP rbox APP [label="Application traverses its queue and executes the write operations (memcpy)"]; - * APP rbox APP [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: peer_value_2"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #3 Attribute values validation failed "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, INVALID_OFFSET)"]; - * APP rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Error Response {Invalid Offset}", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC GATTS Queued Writes: App handled, one or more attributes require authorization - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox APP [label="Values in ATT Table (in user memory):\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_REQUEST {BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES}"]; - * APP=>SD [label = "sd_ble_user_mem_reply {NULL}"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_1, offset_1, peer_value_1}"]; - * APP rbox APP [label="App queues {handle_1, offset_1, peer_value_1}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_2, offset_2, peer_value_2}"]; - * |||; - * --- [label = " Variant #1 App Authorizes both Prepare Write and Execute Write"]; - * APP rbox APP [label="App queues {handle_2, offset_2, peer_value_2}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="Application traverses its queue and executes the write operations (memcpy)"]; - * APP rbox APP [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: peer_value_2"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #2 App Disallows Prepare Write and Authorizes Execute Write "]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, INSUF_AUTHORIZATION)"]; - * SD:>PEER [label = "ATT Error Response {Insufficient Authorization}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="Application traverses its queue and executes the write operations (memcpy)"]; - * APP rbox APP [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: current_value_2"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * |||; - * --- [label = " Variant #3 App Authorizes Prepare Write and Disallows Execute Write "]; - * APP rbox APP [label="App queues {handle_2, offset_2, peer_value_2}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, APP_ERROR_CODE)"]; - * APP rbox APP [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Error Response {APP_ERROR_CODE}", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC GATTS Queued Writes: Prepare Queue Full - * @msc - * hscale = "2"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: current_value_1\nhandle_2: current_value_2"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_REQUEST {BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES}"]; - * |||; - * --- [label = " Variant #1 Stack handled "]; - * APP=>SD [label = "sd_ble_user_mem_reply {user_mem_block}"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * SD:>PEER [label = "ATT Error Response {Prepare Queue Full}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: current_value_2"]; - * APP<<=SD [label = "BLE_GATTS_EVT_WRITE {EXEC_WRITE_REQ_NOW}"]; - * APP rbox APP [label="App parses the memory it provided"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_USER_MEM_RELEASE {user_mem_block}"]; - * |||; - * --- [label = " Variant #2 App handled "]; - * APP=>SD [label = "sd_ble_user_mem_reply {NULL}"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_1, offset_1, peer_value_1}"]; - * APP rbox APP [label="App queues {handle_1, offset_1, peer_value_1}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD:>PEER [label = "ATT Prepare Write Response {handle_1, offset_1, peer_value_1}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Prepare Write Request {handle_2, offset_2, peer_value_2}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, PREP_WRITE_REQ, handle_2, offset_2, peer_value_2}"]; - * APP=>SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, PREPARE_QUEUE_FULL)"]; - * SD:>PEER [label = "ATT Error Response {Prepare Queue Full}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Execute Write Request {WRITE}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST {WRITE, EXEC_WRITE_REQ_NOW}"]; - * APP=>SD [label = "sd_ble_gatts_value_set {handle_1, offset_1, peer_value_1}"]; - * APP<SD [label = "sd_ble_gatts_rw_authorize_reply(WRITE, SUCCESS)"]; - * SD rbox SD [label="Values in ATT Table:\nhandle_1: peer_value_1\nhandle_2: current_value_2"]; - * SD:>PEER [label = "ATT Execute Write Response", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_HVI_MSC GATTS Handle Value Indication - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox PEER [label="Indications Enabled in CCCD"]; - * |||; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * APP=>SD [label = "sd_ble_gatts_hvx(INDICATION, app_value)"]; - * APP<PEER [label = "ATT Handle Value Indication {app_value}", textcolor="#000080", linecolor="#000080"]; - * --- [label = " Variant #1 Peer Confirms "]; - * SD<:PEER [label = "ATT Handle Value Confirmation", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_HVC"]; - * --- [label = " Variant #2 Peer Ignores "]; - * |||; - * ...; - * |||; - * SD box SD [label="Timeout"]; - * APP<<=SD [label = "BLE_GATTS_EVT_TIMEOUT"]; - * @endmsc - * - * @defgroup BLE_GATTS_HVN_MSC GATTS Handle Value Notification - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox PEER [label="Notifications Enabled in CCCD"]; - * |||; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * APP=>SD [label = "sd_ble_gatts_hvx(NOTIFICATION, app_value)"]; - * APP<PEER [label = "ATT Handle Value Notification {app_value}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_TX_COMPLETE"]; - * @endmsc - * - * @defgroup BLE_GATTS_HVX_DISABLED_MSC GATTS Handle Value Indication or Notification disabled - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established"]; - * |||; - * APP rbox PEER [label="Indications and Notifications Disabled in CCCD"]; - * |||; - * SD rbox SD [label="Value in ATT Table: current_value"]; - * APP=>SD [label = "sd_ble_gatts_hvx(INDICATION or NOTIFICATION, app_value)"]; - * APP<SD [label = "sd_ble_gatts_hvx(INDICATION or NOTIFICATION, app_value)"]; - * APP<SD [label = "sd_ble_gatts_sys_attr_set()"]; - * APP<SD [label = "sd_ble_gatts_service_changed(N, M)"]; - * APP<PEER [label = "ATT Handle Value Indication {N, M}", textcolor="#000080", linecolor="#000080"]; - * SD<:PEER [label = "ATT Handle Value Confirmation", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_SC_CONFIRM"]; - * |||; - * SD rbox PEER [label="Service Discovery"]; - * @endmsc - * - * @defgroup BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC GATTS System Attributes Handling: Unknown Peer - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established with an Unknown Peer"]; - * |||; - * SD<:PEER [label = "ATT Read Request {sys_attr_handle}", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_GATTS_EVT_SYS_ATTR_MISSING"]; - * APP=>SD [label = "sd_ble_gatts_sys_attr_set(NULL)"]; - * APP<PEER [label = "ATT Read Response {sys_attr_value}", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * - * @defgroup BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC GATTS System Attributes Handling: Bonded Peer - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP rbox PEER [label="Connection Established with a Bonded Peer"]; - * |||; - * APP rbox PEER [label="ATT Traffic"]; - * |||; - * APP rbox PEER [label="Connection Terminated"]; - * APP<<=SD [label = "BLE_GAP_EVT_DISCONNECTED {reason}"]; - * |||; - * APP=>SD [label = "sd_ble_gatts_sys_attr_get()"]; - * APP<SD [label = "sd_ble_gatts_sys_attr_set(sys_attr_data)"]; - * APP<PEER [label = "ATT Read Response {sys_attr_value}", textcolor="#000080", linecolor="#000080"]; - * @endmsc - * @} - * - * @addtogroup BLE_GATTS_QUEUED_WRITES_USER_MEM User memory layout for Queued Writes - * @{ - * The following table shows the memory layout used by the SoftDevice to queue a Queued Write operation (Prepare Write ATT packet) in user memory: - * - *
    Toolchain Project
    - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
    Queued Write
    ParameterSize (octets)Description
    Handle2Attribute Handle
    Offset2Value Offset
    Length2Value Length
    ValueLengthAttribute Value
    - * - * The application can parse the array of Queued Write instances at any time, but it is recommended to do so whenever an Execute Write ATT packet - * has been received over the air. See the GATT Server Queued Writes MSCs for more details. - * The array will be terminated by an Queued Write instance with its handle set to @ref BLE_GATT_HANDLE_INVALID. - * @} - * @} - */ - -/** - * @addtogroup BLE_L2CAP - * @{ - * @defgroup BLE_L2CAP_MSC Message Sequence Charts - * @{ - * @defgroup BLE_L2CAP_API_MSC L2CAP API - * @msc - * hscale = "1.5"; - * APP,SD,PEER; - * |||; - * APP=>SD [label = "sd_ble_l2cap_cid_register(cid)"]; - * APP<SD [label = "sd_ble_l2cap_tx(data)"]; - * APP<PEER [label = "L2CAP packet", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_EVT_TX_COMPLETE"]; - * SD<:PEER [label = "L2CAP packet", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_L2CAP_EVT_RX"]; - * SD<:PEER [label = "L2CAP packet", textcolor="#000080", linecolor="#000080"]; - * APP<<=SD [label = "BLE_L2CAP_EVT_RX"]; - * |||; - * APP=>SD [label = "sd_ble_l2cap_tx(data)"]; - * APP<PEER [label = "L2CAP packet", textcolor="#000080", linecolor="#000080"]; - * SD=>>APP [label = "BLE_EVT_TX_COMPLETE"]; - * |||; - * APP rbox PEER [label="Terminate Connection"]; - * |||; - * APP=>SD [label = "sd_ble_l2cap_cid_unregister(cid)"]; - * APP<_EVT series. */ - uint16_t evt_len; /**< Length in octets excluding this header. */ -} ble_evt_hdr_t; - -/**@brief Common BLE Event type, wrapping the module specific event reports. */ -typedef struct -{ - ble_evt_hdr_t header; /**< Event header. */ - union - { - ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ - ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ - ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ - ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ - ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ - } evt; -} ble_evt_t; - - -/** - * @brief Version Information. - */ -typedef struct -{ - uint8_t version_number; /**< Link Layer Version number for BT 4.1 spec is 7 (https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer). */ - uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ - uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ -} ble_version_t; - -/**@brief Mutual exclusion of radio activity and CPU execution. - * - * This option configures the application's access to the CPU when the radio is active. The - * application can configure itself to have access to the CPU while the radio is active. - * By default, the application will be not able to share CPU time with the SoftDevice - * during radio activity. This parameter structure is used together with @ref sd_ble_opt_set - * to configure the @ref BLE_COMMON_OPT_RADIO_CPU_MUTEX option. - * - * @note Note that the mutual exclusion of radio activity and CPU execution should remain enabled - * when running the SoftDevice on hardware affected by PAN #44 "CCM may exceed real time - * requirements"and PAN #45 "AAR may exceed real time requirements". - * - * @note @ref sd_ble_opt_get is not supported for this option. - * - */ -typedef struct -{ - uint8_t enable : 1; /**< Enable mutual exclusion of radio activity and the CPU execution. */ -} ble_common_opt_radio_cpu_mutex_t; - -/**@brief Option structure for common options. */ -typedef union -{ - ble_common_opt_radio_cpu_mutex_t radio_cpu_mutex; /**< Parameters for the option for the mutual exclusion of radio activity and CPU execution. */ -} ble_common_opt_t; - -/**@brief Common BLE Option type, wrapping the module specific options. */ -typedef union -{ - ble_common_opt_t common_opt; /**< Common option, opt_id in BLE_COMMON_OPT_* series. */ - ble_gap_opt_t gap; /**< GAP option, opt_id in BLE_GAP_OPT_* series. */ -} ble_opt_t; - -/** - * @brief BLE GATTS init options - */ -typedef struct -{ - ble_gatts_enable_params_t gatts_enable_params; /**< GATTS init options @ref ble_gatts_enable_params_t. */ -} ble_enable_params_t; - -/** @} */ - -/** @addtogroup BLE_COMMON_FUNCTIONS Functions - * @{ */ - -/**@brief Enable the bluetooth stack - * - * @param[in] p_ble_enable_params Pointer to ble_enable_params_t - * - * @details This call initializes the bluetooth stack, no other BLE related call can be called before this one has been executed. - * - * @return @ref NRF_SUCCESS BLE stack has been initialized successfully - * @return @ref NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. - */ -SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(ble_enable_params_t * p_ble_enable_params)); - -/**@brief Get an event from the pending events queue. - * - * @param[in] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. This buffer must be 4-byte aligned in memory. - * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length. - * - * @details This call allows the application to pull a BLE event from the BLE stack. The application is signalled that an event is - * available from the BLE Stack by the triggering of the SD_EVT_IRQn interrupt (mapped to IRQ 22). - * The application is free to choose whether to call this function from thread mode (main context) or directly from the Interrupt Service Routine - * that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher priority than the application, this function should be called - * in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the stack. - * Failure to do so could potentially leave events in the internal queue without the application being aware of this fact. - * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to be copied into - * application memory. If the buffer provided is not large enough to fit the entire contents of the event, @ref NRF_ERROR_DATA_SIZE will be returned - * and the application can then call again with a larger buffer size. - * Please note that because of the variable length nature of some events, sizeof(ble_evt_t) will not always be large enough to fit certain events, - * and so it is the application's responsability to provide an amount of memory large enough so that the relevant event is copied in full. - * The application may "peek" the event length by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return. - * - * @note The pointer supplied must be aligned to the extend defined by @ref BLE_EVTS_PTR_ALIGNMENT - * - * @return @ref NRF_SUCCESS Event pulled and stored into the supplied buffer. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. - * @return @ref NRF_ERROR_NOT_FOUND No events ready to be pulled. - * @return @ref NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. - */ -SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t* p_dest, uint16_t *p_len)); - - -/**@brief Get the total number of available application transmission buffers in the BLE stack. - * - * @details This call allows the application to obtain the total number of - * transmission buffers available for application data. Please note that - * this does not give the number of free buffers, but rather the total amount of them. - * The application has two options to handle its own application transmission buffers: - * - Use a simple arithmetic calculation: at boot time the application should use this function - * to find out the total amount of buffers available to it and store it in a variable. - * Every time a packet that consumes an application buffer is sent using any of the - * exposed functions in this BLE API, the application should decrement that variable. - * Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event is received by the application - * it should retrieve the count field in such event and add that number to the same - * variable storing the number of available packets. - * This mechanism allows the application to be aware at any time of the number of - * application packets available in the BLE stack's internal buffers, and therefore - * it can know with certainty whether it is possible to send more data or it has to - * wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds. - * - Choose to simply not keep track of available buffers at all, and instead handle the - * @ref BLE_ERROR_NO_TX_BUFFERS error by queueing the packet to be transmitted and - * try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives. - * - * The API functions that may consume an application buffer depending on - * the parameters supplied to them can be found below: - * - * - @ref sd_ble_gattc_write (write witout response only) - * - @ref sd_ble_gatts_hvx (notifications only) - * - @ref sd_ble_l2cap_tx (all packets) - * - * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission buffers upon - * successful return. - * - * @return @ref NRF_SUCCESS Number of application transmission buffers retrieved successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_TX_BUFFER_COUNT_GET, uint32_t, sd_ble_tx_buffer_count_get(uint8_t* p_count)); - - -/**@brief Add a Vendor Specific UUID. - * - * @details This call enables the application to add a vendor specific UUID to the BLE stack's table, - * for later use all other modules and APIs. This then allows the application to use the shorter, - * 24-bit @ref ble_uuid_t format when dealing with both 16-bit and 128-bit UUIDs without having to - * check for lengths and having split code paths. The way that this is accomplished is by extending the - * grouping mechanism that the Bluetooth SIG standard base UUID uses for all other 128-bit UUIDs. The - * type field in the @ref ble_uuid_t structure is an index (relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN) - * to the table populated by multiple calls to this function, and the uuid field in the same structure - * contains the 2 bytes at indices 12 and 13. The number of possible 128-bit UUIDs available to the - * application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536, - * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array. - * - * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by - * the 16-bit uuid field in @ref ble_uuid_t. - * - * - * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding - * bytes 12 and 13. - * @param[out] p_uuid_type Pointer where the type field in @ref ble_uuid_t corresponding to this UUID will be stored. - * - * @return @ref NRF_SUCCESS Successfully added the Vendor Specific UUID. - * @return @ref NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. - * @return @ref NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. - * @return @ref NRF_ERROR_FORBIDDEN If p_vs_uuid has already been added to the VS UUID table. - */ -SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const * const p_vs_uuid, uint8_t * const p_uuid_type)); - - -/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. - * - * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared - * to the corresponding ones in each entry of the table of vendor specific UUIDs pouplated with @ref sd_ble_uuid_vs_add - * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index - * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type. - * - * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE. - * - * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes). - * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes. - * @param[in,out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in. - * - * @return @ref NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_LENGTH Invalid UUID length. - * @return @ref NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. - */ -SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const * const p_uuid_le, ble_uuid_t * const p_uuid)); - - -/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). - * - * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validitiy and size of p_uuid is computed. - * - * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes. - * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes). - * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored. - * - * @return @ref NRF_SUCCESS Successfully encoded into the buffer. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid UUID type. - */ -SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const * const p_uuid, uint8_t * const p_uuid_le_len, uint8_t * const p_uuid_le)); - - -/**@brief Get Version Information. - * - * @details This call allows the application to get the BLE stack version information. - * - * @param[in] p_version Pointer to ble_version_t structure to be filled in. - * - * @return @ref NRF_SUCCESS Version information stored successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY The stack is busy (typically doing a locally-initiated disconnection procedure). - */ -SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t * p_version)); - - -/**@brief Provide a user memory block. - * - * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_block Pointer to a user memory block structure. - * - * @return @ref NRF_SUCCESS Successfully queued a response to the peer. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_STATE No execute write request pending. - */ -SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t *p_block)); - - -/**@brief Set a BLE option. - * - * @details This call allows the application to set the value of an option. - * - * @param[in] opt_id Option ID. - * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value. - * - * @retval ::NRF_SUCCESS Option set successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time. - * @retval ::NRF_ERROR_BUSY The stack is busy or the previous procedure has not completed. - */ -SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)); - - -/**@brief Get a BLE option. - * - * @details This call allows the application to retrieve the value of an option. - * - * @param[in] opt_id Option ID. - * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in. - * - * @retval ::NRF_SUCCESS Option retrieved successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time. - * @retval ::NRF_ERROR_BUSY The stack is busy or the previous procedure has not completed. - * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. - * - */ -SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); - -/** @} */ - -#endif /* BLE_H__ */ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_err.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_err.h deleted file mode 100644 index 19f43a9275..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_err.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - /** - @addtogroup BLE_COMMON - @{ - @addtogroup nrf_error - @{ - @ingroup BLE_COMMON - @} - - @defgroup ble_err General error codes - @{ - - @brief General error code definitions for the BLE API. - - @ingroup BLE_COMMON -*/ -#ifndef NRF_BLE_ERR_H__ -#define NRF_BLE_ERR_H__ - -#include "nrf_error.h" - -/* @defgroup BLE_ERRORS Error Codes - * @{ */ -#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ -#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ -#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ -#define BLE_ERROR_NO_TX_BUFFERS (NRF_ERROR_STK_BASE_NUM+0x004) /**< Buffer capacity exceeded. */ -/** @} */ - - -/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges - * @brief Assignment of subranges for module specific error codes. - * @note For specific error codes, see ble_.h or ble_error_.h. - * @{ */ -#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ -#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ -#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ -#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ -/** @} */ - -#endif - - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gap.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gap.h deleted file mode 100644 index 4e508cacc3..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gap.h +++ /dev/null @@ -1,1035 +0,0 @@ -/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @addtogroup BLE_GAP Generic Access Profile (GAP) - @{ - @brief Definitions and prototypes for the GAP interface. - */ - -#ifndef BLE_GAP_H__ -#define BLE_GAP_H__ - -#include "ble_types.h" -#include "ble_ranges.h" -#include "nrf_svc.h" - - -/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations - * @{ */ - -/**@brief GAP API SVC numbers. - */ -enum BLE_GAP_SVCS -{ - SD_BLE_GAP_ADDRESS_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ - SD_BLE_GAP_ADDRESS_GET, /**< Get own Bluetooth Address. */ - SD_BLE_GAP_ADV_DATA_SET, /**< Set Advertisement Data. */ - SD_BLE_GAP_ADV_START, /**< Start Advertising. */ - SD_BLE_GAP_ADV_STOP, /**< Stop Advertising. */ - SD_BLE_GAP_CONN_PARAM_UPDATE, /**< Connection Parameter Update. */ - SD_BLE_GAP_DISCONNECT, /**< Disconnect. */ - SD_BLE_GAP_TX_POWER_SET, /**< Set TX Power. */ - SD_BLE_GAP_APPEARANCE_SET, /**< Set Appearance. */ - SD_BLE_GAP_APPEARANCE_GET, /**< Get Appearance. */ - SD_BLE_GAP_PPCP_SET, /**< Set PPCP. */ - SD_BLE_GAP_PPCP_GET, /**< Get PPCP. */ - SD_BLE_GAP_DEVICE_NAME_SET, /**< Set Device Name. */ - SD_BLE_GAP_DEVICE_NAME_GET, /**< Get Device Name. */ - SD_BLE_GAP_AUTHENTICATE, /**< Initiate Pairing/Bonding. */ - SD_BLE_GAP_SEC_PARAMS_REPLY, /**< Reply with Security Parameters. */ - SD_BLE_GAP_AUTH_KEY_REPLY, /**< Reply with an authentication key. */ - SD_BLE_GAP_SEC_INFO_REPLY, /**< Reply with Security Information. */ - SD_BLE_GAP_CONN_SEC_GET, /**< Obtain connection security level. */ - SD_BLE_GAP_RSSI_START, /**< Start reporting of changes in RSSI. */ - SD_BLE_GAP_RSSI_STOP, /**< Stop reporting of changes in RSSI. */ -}; -/**@} */ - -/**@addtogroup BLE_GAP_DEFINES Defines - * @{ */ - -/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP - * @{ */ -#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */ -#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */ -#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */ -/**@} */ - - -/**@defgroup BLE_GAP_ROLES GAP Roles - * @note Not explicitly used in peripheral API, but will be relevant for central API. - * @{ */ -#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */ -#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */ -#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */ -/**@} */ - - -/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources - * @{ */ -#define BLE_GAP_TIMEOUT_SRC_ADVERTISEMENT 0x00 /**< Advertisement timeout. */ -#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST 0x01 /**< Security request timeout. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types - * @{ */ -#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random Static address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Private Resolvable address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Private Non-Resolvable address. */ -/**@} */ - -/**@defgroup BLE_GAP_ADDR_CYCLE_MODES GAP Address cycle modes - * @{ */ -#define BLE_GAP_ADDR_CYCLE_MODE_NONE 0x00 /**< Set addresses directly, no automatic address cycling. */ -#define BLE_GAP_ADDR_CYCLE_MODE_AUTO 0x01 /**< Automatically generate and update private addresses. */ -/** @} */ - -/**@brief The default interval in seconds at which a private address is refreshed when address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. */ -#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (60 * 15) - -/** @brief BLE address length. */ -#define BLE_GAP_ADDR_LEN 6 - - -/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format - * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm - * @{ */ -#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */ -#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */ -#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */ -#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */ -#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */ -#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */ -#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */ -#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */ -#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */ -#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data - 16-bit UUID. */ -#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */ -#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */ -#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */ -#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL 0x1A /**< Advertising Interval. */ -#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B /**< LE Bluetooth Device Address. */ -#define BLE_GAP_AD_TYPE_LE_ROLE 0x1C /**< LE Role. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256 0x1D /**< Simple Pairing Hash C-256. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256 0x1E /**< Simple Pairing Randomizer R-256. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID 0x20 /**< Service Data - 32-bit UUID. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID 0x21 /**< Service Data - 128-bit UUID. */ -#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA 0x3D /**< 3D Information Data. */ -#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags - * @{ */ -#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */ -#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */ -#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */ -#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */ -#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */ -#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */ -#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min - * @{ */ -#define BLE_GAP_ADV_INTERVAL_MIN 0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ -#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */ -#define BLE_GAP_ADV_INTERVAL_MAX 0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ - /**@} */ - - -/**@brief Maximum size of advertising data in octets. */ -#define BLE_GAP_ADV_MAX_SIZE 31 - - -/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types - * @{ */ -#define BLE_GAP_ADV_TYPE_ADV_IND 0x00 /**< Connectable undirected. */ -#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND 0x01 /**< Connectable directed. */ -#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND 0x02 /**< Scannable undirected. */ -#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND 0x03 /**< Non connectable undirected. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies - * @{ */ -#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */ -#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */ -#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */ -#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values - * @{ */ -#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX 180 /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s in spec (Addendum 2)). */ -#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED 0 /**< Unlimited advertising in general discoverable mode. */ -/**@} */ - - -/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes - * @{ */ -#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */ -#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */ -#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */ -/**@} */ - -/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities - * @{ */ -#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */ -#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */ -#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */ -#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */ -#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */ -/**@} */ - - -/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types - * @{ */ -#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */ -#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */ -#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */ -/**@} */ - -/**@defgroup BLE_GAP_SEC_STATUS GAP Security status - * @{ */ -#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Successful parameters. */ -#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */ -#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */ -#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user cancelled or other). */ -#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */ -#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */ -#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */ -#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */ -#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */ -#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */ -#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */ -#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */ -#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */ -/**@} */ - -/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources - * @{ */ -#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */ -#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */ -/**@} */ - -/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits - * @{ */ -#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connction interval specified in connect parameters. */ -#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest mimimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ -#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connction interval specified in connect parameters. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ -#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x03E8 /**< Highest slave latency permitted, in connection events. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */ -/**@} */ - - -/**@brief GAP device name maximum length. */ -#define BLE_GAP_DEVNAME_MAX_LEN 31 - - -/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters - * - * See @ref ble_gap_conn_sec_mode_t. - * @{ */ -/**@brief Set sec_mode pointed to by ptr to have no access rights.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) -/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) -/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) -/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) -/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) -/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) -/**@} */ - - -/**@brief GAP Security Key Length. */ -#define BLE_GAP_SEC_KEY_LEN 16 - -/**@brief GAP Passkey Length. */ -#define BLE_GAP_PASSKEY_LEN 6 - -/**@brief Maximum amount of addresses in a whitelist. */ -#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8) - -/**@brief Maximum amount of IRKs in a whitelist. - * @note The number of IRKs is limited to 8, even if the hardware supports more. - */ -#define BLE_GAP_WHITELIST_IRK_MAX_COUNT (8) - -/**@defgroup GAP_SEC_MODES GAP Security Modes - * @{ */ -#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */ -/**@} */ - -/**@} */ - -/**@addtogroup BLE_GAP_STRUCTURES Structures - * @{ */ - -/**@brief Bluetooth Low Energy address. */ -typedef struct -{ - uint8_t addr_type; /**< See @ref BLE_GAP_ADDR_TYPES. */ - uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. */ -} ble_gap_addr_t; - - -/**@brief GAP connection parameters. - * - * @note When ble_conn_params_t is received in an event, both min_conn_interval and - * max_conn_interval will be equal to the connection interval set by the central. - */ -typedef struct -{ - uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ -} ble_gap_conn_params_t; - - -/**@brief GAP link requirements. - * - * See Bluetooth Core specification, Volume 3 Part C 10.2 for details. - * - * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n - * Security Mode 1 Level 1: No security is needed (aka open link).\n - * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n - * Security Mode 1 Level 3: MITM protected encrypted link required.\n - * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n - * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n - */ -typedef struct -{ - uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ - uint8_t lv : 4; /**< Level (1, 2 or 3), 0 for no permissions at all. */ - -} ble_gap_conn_sec_mode_t; - - -/**@brief GAP connection security status.*/ -typedef struct -{ - ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ - uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ -} ble_gap_conn_sec_t; - - -/**@brief Identity Resolving Key. */ -typedef struct -{ - uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ -} ble_gap_irk_t; - - -/**@brief Whitelist structure. */ -typedef struct -{ - ble_gap_addr_t ** pp_addrs; /**< Pointer to array of device address pointers, pointing to addresses to be used in whitelist. NULL if none are given. */ - uint8_t addr_count; /**< Count of device addresses in array, up to @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. */ - ble_gap_irk_t ** pp_irks; /**< Pointer to array of Identity Resolving Key (IRK) pointers, each pointing to an IRK in the whitelist. NULL if none are given. */ - uint8_t irk_count; /**< Count of IRKs in array, up to @ref BLE_GAP_WHITELIST_IRK_MAX_COUNT. */ -} ble_gap_whitelist_t; - - -/**@brief GAP advertising parameters.*/ -typedef struct -{ - uint8_t type; /**< See @ref BLE_GAP_ADV_TYPES. */ - ble_gap_addr_t* p_peer_addr; /**< For BLE_GAP_CONN_MODE_DIRECTED mode only, known peer address. */ - uint8_t fp; /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */ - ble_gap_whitelist_t * p_whitelist; /**< Pointer to whitelist, NULL if none is given. */ - uint16_t interval; /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS. - - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for high duty cycle directed advertising. - - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, set @ref BLE_GAP_ADV_INTERVAL_MIN <= interval <= @ref BLE_GAP_ADV_INTERVAL_MAX for low duty cycle advertising */ - uint16_t timeout; /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for High duty cycle directed advertising. */ -} ble_gap_adv_params_t; - - -/**@brief GAP scanning parameters. */ -typedef struct -{ - uint8_t filter; /**< Filter based on discovery mode, see @ref BLE_GAP_DISC_MODES. */ - uint8_t active : 1; /**< If 1, perform active scanning (scan requests). */ - uint8_t selective : 1; /**< If 1, ignore unknown devices (non whitelisted). */ - uint16_t interval; /**< Scan interval between 0x0020 and 0x4000 in 0.625ms units (20ms to 10.24s). */ - uint16_t window; /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ - uint16_t timeout; /**< Scan timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. */ -} ble_gap_scan_params_t; - - -/**@brief GAP security parameters. */ -typedef struct -{ - uint16_t timeout; /**< Timeout for SMP transactions or Security Request in seconds, see @ref sd_ble_gap_authenticate and @ref sd_ble_gap_sec_params_reply for more information. */ - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Man In The Middle protection required. */ - uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ - uint8_t oob : 1; /**< Out Of Band data available. */ - uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. */ - uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ -} ble_gap_sec_params_t; - - -/**@brief GAP Encryption Information. */ -typedef struct -{ - uint16_t div; /**< Encryption Diversifier. */ - uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ - uint8_t auth : 1; /**< Authenticated Key. */ - uint8_t ltk_len : 7; /**< LTK length in octets. */ -} ble_gap_enc_info_t; - - -/**@brief GAP Master Identification. */ -typedef struct -{ - uint16_t ediv; /**< Encrypted Diversifier. */ - uint8_t rand[8]; /**< Random Number. */ -} ble_gap_master_id_t; - - -/**@brief GAP Identity Information. */ -typedef struct -{ - ble_gap_addr_t addr; /**< Bluetooth address to which this key applies. */ - uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Identity Resolution Key. */ -} ble_gap_id_info_t; - - -/**@brief GAP Signing Information. */ -typedef struct -{ - uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /* Connection Signature Resolving Key. */ -} ble_gap_sign_info_t; - - -/**@brief GAP Event IDs. - * Those IDs uniquely identify an event coming from the stack to the application. - */ -enum BLE_GAP_EVTS -{ - BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connection established. */ - BLE_GAP_EVT_DISCONNECTED, /**< Disconnected from peer. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE, /**< Connection Parameters updated. */ - BLE_GAP_EVT_SEC_PARAMS_REQUEST, /**< Request to provide security parameters. */ - BLE_GAP_EVT_SEC_INFO_REQUEST, /**< Request to provide security information. */ - BLE_GAP_EVT_PASSKEY_DISPLAY, /**< Request to display a passkey to the user. */ - BLE_GAP_EVT_AUTH_KEY_REQUEST, /**< Request to provide an authentication key. */ - BLE_GAP_EVT_AUTH_STATUS, /**< Authentication procedure completed with status. */ - BLE_GAP_EVT_CONN_SEC_UPDATE, /**< Connection security updated. */ - BLE_GAP_EVT_TIMEOUT, /**< Timeout expired. */ - BLE_GAP_EVT_RSSI_CHANGED, /**< Signal strength measurement report. */ -}; - - -/** - * @brief GAP Option IDs. - * IDs that uniquely identify a GAP option. - */ -enum BLE_GAP_OPTS -{ - BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE, /**< Local connection latency. */ - BLE_GAP_OPT_PASSKEY, /**< Set passkey to be used during pairing. This option can be used to make the SoftDevice use an application provided passkey instead of generating a random passkey.*/ - BLE_GAP_OPT_PRIVACY, /**< Set or get custom IRK or custom private address cycle interval. */ -}; -/**@} */ - - -/**@brief Event data for connected event. */ -typedef struct -{ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - uint8_t irk_match :1; /**< If 1, peer device's address resolved using an IRK. */ - uint8_t irk_match_idx :7; /**< Index in IRK list where the address was matched. */ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ -} ble_gap_evt_connected_t; - - -/**@brief Event data for disconnected event. */ -typedef struct -{ - uint8_t reason; /**< HCI error code. */ -} ble_gap_evt_disconnected_t; - - -/**@brief Event data for connection parameter update event. */ -typedef struct -{ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ -} ble_gap_evt_conn_param_update_t; - - -/**@brief Event data for security parameters request event. */ -typedef struct -{ - ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ -} ble_gap_evt_sec_params_request_t; - - -/**@brief Event data for security info request event. */ -typedef struct -{ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - uint16_t div; /**< Encryption diversifier for LTK lookup. */ - uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ - uint8_t id_info : 1; /**< If 1, Identity Information required. */ - uint8_t sign_info : 1; /**< If 1, Signing Information required. */ -} ble_gap_evt_sec_info_request_t; - - -/**@brief Event data for passkey display event. */ -typedef struct -{ - uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ -} ble_gap_evt_passkey_display_t; - - -/**@brief Event data for authentication key request event. */ -typedef struct -{ - uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ -} ble_gap_evt_auth_key_request_t; - - -/**@brief Security levels supported. - * @note See Bluetooth Specification Version 4.1 Volume 3, Part C, Chapter 10. -*/ -typedef struct -{ - uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ - uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ - uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ -} ble_gap_sec_levels_t; - - -/**@brief Keys that have been exchanged. */ -typedef struct -{ - uint8_t ltk : 1; /**< Long Term Key. */ - uint8_t ediv_rand : 1; /**< Encrypted Diversifier and Random value. */ - uint8_t irk : 1; /**< Identity Resolving Key. */ - uint8_t address : 1; /**< Public or static random address. */ - uint8_t csrk : 1; /**< Connection Signature Resolving Key. */ -} ble_gap_sec_keys_t; - - -/**@brief Event data for authentication status event. */ -typedef struct -{ - uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ - uint8_t error_src; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ - ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ - ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ - ble_gap_sec_keys_t periph_kex; /**< Bitmap stating which keys were exchanged (distributed) by the peripheral. */ - ble_gap_sec_keys_t central_kex; /**< Bitmap stating which keys were exchanged (distributed) by the central. */ - struct periph_keys_t - { - ble_gap_enc_info_t enc_info; /**< Peripheral's Encryption information. */ - } periph_keys; /**< Actual keys distributed from the Peripheral to the Central. */ - struct central_keys_t - { - ble_gap_irk_t irk; /**< Central's IRK. */ - ble_gap_addr_t id_info; /**< Central's Identity Info. */ - } central_keys; /**< Actual keys distributed from the Central to the Peripheral. */ -} ble_gap_evt_auth_status_t; - - -/**@brief Event data for connection security update event. */ -typedef struct -{ - ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ -} ble_gap_evt_conn_sec_update_t; - - -/**@brief Event data for timeout event. */ -typedef struct -{ - uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ -} ble_gap_evt_timeout_t; - - -/**@brief Event data for advertisement report event. */ -typedef struct -{ - int8_t rssi; /**< Received Signal Strength Indication in dBm. */ -} ble_gap_evt_rssi_changed_t; - - -/**@brief GAP event callback event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occured. */ - union /**< union alternative identified by evt_id in enclosing struct. */ - { - ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ - ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ - ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ - ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ - ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ - ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ - ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ - ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ - ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event parameters. */ - } params; - -} ble_gap_evt_t; - - -/**@brief Local connection latency option. - * - * Local connection latency is a feature which enables the slave to improve - * current consumption by ignoring the slave latency set by the peer. The - * local connection latency can only be set to a multiple of the slave latency, - * and cannot be longer than half of the supervision timeout. - * - * Used with @ref sd_ble_opt_set to set the local connection latency. The - * @ref sd_ble_opt_get is not supported for this option, but the actual - * local connection latency (unless set to NULL) is set as a return parameter - * when setting the option. - * - * @note The latency set will be truncated down to the closest slave latency event - * multiple, or the nearest multiple before half of the supervision timeout. - * - * @note The local connection latency is default off, and needs to be set for new - * connections and whenever the connection is updated. - * - * @retval ::NRF_SUCCESS Set successfully. - * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. - */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle */ - uint16_t requested_latency; /**< Requested local connection latency. */ - uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ -} ble_gap_opt_local_conn_latency_t; - - -/**@brief Passkey Option. - * - * Structure containing the passkey to be used during pairing. This can be used with @ref - * sd_ble_opt_set to make the SoftDevice use a pre-programmed passkey for authentication - * instead of generating a random one. - * - * @note @ref sd_ble_opt_get is not supported for this option. - * - */ -typedef struct -{ - uint8_t * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ -} ble_gap_opt_passkey_t; - - -/**@brief Custom Privacy Options. - * - * @note The specified address cycle interval is used when the address cycle mode is - * @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. If 0 is given, the address will not be refreshed at any - * interval, and not at start of advertising. A new address can be generated manually by calling - * @ref sd_ble_gap_address_set with the same type again. The default interval is - * @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. - * - * @note If cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address will immediately be - * refreshed when this option is set. - */ -typedef struct -{ - ble_gap_irk_t * p_irk; /**< When input: Pointer to custom IRK, or NULL to use/reset to the device's default IRK. When output: Pointer to where the current IRK is to be stored, or NULL to not read out the IRK. */ - uint16_t interval_s; /**< When input: Custom private address cycle interval in seconds. When output: The current private address cycle interval. */ -} ble_gap_opt_privacy_t; - - -/**@brief Option structure for GAP options. */ -typedef union -{ - ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Local connection latency. */ - ble_gap_opt_passkey_t passkey; /**< Passkey to be used for pairing.*/ - ble_gap_opt_privacy_t privacy; /**< Custom privacy options. */ -} ble_gap_opt_t; -/**@} */ - - -/**@addtogroup BLE_GAP_FUNCTIONS Functions - * @{ */ - -/**@brief Set local Bluetooth address. - * - * If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address type is required to - * be @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or - * @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. The given address is ignored and the - * SoftDevice will generate a new private address automatically every time advertising is - * (re)started, and every @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S seconds. If this API - * call is used again with the same parameters while advertising, the SoftDevice will immediately - * generate a new private address to replace the current address. - * - * If the application wishes to use a @ref BLE_GAP_ADDR_TYPE_PUBLIC or - * @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC address, the cycle mode must be - * @ref BLE_GAP_ADDR_CYCLE_MODE_NONE. - * - * If this API function is called while advertising, the softdevice will immediately update the - * advertising address without the need to stop advertising in the following cases: - * - If the previously set address is of type @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address - * is also of type @ref BLE_GAP_ADDR_TYPE_PUBLIC - * - If the previously set address is not @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address is - * also not @ref BLE_GAP_ADDR_TYPE_PUBLIC. - * - * If the address is changed from a @ref BLE_GAP_ADDR_TYPE_PUBLIC address to another type or from - * another type to a @ref BLE_GAP_ADDR_TYPE_PUBLIC address, the change will take effect the next - * time advertising is started. - * - * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_NONE and the application is - * using privacy, the application must take care to generate and set new private addresses - * periodically to comply with the Privacy specification in Bluetooth Core Spec. - * - * @param[in] addr_cycle_mode Address cycle mode, see @ref BLE_GAP_ADDR_CYCLE_MODES. - * @param[in] p_addr Pointer to address structure. - * - * @return @ref NRF_SUCCESS Address successfully set. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameters. - * @return @ref BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address. - * @return @ref NRF_ERROR_BUSY The stack is busy, process pending events and retry. - */ -SVCALL(SD_BLE_GAP_ADDRESS_SET, uint32_t, sd_ble_gap_address_set(uint8_t addr_cycle_mode, ble_gap_addr_t const * const p_addr)); - - -/**@brief Get local Bluetooth address. - * - * @param[out] p_addr Pointer to address structure. - * - * @return @ref NRF_SUCCESS Address successfully retrieved. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_ADDRESS_GET, uint32_t, sd_ble_gap_address_get(ble_gap_addr_t * const p_addr)); - - -/**@brief Set, clear or update advertisement and scan response data. - * - * @note The format of the advertisement data will be checked by this call to ensure interoperability. - * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and - * duplicating the local name in the advertisement data and scan response data. - * - * @note: To clear the advertisement data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding - * length (dlen/srdlen) set to 0. - * - * @note: The call will fail if p_data and p_sr_data are both NULL since this would have no effect. - * - * @param[in] p_data Raw data to be placed in advertisement packet. If NULL, no changes are made to the current advertisement packet data. - * @param[in] dlen Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL. - * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data. - * @param[in] srdlen Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL. - * - * @return @ref NRF_SUCCESS Advertisement data successfully updated or cleared. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied. - * @return @ref NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification. - * @return @ref NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied. - * @return @ref BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. - * @return @ref NRF_ERROR_BUSY The stack is busy, process pending events and retry. - */ -SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const * const p_data, uint8_t dlen, uint8_t const * const p_sr_data, uint8_t srdlen)); - - -/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). - * - * @param[in] p_adv_params Pointer to advertising parameters structure. - * - * @return @ref NRF_SUCCESS The BLE stack has started advertising. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits. - * @return @ref BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied. - * @return @ref BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible. - */ -SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const * const p_adv_params)); - - -/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). - * - * @return @ref NRF_SUCCESS The BLE stack has stopped advertising. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state). - */ -SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void)); - - -/**@brief Update connection parameters. - * - * @details In the central role this will initiate a Link Layer connection parameter update procedure, - * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for - * the central to perform the procedure. In both cases, and regardless of success or failure, the application - * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event. - * - * @note If both a connection supervision timeout and a maximum connection interval are specified, then the following constraint - * applies: (conn_sup_timeout * 8) >= (max_conn_interval * (slave_latency + 1)) - * - * @param[in] conn_handle Connection handle. - * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role, - * the parameters in the PPCP characteristic of the GAP service will be used instead. - * - * @return @ref NRF_SUCCESS The Connection Update procedure has been started successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @return @ref NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and retry. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const * const p_conn_params)); - - -/**@brief Disconnect (GAP Link Termination). - * - * @details This call initiates the disconnection procedure, and its completion will be communicated to the application - * with a BLE_GAP_EVT_DISCONNECTED event. - * - * @param[in] conn_handle Connection handle. - * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are BTLE_REMOTE_USER_TERMINATED_CONNECTION and BTLE_CONN_INTERVAL_UNACCEPTABLE). - * - * @return @ref NRF_SUCCESS The disconnection procedure has been started successfully. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress or not connected at all). - */ -SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)); - - -/**@brief Set the radio's transmit power. - * - * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm). - * - * @note -40 dBm will not actually give -40 dBm, but will instead be remapped to -30 dBm. - * - * @return @ref NRF_SUCCESS Successfully changed the transmit power. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_BUSY The stack is busy, process pending events and retry. - */ -SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power)); - - -/**@brief Set GAP Appearance value. - * - * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES. - * - * @return @ref NRF_SUCCESS Appearance value set successfully. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - */ -SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance)); - - -/**@brief Get GAP Appearance value. - * - * @param[out] p_appearance Appearance (16-bit), see @ref BLE_APPEARANCES. - * - * @return @ref NRF_SUCCESS Appearance value retrieved successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t * const p_appearance)); - - -/**@brief Set GAP Peripheral Preferred Connection Parameters. - * - * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters. - * - * @return @ref NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - */ -SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const * const p_conn_params)); - - -/**@brief Get GAP Peripheral Preferred Connection Parameters. - * - * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored. - * - * @return @ref NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t * const p_conn_params)); - - -/**@brief Set GAP device name. - * - * @param[in] p_write_perm Write permissions for the Device Name characteristic see @ref ble_gap_conn_sec_mode_t. - * @param[in] p_dev_name Pointer to a UTF-8 encoded, non NULL-terminated string. - * @param[in] len Length of the UTF-8, non NULL-terminated string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN). - * - * @return @ref NRF_SUCCESS GAP device name and permissions set successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const * const p_write_perm, uint8_t const * const p_dev_name, uint16_t len)); - - -/**@brief Get GAP device name. - * - * @param[in] p_dev_name Pointer to an empty buffer where the UTF-8 non NULL-terminated string will be placed. Set to NULL to obtain the complete device name length. - * @param[in,out] p_len Length of the buffer pointed by p_dev_name, complete device name length on output. - * - * @note If the device name is longer than the size of the supplied buffer, - * p_len will return the complete device name length, - * and not the number of bytes actually returned in p_dev_name. - * The application may use this information to allocate a suitable buffer size. - * - * @return @ref NRF_SUCCESS GAP device name retrieved successfully. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * const p_dev_name, uint16_t * const p_len)); - - -/**@brief Initiate GAP Authentication procedure. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing procedure. - * - * @details In the central role, this function will send an SMP Pairing Request, otherwise in the peripheral role, an SMP Security Request will be sent. - * In the peripheral role, only the timeout, bond and mitm fields of @ref ble_gap_sec_params_t are used. - * - * @note The GAP Authentication procedure may be triggered by the central without calling this function when accessing a secure service. - * @note Calling this function may result in the following events depending on the outcome and parameters: @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, - * @ref BLE_GAP_EVT_SEC_INFO_REQUEST, @ref BLE_GAP_EVT_AUTH_KEY_REQUEST, @ref BLE_GAP_EVT_AUTH_STATUS. - * @note The timeout parameter in @ref ble_gap_sec_params_t is interpreted here as the Security Request timeout - * - * - * @return @ref NRF_SUCCESS Successfully initiated authentication procedure. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @return @ref NRF_ERROR_TIMEOUT A SMP timeout has occured, and further SMP operations on this link is prohibited. - */ -SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const * const p_sec_params)); - - -/**@brief Reply with GAP security parameters. - * - * @param[in] conn_handle Connection handle. - * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS. - * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * @note The timeout parameter in @ref ble_gap_sec_params_t is interpreted here as the SMP procedure timeout, and must be 30 seconds. The function will fail - * if the application supplies a different value. - * - * @return @ref NRF_SUCCESS Successfully accepted security parameter from the application. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const * const p_sec_params)); - - -/**@brief Reply with an authentication key. - * - * @param[in] conn_handle Connection handle. - * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES. - * @param[in] key If key type is BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL. - * If key type is BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination). - * If key type is BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST, calling it at other times will result in an NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * - * @return @ref NRF_SUCCESS Authentication key successfully set. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const * const key)); - - -/**@brief Reply with GAP security information. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available. - * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * @note Data signing is not implemented yet. p_sign_info must therefore be NULL. - * - * @return @ref NRF_SUCCESS Successfully accepted security information. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @return @ref NRF_ERROR_BUSY The stack is busy, process pending events and retry. - */ -SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const * const p_enc_info, ble_gap_sign_info_t const * const p_sign_info)); - - -/**@brief Get the current connection security. - * - * @param[in] conn_handle Connection handle. - * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in. - * - * @return @ref NRF_SUCCESS Current connection security successfully retrieved. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t * const p_conn_sec)); - - -/**@brief Start reporting the received signal strength to the application. - * - * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called. - * - * @param[in] conn_handle Connection handle. - * - * @return @ref NRF_SUCCESS Successfully activated RSSI reporting. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle)); - - -/**@brief Stop reporting the received singnal strength. - * - * An RSSI change detected before the call but not yet received by the application - * may be reported after @ref sd_ble_gap_rssi_stop has been called. - * - * @param[in] conn_handle Connection handle. - * - * @return @ref NRF_SUCCESS Successfully deactivated RSSI reporting. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle)); -/**@} */ - -#endif // BLE_GAP_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatt.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatt.h deleted file mode 100644 index 2ca27ac3ae..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatt.h +++ /dev/null @@ -1,171 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - /** - @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common - @{ - @brief Common definitions and prototypes for the GATT interfaces. - */ - -#ifndef BLE_GATT_H__ -#define BLE_GATT_H__ - -#include "ble_types.h" -#include "ble_ranges.h" - - -/** @addtogroup BLE_GATT_DEFINES Defines - * @{ */ - -/** @brief Default MTU size. */ -#define GATT_MTU_SIZE_DEFAULT 23 - -/** @brief Only the default MTU size of 23 is currently supported. */ -#define GATT_RX_MTU 23 - - -/**@brief Invalid Attribute Handle. */ -#define BLE_GATT_HANDLE_INVALID 0x0000 - -/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources - * @{ */ -#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */ -/** @} */ - -/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations - * @{ */ -#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */ -#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */ -#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ -#define BLE_GATT_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ -#define BLE_GATT_OP_EXEC_WRITE_REQ 0x05 /**< Execute Write Request. */ -/** @} */ - -/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags - * @{ */ -#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00 -#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE 0x01 -/** @} */ - -/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations - * @{ */ -#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */ -#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */ -/** @} */ - -/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes - * @{ */ -#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */ -#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */ -#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */ -#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */ -#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */ -#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorisation. */ -#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */ -#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */ -#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */ -#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */ -#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */ -#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */ -#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */ -#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */ -#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */ -#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */ -/** @} */ - - -/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats - * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml - * @{ */ -#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */ -#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */ -#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */ -#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */ -#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */ -#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */ -#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */ -#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */ -#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */ -#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */ -#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */ -#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */ -/** @} */ - -/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces - * @{ - */ -#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 -#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 -/** @} */ - -/** @} */ - -/** @addtogroup BLE_GATT_STRUCTURES Structures - * @{ */ - -/**@brief GATT Characteristic Properties. */ -typedef struct -{ - /* Standard properties */ - uint8_t broadcast :1; /**< Broadcasting of value permitted. */ - uint8_t read :1; /**< Reading value permitted. */ - uint8_t write_wo_resp :1; /**< Writing value with Write Command permitted. */ - uint8_t write :1; /**< Writing value with Write Request permitted. */ - uint8_t notify :1; /**< Notications of value permitted. */ - uint8_t indicate :1; /**< Indications of value permitted. */ - uint8_t auth_signed_wr :1; /**< Writing value with Signed Write Command permitted. */ -} ble_gatt_char_props_t; - -/**@brief GATT Characteristic Extended Properties. */ -typedef struct -{ - /* Extended properties */ - uint8_t reliable_wr :1; /**< Writing value with Queued Write Request permitted. */ - uint8_t wr_aux :1; /**< Writing the Characteristic User Description permitted. */ -} ble_gatt_char_ext_props_t; - -#endif // BLE_GATT_H__ - -/** @} */ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gattc.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gattc.h deleted file mode 100644 index 14bad6b1e1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gattc.h +++ /dev/null @@ -1,406 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client - @{ - @brief Definitions and prototypes for the GATT Client interface. - */ - -#ifndef BLE_GATTC_H__ -#define BLE_GATTC_H__ - -#include "ble_gatt.h" -#include "ble_types.h" -#include "ble_ranges.h" -#include "nrf_svc.h" - -/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations - * @{ */ - -/**@brief GATTC API SVC numbers. */ -enum BLE_GATTC_SVCS -{ - SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ - SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ - SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ - SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ - SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ - SD_BLE_GATTC_READ, /**< Generic read. */ - SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ - SD_BLE_GATTC_WRITE, /**< Generic write. */ - SD_BLE_GATTC_HV_CONFIRM /**< Handle Value Confirmation. */ -}; - -/** @} */ - -/** @addtogroup BLE_GATTC_DEFINES Defines - * @{ */ - -/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC - * @{ */ -#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) -/** @} */ - -/**@brief Last Attribute Handle. */ -#define BLE_GATTC_HANDLE_END 0xFFFF - -/** @} */ - -/** @addtogroup BLE_GATTC_STRUCTURES Structures - * @{ */ - -/**@brief Operation Handle Range. */ -typedef struct -{ - uint16_t start_handle; /**< Start Handle. */ - uint16_t end_handle; /**< End Handle. */ -} ble_gattc_handle_range_t; - - -/**@brief GATT service. */ -typedef struct -{ - ble_uuid_t uuid; /**< Service UUID. */ - ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ -} ble_gattc_service_t; - - -/**@brief GATT include. */ -typedef struct -{ - uint16_t handle; /**< Include Handle. */ - ble_gattc_service_t included_srvc; /**< Handle of the included service. */ -} ble_gattc_include_t; - - -/**@brief GATT characteristic. */ -typedef struct -{ - ble_uuid_t uuid; /**< Characteristic UUID. */ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - uint8_t char_ext_props : 1; /**< Extended properties present. */ - uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ - uint16_t handle_value; /**< Handle of the Characteristic Value. */ -} ble_gattc_char_t; - - -/**@brief GATT descriptor. */ -typedef struct -{ - uint16_t handle; /**< Descriptor Handle. */ - ble_uuid_t uuid; /**< Descriptor UUID. */ -} ble_gattc_desc_t; - - -/**@brief Write Parameters. */ -typedef struct -{ - uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ - uint16_t handle; /**< Handle to the attribute to be written. */ - uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ - uint16_t len; /**< Length of data in bytes. */ - uint8_t* p_value; /**< Pointer to the value data. */ - uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ -} ble_gattc_write_params_t; - - -/** - * @brief GATT Client Event IDs. - */ -enum BLE_GATTC_EVTS -{ - BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. */ - BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. */ - BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. */ - BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. */ - BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. */ - BLE_GATTC_EVT_READ_RSP, /**< Read Response event. */ - BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. */ - BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. */ - BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. */ - BLE_GATTC_EVT_TIMEOUT /**< Timeout event. */ -}; - -/**@brief Event structure for BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Service count. */ - ble_gattc_service_t services[1]; /**< Service data, variable length. */ -} ble_gattc_evt_prim_srvc_disc_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_REL_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Include count. */ - ble_gattc_include_t includes[1]; /**< Include data, variable length. */ -} ble_gattc_evt_rel_disc_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_CHAR_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Characteristic count. */ - ble_gattc_char_t chars[1]; /**< Characteristic data, variable length. */ -} ble_gattc_evt_char_disc_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_DESC_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Descriptor count. */ - ble_gattc_desc_t descs[1]; /**< Descriptor data, variable length. */ -} ble_gattc_evt_desc_disc_rsp_t; - -/**@brief GATT read by UUID handle value pair. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint8_t *p_value; /**< Pointer to value, variable length (length available as value_len in ble_gattc_evt_read_by_uuid_rsp_t). - Please note that this pointer is absolute to the memory provided by the user when retrieving the event, - so it will effectively point to a location inside the handle_value array. */ -} ble_gattc_handle_value_t; - -/**@brief Event structure for BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ -typedef struct -{ - uint16_t count; /**< Handle-Value Pair Count. */ - uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ - ble_gattc_handle_value_t handle_value[1]; /**< Handle-Value(s) list, variable length. */ -} ble_gattc_evt_char_val_by_uuid_read_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_READ_RSP. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint16_t offset; /**< Offset of the attribute data. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data, variable length. */ -} ble_gattc_evt_read_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ -typedef struct -{ - uint16_t len; /**< Concatenated Attribute values length. */ - uint8_t values[1]; /**< Attribute values, variable length. */ -} ble_gattc_evt_char_vals_read_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_WRITE_RSP. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ - uint16_t offset; /**< Data Offset. */ - uint16_t len; /**< Data length. */ - uint8_t data[1]; /**< Data, variable length. */ -} ble_gattc_evt_write_rsp_t; - -/**@brief Event structure for BLE_GATTC_EVT_HVX. */ -typedef struct -{ - uint16_t handle; /**< Handle to which the HVx operation applies. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data, variable length. */ -} ble_gattc_evt_hvx_t; - -/**@brief Event structure for BLE_GATTC_EVT_TIMEOUT. */ -typedef struct -{ - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ -} ble_gattc_evt_timeout_t; - -/**@brief GATTC event type. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occured. */ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases BLE_GATT_HANDLE_INVALID. */ - union - { - ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ - ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ - ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ - ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ - ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ - ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ - ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ - ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ - ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ - ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - } params; /**< Event Parameters. @note Only valid if @ref gatt_status == BLE_GATT_STATUS_SUCCESS. */ -} ble_gattc_evt_t; -/** @} */ - -/** @addtogroup BLE_GATTC_FUNCTIONS Functions - * @{ */ - -/**@brief Initiate or continue a GATT Primary Service Discovery procedure. - * - * @details This function initiates a Primary Service discovery, starting from the supplied handle. - * If the last service has not been reached, this must be called again with an updated start handle value to continue the search. - * - * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with - * type BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] start_handle Handle to start searching from. - * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const * const p_srvc_uuid)); - - -/**@brief Initiate or continue a GATT Relationship Discovery procedure. - * - * @details This function initiates the Find Included Services sub-procedure. If the last included service has not been reached, - * this must be called again with an updated handle range to continue the search. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range)); - - -/**@brief Initiate or continue a GATT Characteristic Discovery procedure. - * - * @details This function initiates a Characteristic discovery procedure. If the last Characteristic has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with - * type BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range)); - - -/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure. - * - * @details This function initiates the Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * const p_handle_range)); - - -/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure. - * - * @details This function initiates the Read using Characteristic UUID procedure. If the last Characteristic has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_uuid Pointer to a Characteristic value UUID to read. - * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const * const p_uuid, ble_gattc_handle_range_t const * const p_handle_range)); - - -/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure. - * - * @details This function initiates a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor - * to be read is longer than GATT_MTU - 1, this function must be called multiple times with appropriate offset to read the - * complete value. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] handle The handle of the attribute to be read. - * @param[in] offset Offset into the attribute value to be read. - * - * @return @ref NRF_SUCCESS Successfully started or resumed the Read (Long) procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)); - - -/**@brief Initiate a GATT Read Multiple Characteristic Values procedure. - * - * @details This function initiates a GATT Read Multiple Characteristic Values procedure. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read. - * @param[in] handle_count The number of handles in p_handles. - * - * @return @ref NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const * const p_handles, uint16_t handle_count)); - - -/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure. - * - * @details This function can perform all write procedures described in GATT. - * - * @note It is important to note that a write without response will consume an application buffer, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write on the other hand will use the - * standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response - * has been received from the peer. Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_write_params A pointer to a write parameters structure. - * - * @return @ref NRF_SUCCESS Successfully started the Write procedure. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - * @return @ref NRF_ERROR_BUSY Procedure already in progress. - * @return @ref BLE_ERROR_NO_TX_BUFFERS There are no available buffers left. - */ -SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const * const p_write_params)); - - -/**@brief Send a Handle Value Confirmation to the GATT Server. - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] handle The handle of the attribute in the indication. - * - * @return @ref NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_STATE No Indication pending to be confirmed. - * @return @ref BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle. - * @return @ref BLE_ERROR_NO_TX_BUFFERS There are no available buffers left. - */ -SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)); - -/** @} */ - -#endif /* BLE_GATTC_H__ */ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatts.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatts.h deleted file mode 100644 index dec649f28a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_gatts.h +++ /dev/null @@ -1,566 +0,0 @@ -/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server - @{ - @brief Definitions and prototypes for the GATTS interface. - */ - -#ifndef BLE_GATTS_H__ -#define BLE_GATTS_H__ - -#include "ble_types.h" -#include "ble_ranges.h" -#include "ble_l2cap.h" -#include "ble_gap.h" -#include "ble_gatt.h" -#include "nrf_svc.h" - -/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations - * @{ */ - -/** - * @brief GATTS API SVC numbers. - */ -enum BLE_GATTS_SVCS -{ - SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ - SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ - SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ - SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ - SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ - SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ - SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ - SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ - SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ - SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ - SD_BLE_GATTS_SYS_ATTR_GET, /**< Get updated persistent system attributes after terminating a connection. */ -}; - -/** @} */ - -/** @addtogroup BLE_GATTS_DEFINES Defines - * @{ */ - -/** @brief Only the default MTU size of 23 is currently supported. */ -#define GATT_RX_MTU 23 - -/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS - * @{ */ -#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */ -#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */ -/** @} */ - -/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths - * @{ */ -#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */ -#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */ -/** @} */ - -/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types - * @{ */ -#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */ -#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */ -#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */ -/** @} */ - - -/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types - * @{ */ -#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */ -#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */ -#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */ -#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */ -#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */ -#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */ -#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */ -#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */ -/** @} */ - - -/** @defgroup BLE_GATTS_OPS GATT Server Operations - * @{ */ -#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */ -#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */ -#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ -#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ -#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */ -#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */ -/** @} */ - -/** @defgroup BLE_GATTS_VLOCS GATT Value Locations - * @{ */ -#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */ -#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */ -#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack - will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */ -/** @} */ - -/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types - * @{ */ -#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */ -#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */ -#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */ -/** @} */ - - -/** @} */ - -/** @addtogroup BLE_GATTS_STRUCTURES Structures - * @{ */ - -/** - * @brief BLE GATTS init options - */ -typedef struct -{ - uint8_t service_changed:1; /**< Include the Service Changed characteristic in the local attributes. */ -} ble_gatts_enable_params_t; - -/**@brief Attribute metadata. */ -typedef struct -{ - ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vlen :1; /**< Variable length attribute. */ - uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t rd_auth :1; /**< Read Authorization and value will be requested from the application on every read operation. */ - uint8_t wr_auth :1; /**< Write Authorization will be requested from the application on every Write Request operation (but not Write Command). */ -} ble_gatts_attr_md_t; - - -/**@brief GATT Attribute. */ -typedef struct -{ - ble_uuid_t* p_uuid; /**< Pointer to the attribute UUID. */ - ble_gatts_attr_md_t* p_attr_md; /**< Pointer to the attribute metadata structure. */ - uint16_t init_len; /**< Initial attribute value length in bytes. */ - uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ - uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ - uint8_t* p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer - that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. - The stack may access that memory directly without the application's knowledge. */ -} ble_gatts_attr_t; - - -/**@brief GATT Attribute Context. */ -typedef struct -{ - ble_uuid_t srvc_uuid; /**< Service UUID. */ - ble_uuid_t char_uuid; /**< Characteristic UUID if applicable (BLE_UUID_TYPE_UNKNOWN if N/A). */ - ble_uuid_t desc_uuid; /**< Descriptor UUID if applicable (BLE_UUID_TYPE_UNKNOWN if N/A). */ - uint16_t srvc_handle; /**< Service Handle. */ - uint16_t value_handle; /**< Characteristic Handle if applicable (BLE_GATT_HANDLE_INVALID if N/A). */ - uint8_t type; /**< Attribute Type, see @ref BLE_GATTS_ATTR_TYPES. */ -} ble_gatts_attr_context_t; - - -/**@brief GATT Characteristic Presentation Format. */ -typedef struct -{ - uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ - int8_t exponent; /**< Exponent for integer data types. */ - uint16_t unit; /**< UUID from Bluetooth Assigned Numbers. */ - uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ - uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ -} ble_gatts_char_pf_t; - - -/**@brief GATT Characteristic metadata. */ -typedef struct -{ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ - uint8_t* p_char_user_desc; /**< Pointer to a UTF-8, NULL if the descriptor is not required. */ - uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ - uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ - ble_gatts_char_pf_t* p_char_pf; /**< Pointer to a presentation format structure or NULL if the descriptor is not required. */ - ble_gatts_attr_md_t* p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ - ble_gatts_attr_md_t* p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ - ble_gatts_attr_md_t* p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ -} ble_gatts_char_md_t; - - -/**@brief GATT Characteristic Definition Handles. */ -typedef struct -{ - uint16_t value_handle; /**< Handle to the characteristic value. */ - uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or BLE_GATT_HANDLE_INVALID if not present. */ -} ble_gatts_char_handles_t; - - -/**@brief GATT HVx parameters. */ -typedef struct -{ - uint16_t handle; /**< Characteristic Value Handle. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t offset; /**< Offset within the attribute value. */ - uint16_t* p_len; /**< Length in bytes to be written, length in bytes written after successful return. */ - uint8_t* p_data; /**< Actual data content, use NULL to use the current attribute value. */ -} ble_gatts_hvx_params_t; - -/**@brief GATT Read Authorization parameters. */ -typedef struct -{ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint8_t update : 1; /**< If set, data supplied in p_data will be used in the ATT response. */ - uint16_t offset; /**< Offset of the attribute value being updated. */ - uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ - uint8_t* p_data; /**< Pointer to new value used to update the attribute value. */ -} ble_gatts_read_authorize_params_t; - -/**@brief GATT Write Authorisation parameters. */ -typedef struct -{ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ -} ble_gatts_write_authorize_params_t; - -/**@brief GATT Read or Write Authorize Reply parameters. */ -typedef struct -{ - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_read_authorize_params_t read; /**< Read authorization parameters. */ - ble_gatts_write_authorize_params_t write; /**< Write authorization parameters. */ - } params; -} ble_gatts_rw_authorize_reply_params_t; - - -/** - * @brief GATT Server Event IDs. - */ -enum BLE_GATTS_EVTS -{ - BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. */ - BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. */ - BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending, awaiting a sd_ble_gatts_sys_attr_set(). */ - BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. */ - BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. */ - BLE_GATTS_EVT_TIMEOUT /**< Timeout. */ -}; - - -/**@brief Event structure for BLE_GATTS_EVT_WRITE. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ - ble_gatts_attr_context_t context; /**< Attribute Context. */ - uint16_t offset; /**< Offset for the write operation. */ - uint16_t len; /**< Length of the incoming data. */ - uint8_t data[1]; /**< Incoming data, variable length. */ -} ble_gatts_evt_write_t; - -/**@brief Event structure for authorize read request. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - ble_gatts_attr_context_t context; /**< Attribute Context. */ - uint16_t offset; /**< Offset for the read operation. */ -} ble_gatts_evt_read_t; - -/**@brief Event structure for BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ -typedef struct -{ - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ - ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ - } request; -} ble_gatts_evt_rw_authorize_request_t; - -/**@brief Event structure for BLE_GATTS_EVT_SYS_ATTR_MISSING. */ -typedef struct -{ - uint8_t hint; -} ble_gatts_evt_sys_attr_missing_t; - - -/**@brief Event structure for BLE_GATTS_EVT_HVC. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ -} ble_gatts_evt_hvc_t; - -/**@brief Event structure for BLE_GATTS_EVT_TIMEOUT. */ -typedef struct -{ - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ -} ble_gatts_evt_timeout_t; - - -/**@brief GATT Server event callback event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - union - { - ble_gatts_evt_write_t write; /**< Write Event Parameters. */ - ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ - ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ - ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ - ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ - } params; -} ble_gatts_evt_t; - -/** @} */ - -/** @addtogroup BLE_GATTS_FUNCTIONS Functions - * @{ */ - -/**@brief Add a service declaration to the local server ATT table. - * - * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES. - * @param[in] p_uuid Pointer to service UUID. - * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to - * add a secondary service declaration that is not referenced by another service later in the ATT table. - * - * @return @ref NRF_SUCCESS Successfully added a service declaration. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table. - * @return @ref NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const*const p_uuid, uint16_t *const p_handle)); - - -/**@brief Add an include declaration to the local server ATT table. - * - * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential addition is supported at this time). - * - * @note The included service must already be present in the ATT table prior to this call. - * - * @param[in] service_handle Handle of the service where the included service is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] inc_srvc_handle Handle of the included service. - * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @return @ref NRF_SUCCESS Successfully added an include declaration. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @return @ref NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @return @ref NRF_ERROR_NOT_FOUND Attribute not found. - */ -SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *const p_include_handle)); - - -/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the local server ATT table. - * - * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential addition is supported at this time). - * - * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits, - * readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values. - * - * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions. - * - * @param[in] service_handle Handle of the service where the characteristic is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] p_char_md Characteristic metadata. - * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value. - * @param[out] p_handles Pointer to the structure where the assigned handles will be stored. - * - * @return @ref NRF_SUCCESS Successfully added a characteristic. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. - * @return @ref NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - */ -SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const*const p_char_md, ble_gatts_attr_t const*const p_attr_char_value, ble_gatts_char_handles_t *const p_handles)); - - -/**@brief Add a descriptor to the local server ATT table. - * - * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential addition is supported at this time). - * - * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] p_attr Pointer to the attribute structure. - * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @return @ref NRF_SUCCESS Successfully added a descriptor. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required. - * @return @ref NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - */ -SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const * const p_attr, uint16_t* const p_handle)); - -/**@brief Set the value of a given attribute. - * - * @param[in] handle Attribute handle. - * @param[in] offset Offset in bytes to write from. - * @param[in,out] p_len Length in bytes to be written, length in bytes written after successful return. - * @param[in] p_value Pointer to a buffer (at least len bytes long) containing the desired attribute value. If value is stored in user memory, only the attribute length is updated when p_value == NULL. - * - * @return @ref NRF_SUCCESS Successfully set the value of the attribute. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_NOT_FOUND Attribute not found. - * @return @ref NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - */ -SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t handle, uint16_t offset, uint16_t* const p_len, uint8_t const * const p_value)); - -/**@brief Get the value of a given attribute. - * - * @param[in] handle Attribute handle. - * @param[in] offset Offset in bytes to read from. - * @param[in,out] p_len Length in bytes to be read, total length of attribute value (in bytes, starting from offset) after successful return. - * @param[in,out] p_data Pointer to a buffer (at least len bytes long) where to store the attribute value. Set to NULL to obtain the complete length of attribute value. - * - * @note If the attribute value is longer than the size of the supplied buffer, - * p_len will return the total attribute value length (excluding offset), - * and not the number of bytes actually returned in p_data. - * The application may use this information to allocate a suitable buffer size. - * - * @return @ref NRF_SUCCESS Successfully retrieved the value of the attribute. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_NOT_FOUND Attribute not found. - */ -SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t handle, uint16_t offset, uint16_t *const p_len, uint8_t* const p_data)); - -/**@brief Notify or Indicate an attribute value. - * - * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation - * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that - * the application can atomically perform a value update and a server initiated transaction with a single API call. - * If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC will be sent up as soon as the confirmation arrives from - * the peer. - * - * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution. - * When receiveing the error codes @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and - * @ref BLE_ERROR_NO_TX_BUFFERS the ATT table has been updated. - * The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len). - * - * @note It is important to note that a notification will consume an application buffer, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the - * standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation - * has been received from the peer. Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with - * the contents pointed by it before sending the notification or indication. - * - * @return @ref NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate. - * @return @ref BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated. - * @return @ref NRF_ERROR_NOT_FOUND Attribute not found. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation, notifications or indications must be enabled in the CCCD. - * @return @ref NRF_ERROR_BUSY Procedure already in progress. - * @return @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. - * @return @ref BLE_ERROR_NO_TX_BUFFERS There are no available buffers to send the data, applies only to notifications. - */ -SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const*const p_hvx_params)); - -/**@brief Indicate the Service Changed attribute value. - * - * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the attribute - * table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will - * be issued. - * - * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here. - * - * @param[in] conn_handle Connection handle. - * @param[in] start_handle Start of affected attribute handle range. - * @param[in] end_handle End of affected attribute handle range. - * - * @return @ref NRF_SUCCESS Successfully queued the Service Changed indication for transmission. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application. - * @return @ref NRF_ERROR_INVALID_STATE Invalid state to perform operation, notifications or indications must be enabled in the CCCD. - * @return @ref NRF_ERROR_BUSY Procedure already in progress. - * @return @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. - */ -SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)); - -/**@brief Respond to a Read/Write authorization request. - * - * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application. - * - * @return @ref NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, ATT table updated. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_STATE No authorization request pending. - * @return @ref NRF_ERROR_INVALID_PARAM Authorization op invalid, - * or for Read Authorization reply: requested handles not replied with, - * or for Write Authorization reply: handle supplied does not match requested handle. - */ -SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const*const p_rw_authorize_reply_params)); - - -/**@brief Update persistent system attribute information. - * - * @details Supply to the stack information about persistent system attributes. - * This call is legal in the connected state only, and is usually - * made immediately after a connection is established and the bond identified. - * usually as a response to a BLE_GATTS_EVT_SYS_ATTR_MISSING. - * - * p_sysattrs may point directly to the application's stored copy of the struct. - * If the pointer is NULL, the system attribute info is initialized, assuming that - * the application does not have any previously saved data for this bond. - * - * @note The state of persistent system attributes is reset upon connection and then remembered for its duration. - * - * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially. - * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or - * reset the SoftDevice to return to a known state. - * - * @param[in] conn_handle Connection handle. - * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL. - * @param[in] len Size of data pointed by p_sys_attr_data, in octets. - * - * @return @ref NRF_SUCCESS Successfully set the system attribute information. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const*const p_sys_attr_data, uint16_t len)); - - -/**@brief Retrieve persistent system attribute information from the stack. - * - * @details This call is used to retrieve information about values to be stored perisistently by the application - * after a connection has been terminated. When a new connection is made to the same bond, the values - * should be restored using @ref sd_ble_gatts_sys_attr_set. - * The data should be read before any new advertising is started, or any new connection established. The connection handle for - * the previous now defunct connection will remain valid until a new one is created to allow this API call to refer to it. - * - * @param[in] conn_handle Connection handle of the recently terminated connection. - * @param[in] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. NULL can be provided to - * obtain the length of the data - * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data. - * - * @return @ref NRF_SUCCESS Successfully retrieved the system attribute information. - * @return @ref BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. - */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t * const p_sys_attr_data, uint16_t* const p_len)); - -/** @} */ - -#endif // BLE_GATTS_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_hci.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_hci.h deleted file mode 100644 index faed593cc2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_hci.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - - The information contained herein is confidential property of Nordic Semiconductor. The use, - copying, transfer or disclosure of such information is prohibited except by express written - agreement with Nordic Semiconductor. - */ -/** - @addtogroup BLE_COMMON - @{ -*/ - - -#ifndef BLE_HCI_H__ -#define BLE_HCI_H__ - -/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes - * @{ */ - -#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 -#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 -#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 -/*0x03 Hardware Failure -0x04 Page Timeout -*/ -#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 -#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 -#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 -#define BLE_HCI_CONNECTION_TIMEOUT 0x08 -/*0x09 Connection Limit Exceeded -0x0A Synchronous Connection Limit To A Device Exceeded -0x0B ACL Connection Already Exists*/ -#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C -/*0x0D Connection Rejected due to Limited Resources -0x0E Connection Rejected Due To Security Reasons -0x0F Connection Rejected due to Unacceptable BD_ADDR -0x10 Connection Accept Timeout Exceeded -0x11 Unsupported Feature or Parameter Value*/ -#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 -#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 -#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 -#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 -#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 -/* -0x17 Repeated Attempts -0x18 Pairing Not Allowed -0x19 Unknown LMP PDU -*/ -#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A -/* -0x1B SCO Offset Rejected -0x1C SCO Interval Rejected -0x1D SCO Air Mode Rejected*/ -#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E -#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F -/*0x20 Unsupported LMP Parameter Value -0x21 Role Change Not Allowed -*/ -#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 -/*0x23 LMP Error Transaction Collision*/ -#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 -/*0x25 Encryption Mode Not Acceptable -0x26 Link Key Can Not be Changed -0x27 Requested QoS Not Supported -*/ -#define BLE_HCI_INSTANT_PASSED 0x28 -#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 -#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A -/* -0x2B Reserved -0x2C QoS Unacceptable Parameter -0x2D QoS Rejected -0x2E Channel Classification Not Supported -0x2F Insufficient Security -0x30 Parameter Out Of Mandatory Range -0x31 Reserved -0x32 Role Switch Pending -0x33 Reserved -0x34 Reserved Slot Violation -0x35 Role Switch Failed -0x36 Extended Inquiry Response Too Large -0x37 Secure Simple Pairing Not Supported By Host. -0x38 Host Busy - Pairing -0x39 Connection Rejected due to No Suitable Channel Found*/ -#define BLE_HCI_CONTROLLER_BUSY 0x3A -#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B -#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C -#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D -#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E - -/** @} */ - - -#endif // BLE_HCI_H__ - -/** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_l2cap.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_l2cap.h deleted file mode 100644 index d74ee21865..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_l2cap.h +++ /dev/null @@ -1,144 +0,0 @@ -/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP) - @{ - @brief Definitions and prototypes for the L2CAP interface. - */ - -#ifndef BLE_L2CAP_H__ -#define BLE_L2CAP_H__ - -#include "ble_types.h" -#include "ble_ranges.h" -#include "ble_err.h" -#include "nrf_svc.h" - -/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations - * @{ */ - -/**@brief L2CAP API SVC numbers. */ -enum BLE_L2CAP_SVCS -{ - SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE, /**< Register a CID. */ - SD_BLE_L2CAP_CID_UNREGISTER, /**< Unregister a CID. */ - SD_BLE_L2CAP_TX /**< Transmit a packet. */ -}; - -/** @} */ - -/**@addtogroup BLE_L2CAP_DEFINES Defines - * @{ */ - -/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP - * @{ */ -#define BLE_ERROR_L2CAP_CID_IN_USE (NRF_L2CAP_ERR_BASE + 0x000) /**< CID already in use. */ -/** @} */ - -/**@brief Default L2CAP MTU. */ -#define BLE_L2CAP_MTU_DEF (23) - -/**@brief Invalid Channel Identifier. */ -#define BLE_L2CAP_CID_INVALID (0x0000) - -/**@brief Dynamic Channel Identifier base. */ -#define BLE_L2CAP_CID_DYN_BASE (0x0040) - -/**@brief Maximum amount of dynamic CIDs. */ -#define BLE_L2CAP_CID_DYN_MAX (8) - -/** @} */ - -/**@addtogroup BLE_L2CAP_STRUCTURES Structures - * @{ */ - -/**@brief Packet header format for L2CAP transmission. */ -typedef struct -{ - uint16_t len; /**< Length of valid info in data member. */ - uint16_t cid; /**< Channel ID on which packet is transmitted. */ -} ble_l2cap_header_t; - -/**@brief L2CAP Event IDs. */ -enum BLE_L2CAP_EVTS -{ - BLE_L2CAP_EVT_RX = BLE_L2CAP_EVT_BASE /**< L2CAP packet received. */ -}; - - -/**@brief L2CAP Received packet event report. */ -typedef struct -{ - ble_l2cap_header_t header; /** L2CAP packet header. */ - uint8_t data[1]; /**< Packet data, variable length. */ -} ble_l2cap_evt_rx_t; - - -/**@brief L2CAP event callback event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occured. */ - union - { - ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ - } params; -} ble_l2cap_evt_t; - - -/**@brief Register a CID with L2CAP. - * - * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID. - * - * @param[in] cid L2CAP CID. - * - * @return @ref NRF_SUCCESS Successfully registered a CID with the L2CAP layer. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE. - * @return @ref BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid)); - -/**@brief Unregister a CID with L2CAP. - * - * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer. - * - * @param[in] cid L2CAP CID. - * - * @return @ref NRF_SUCCESS Successfully unregistered the CID. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @return @ref NRF_ERROR_NOT_FOUND CID not previously registered. - */ -SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid)); - -/**@brief Transmit an L2CAP packet. - * - * @note It is important to note that a call to this function will consume an application buffer, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. - * Please see the documentation of @ref sd_ble_tx_buffer_count_get for more details. - * - * @param[in] conn_handle Connection Handle. - * @param[in] p_header Pointer to a packet header containing length and CID. - * @param[in] p_data Pointer to the data to be transmitted. - * - * @return @ref NRF_SUCCESS Successfully queued an L2CAP packet for transmission. - * @return @ref NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @return @ref NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register. - * @return @ref NRF_ERROR_NOT_FOUND CID not found. - * @return @ref NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @return @ref BLE_ERROR_NO_TX_BUFFERS Not enough application buffers available. - * @return @ref NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF. - */ -SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const * const p_header, uint8_t const * const p_data)); - -/** @} */ - -#endif // BLE_L2CAP_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_ranges.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_ranges.h deleted file mode 100644 index dfd9b63bcf..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_ranges.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - - The information contained herein is confidential property of Nordic Semiconductor. The use, - copying, transfer or disclosure of such information is prohibited except by express written - agreement with Nordic Semiconductor. - */ -/** - @addtogroup BLE_COMMON - @{ - @defgroup ble_ranges Module specific SVC and event number subranges - @{ - - @brief Definition of SVC and event number subranges for each API module. - - @note - SVCs and event numbers are split into subranges for each API module. - Each module receives its entire allocated range of SVC calls, whether implemented or not, - but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range. - - Note that the symbols BLE__SVC_LAST is the end of the allocated SVC range, - rather than the last SVC function call actually defined and implemented. - - Specific SVC and event values are defined in each module's ble_.h file, - which defines names of each individual SVC code based on the range start value. -*/ - -#ifndef BLE_RANGES_H__ -#define BLE_RANGES_H__ - -#define BLE_SVC_BASE 0x60 -#define BLE_SVC_LAST 0x6B /* Total: 12. */ - -#define BLE_RESERVED_SVC_BASE 0x6C -#define BLE_RESERVED_SVC_LAST 0x6F /* Total: 4. */ - -#define BLE_GAP_SVC_BASE 0x70 -#define BLE_GAP_SVC_LAST 0x8F /* Total: 32. */ - -#define BLE_GATTC_SVC_BASE 0x90 -#define BLE_GATTC_SVC_LAST 0x9F /* Total: 16. */ - -#define BLE_GATTS_SVC_BASE 0xA0 -#define BLE_GATTS_SVC_LAST 0xAF /* Total: 16. */ - -#define BLE_L2CAP_SVC_BASE 0xB0 -#define BLE_L2CAP_SVC_LAST 0xBF /* Total: 16. */ - - -#define BLE_EVT_INVALID 0x00 - -#define BLE_EVT_BASE 0x01 -#define BLE_EVT_LAST 0x0F /* Total: 15. */ - -#define BLE_GAP_EVT_BASE 0x10 -#define BLE_GAP_EVT_LAST 0x2F /* Total: 32. */ - -#define BLE_GATTC_EVT_BASE 0x30 -#define BLE_GATTC_EVT_LAST 0x4F /* Total: 32. */ - -#define BLE_GATTS_EVT_BASE 0x50 -#define BLE_GATTS_EVT_LAST 0x6F /* Total: 32. */ - -#define BLE_L2CAP_EVT_BASE 0x70 -#define BLE_L2CAP_EVT_LAST 0x8F /* Total: 32. */ - -#define BLE_OPT_INVALID 0x00 /**< Invalid BLE Option. */ - -#define BLE_OPT_BASE 0x01 /**< Common BLE Option base. */ -#define BLE_OPT_LAST 0x1F /**< Total: 31. */ - -#define BLE_GAP_OPT_BASE 0x20 /**< GAP BLE Option base. */ -#define BLE_GAP_OPT_LAST 0x3F /**< Total: 32. */ - -#define BLE_GATTC_OPT_BASE 0x40 /**< GATTC BLE Option base. */ -#define BLE_GATTC_OPT_LAST 0x5F /**< Total: 32. */ - -#define BLE_GATTS_OPT_BASE 0x60 /**< GATTS BLE Option base. */ -#define BLE_GATTS_OPT_LAST 0x7F /**< Total: 32. */ - -#define BLE_L2CAP_OPT_BASE 0x80 /**< L2CAP BLE Option base. */ -#define BLE_L2CAP_OPT_LAST 0x9F /**< Total: 32. */ - -#endif /* BLE_RANGES_H__ */ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_types.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_types.h deleted file mode 100644 index 820553f0a9..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/ble_types.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @addtogroup BLE_COMMON - @{ - @defgroup ble_types Common types and macro definitions - @{ - - @brief Common types and macro definitions for the S110 SoftDevice. - */ - -#ifndef BLE_TYPES_H__ -#define BLE_TYPES_H__ - -#include - -/** @addtogroup BLE_COMMON_DEFINES Defines - * @{ */ - -/** @defgroup BLE_CONN_HANDLES BLE Connection Handles - * @{ */ -#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */ -#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */ -/** @} */ - - -/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs - * @{ */ -/* Generic UUIDs, applicable to all services */ -#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */ -#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */ -#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */ -#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */ -#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */ -#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */ -#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */ -/* GATT specific UUIDs */ -#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */ -#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */ -/* GAP specific UUIDs */ -#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */ -#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_PPF 0x2A02 /**< Peripheral Privacy Flag Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */ -/** @} */ - - -/** @defgroup BLE_UUID_TYPES Types of UUID - * @{ */ -#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */ -#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */ -#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */ -/** @} */ - - -/** @defgroup BLE_APPEARANCES Bluetooth Appearance values - * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml - * @{ */ -#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */ -#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */ -#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */ -#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */ -#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */ -#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */ -#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */ -#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */ -#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */ -#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */ -#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */ -#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */ -#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */ -#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */ -#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */ -#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */ -#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */ -#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */ -#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */ -#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */ -#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */ -#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */ -#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */ -#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystiq (HID Subtype). */ -#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */ -#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */ -#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */ -#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */ -#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */ -#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */ -#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */ -#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */ -#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */ -#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */ -#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */ -#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */ -#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */ -#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER 3136 /**< Generic Pulse Oximeter. */ -#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 3137 /**< Fingertip (Pulse Oximeter subtype). */ -#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN 3138 /**< Wrist Worn(Pulse Oximeter subtype). */ -#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE 3200 /**< Generic Weight Scale. */ -#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT 5184 /**< Generic Outdoor Sports Activity. */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP 5185 /**< Location Display Device (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD 5187 /**< Location Pod (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD 5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */ -/** @} */ - -/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */ -#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ - instance.type = BLE_UUID_TYPE_BLE; \ - instance.uuid = value;} while(0) - -/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ -#define BLE_UUID_COPY_PTR(dst, src) do {\ - (dst)->type = (src)->type; \ - (dst)->uuid = (src)->uuid;} while(0) - -/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ -#define BLE_UUID_COPY_INST(dst, src) do {\ - (dst).type = (src).type; \ - (dst).uuid = (src).uuid;} while(0) - -/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ -#define BLE_UUID_EQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) - -/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ -#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) - -/** @} */ - -/** @addtogroup BLE_TYPES_STRUCTURES Structures - * @{ */ - -/** @brief 128 bit UUID values. */ -typedef struct -{ - unsigned char uuid128[16]; -} ble_uuid128_t; - -/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ -typedef struct -{ - uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ - uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ -} ble_uuid_t; - -/** @} */ - -#endif /* BLE_TYPES_H__ */ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error.h deleted file mode 100644 index 518ef82b8f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - /** - @defgroup nrf_error SoftDevice Global Error Codes - @{ - - @brief Global Error definitions -*/ - -/* Header guard */ -#ifndef NRF_ERROR_H__ -#define NRF_ERROR_H__ - -/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions - * @{ */ -#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base -#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base -#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base -#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base -/** @} */ - -#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command -#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing -#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled -#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error -#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation -#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found -#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported -#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter -#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state -#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length -#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags -#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data -#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Data size exceeds limit -#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out -#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer -#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation -#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address -#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy - -#endif // NRF_ERROR_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_sdm.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_sdm.h deleted file mode 100644 index ea5413ff3f..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_sdm.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - /** - @addtogroup nrf_sdm_api - @{ - @defgroup nrf_sdm_error SoftDevice Manager Error Codes - @{ - - @brief Error definitions for the SDM API -*/ - -/* Header guard */ -#ifndef NRF_ERROR_SDM_H__ -#define NRF_ERROR_SDM_H__ - -#include "nrf_error.h" - -#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown lfclk source -#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts) -#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing) - -#endif // NRF_ERROR_SDM_H__ - -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_soc.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_soc.h deleted file mode 100644 index 08dc13c3e7..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_error_soc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - /** - @addtogroup nrf_soc_api - @{ - @defgroup nrf_soc_error SoC Library Error Codes - @{ - - @brief Error definitions for the SoC library - -*/ - -/* Header guard */ -#ifndef NRF_ERROR_SOC_H__ -#define NRF_ERROR_SOC_H__ - -#include "nrf_error.h" - -/* Mutex Errors */ -#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken - -/* NVIC errors */ -#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available -#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed -#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return - -/* Power errors */ -#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown -#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown -#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return - -/* Rand errors */ -#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values - -/* PPI errors */ -#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel -#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group - -#endif // NRF_ERROR_SOC_H__ -/** - @} - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_mbr.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_mbr.h deleted file mode 100755 index 4f323aefc2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_mbr.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @defgroup nrf_mbr_api Master Boot Record API - @{ - - @brief APIs for updating SoftDevice and BootLoader - -*/ - -/* Header guard */ -#ifndef NRF_MBR_H__ -#define NRF_MBR_H__ - -#include "nrf_svc.h" -#include - - -/** @addtogroup NRF_MBR_DEFINES Defines - * @{ */ - -/**@brief MBR SVC Base number. */ -#define MBR_SVC_BASE 0x18 -/** @} */ - -/** @addtogroup NRF_MBR_ENUMS Enumerations - * @{ */ - -/**@brief nRF Master Boot Record API SVC numbers. */ -enum NRF_MBR_SVCS -{ - SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ -}; - -/**@brief Possible values for ::sd_mbr_command_t.command */ -enum NRF_MBR_COMMANDS -{ - SD_MBR_COMMAND_COPY_BL, /**< Copy a new a new BootLoader. @see sd_mbr_command_copy_bl_t */ - SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ - SD_MBR_COMMAND_INIT_SD, /**< Init forwarding interrupts to SD, and run reset function in SD*/ - SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ - SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Start forwarding all exception to this address @see ::sd_mbr_command_vector_table_base_set_t*/ -}; - -/** @} */ - -/** @addtogroup NRF_MBR_TYPES Types - * @{ */ - -/**@brief This command copies part of a new SoftDevice - * The destination area is erased before copying. - * If dst is in the middle of a flash page, that whole flash page will be erased. - * If (dst+len) is in the middle of a flash page, that whole flash page will be erased. - * - * The user of this function is responsible for setting the PROTENSET registers. - * - * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly. - * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying. - */ -typedef struct -{ - uint32_t *src; /**< Pointer to the source of data to be copied.*/ - uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ - uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of 256 words*/ -}sd_mbr_command_copy_sd_t; - - -/**@brief This command works like memcmp, but takes the length in words. - * - * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal. - * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal. - */ -typedef struct -{ - uint32_t *ptr1; /**< Pointer to block of memory */ - uint32_t *ptr2; /**< Pointer to block of memory */ - uint32_t len; /**< Number of 32 bit words to compare*/ -}sd_mbr_command_compare_t; - - -/**@brief This command copies a new BootLoader. - * With this command, destination of BootLoader is always the address written in NRF_UICR->BOOTADDR. - * - * Destination is erased by this function. - * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased. - * - * This function will use PROTENSET to protect the flash that is not intended to be written. - * - * On Success, this function will not return. It will start the new BootLoader from reset-vector as normal. - * - * @retval ::NRF_ERROR_INVALID_STATE indicates that something was wrong. - * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen. - * @retval ::NRF_ERROR_FORBIDDEN if NRF_UICR->BOOTADDR is not set - * @retval ::NRF_ERROR_INVALID_LENGTH is invalid. - */ -typedef struct -{ - uint32_t *bl_src; /**< Pointer to the source of the Bootloader to be be copied.*/ - uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader */ -}sd_mbr_command_copy_bl_t; - -/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR - * - * Once this function has been called, this address is where the MBR will start to forward interrupts to after a reset. - * - * To restore default forwarding thiss function should be called with @param address set to 0. - * The MBR will then start forwarding to interrupts to the adress in NFR_UICR->BOOTADDR or to the SoftDevice if the BOOTADDR is not set. - * - * @retval ::NRF_SUCCESS - */ -typedef struct -{ - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ -}sd_mbr_command_vector_table_base_set_t; - -typedef struct -{ - uint32_t command; /**< type of command to be issued see @ref NRF_MBR_COMMANDS. */ - union - { - sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy*/ - sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy SoftDevice and BootLoader*/ - sd_mbr_command_compare_t compare; /**< Parameters for verify*/ - sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set.*/ - } params; -}sd_mbr_command_t; - -/** @} */ - -/** @addtogroup NRF_MBR_FUNCTIONS Functions - * @{ */ - -/**@brief Issue Master Boot Record commands - * - * Commands used when updating a SoftDevice and bootloader - * - * @param[in] param Pointer to a struct describing the command - * - *@note for retvals see ::sd_mbr_command_copy_sd_t ::sd_mbr_command_copy_bl_t ::sd_mbr_command_compare_t - -*/ -SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param)); - -/** @} */ -#endif // NRF_MBR_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_sdm.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_sdm.h deleted file mode 100644 index dc24036b4d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_sdm.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ -/** - @defgroup nrf_sdm_api SoftDevice Manager API - @{ - - @brief APIs for SoftDevice management. - -*/ - -/* Header guard */ -#ifndef NRF_SDM_H__ -#define NRF_SDM_H__ - -#include "nrf_svc.h" -#include "nrf51.h" -#include "nrf_soc.h" -#include "nrf_error_sdm.h" - -/** @addtogroup NRF_SDM_DEFINES Defines - * @{ */ - -/**@brief SoftDevice Manager SVC Base number. */ -#define SDM_SVC_BASE (0x10) - -/** @} */ - -/** @addtogroup NRF_SDM_ENUMS Enumerations - * @{ */ - -/**@brief nRF SoftDevice Manager API SVC numbers. */ -enum NRF_SD_SVCS -{ - SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ - SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ - SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ - SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ - SVC_SDM_LAST /**< Placeholder for last SDM SVC */ -}; - -/**@brief Possible lfclk oscillator sources. */ -enum NRF_CLOCK_LFCLKSRCS -{ - NRF_CLOCK_LFCLKSRC_SYNTH_250_PPM, /**< LFCLK Synthesized from HFCLK. */ - NRF_CLOCK_LFCLKSRC_XTAL_500_PPM, /**< LFCLK crystal oscillator 500 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_250_PPM, /**< LFCLK crystal oscillator 250 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_150_PPM, /**< LFCLK crystal oscillator 150 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_100_PPM, /**< LFCLK crystal oscillator 100 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_75_PPM, /**< LFCLK crystal oscillator 75 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_50_PPM, /**< LFCLK crystal oscillator 50 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_30_PPM, /**< LFCLK crystal oscillator 30 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, /**< LFCLK crystal oscillator 20 PPM accuracy. */ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_250MS_CALIBRATION, /**< LFCLK RC oscillator, 250ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_500MS_CALIBRATION, /**< LFCLK RC oscillator, 500ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_1000MS_CALIBRATION, /**< LFCLK RC oscillator, 1000ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_2000MS_CALIBRATION, /**< LFCLK RC oscillator, 2000ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_4000MS_CALIBRATION, /**< LFCLK RC oscillator, 4000ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_8000MS_CALIBRATION, /**< LFCLK RC oscillator, 8000ms calibration interval.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_TEMP_1000MS_CALIBRATION, /**< LFCLK RC oscillator. Temperature checked every 1000ms, if changed above a threshold, a calibration is done.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_TEMP_2000MS_CALIBRATION, /**< LFCLK RC oscillator. Temperature checked every 2000ms, if changed above a threshold, a calibration is done.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_TEMP_4000MS_CALIBRATION, /**< LFCLK RC oscillator. Temperature checked every 4000ms, if changed above a threshold, a calibration is done.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_TEMP_8000MS_CALIBRATION, /**< LFCLK RC oscillator. Temperature checked every 8000ms, if changed above a threshold, a calibration is done.*/ - NRF_CLOCK_LFCLKSRC_RC_250_PPM_TEMP_16000MS_CALIBRATION, /**< LFCLK RC oscillator. Temperature checked every 16000ms, if changed above a threshold, a calibration is done.*/ -}; - -/** @} */ - -/** @addtogroup NRF_SDM_TYPES Types - * @{ */ - -/**@brief Type representing lfclk oscillator source. */ -typedef uint32_t nrf_clock_lfclksrc_t; - - -/**@brief SoftDevice Assertion Handler type. - * - * When an unexpected error occurs within the SoftDevice it will call the SoftDevice assertion handler callback. - * The protocol stack will be in an undefined state when this happens and the only way to recover will be to - * perform a reset, using e.g. CMSIS NVIC_SystemReset(). - * - * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the SoftDevice assert callback. - * - * @param[in] pc The program counter of the failed assert. - * @param[in] line_number Line number where the assert failed. - * @param[in] file_name File name where the assert failed. - */ -typedef void (*softdevice_assertion_handler_t)(uint32_t pc, uint16_t line_number, const uint8_t * p_file_name); - -/** @} */ - -/** @addtogroup NRF_SDM_FUNCTIONS Functions - * @{ */ - -/**@brief Enables the SoftDevice and by extension the protocol stack. - * - * Idempotent function to enable the SoftDevice. - * - * @note Some care must be taken if a low frequency clock source is already running when calling this function: - * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new - * clock source will be started. - * - * @note This function has no effect when returning with an error. - * - * @post If return code is ::NRF_SUCCESS - * - SoC library and protocol stack APIs are made available - * - A portion of RAM will be unavailable (see relevant SDS documentation) - * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation) - * - Interrupts will not arrive from protected peripherals or interrupts - * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the softdevice. - * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation) - * - Chosen low frequency clock source will be running - * - * @param clock_source Low frequency clock source and accuracy. (Note: In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock). - * @param assertion_handler Callback for SoftDevice assertions. - * - * @retval ::NRF_SUCCESS - * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDeviceinterrupt is already enabled, or an enabled interrupt has an illegal priority level - * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected - */ -SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lfclksrc_t clock_source, softdevice_assertion_handler_t assertion_handler)); - -/**@brief Disables the SoftDevice and by extension the protocol stack. - * - * Idempotent function to disable the SoftDevice. - * - * @post SoC library and protocol stack APIs are made unavailable. - * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest). - * @post All peripherals used by the SoftDevice will be reset to default values. - * @post All of RAM become available. - * @post All interrupts are forwarded to the application. - * @post LFCLK source chosen in ::sd_softdevice_enable will be left running. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void)); - -/**@brief Check if the SoftDevice is enabled. - * - * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)); - -/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice - * - * This function is only intended to be called when a bootloader is enabled. - * - * @param[in] address The base address of the interrupt vector table for forwarded interrupts. - - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address)); - -/** @} */ - -#endif // NRF_SDM_H__ - -/** - @} -*/ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_soc.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_soc.h deleted file mode 100644 index 9d13de386d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_soc.h +++ /dev/null @@ -1,958 +0,0 @@ -/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - -/** - * @defgroup nrf_soc_api SoC Library API - * @{ - * - * @brief APIs for the SoC library. - * -*/ - -#ifndef NRF_SOC_H__ -#define NRF_SOC_H__ - -#include -#include -#include "nrf_svc.h" -#include "nrf51.h" -#include "nrf51_bitfields.h" -#include "nrf_error_soc.h" - -/** @addtogroup NRF_SOC_DEFINES Defines - * @{ */ - -/**@brief The number of the lowest SVC number reserved for the SoC library. */ -#define SOC_SVC_BASE (0x20) -#define SOC_SVC_BASE_NOT_AVAILABLE (0x23) - -/**@brief Guranteed time for application to process radio inactive notification. */ -#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) - -/**@brief The minimum allowed timeslot extension time. */ -#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200) - -#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ -#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ -#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ - -#define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ -#define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */ -#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ -#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. */ - -#define NRF_RADIO_LENGTH_MIN_US (100) /**< The shortest allowed radio timeslot, in microseconds. */ -#define NRF_RADIO_LENGTH_MAX_US (100000) /**< The longest allowed radio timeslot, in microseconds. */ - -#define NRF_RADIO_DISTANCE_MAX_US (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */ - -#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */ - -#define NRF_RADIO_START_JITTER_US (2) /**< The maximum jitter in NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */ - -/** @} */ - -/** @addtogroup NRF_SOC_TYPES Types - * @{ */ - -/**@brief The SVC numbers used by the SVC functions in the SoC library. */ -enum NRF_SOC_SVCS -{ - SD_FLASH_PAGE_ERASE = SOC_SVC_BASE, - SD_FLASH_WRITE, - SD_FLASH_PROTECT, - SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, - SD_MUTEX_ACQUIRE, - SD_MUTEX_RELEASE, - SD_NVIC_ENABLEIRQ, - SD_NVIC_DISABLEIRQ, - SD_NVIC_GETPENDINGIRQ, - SD_NVIC_SETPENDINGIRQ, - SD_NVIC_CLEARPENDINGIRQ, - SD_NVIC_SETPRIORITY, - SD_NVIC_GETPRIORITY, - SD_NVIC_SYSTEMRESET, - SD_NVIC_CRITICAL_REGION_ENTER, - SD_NVIC_CRITICAL_REGION_EXIT, - SD_RAND_APPLICATION_POOL_CAPACITY, - SD_RAND_APPLICATION_BYTES_AVAILABLE, - SD_RAND_APPLICATION_GET_VECTOR, - SD_POWER_MODE_SET, - SD_POWER_SYSTEM_OFF, - SD_POWER_RESET_REASON_GET, - SD_POWER_RESET_REASON_CLR, - SD_POWER_POF_ENABLE, - SD_POWER_POF_THRESHOLD_SET, - SD_POWER_RAMON_SET, - SD_POWER_RAMON_CLR, - SD_POWER_RAMON_GET, - SD_POWER_GPREGRET_SET, - SD_POWER_GPREGRET_CLR, - SD_POWER_GPREGRET_GET, - SD_POWER_DCDC_MODE_SET, - SD_APP_EVT_WAIT, - SD_CLOCK_HFCLK_REQUEST, - SD_CLOCK_HFCLK_RELEASE, - SD_CLOCK_HFCLK_IS_RUNNING, - SD_PPI_CHANNEL_ENABLE_GET, - SD_PPI_CHANNEL_ENABLE_SET, - SD_PPI_CHANNEL_ENABLE_CLR, - SD_PPI_CHANNEL_ASSIGN, - SD_PPI_GROUP_TASK_ENABLE, - SD_PPI_GROUP_TASK_DISABLE, - SD_PPI_GROUP_ASSIGN, - SD_PPI_GROUP_GET, - SD_RADIO_NOTIFICATION_CFG_SET, - SD_ECB_BLOCK_ENCRYPT, - SD_RADIO_SESSION_OPEN, - SD_RADIO_SESSION_CLOSE, - SD_RADIO_REQUEST, - SD_EVT_GET, - SD_TEMP_GET, - SVC_SOC_LAST -}; - -/**@brief Possible values of a ::nrf_mutex_t. */ -enum NRF_MUTEX_VALUES -{ - NRF_MUTEX_FREE, - NRF_MUTEX_TAKEN -}; - -/**@brief Possible values of ::nrf_app_irq_priority_t. */ -enum NRF_APP_PRIORITIES -{ - NRF_APP_PRIORITY_HIGH = 1, - NRF_APP_PRIORITY_LOW = 3 -}; - -/**@brief Possible values of ::nrf_power_mode_t. */ -enum NRF_POWER_MODES -{ - NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ - NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ -}; - - -/**@brief Possible values of ::nrf_power_failure_threshold_t */ -enum NRF_POWER_THRESHOLDS -{ - NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V27 /**< 2.7 Volts power failure threshold. */ -}; - - -/**@brief Possible values of ::nrf_power_dcdc_mode_t. */ -enum NRF_POWER_DCDC_MODES -{ - NRF_POWER_DCDC_MODE_OFF, /**< The DCDC is always off. */ - NRF_POWER_DCDC_MODE_ON, /**< The DCDC is always on. */ - NRF_POWER_DCDC_MODE_AUTOMATIC /**< The DCDC is automatically managed. */ -}; - -/**@brief Possible values of ::nrf_radio_notification_distance_t. */ -enum NRF_RADIO_NOTIFICATION_DISTANCES -{ - NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ - NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ -}; - - -/**@brief Possible values of ::nrf_radio_notification_type_t. */ -enum NRF_RADIO_NOTIFICATION_TYPES -{ - NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ -}; - -/**@brief SoC Events. */ -enum NRF_SOC_EVTS -{ - NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ - NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ - NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ - NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ - NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ - NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ - NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio signal callback handler return was invalid. */ - NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio session is idle. */ - NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio session is closed. */ - NRF_EVT_NUMBER_OF_EVTS -}; - -/** @} */ - -/** @addtogroup NRF_SOC_TYPES Types - * @{ */ - -/**@brief Represents a mutex for use with the nrf_mutex functions. - * @note Accessing the value directly is not safe, use the mutex functions! - */ -typedef volatile uint8_t nrf_mutex_t; - -/**@brief The interrupt priorities available to the application while the softdevice is active. */ -typedef uint8_t nrf_app_irq_priority_t; - -/**@brief Represents a power mode, used in power mode functions */ -typedef uint8_t nrf_power_mode_t; - -/**@brief Represents a power failure threshold value. */ -typedef uint8_t nrf_power_failure_threshold_t; - -/**@brief Represents a DCDC mode value. */ -typedef uint32_t nrf_power_dcdc_mode_t; - -/**@brief Radio notification distances. */ -typedef uint8_t nrf_radio_notification_distance_t; - -/**@brief Radio notification types. */ -typedef uint8_t nrf_radio_notification_type_t; - -/** @brief The Radio signal callback types. */ -enum NRF_RADIO_CALLBACK_SIGNAL_TYPE -{ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ -}; - -/** @brief The actions requested by the signal callback. - * - * This code gives the SOC instructions about what action to take when the signal callback has - * returned. - */ -enum NRF_RADIO_SIGNAL_CALLBACK_ACTION -{ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current timeslot (maximum execution time for this action is when the extension succeeded). */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ -}; - -/**@brief Radio timeslot high frequency clock source configuration. */ -enum NRF_RADIO_HFCLK_CFG -{ - NRF_RADIO_HFCLK_CFG_DEFAULT, /**< Use the currently selected oscillator as HF clock source during the timeslot (i.e. the source is not specified). */ - NRF_RADIO_HFCLK_CFG_FORCE_XTAL, /**< Force external crystal to be used as HF clock source during whole the timeslot. */ -}; - -/** @brief Radio timeslot priorities. */ -enum NRF_RADIO_PRIORITY -{ - NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ - NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activites of the SoftDevice stack(s)). */ -}; - -/** @brief Radio timeslot request type. */ -enum NRF_RADIO_REQUEST_TYPE -{ - NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request timeslot as early as possible. This should always be used for the first request in a session. */ - NRF_RADIO_REQ_TYPE_NORMAL /**< Normal timeslot request. */ -}; - -/** @brief Parameters for a request for a timeslot as early as possible. */ -typedef struct -{ - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ - uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ -} nrf_radio_request_earliest_t; - -/** @brief Parameters for a normal radio request. */ -typedef struct -{ - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ - uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ -} nrf_radio_request_normal_t; - -/** @brief Radio request parameters. */ -typedef struct -{ - uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ - union - { - nrf_radio_request_earliest_t earliest; /**< Parameters for a request for a timeslot as early as possible. */ - nrf_radio_request_normal_t normal; /**< Parameters for a normal radio request. */ - } params; -} nrf_radio_request_t; - -/**@brief Return parameters of the radio timeslot signal callback. */ -typedef struct -{ - uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ - union - { - struct - { - nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ - } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ - struct - { - uint32_t length_us; /**< Requested extension of the timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ - } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ - } params; -} nrf_radio_signal_callback_return_param_t; - -/**@brief The radio signal callback type. - * - * @note In case of invalid return parameters, the radio timeslot will automatically end - * immediately after returning from the signal callback and the - * @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent. - * @note The returned struct pointer must remain valid after the signal callback - * function returns. For instance, this means that it must not point to a stack variable. - * - * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE. - * - * @return Pointer to structure containing action requested by the application. - */ -typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); - -/**@brief AES ECB data structure */ -typedef struct -{ - uint8_t key[SOC_ECB_KEY_LENGTH]; /**< Encryption key. */ - uint8_t cleartext[SOC_ECB_CLEARTEXT_LENGTH]; /**< Clear Text data. */ - uint8_t ciphertext[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Cipher Text data. */ -} nrf_ecb_hal_data_t; - -/** @} */ - -/** @addtogroup NRF_SOC_FUNCTIONS Functions - * @{ */ - -/**@brief Initialize a mutex. - * - * @param[in] p_mutex Pointer to the mutex to initialize. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); - -/**@brief Attempt to acquire a mutex. - * - * @param[in] p_mutex Pointer to the mutex to acquire. - * - * @retval ::NRF_SUCCESS The mutex was successfully acquired. - * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. - */ -SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); - -/**@brief Release a mutex. - * - * @param[in] p_mutex Pointer to the mutex to release. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); - -/**@brief Enable External Interrupt. - * @note Corresponds to NVIC_EnableIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt was enabled. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. - */ -SVCALL(SD_NVIC_ENABLEIRQ, uint32_t, sd_nvic_EnableIRQ(IRQn_Type IRQn)); - -/**@brief Disable External Interrupt. - * @note Corresponds to NVIC_DisableIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS - * - * @retval ::NRF_SUCCESS The interrupt was disabled. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. - */ -SVCALL(SD_NVIC_DISABLEIRQ, uint32_t, sd_nvic_DisableIRQ(IRQn_Type IRQn)); - -/**@brief Get Pending Interrupt. - * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. - * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. - * - * @retval ::NRF_SUCCESS The interrupt is available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -SVCALL(SD_NVIC_GETPENDINGIRQ, uint32_t, sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)); - -/**@brief Set Pending Interrupt. - * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt is set pending. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -SVCALL(SD_NVIC_SETPENDINGIRQ, uint32_t, sd_nvic_SetPendingIRQ(IRQn_Type IRQn)); - -/**@brief Clear Pending Interrupt. - * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -SVCALL(SD_NVIC_CLEARPENDINGIRQ, uint32_t, sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)); - -/**@brief Set Interrupt Priority. - * @note Corresponds to NVIC_SetPriority in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * @pre{priority is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. - * @param[in] priority A valid IRQ priority for use by the application. - * - * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. - */ -SVCALL(SD_NVIC_SETPRIORITY, uint32_t, sd_nvic_SetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t priority)); - -/**@brief Get Interrupt Priority. - * @note Corresponds to NVIC_GetPriority in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. - * @param[out] p_priority Return value from NVIC_GetPriority. - * - * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. - */ -SVCALL(SD_NVIC_GETPRIORITY, uint32_t, sd_nvic_GetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t * p_priority)); - -/**@brief System Reset. - * @note Corresponds to NVIC_SystemReset in CMSIS. - * - * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN - */ -SVCALL(SD_NVIC_SYSTEMRESET, uint32_t, sd_nvic_SystemReset(void)); - -/**@brief Enters critical region. - * - * @post Application interrupts will be disabled. - * @sa sd_nvic_critical_region_exit - * - * @param[out] p_is_nested_critical_region 1: If in a nested critical region. - * 0: Otherwise. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_NVIC_CRITICAL_REGION_ENTER, uint32_t, sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)); - -/**@brief Exit critical region. - * - * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. - * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. - * - * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_NVIC_CRITICAL_REGION_EXIT, uint32_t, sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)); - -/**@brief Query the capacity of the application random pool. - * - * @param[out] p_pool_capacity The capacity of the pool. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); - -/**@brief Get number of random bytes available to the application. - * - * @param[out] p_bytes_available The number of bytes currently available in the pool. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); - -/**@brief Get random bytes from the application pool. - * - * @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. - * @param[in] length Number of bytes to take from pool and place in p_buff. - * - * @retval ::NRF_SUCCESS The requested bytes were written to p_buff. - * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. -*/ -SVCALL(SD_RAND_APPLICATION_GET_VECTOR, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); - -/**@brief Gets the reset reason register. - * - * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); - -/**@brief Clears the bits of the reset reason register. - * - * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); - -/**@brief Sets the power mode when in CPU sleep. - * - * @param[in] power_mode The power mode to use when in CPU sleep. @sa sd_app_evt_wait - * - * @retval ::NRF_SUCCESS The power mode was set. - * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. - */ -SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(nrf_power_mode_t power_mode)); - -/**@brief Puts the chip in System OFF mode. - * - * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN - */ -SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); - -/**@brief Enables or disables the power-fail comparator. - * - * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. - * The event can be retrieved with sd_evt_get(); - * - * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); - -/**@brief Sets the power-fail threshold value. - * - * @param[in] threshold The power-fail threshold value to use. - * - * @retval ::NRF_SUCCESS The power failure threshold was set. - * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. - */ -SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(nrf_power_failure_threshold_t threshold)); - -/**@brief Sets bits in the NRF_POWER->RAMON register. - * - * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon)); - -/** @brief Clears bits in the NRF_POWER->RAMON register. - * - * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon)); - -/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks. - * - * @param[out] p_ramon Content of NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon)); - -/**@brief Set bits in the NRF_POWER->GPREGRET register. - * - * @param[in] gpregret_msk Bits to be set in the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk)); - -/**@brief Clear bits in the NRF_POWER->GPREGRET register. - * - * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk)); - -/**@brief Get contents of the NRF_POWER->GPREGRET register. - * - * @param[out] p_gpregret Contents of the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret)); - -/**@brief Sets the DCDC mode. - * - * Depending on the internal state of the SoftDevice, the mode change may not happen immediately. - * The DCDC mode switch will be blocked when occurring in close proximity to radio transmissions. When - * the radio transmission is done, the last mode will be used. - * - * @param[in] dcdc_mode The mode of the DCDC. - * - * @retval ::NRF_SUCCESS - * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. - */ -SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(nrf_power_dcdc_mode_t dcdc_mode)); - -/**@brief Request the high frequency crystal oscillator. - * - * Will start the high frequency crystal oscillator, the startup time of the crystal varies - * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. - * - * @see sd_clock_hfclk_is_running - * @see sd_clock_hfclk_release - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); - -/**@brief Releases the high frequency crystal oscillator. - * - * Will stop the high frequency crystal oscillator, this happens immediately. - * - * @see sd_clock_hfclk_is_running - * @see sd_clock_hfclk_request - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); - -/**@brief Checks if the high frequency crystal oscillator is running. - * - * @see sd_clock_hfclk_request - * @see sd_clock_hfclk_release - * - * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); - -/**@brief Waits for an application event. - * - * An application event is either an application interrupt or a pended interrupt when the - * interrupt is disabled. When the interrupt is enabled it will be taken immediately since - * this function will wait in thread mode, then the execution will return in the application's - * main thread. When an interrupt is disabled and gets pended it will return to the application's - * thread main. The application must ensure that the pended flag is cleared using - * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for - * disabled interrupts, as the interrupt handler will clear the pending flag automatically for - * enabled interrupts. - * - * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0 - * System Control Register (SCR). @sa CMSIS_SCB - * - * @note If an application interrupt has happened since the last time sd_app_evt_wait was - * called this function will return immediately and not go to sleep. This is to avoid race - * conditions that can occur when a flag is updated in the interrupt handler and processed - * in the main loop. - * - * @post An application interrupt has happened or a interrupt pending flag is set. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); - -/**@brief Get PPI channel enable register contents. - * - * @param[out] p_channel_enable The contents of the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); - -/**@brief Set PPI channel enable register. - * - * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); - -/**@brief Clear PPI channel enable register. - * - * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); - -/**@brief Assign endpoints to a PPI channel. - * - * @param[in] channel_num Number of the PPI channel to assign. - * @param[in] evt_endpoint Event endpoint of the PPI channel. - * @param[in] task_endpoint Task endpoint of the PPI channel. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); - -/**@brief Task to enable a channel group. - * - * @param[in] group_num Number of the channel group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); - -/**@brief Task to disable a channel group. - * - * @param[in] group_num Number of the PPI group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); - -/**@brief Assign PPI channels to a channel group. - * - * @param[in] group_num Number of the channel group. - * @param[in] channel_msk Mask of the channels to assign to the group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); - -/**@brief Gets the PPI channels of a channel group. - * - * @param[in] group_num Number of the channel group. - * @param[out] p_channel_msk Mask of the channels assigned to the group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); - -/**@brief Configures the Radio Notification signal. - * - * @note - * - The notification signal latency depends on the interrupt priority settings of SWI used - * for notification signal. - * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice - * will interrupt the application to do Radio Event preparation. - * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have - * to shorten the connection events to have time for the Radio Notification signals. - * - * @param[in] type Type of notification signal. - * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio - * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is - * recommended (but not required) to be used with - * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. - * - * @param[in] distance Distance between the notification signal and start of radio activity. - * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or - * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. - * - * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(nrf_radio_notification_type_t type, nrf_radio_notification_distance_t distance)); - -/**@brief Encrypts a block according to the specified parameters. - * - * 128-bit AES encryption. - * - * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input - * parameters and one output parameter). - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); - -/**@brief Gets any pending events generated by the SoC API. - * - * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. - * - * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. - * - * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. - * @retval ::NRF_ERROR_NOT_FOUND No pending events. - */ -SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); - -/**@brief Get the temperature measured on the chip - * - * This function will block until the temperature measurement is done. - * It takes around 50us from call to return. - * - * @note Pan #28 in PAN-028 v 1.6 "Negative measured values are not represented correctly" is corrected by this function. - * - * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius. - * - * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp - */ -SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); - -/**@brief Flash Write - * - * Commands to write a buffer to flash - * - * This call initiates the flash access command, and its completion will be communicated to the - * application with exactly one of the following events: - * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. - * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. - * - * @note - * - This call takes control over the radio and the CPU during flash erase and write to make sure that - * they will not interfere with the flash access. This means that all interrupts will be blocked - * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual - * and the command parameters). - * - * - * @param[in] p_dst Pointer to start of flash location to be written. - * @param[in] p_src Pointer to buffer with data to be written - * @param[in] size Number of 32-bit words to write. Maximum size is 256 32bit words. - * - * @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. - * @retval ::NRF_ERROR_BUSY The previous command has not yet completed. - * @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or more than 256 words. - * @retval ::NRF_ERROR_FORBIDDEN Tried to write to or read from protected location. - * @retval ::NRF_SUCCESS The command was accepted. - */ -SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size)); - - -/**@brief Flash Erase page - * - * Commands to erase a flash page - * - * This call initiates the flash access command, and its completion will be communicated to the - * application with exactly one of the following events: - * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. - * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. - * - * @note - * - This call takes control over the radio and the CPU during flash erase and write to make sure that - * they will not interfere with the flash access. This means that all interrupts will be blocked - * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual - * and the command parameters). - * - * - * @param[in] page_number Pagenumber of the page to erase - * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. - * @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. - * @retval ::NRF_ERROR_BUSY The previous command has not yet completed. - * @retval ::NRF_ERROR_FORBIDDEN Tried to erase a protected page. - * @retval ::NRF_SUCCESS The command was accepted. - */ -SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)); - - -/**@brief Flash Protection set - * - * Commands to set the flash protection registers PROTENSETx - * - * @note To read the values in PROTENSETx you can read them directly. They are only write-protected. - * - * @param[in] protenset0 Value to be written to PROTENSET0 - * @param[in] protenset1 Value to be written to PROTENSET1 - * - * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice - * @retval ::NRF_SUCCESS Values successfully written to PROTENSETx - */ -SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t protenset0, uint32_t protenset1)); - -/**@brief Opens a session for radio requests. - * - * @note Only one session can be open at a time. - * @note p_radio_signal_callback(NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot - * starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed - * by the application. - * @note p_radio_signal_callback(NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0 - * interrupt occurs. - * @note p_radio_signal_callback(NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO - * interrupt occurs. - * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This - * implies that none of the sd_* API calls can be used from p_radio_signal_callback(). - * - * @param[in] p_radio_signal_callback The signal callback. - * - * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer. - * @retval ::NRF_ERROR_BUSY If session cannot be opened. - * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); - -/**@brief Closes a session for radio requests. - * - * @note Any current radio timeslot will be finished before the session is closed. - * @note If a radio timeslot is scheduled when the session is closed, it will be canceled. - * @note The application cannot consider the session closed until the NRF_EVT_RADIO_SESSION_CLOSED - * event is received. - * - * @retval ::NRF_ERROR_FORBIDDEN If session not opened. - * @retval ::NRF_ERROR_BUSY If session is currently being closed. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); - - /**@brief Requests a radio timeslot. - * - * @note The timing of the radio timeslot is specified by p_request->distance_us. For the first - * request in a session, p_request->distance_us is required to be 0 by convention, and - * the timeslot is scheduled at the first possible opportunity. All following radio timeslots are - * requested with a distance of p_request->distance_us measured from the start of the - * previous radio timeslot. - * @note A too small p_request->distance_us will lead to a NRF_EVT_RADIO_BLOCKED event. - * @note Timeslots scheduled too close will lead to a NRF_EVT_RADIO_BLOCKED event. - * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths. - * @note If an opportunity for the first radio timeslot is not found before 100ms after the call to this - * function, it is not scheduled, and instead a NRF_EVT_RADIO_BLOCKED event is sent. - * The application may then try to schedule the first radio timeslot again. - * @note Successful requests will result in nrf_radio_signal_callback_t(NRF_RADIO_CALLBACK_SIGNAL_TYPE_START). - * Unsuccessful requests will result in a NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS. - * @note The jitter in the start time of the radio timeslots is +/- NRF_RADIO_START_JITTER_US us. - * @note The nrf_radio_signal_callback_t(NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the - * specified radio timeslot start, but this does not affect the actual start time of the timeslot. - * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency - * (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is - * guaranteed to be clocked from the external crystal. - * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral - * during the radio timeslot. - * - * @param[in] p_request Pointer to the request parameters. - * - * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE. - * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid. - * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t * p_request )); - -/** @} */ - -#endif // NRF_SOC_H__ - -/**@} */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_svc.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_svc.h deleted file mode 100644 index 5604b957a4..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/nrf_svc.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef NRF_SVC__ -#define NRF_SVC__ - -#ifdef SVCALL_AS_NORMAL_FUNCTION -#define SVCALL(number, return_type, signature) return_type signature -#else - -#ifndef SVCALL -#if defined (__CC_ARM) -#define SVCALL(number, return_type, signature) return_type __svc(number) signature -#elif defined (__GNUC__) -#define SVCALL(number, return_type, signature) \ - _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ - _Pragma("GCC diagnostic ignored \"-Wunused-function\"") \ - __attribute__((naked)) static return_type signature \ - { \ - __asm( \ - "svc %0\n" \ - "bx r14" : : "I" ((uint32_t)number) : "r0" \ - ); \ - } -#elif defined (__ICCARM__) -#define PRAGMA(x) _Pragma(#x) -#define SVCALL(number, return_type, signature) \ -PRAGMA(swi_number = number) \ - __swi return_type signature; -#else -#define SVCALL(number, return_type, signature) return_type signature -#endif -#endif // SVCALL - -#endif // SVCALL_AS_NORMAL_FUNCTION -#endif // NRF_SVC__ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/softdevice_assert.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/softdevice_assert.h deleted file mode 100644 index 42494477bf..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_API/include/softdevice_assert.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is confidential property of Nordic Semiconductor. The use, - * copying, transfer or disclosure of such information is prohibited except by express written - * agreement with Nordic Semiconductor. - * - */ - -/** @brief Utilities for verifying program logic - */ - -#ifndef SOFTDEVICE_ASSERT_H_ -#define SOFTDEVICE_ASSERT_H_ - -#include - -/** @brief This function handles assertions. - * - * - * @note - * This function is called when an assertion has triggered. - * - * - * @param line_num The line number where the assertion is called - * @param file_name Pointer to the file name - */ -void assert_softdevice_callback(uint16_t line_num, const uint8_t *file_name); - - -/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */ -/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \ -/** @brief Check intended for production code - * - * Check passes if "expr" evaluates to true. */ -#define ASSERT(expr) \ -if (expr) \ -{ \ -} \ -else \ -{ \ - assert_softdevice_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \ - /*lint -unreachable */ \ -} - -#endif /* SOFTDEVICE_ASSERT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_licence_agreement.pdf b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_licence_agreement.pdf deleted file mode 100644 index 7aab95c8e7ae8c764467d3d81fa9069d2ff9c2ef..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5553 zcmc(jXIPZUvVau{imnJEC~=4mpiE+jLk*m+>M^e8(`;moR@SEiSv3zTNagMaQ2j>9;4npZvMD4Uri_x$ncIO8Gkw z%tMWZSvf%~?| z-jJcXWRnHj=U8&nVoF|V2<{6lpH$SLnszpOe0<-v`K#czwI6$X^(`*8hID zoqa@~I{3`-ytKrcad?LX^Q!@-6>4;gHkFVb6P}K3)sb()$D7a~&qSb}Toh3B^-7T8 zb7aA%Sx;hhA2Z9d&BX6}QC0!M%nLSMt3vM~E#^-G%Ln45fzOzdIdhfm zsp_%o&GjD&InTI$89ygxXsB}Hczt|Orv^J#>d=Yp9Y3p-kcWC>gvTU_Ik}PItex*$ z&AqkF0k>BRVKBZT6z2`^MDdWhv5ig@rJ6{W-pVf)ihf;BO9fOxldpz5e8pm=FWzok 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+:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000196401000000000009 +:0869100000000000000000007F +:00000001FF diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 2c64876afd..3efd014359 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -419,7 +419,7 @@ class K20D50M(Target): class TEENSY3_1(Target): OUTPUT_EXT = 'hex' - + def __init__(self): Target.__init__(self) self.core = "Cortex-M4" @@ -630,7 +630,7 @@ class ARCH_MAX(Target): self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"] - + def program_cycle_s(self): return 2 @@ -809,15 +809,19 @@ class NRF51822(Target): # of preference. EXPECTED_SOFTDEVICES_WITH_OFFSETS = [ { - 'name' : 's110_nrf51822_7.1.0_softdevice.hex', + 'name' : 's110_nrf51822_8.0.0_softdevice.hex', + 'offset' : 0x18000 + }, + { + 'name' : 's110_nrf51822_7.1.0_softdevice.hex', 'offset' : 0x16000 }, { - 'name' : 's110_nrf51822_7.0.0_softdevice.hex', + 'name' : 's110_nrf51822_7.0.0_softdevice.hex', 'offset' : 0x16000 }, { - 'name' : 's110_nrf51822_6.0.0_softdevice.hex', + 'name' : 's110_nrf51822_6.0.0_softdevice.hex', 'offset' : 0x14000 } ] @@ -918,7 +922,7 @@ class NRF51_DK_BOOT(NRF51822): self.supported_toolchains = ["ARM", "GCC_ARM"] self.MERGE_SOFT_DEVICE = True self.MERGE_BOOTLOADER = True - + class NRF51_DK_OTA(NRF51822): def __init__(self): NRF51822.__init__(self) From 3b5bda9aa4968f05017822b73a1c3ea1a17d347c Mon Sep 17 00:00:00 2001 From: ytsuboi Date: Tue, 21 Apr 2015 01:35:11 +0900 Subject: [PATCH 135/143] [LPC1114] Add GCC_CR to official mbed library build --- workspace_tools/build_release.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 602560831b..3a921fdcf5 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -38,7 +38,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('LPC1347', ('ARM','IAR')), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC4088_DM', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), - ('LPC1114', ('uARM','GCC_ARM', 'IAR')), + ('LPC1114', ('uARM','GCC_ARM', 'GCC_CR', 'IAR')), ('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('LPC1549', ('uARM','GCC_ARM','GCC_CR', 'IAR')), From f522ea7967185b865505a17692c33b5806fa0a06 Mon Sep 17 00:00:00 2001 From: Neil Thiessen Date: Mon, 20 Apr 2015 12:28:47 -0600 Subject: [PATCH 136/143] NUCLEO-F411RE USB clock frequency fix HAL: NUCLEO_F411RE - Corrected USB clock frequency Modified the main PLL settings so that the USB clock will run at a proper 48MHz instead of 44.44MHz. Consequently, the core clock will now run at 96MHz instead of 100MHz. --- .../TARGET_NUCLEO_F411RE/system_stm32f4xx.c | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c index efb6464a73..2bb21f1617 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c @@ -27,15 +27,15 @@ * | 2- PLL_HSE_XTAL | * | (external 8 MHz xtal) | *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 100 | 100 + * SYSCLK(MHz) | 96 | 96 *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 100 | 100 + * AHBCLK (MHz) | 96 | 96 *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 50 | 50 + * APB1CLK (MHz) | 48 | 48 *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 100 | 100 + * APB2CLK (MHz) | 96 | 96 *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | NO | NO + * USB capable (48 MHz precise clock) | YES | YES *----------------------------------------------------------------------------- ****************************************************************************** * @attention @@ -611,11 +611,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) - //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -623,10 +623,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { return 0; // FAIL @@ -665,11 +665,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) - //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -677,10 +677,10 @@ uint8_t SetSysClock_PLL_HSI(void) /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { return 0; // FAIL From bae48d52edc2b6e7124d6e71f778cd10a1f28d13 Mon Sep 17 00:00:00 2001 From: Yihui Xiong Date: Tue, 21 Apr 2015 15:03:52 +0800 Subject: [PATCH 137/143] fix LSI clock value for Arch Max (STM32F407) --- workspace_tools/targets.py | 1 + 1 file changed, 1 insertion(+) diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 3efd014359..685cea4171 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -630,6 +630,7 @@ class ARCH_MAX(Target): self.extra_labels = ['STM', 'STM32F4', 'STM32F407', 'STM32F407VG'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"] + self.macros = ['LSI_VALUE=32000'] def program_cycle_s(self): return 2 From f3936afa344dcec377c594de204cb896423eba69 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 21 Apr 2015 11:24:58 +0100 Subject: [PATCH 138/143] Revert "Fixed interrupt handler in serial_api.c for the Nordic NRF51. The last b..." --- .../TARGET_MCU_NRF51822/serial_api.c | 39 +++++-------------- 1 file changed, 10 insertions(+), 29 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c index 4cf1819f60..8e3e8c34c7 100755 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c @@ -76,7 +76,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart->TXD = 0; obj->index = 0; - + obj->uart->PSELRTS = RTS_PIN_NUMBER; obj->uart->PSELTXD = tx; //TX_PIN_NUMBER; obj->uart->PSELCTS = CTS_PIN_NUMBER; @@ -162,20 +162,14 @@ extern "C" { #endif void UART0_IRQHandler() { - if((NRF_UART0->INTENSET & UART_INTENSET_TXDRDY_Msk) && NRF_UART0->EVENTS_TXDRDY) - { - uart_irq(1, 0); + uint32_t irtype = 0; - /* Explicitly clear TX flag to prevent interrupt from firing - immediately after returning from ISR. This ensures that the - last interrupt in a transmission sequence is correcly handled. - */ - NRF_UART0->EVENTS_TXDRDY = 0; - } - else if((NRF_UART0->INTENSET & UART_INTENSET_RXDRDY_Msk) && NRF_UART0->EVENTS_RXDRDY) - { - uart_irq(2, 0); + if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) { + irtype = 1; + } else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) { + irtype = 2; } + uart_irq(irtype, 0); } #ifdef __cplusplus @@ -245,24 +239,11 @@ int serial_getc(serial_t *obj) void serial_putc(serial_t *obj, int c) { - /* In interrupt mode, send character immediately. Otherwise, block until - UART is ready to receive next character before sending. - - The TXDRDY flag is cleared in interrupt handler to ensure that it is - cleared even if there are no more characters to send. - */ - if (NRF_UART0->INTENSET & UART_INTENSET_TXDRDY_Msk) - { - obj->uart->TXD = (uint8_t)c; + while (!serial_writable(obj)) { } - else - { - while (!serial_writable(obj)) { - } - obj->uart->EVENTS_TXDRDY = 0; - obj->uart->TXD = (uint8_t)c; - } + obj->uart->EVENTS_TXDRDY = 0; + obj->uart->TXD = (uint8_t)c; } int serial_readable(serial_t *obj) From f67632b347a117d2f98ec57bc8e349cd438c3f13 Mon Sep 17 00:00:00 2001 From: Giuliano Dianda Date: Tue, 21 Apr 2015 16:01:30 +0200 Subject: [PATCH 139/143] STM32: Fix HSE/HSI clk source detection When using online compiler (Keil) SystemInit (and systick stuff) is call before RW data is initialized, so static and global variables contains garbage. AHBPrescTable was one of these. --- .../TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c | 1 + .../TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c | 1 + .../TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c | 2 +- .../TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c | 2 +- .../cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c | 4 ++-- .../cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c | 2 +- .../TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c | 2 +- .../TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c | 2 +- .../TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c | 2 +- .../TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c | 2 +- .../TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c | 2 +- .../cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h | 2 +- .../cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c | 2 +- .../TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c | 6 +++--- .../TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c | 6 +++--- .../TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c | 6 +++--- .../cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h | 2 +- .../cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c | 4 ++-- .../cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h | 2 +- 19 files changed, 27 insertions(+), 25 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c index b20d91c33b..164d05f195 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c @@ -209,6 +209,7 @@ void SystemInit(void) RCC->CIR = 0x00000000; /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock HAL_Init(); /* Configure the System clock source, PLL Multiplier and Divider factors, diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c index b2fc901df2..5b7227f3c8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c @@ -226,6 +226,7 @@ void SystemInit(void) RCC->CIR = 0x00000000; /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock HAL_Init(); /* Configure the System clock source, PLL Multiplier and Divider factors, diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c index 937b24e597..abbe81c0f0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c @@ -159,7 +159,7 @@ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ #endif -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c index 5073ffc87c..196ddfff57 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c @@ -161,7 +161,7 @@ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ #endif -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c index 3b8f7b6f32..d70377b7d7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c @@ -141,8 +141,8 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 }; +const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 }; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c index fb191f7aa8..5741c6da81 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c @@ -143,7 +143,7 @@ uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */ -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c index c935079912..793c597be4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c @@ -155,7 +155,7 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 168000000; - __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c index 47507ff930..bbe76cd827 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c @@ -158,7 +158,7 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 16000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c index 036582380a..2a2ff56b73 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c @@ -163,7 +163,7 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 16000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c index efb6464a73..4f4a6339c7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c @@ -157,7 +157,7 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 16000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c index efb6464a73..4f4a6339c7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c @@ -157,7 +157,7 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 16000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h index 3164db2057..fa720c9474 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h @@ -190,7 +190,7 @@ typedef struct #define DBP_TIMEOUT_VALUE ((uint32_t)100) -#define LSE_TIMEOUT_VALUE ((uint32_t)600) +#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c index 9e0004e7bf..02eb8f81df 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c @@ -184,7 +184,7 @@ uint32_t SystemCoreClock = 168000000; - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c index 2c7167a6a7..f2a95c6667 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c @@ -145,9 +145,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 32000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +uint32_t SystemCoreClock = 32000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c index 2c7167a6a7..f2a95c6667 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c @@ -145,9 +145,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 32000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +uint32_t SystemCoreClock = 32000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c index 2c7167a6a7..f2a95c6667 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c @@ -145,9 +145,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 32000000; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +uint32_t SystemCoreClock = 32000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h index e769428483..b68cdd89e1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h @@ -123,7 +123,7 @@ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c index 01a586c3f7..f48f17eb5a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c @@ -118,8 +118,8 @@ /** @defgroup RCC_Private_Vatiables RCC Private Data * @{ */ -static __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -static __IO const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h index f085833f52..81c5571b5f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h @@ -122,7 +122,7 @@ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ From ddd3e8859f78aa63886142738e828f405f6452e7 Mon Sep 17 00:00:00 2001 From: rnestler Date: Thu, 23 Apr 2015 00:23:19 +0200 Subject: [PATCH 140/143] workspace_tools: Use python2 in shebang The scripts are not python3 compatible so we should explicitly call python2. --- workspace_tools/build.py | 2 +- workspace_tools/build_travis.py | 2 +- workspace_tools/make.py | 2 +- workspace_tools/singletest.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/workspace_tools/build.py b/workspace_tools/build.py index 2709592129..f402cb0222 100755 --- a/workspace_tools/build.py +++ b/workspace_tools/build.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python2 """ mbed SDK Copyright (c) 2011-2013 ARM Limited diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index df534b3175..46e7e6c3e8 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 """ Travis-CI build script diff --git a/workspace_tools/make.py b/workspace_tools/make.py index 932a03c125..828f3644ab 100755 --- a/workspace_tools/make.py +++ b/workspace_tools/make.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#! /usr/bin/env python2 """ mbed SDK Copyright (c) 2011-2013 ARM Limited diff --git a/workspace_tools/singletest.py b/workspace_tools/singletest.py index e1ee3a449f..e7caef72ca 100644 --- a/workspace_tools/singletest.py +++ b/workspace_tools/singletest.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 """ mbed SDK From 809d8aa82baa0e196695d0c8bfec84e654676705 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Thu, 23 Apr 2015 08:55:29 +0100 Subject: [PATCH 141/143] Squashed commit of the following (PR #1023): commit 5390a0eb7fc28dda30993602652350fd0ad87df0 Merge: 7c4831f 3998966 Author: 0xc0170 Date: Thu Apr 23 08:48:31 2015 +0100 Merge branch 'master' of https://github.com/dudmuck/mbed into dudmuck-master Conflicts: workspace_tools/export/uvision4.py commit 3998966b1b130716855ac01142d8da917c3e1d2f Author: U-owner-PC\owner Date: Thu Apr 9 13:45:09 2015 -0700 using defines for platform specific requirement commit 755c5d9b0713768771d110468a6750abf506bb1c Author: U-owner-PC\owner Date: Wed Apr 8 14:59:47 2015 -0700 added device ID for MOTE_L152RC commit d812fb0002dbc1eea64984bdaf4c18b335979d7d Merge: 6ad66e8 158cbeb Author: U-owner-PC\owner Date: Wed Apr 8 07:25:23 2015 -0700 Merge remote-tracking branch 'upstream/master' commit 6ad66e89d818e595a9327710a9c79bee078b067f Merge: 14a1807 cfb9dd1 Author: U-owner-PC\owner Date: Fri Mar 27 15:54:03 2015 -0700 merged upstream commit 14a18078ca11b4126779914b02df6b75225e1315 Author: U-owner-PC\owner Date: Tue Mar 24 10:01:02 2015 -0700 RTC subSeconds at 16384Hz commit 32d75d04c18177b2fb823f011e002ec36190005a Merge: bc84c03 ea01d61 Author: U-owner-PC\owner Date: Tue Mar 24 09:59:43 2015 -0700 Merge remote-tracking branch 'upstream/master' commit bc84c03a37e10c819e55592aa1efcb621900460b Author: U-owner-PC\owner Date: Mon Mar 16 16:26:18 2015 -0700 handle HSE-PLL enabled upone deepsleep wakeup commit 11bfe693b9a03744b1624f943fa6ed0f6b05ede6 Merge: b7cec55 fdc75bf Author: U-owner-PC\owner Date: Mon Mar 16 14:37:11 2015 -0700 Merge remote-tracking branch 'upstream/master' commit b7cec55d08020fd007046ea93f0ed968e0fb953e Merge: c5b61f5 4b74c54 Author: U-owner-PC\owner Date: Mon Mar 9 13:15:56 2015 -0700 syncd with upstream commit c5b61f5c1d366a789b426f9147cee3fc6e8cd6e3 Merge: c16a115 9d2fd3e Author: U-owner-PC\owner Date: Tue Mar 3 14:05:54 2015 -0800 syncd with upstream commit c16a115e183b340589fb8d61f79ada1f1ce8a7e2 Merge: 51efd61 1b2a621 Author: U-owner-PC\owner Date: Tue Feb 24 09:48:55 2015 -0800 Merge remote-tracking branch 'upstream/master' commit 51efd619f14b0534037167d5a2080106a2ac0adc Author: U-owner-PC\owner Date: Tue Feb 24 09:48:22 2015 -0800 MOTE_L152RC commit a122226e460e2910dfcc8e379ac3484fd5ac5e78 Author: U-owner-PC\owner Date: Tue Feb 24 09:46:08 2015 -0800 renamed SEMTECH_LORA915 to MOTE_L152RC commit 88fcf53069d8a7e602ddfc997947d2871cb93ffa Merge: 3e291c1 8648ff5 Author: U-owner-PC\owner Date: Mon Feb 23 08:11:48 2015 -0800 Merge remote-tracking branch 'upstream/master' commit 3e291c1ccec69901c498b061a6108f0df4b6db2f Merge: a59aefc c9e93d2 Author: U-owner-PC\owner Date: Tue Feb 17 19:04:04 2015 -0800 Merge remote-tracking branch 'upstream/master' syncing my fork with master commit a59aefc6eddfeda6df91ad526f3727c2afcd1da2 Author: U-owner-PC\owner Date: Tue Feb 17 18:46:27 2015 -0800 added SEMTECH_LORA915 to python scripts commit 15b1989b692673edfa1d69ef7ffdd7b5795e9778 Author: U-owner-PC\owner Date: Tue Feb 17 18:42:13 2015 -0800 added platform SEMTECH_LORA915 --- .../TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s | 325 + .../TOOLCHAIN_ARM_MICRO/stm32l152rc.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l152xc.s | 298 + .../TOOLCHAIN_ARM_STD/stm32l152rc.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L152XC.ld | 156 + .../TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s | 421 ++ .../TOOLCHAIN_IAR/startup_stm32l152xc.s | 536 ++ .../TOOLCHAIN_IAR/stm32l152xc.icf | 30 + .../TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h | 38 + .../TARGET_MOTE_L152RC/cmsis_nvic.c | 55 + .../TARGET_MOTE_L152RC/cmsis_nvic.h | 55 + .../TARGET_MOTE_L152RC/hal_tick.c | 121 + .../TARGET_MOTE_L152RC/hal_tick.h | 60 + .../TARGET_MOTE_L152RC/stm32l152xc.h | 5793 +++++++++++++++++ .../TARGET_MOTE_L152RC/stm32l1xx.h | 247 + .../TARGET_MOTE_L152RC/system_stm32l1xx.c | 607 ++ .../TARGET_MOTE_L152RC/system_stm32l1xx.h | 123 + .../TARGET_MOTE_L152RC/PeripheralNames.h | 82 + .../TARGET_MOTE_L152RC/PeripheralPins.c | 188 + .../TARGET_MOTE_L152RC/PinNames.h | 183 + .../TARGET_MOTE_L152RC/PortNames.h | 48 + .../TARGET_MOTE_L152RC/device.h | 70 + .../TARGET_MOTE_L152RC/objects.h | 110 + .../TARGET_STM/TARGET_STM32L1/gpio_object.h | 4 + .../hal/TARGET_STM/TARGET_STM32L1/rtc_api.c | 6 + .../TARGET_STM/TARGET_STM32L1/serial_api.c | 18 +- .../hal/TARGET_STM/TARGET_STM32L1/sleep.c | 31 + workspace_tools/export/coide.py | 1 + .../export/coide_mote_l152rc.coproj.tmpl | 90 + .../export/gcc_arm_mote_l152rc.tmpl | 71 + workspace_tools/export/gccarm.py | 3 +- workspace_tools/export/iar.py | 1 + .../export/iar_mote_l152rc.ewp.tmpl | 1903 ++++++ workspace_tools/export/uvision4.py | 2 + .../export/uvision4_mote_l152rc.uvopt.tmpl | 218 + .../export/uvision4_mote_l152rc.uvproj.tmpl | 438 ++ workspace_tools/targets.py | 10 + 39 files changed, 12541 insertions(+), 3 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s create mode 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.s create mode 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c create mode 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h create mode 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx.h create mode 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h create mode 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h create mode 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c create mode 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h create mode 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h mode change 100644 => 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h mode change 100644 => 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c mode change 100644 => 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c mode change 100644 => 100755 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c mode change 100644 => 100755 workspace_tools/export/coide.py create mode 100755 workspace_tools/export/coide_mote_l152rc.coproj.tmpl create mode 100644 workspace_tools/export/gcc_arm_mote_l152rc.tmpl mode change 100644 => 100755 workspace_tools/export/gccarm.py mode change 100644 => 100755 workspace_tools/export/iar.py create mode 100755 workspace_tools/export/iar_mote_l152rc.ewp.tmpl create mode 100755 workspace_tools/export/uvision4_mote_l152rc.uvopt.tmpl create mode 100755 workspace_tools/export/uvision4_mote_l152rc.uvproj.tmpl mode change 100644 => 100755 workspace_tools/targets.py diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s new file mode 100644 index 0000000000..3ad2ad7815 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s @@ -0,0 +1,325 @@ +; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20008000 ; Top of RAM (32 KB) + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_ACQ_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_ACQ_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct new file mode 100644 index 0000000000..2526dd7acc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32L152RC: 256KB FLASH + 32KB SRAM +LR_IROM1 0x08000000 0x40000 { ; load region size_region + + ER_IROM1 0x08000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 73 vectors = 292 bytes (0x124) to be reserved in RAM + RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.s new file mode 100644 index 0000000000..944c7b6812 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.s @@ -0,0 +1,298 @@ +; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +__initial_sp EQU 0x20008000 ; Top of RAM (32 KB) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_ACQ_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_ACQ_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct new file mode 100644 index 0000000000..2526dd7acc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32L152RC: 256KB FLASH + 32KB SRAM +LR_IROM1 0x08000000 0x40000 { ; load region size_region + + ER_IROM1 0x08000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 73 vectors = 292 bytes (0x124) to be reserved in RAM + RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld new file mode 100644 index 0000000000..3a778eb3bb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld @@ -0,0 +1,156 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292 + * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138 + */ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k + RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s new file mode 100644 index 0000000000..8ff7570d7b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file startup_stm32l152xc.s + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief STM32L152XC Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L152XE devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.s new file mode 100755 index 0000000000..44c8aacb9c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.s @@ -0,0 +1,536 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32l152xc.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 5-September-2014 +;* Description : STM32L152XC Devices vector for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

    © COPYRIGHT(c) 2014 STMicroelectronics

    +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK COMP_ACQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_ACQ_IRQHandler + B COMP_ACQ_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf new file mode 100755 index 0000000000..aed878fb05 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf @@ -0,0 +1,30 @@ +/* [ROM = 256kb = 0x40000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x0803FFFF; + +/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000128; +define symbol __region_RAM_end__ = 0x20007FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x800; +define symbol __size_heap__ = 0x800; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h new file mode 100644 index 0000000000..8c32259ba3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l1xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h new file mode 100755 index 0000000000..29fbb15f40 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32L152RC +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123 +// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM +#define NVIC_NUM_VECTORS 73 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c new file mode 100644 index 0000000000..ec96c6ce0d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h new file mode 100644 index 0000000000..ee23af91ec --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l1xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h new file mode 100644 index 0000000000..7951485466 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h @@ -0,0 +1,5793 @@ +/** + ****************************************************************************** + * @file stm32l152xc.h + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xc + * @{ + */ + +#ifndef __STM32L152xC_H +#define __STM32L152xC_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
    © COPYRIGHT(c) 2014 STMicroelectronics
    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ + !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ + !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ + !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) + /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ + /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ + /* #define STM32L100xC */ /*!< STM32L100RC Devices */ + /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ + /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ + /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ + /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ + /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ + /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ + /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ + /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ +#define STM32L152xC /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ + /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ + /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ + /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ + /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ + /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ + /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ + /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.0.0 + */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L100xB) + #include "stm32l100xb.h" +#elif defined(STM32L100xBA) + #include "stm32l100xba.h" +#elif defined(STM32L100xC) + #include "stm32l100xc.h" +#elif defined(STM32L151xB) + #include "stm32l151xb.h" +#elif defined(STM32L151xBA) + #include "stm32l151xba.h" +#elif defined(STM32L151xC) + #include "stm32l151xc.h" +#elif defined(STM32L151xCA) + #include "stm32l151xca.h" +#elif defined(STM32L151xD) + #include "stm32l151xd.h" +#elif defined(STM32L151xE) + #include "stm32l151xe.h" +#elif defined(STM32L152xB) + #include "stm32l152xb.h" +#elif defined(STM32L152xBA) + #include "stm32l152xba.h" +#elif defined(STM32L152xC) + #include "stm32l152xc.h" +#elif defined(STM32L152xCA) + #include "stm32l152xca.h" +#elif defined(STM32L152xD) + #include "stm32l152xd.h" +#elif defined(STM32L152xE) + #include "stm32l152xe.h" +#elif defined(STM32L162xC) + #include "stm32l162xc.h" +#elif defined(STM32L162xCA) + #include "stm32l162xca.h" +#elif defined(STM32L162xD) + #include "stm32l162xd.h" +#elif defined(STM32L162xE) + #include "stm32l162xe.h" +#else + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c new file mode 100755 index 0000000000..b0c277141a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c @@ -0,0 +1,607 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 24 | 32 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 24 | 32 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 24 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 24 | 32 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" +#include "hal_tick.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM32L152D_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ +const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in SystemInit() function before jump to main. + * This function configures the external SRAM mounted on STM32L152D_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ + | PD15 <-> FSMC_D1 |--------------------+ + +-------------------+ +*/ + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHBENR = 0x000080D8; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00CC00CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A0A; + /* Configure PDx pins speed to 40 MHz */ + GPIOD->OSPEEDR = 0xFFFF0F0F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 40 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 40 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x00000C00; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 40 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHBENR = 0x400080D8; + + /* Configure and enable Bank1_SRAM3 */ + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000300; + FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; +/* + Bank1_SRAM3 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 3; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +*/ + +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) + return 1; // already on HSE PLL, could occur from deepsleep waking + + /* Used to gain time after DeepSleep in case HSI is used */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + return 0; + } + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + // SYSCLK = 24 MHz ((8 MHz * 6) / 2) + // USBCLK = 48 MHz (8 MHz * 6) --> USB OK + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + //else + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + // SYSCLK = 32 MHz ((16 MHz * 4) / 2) + // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ + while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h new file mode 100644 index 0000000000..62e216539a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.h + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L1XX_H +#define __SYSTEM_STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L1xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L1xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L1XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h new file mode 100755 index 0000000000..cb931d9cfb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE +} I2CName; + +typedef enum { + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c new file mode 100755 index 0000000000..02389685df --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c @@ -0,0 +1,188 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN9 + {PB_12, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN18 + {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN19 + {PB_14, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN20 + {PB_15, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN21 + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN10 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN11 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN12 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN13 + {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN14 + {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN15 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT2 (Warning: LED1 is also on this pin) + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker. +const PinMap PinMap_PWM[] = { +// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 + {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 +// {PA_6, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 +// {PA_7, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 +// {PB_8, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 +// {PB_9, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 + {PB_12, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PB_13, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 + {PB_14, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PB_15, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h new file mode 100755 index 0000000000..b8ec33bc5f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h @@ -0,0 +1,183 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32l0xx_hal_gpio.h and stm32l0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + //PH_0 = 0x70, + //PH_1 = 0x71, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_0, + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_3, + D4 = PB_5, + D5 = PB_4, + D6 = PB_10, + D7 = PA_8, + D8 = PA_9, + D9 = PC_7, + D10 = PB_6, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_1, + LED2 = PB_7, + LED3 = PA_10, + //LED4 = PA_5, + //USER_BUTTON = PC_13, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + USBTX = PA_2, + USBRX = PA_3, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_6, + PWM_OUT = PB_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h new file mode 100755 index 0000000000..14295a0b4d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h new file mode 100644 index 0000000000..fd151e3566 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h new file mode 100644 index 0000000000..c6048cfcbd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct dac_s { + DACName dac; + PinName pin; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h old mode 100644 new mode 100755 index 684d968757..3339350902 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h @@ -54,7 +54,11 @@ static inline void gpio_write(gpio_t *obj, int value) if (value) { *obj->reg_set = obj->mask; } else { +#if defined(TARGET_STM32L152RC) + *obj->reg_set = obj->mask << 16; +#else *obj->reg_clr = obj->mask; +#endif } } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c old mode 100644 new mode 100755 index 1bf0ba85f4..9c69525438 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c @@ -86,8 +86,14 @@ void rtc_init(void) __HAL_RCC_RTC_ENABLE(); RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; +#ifdef TARGET_MOTE_L152RC + /* SubSecond resolution of 16384Hz */ + RtcHandle.Init.AsynchPrediv = 1; + RtcHandle.Init.SynchPrediv = (rtc_freq / 2) - 1; +#else RtcHandle.Init.AsynchPrediv = 127; RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; +#endif RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c old mode 100644 new mode 100755 index 27731b903d..7698824df8 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c @@ -95,15 +95,18 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = 2; } +#if defined(USART4_BASE) if (obj->uart == UART_4) { __UART4_CLK_ENABLE(); obj->index = 3; } - +#endif +#if defined(USART5_BASE) if (obj->uart == UART_5) { __UART5_CLK_ENABLE(); obj->index = 4; } +#endif // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); @@ -153,17 +156,20 @@ void serial_free(serial_t *obj) __USART3_CLK_DISABLE(); } +#if defined(USART4_BASE) if (obj->uart == UART_4) { __UART4_FORCE_RESET(); __UART4_RELEASE_RESET(); __UART4_CLK_DISABLE(); } - +#endif +#if defined(USART5_BASE) if (obj->uart == UART_5) { __UART5_FORCE_RESET(); __UART5_RELEASE_RESET(); __UART5_CLK_DISABLE(); } +#endif // Configure GPIOs pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -243,15 +249,19 @@ static void uart3_irq(void) uart_irq(UART_3, 2); } +#if defined(USART4_BASE) static void uart4_irq(void) { uart_irq(UART_4, 3); } +#endif +#if defined(USART5_BASE) static void uart5_irq(void) { uart_irq(UART_5, 4); } +#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -281,15 +291,19 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart3_irq; } +#if defined(USART4_BASE) if (obj->uart == UART_4) { irq_n = UART4_IRQn; vector = (uint32_t)&uart4_irq; } +#endif +#if defined(USART5_BASE) if (obj->uart == UART_5) { irq_n = UART5_IRQn; vector = (uint32_t)&uart5_irq; } +#endif if (enable) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c old mode 100644 new mode 100755 index 07b90c4caf..7031a00e01 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c @@ -50,12 +50,43 @@ void sleep(void) void deepsleep(void) { +#if defined(TARGET_MOTE_L152RC) + int8_t STOPEntry = PWR_STOPENTRY_WFI; +#endif + // Disable HAL tick interrupt TimMasterHandle.Instance = TIM5; __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); +#if defined(TARGET_MOTE_L152RC) + /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + __NOP(); + __NOP(); + __NOP(); + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +#else // Request to enter STOP mode with regulator in low power mode HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); +#endif // After wake-up from STOP reconfigure the PLL SetSysClock(); diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py old mode 100644 new mode 100755 index ff2c31ace3..6dab08e9b8 --- a/workspace_tools/export/coide.py +++ b/workspace_tools/export/coide.py @@ -51,6 +51,7 @@ class CoIDE(Exporter): 'DISCO_F429ZI', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', + 'MOTE_L152RC', ] # seems like CoIDE currently supports only one type diff --git a/workspace_tools/export/coide_mote_l152rc.coproj.tmpl b/workspace_tools/export/coide_mote_l152rc.coproj.tmpl new file mode 100755 index 0000000000..91ec35ee94 --- /dev/null +++ b/workspace_tools/export/coide_mote_l152rc.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + diff --git a/workspace_tools/export/gcc_arm_mote_l152rc.tmpl b/workspace_tools/export/gcc_arm_mote_l152rc.tmpl new file mode 100644 index 0000000000..8a9f703b28 --- /dev/null +++ b/workspace_tools/export/gcc_arm_mote_l152rc.tmpl @@ -0,0 +1,71 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m3 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex size + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py old mode 100644 new mode 100755 index a803e1451b..21a56ba718 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -82,8 +82,9 @@ class GccArm(Exporter): 'NRF51_DONGLE', 'SEEED_TINY_BLE', 'DISCO_F401VC', - 'DELTA_DFCM_NNN40', + 'DELTA_DFCM_NNN40', 'RZ_A1H', + 'MOTE_L152RC', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py old mode 100644 new mode 100755 index a0ca0afcd6..352ec189c1 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -72,6 +72,7 @@ class IAREmbeddedWorkbench(Exporter): 'SEEED_TINY_BLE', 'HRM1017', 'ARCH_BLE', + 'MOTE_L152RC', ] def generate(self): diff --git a/workspace_tools/export/iar_mote_l152rc.ewp.tmpl b/workspace_tools/export/iar_mote_l152rc.ewp.tmpl new file mode 100755 index 0000000000..cb4c55d0c9 --- /dev/null +++ b/workspace_tools/export/iar_mote_l152rc.ewp.tmpl @@ -0,0 +1,1903 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + {% for files in source_files %} + + $PROJ_DIR$\{{files}} + + {% endfor %} + + + diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 1f1c053829..a061a96689 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -75,6 +75,7 @@ class Uvision4(Exporter): 'DELTA_DFCM_NNN40', 'MAXWSNENV', 'MAX32600MBED', + 'MOTE_L152RC', ] USING_MICROLIB = [ @@ -100,6 +101,7 @@ class Uvision4(Exporter): 'LPC11U35_501', 'KL05Z', 'LPC11U37H_401', + 'MOTE_L152RC', ] FILE_TYPES = { diff --git a/workspace_tools/export/uvision4_mote_l152rc.uvopt.tmpl b/workspace_tools/export/uvision4_mote_l152rc.uvopt.tmpl new file mode 100755 index 0000000000..454e48b3d4 --- /dev/null +++ b/workspace_tools/export/uvision4_mote_l152rc.uvopt.tmpl @@ -0,0 +1,218 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed MOTE_L152RC + 0x4 + ARM-ADS + + 32000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 13 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L1xx_384.FLM -FS08000000 -FL060000 -FP0($$Device:STM32L152RC$Flash\STM32L1xx_384.FLM) + + + 0 + UL2CM3 + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0STM32L1xx_384 -FL060000 -FS08000000 -FP0($$Device:STM32L152RC$Flash\STM32L1xx_384.FLM) + + + 0 + ULP2CM3 + -U -O207 -S8 -C0 -P00 -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_256 -FS08000000 -FL040000 + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_48MHZ -FS00 -FL020000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + +     diff --git a/workspace_tools/export/uvision4_mote_l152rc.uvproj.tmpl b/workspace_tools/export/uvision4_mote_l152rc.uvproj.tmpl new file mode 100755 index 0000000000..8e1685d8a3 --- /dev/null +++ b/workspace_tools/export/uvision4_mote_l152rc.uvproj.tmpl @@ -0,0 +1,438 @@ + + + + 1.1 + +
    ### uVision Project, (C) Keil Software
    + + + + mbed MOTE_L152RC + 0x4 + ARM-ADS + + + STM32L152RC + STMicroelectronics + IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + + ULP2CM3(-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_256 -FS08000000 -FL040000) + 6520 + $$Device:STM32L152RC$Device\Include\STM32L1xx.h + + + + + + + + + + $$Device:STM32L152RC$SVD\STM32L15x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_MOTE_L152RC.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 13 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4103 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc000 + + + 1 + 0x8000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x60000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + +     diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py old mode 100644 new mode 100755 index 685cea4171..20c54be0d4 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -783,6 +783,15 @@ class MTS_DRAGONFLY_F411RE(Target): os.remove(binf) os.rename(target, binf) +class MOTE_L152RC(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['STM', 'STM32L1', 'STM32L152RC'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.detect_code = ["4100"] + class DISCO_F401VC(Target): def __init__(self): Target.__init__(self) @@ -1200,6 +1209,7 @@ TARGETS = [ DISCO_L053C8(), MTS_MDOT_F405RG(), MTS_MDOT_F411RE(), + MOTE_L152RC(), MTS_DRAGONFLY_F411RE(), DISCO_F401VC(), UBLOX_C029(), # STM32F439 From 77d3559f88b77fb9410480eb08e4b06cf98b15e2 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Thu, 23 Apr 2015 12:36:07 -0500 Subject: [PATCH 142/143] Fixed and suppressed compiler warnings. --- libraries/mbed/common/pinmap_common.c | 2 +- .../targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c | 4 ++++ .../targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/common/pinmap_common.c b/libraries/mbed/common/pinmap_common.c index 736e8448fd..5aab0e6176 100644 --- a/libraries/mbed/common/pinmap_common.c +++ b/libraries/mbed/common/pinmap_common.c @@ -86,4 +86,4 @@ uint32_t pinmap_function(PinName pin, const PinMap* map) { if ((uint32_t)NC == function) // no mapping available error("pinmap not found for function"); return function; -} \ No newline at end of file +} diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c index f32942d57f..fe9fccc2be 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c @@ -45,6 +45,10 @@ * the pointers to the "function" data members. */ +#ifdef TOOLCHAIN_ARM_STD +#pragma diag_suppress 1296 +#endif + /************I2C***************/ const PinMap PinMap_I2C_SDA[] = { { P2_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c index def88c99aa..65ca064048 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c @@ -45,6 +45,10 @@ * the pointers to the "function" data members. */ +#ifdef TOOLCHAIN_ARM_STD +#pragma diag_suppress 1296 +#endif + /************I2C***************/ const PinMap PinMap_I2C_SDA[] = { { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) }, From 2d019a694b653191d1bc02e68b59c34e4be5bb98 Mon Sep 17 00:00:00 2001 From: Jun Wako Date: Fri, 24 Apr 2015 14:55:44 +0900 Subject: [PATCH 143/143] Rename back files of TARGET_K20XX --- .../TOOLCHAIN_GCC_ARM/{startup_MK20D5..s => startup_MK20D5.s} | 0 .../hal/TARGET_Freescale/TARGET_K20XX/{rtc.api.c => rtc_api.c} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/{startup_MK20D5..s => startup_MK20D5.s} (100%) rename libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/{rtc.api.c => rtc_api.c} (100%) diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc_api.c
    +

    - {% if report.failing|length > 0 %} - [FAIL] - {% else %} - [OK] - {% endif %} + + + {% if report.failing|length > 0 %} + [FAIL] + {% else %} + [OK] + {% endif %} - {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}}

    -

    Failing

    - {% with build = report.failing %} - {% include 'build_report_table.html' %} - {% endwith %} + {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}} +     + -

    Passing

    - {% with build = report.passing %} - {% include 'build_report_table.html' %} - {% endwith %} +
    +

    Failing

    + {% with build = report.failing %} + {% include 'build_report_table.html' %} + {% endwith %} + +

    Passing

    + {% with build = report.passing %} + {% include 'build_report_table.html' %} + {% endwith %} +
    diff --git a/workspace_tools/ci_templates/library_build/report.html b/workspace_tools/ci_templates/library_build/report.html index 3fcfd73094..a42c176cec 100644 --- a/workspace_tools/ci_templates/library_build/report.html +++ b/workspace_tools/ci_templates/library_build/report.html @@ -7,3 +7,57 @@ {% for report in passing_builds %} {% include 'build_report.html' %} {% endfor %} + + From cb4e13c1e35276b3c775db7e877104e91e7385d8 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Mon, 13 Apr 2015 17:07:21 -0500 Subject: [PATCH 109/143] Reorganized test_api.py to build all required libraries (RTOS, Ethernet, etc) for tests up front, before any tests are built --- workspace_tools/singletest.py | 1 + workspace_tools/test_api.py | 366 +++++++++++++++++++++------------- 2 files changed, 232 insertions(+), 135 deletions(-) diff --git a/workspace_tools/singletest.py b/workspace_tools/singletest.py index 28dc43427a..b88215a977 100644 --- a/workspace_tools/singletest.py +++ b/workspace_tools/singletest.py @@ -209,6 +209,7 @@ if __name__ == '__main__': _opts_log_file_name=opts.log_file_name, _opts_report_html_file_name=opts.report_html_file_name, _opts_report_junit_file_name=opts.report_junit_file_name, + _opts_report_jenkins_file_name=opts.report_jenkins_file_name, _test_spec=test_spec, _opts_goanna_for_mbed_sdk=opts.goanna_for_mbed_sdk, _opts_goanna_for_tests=opts.goanna_for_tests, diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index 7b3bc93d80..1b01a1da00 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -48,6 +48,7 @@ from workspace_tools.targets import TARGET_MAP from workspace_tools.test_db import BaseDBAccess from workspace_tools.build_api import build_project, build_mbed_libs, build_lib from workspace_tools.build_api import get_target_supported_toolchains +from workspace_tools.build_api import write_build_report from workspace_tools.libraries import LIBRARIES, LIBRARY_MAP from workspace_tools.toolchains import TOOLCHAIN_BIN_PATH from workspace_tools.test_exporters import ReportExporter, ResultExporterType @@ -153,6 +154,7 @@ class SingleTestRunner(object): _opts_log_file_name=None, _opts_report_html_file_name=None, _opts_report_junit_file_name=None, + _opts_report_jenkins_file_name=None, _test_spec={}, _opts_goanna_for_mbed_sdk=None, _opts_goanna_for_tests=None, @@ -205,6 +207,7 @@ class SingleTestRunner(object): self.opts_log_file_name = _opts_log_file_name self.opts_report_html_file_name = _opts_report_html_file_name self.opts_report_junit_file_name = _opts_report_junit_file_name + self.opts_report_jenkins_file_name = _opts_report_jenkins_file_name self.opts_goanna_for_mbed_sdk = _opts_goanna_for_mbed_sdk self.opts_goanna_for_tests = _opts_goanna_for_tests self.opts_shuffle_test_order = _opts_shuffle_test_order @@ -294,8 +297,17 @@ class SingleTestRunner(object): test_summary_ext = {} execute_thread_slice_lock = Lock() - def execute_thread_slice(self, q, target, toolchains, clean, test_ids): + def execute_thread_slice(self, q, target, toolchains, clean, test_ids, build_report): for toolchain in toolchains: + # Toolchain specific build successes and failures + build_report[toolchain] = { + "mbed_failure": False, + "library_failure": False, + "library_build_successes": [], + "library_build_failures": [], + "test_build_successes": [], + "test_build_failures": [] + } # print target, toolchain # Test suite properties returned to external tools like CI test_suite_properties = {} @@ -306,6 +318,7 @@ class SingleTestRunner(object): test_suite_properties['toolchain'] = toolchain test_suite_properties['shuffle_random_seed'] = self.shuffle_random_seed + # print '=== %s::%s ===' % (target, toolchain) # Let's build our test if target not in TARGET_MAP: @@ -328,9 +341,9 @@ class SingleTestRunner(object): continue except ToolException: print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building MBED libs for %s using %s'% (target, toolchain)) + build_report[toolchain]["mbed_failure"] = True #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext - q.put(target + '_'.join(toolchains)) - return + continue build_dir = join(BUILD_DIR, "test", target, toolchain) @@ -340,6 +353,7 @@ class SingleTestRunner(object): # Enumerate through all tests and shuffle test order if requested test_map_keys = sorted(TEST_MAP.keys()) + if self.opts_shuffle_test_order: random.shuffle(test_map_keys, self.shuffle_random_func) # Update database with shuffle seed f applicable @@ -358,148 +372,128 @@ class SingleTestRunner(object): self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options())) self.db_logger.disconnect(); - for test_id in test_map_keys: + valid_test_map_keys = self.get_valid_tests(test_map_keys, target, toolchain, test_ids) + skipped_test_map_keys = self.get_skipped_tests(test_map_keys, valid_test_map_keys) + + for skipped_test_id in skipped_test_map_keys: + test_suite_properties['skipped'].append(skipped_test_id) + + + # First pass through all tests and determine which libraries need to be built + libraries = set() + for test_id in valid_test_map_keys: test = TEST_MAP[test_id] - if self.opts_test_by_names and test_id not in self.opts_test_by_names.split(','): + + # Detect which lib should be added to test + # Some libs have to compiled like RTOS or ETH + for lib in LIBRARIES: + if lib['build_dir'] in test.dependencies: + libraries.add(lib['id']) + + + build_project_options = ["analyze"] if self.opts_goanna_for_tests else None + clean_project_options = True if self.opts_goanna_for_tests or clean or self.opts_clean else None + + # Build all required libraries + for lib_id in libraries: + try: + build_lib(lib_id, + T, + toolchain, + options=build_project_options, + verbose=self.opts_verbose, + clean=clean_mbed_libs_options, + jobs=self.opts_jobs) + except ToolException: + print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id)) + build_report[toolchain]["library_failure"] = True + build_report[toolchain]["library_build_failures"].append(lib_id) + #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext continue - if test_ids and test_id not in test_ids: + build_report[toolchain]["library_build_successes"].append(lib_id) + + + for test_id in valid_test_map_keys: + test = TEST_MAP[test_id] + + test_suite_properties['test.libs.%s.%s.%s'% (target, toolchain, test_id)] = ', '.join(libraries) + + # TODO: move this 2 below loops to separate function + INC_DIRS = [] + for lib_id in libraries: + if 'inc_dirs_ext' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['inc_dirs_ext']: + INC_DIRS.extend(LIBRARY_MAP[lib_id]['inc_dirs_ext']) + + MACROS = [] + for lib_id in libraries: + if 'macros' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['macros']: + MACROS.extend(LIBRARY_MAP[lib_id]['macros']) + MACROS.append('TEST_SUITE_TARGET_NAME="%s"'% target) + MACROS.append('TEST_SUITE_TEST_ID="%s"'% test_id) + test_uuid = uuid.uuid4() + MACROS.append('TEST_SUITE_UUID="%s"'% str(test_uuid)) + + project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None + try: + path = build_project(test.source_dir, + join(build_dir, test_id), + T, + toolchain, + test.dependencies, + options=build_project_options, + clean=clean_project_options, + verbose=self.opts_verbose, + name=project_name, + macros=MACROS, + inc_dirs=INC_DIRS, + jobs=self.opts_jobs) + except ToolException: + project_name_str = project_name if project_name is not None else test_id + print "DIS BE MAH ERRRRR: %s" % (str(ToolException)) + print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) + build_report[toolchain]["test_build_failures"].append(test_id) + # return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext continue - if self.opts_test_only_peripheral and not test.peripherals: - if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) - test_suite_properties['skipped'].append(test_id) + build_report[toolchain]["test_build_successes"].append(test_id) + + if self.opts_only_build_tests: + # With this option we are skipping testing phase continue - if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names.split(',')]): - # We will skip tests not forced with -p option - if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) - test_suite_properties['skipped'].append(test_id) - continue + # Test duration can be increased by global value + test_duration = test.duration + if self.opts_extend_test_timeout is not None: + test_duration += self.opts_extend_test_timeout - if self.opts_test_only_common and test.peripherals: - if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target)) - test_suite_properties['skipped'].append(test_id) - continue + # For an automated test the duration act as a timeout after + # which the test gets interrupted + test_spec = self.shape_test_request(target, path, test_id, test_duration) + test_loops = self.get_test_loop_count(test_id) - if test.automated and test.is_supported(target, toolchain): - if test.peripherals is None and self.opts_only_build_tests: - # When users are using 'build only flag' and test do not have - # specified peripherals we can allow test building by default - pass - elif self.opts_peripheral_by_names and test_id not in self.opts_peripheral_by_names.split(','): - # If we force peripheral with option -p we expect test - # to pass even if peripheral is not in MUTs file. - pass - elif not self.is_peripherals_available(target, test.peripherals): - if self.opts_verbose_skipped_tests: - if test.peripherals: - print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target)) - else: - print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target)) - test_suite_properties['skipped'].append(test_id) - continue + test_suite_properties['test.duration.%s.%s.%s'% (target, toolchain, test_id)] = test_duration + test_suite_properties['test.loops.%s.%s.%s'% (target, toolchain, test_id)] = test_loops + test_suite_properties['test.path.%s.%s.%s'% (target, toolchain, test_id)] = path - build_project_options = ["analyze"] if self.opts_goanna_for_tests else None - clean_project_options = True if self.opts_goanna_for_tests or clean or self.opts_clean else None + # read MUTs, test specification and perform tests + single_test_result, detailed_test_results = self.handle(test_spec, target, toolchain, test_loops=test_loops) - # Detect which lib should be added to test - # Some libs have to compiled like RTOS or ETH - libraries = [] - for lib in LIBRARIES: - if lib['build_dir'] in test.dependencies: - libraries.append(lib['id']) - # Build libs for test - for lib_id in libraries: - try: - build_lib(lib_id, - T, - toolchain, - options=build_project_options, - verbose=self.opts_verbose, - clean=clean_mbed_libs_options, - jobs=self.opts_jobs) - except ToolException: - print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id)) - #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext - q.put(target + '_'.join(toolchains)) - return + # Append test results to global test summary + if single_test_result is not None: + self.test_summary.append(single_test_result) - test_suite_properties['test.libs.%s.%s.%s'% (target, toolchain, test_id)] = ', '.join(libraries) - - # TODO: move this 2 below loops to separate function - INC_DIRS = [] - for lib_id in libraries: - if 'inc_dirs_ext' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['inc_dirs_ext']: - INC_DIRS.extend(LIBRARY_MAP[lib_id]['inc_dirs_ext']) - - MACROS = [] - for lib_id in libraries: - if 'macros' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['macros']: - MACROS.extend(LIBRARY_MAP[lib_id]['macros']) - MACROS.append('TEST_SUITE_TARGET_NAME="%s"'% target) - MACROS.append('TEST_SUITE_TEST_ID="%s"'% test_id) - test_uuid = uuid.uuid4() - MACROS.append('TEST_SUITE_UUID="%s"'% str(test_uuid)) - - project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None - try: - path = build_project(test.source_dir, - join(build_dir, test_id), - T, - toolchain, - test.dependencies, - options=build_project_options, - clean=clean_project_options, - verbose=self.opts_verbose, - name=project_name, - macros=MACROS, - inc_dirs=INC_DIRS, - jobs=self.opts_jobs) - except ToolException: - project_name_str = project_name if project_name is not None else test_id - print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) - # return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext - q.put(target + '_'.join(toolchains)) - return - if self.opts_only_build_tests: - # With this option we are skipping testing phase - continue - - # Test duration can be increased by global value - test_duration = test.duration - if self.opts_extend_test_timeout is not None: - test_duration += self.opts_extend_test_timeout - - # For an automated test the duration act as a timeout after - # which the test gets interrupted - test_spec = self.shape_test_request(target, path, test_id, test_duration) - test_loops = self.get_test_loop_count(test_id) - - test_suite_properties['test.duration.%s.%s.%s'% (target, toolchain, test_id)] = test_duration - test_suite_properties['test.loops.%s.%s.%s'% (target, toolchain, test_id)] = test_loops - test_suite_properties['test.path.%s.%s.%s'% (target, toolchain, test_id)] = path - - # read MUTs, test specification and perform tests - single_test_result, detailed_test_results = self.handle(test_spec, target, toolchain, test_loops=test_loops) - - # Append test results to global test summary - if single_test_result is not None: - self.test_summary.append(single_test_result) - - # Prepare extended test results data structure (it can be used to generate detailed test report) - if toolchain not in self.test_summary_ext: - self.test_summary_ext[toolchain] = {} # test_summary_ext : toolchain - if target not in self.test_summary_ext[toolchain]: - self.test_summary_ext[toolchain][target] = {} # test_summary_ext : toolchain : target - if target not in self.test_summary_ext[toolchain][target]: - self.test_summary_ext[toolchain][target][test_id] = detailed_test_results # test_summary_ext : toolchain : target : test_it + # Prepare extended test results data structure (it can be used to generate detailed test report) + if toolchain not in self.test_summary_ext: + self.test_summary_ext[toolchain] = {} # test_summary_ext : toolchain + if target not in self.test_summary_ext[toolchain]: + self.test_summary_ext[toolchain][target] = {} # test_summary_ext : toolchain : target + if target not in self.test_summary_ext[toolchain][target]: + self.test_summary_ext[toolchain][target][test_id] = detailed_test_results # test_summary_ext : toolchain : target : test_it test_suite_properties['skipped'] = ', '.join(test_suite_properties['skipped']) self.test_suite_properties_ext[target][toolchain] = test_suite_properties + # return self.test_summary, self.shuffle_random_seed, test_summary_ext, self.test_suite_properties_ext q.put(target + '_'.join(toolchains)) return @@ -514,6 +508,8 @@ class SingleTestRunner(object): if self.opts_shuffle_test_seed is not None and self.is_shuffle_seed_float(): self.shuffle_random_seed = round(float(self.opts_shuffle_test_seed), self.SHUFFLE_SEED_ROUND) + build_reports = [] + if self.opts_parallel_test_exec: ################################################################### # Experimental, parallel test execution per singletest instance. @@ -526,7 +522,9 @@ class SingleTestRunner(object): # get information about available MUTs (per target). for target, toolchains in self.test_spec['targets'].iteritems(): self.test_suite_properties_ext[target] = {} - t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids)) + cur_build_report = {} + t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids, cur_build_report)) + build_reports.append({ "target": target, "report": cur_build_report}) t.daemon = True t.start() execute_threads.append(t) @@ -538,16 +536,107 @@ class SingleTestRunner(object): for target, toolchains in self.test_spec['targets'].iteritems(): if target not in self.test_suite_properties_ext: self.test_suite_properties_ext[target] = {} - self.execute_thread_slice(q, target, toolchains, clean, test_ids) + + cur_build_report = {} + self.execute_thread_slice(q, target, toolchains, clean, test_ids, cur_build_report) + build_reports.append({ "target": target, "report": cur_build_report}) q.get() + print build_reports + + build_report = [] + + for target_build_report in build_reports: + cur_report = { + "target": target_build_report["target"], + "successes": [], + "failures": [] + } + + for toolchain in sorted(target_build_report["report"], key=target_build_report["report"].get): + print "%s - %s" % (target_build_report["target"], toolchain) + report = target_build_report["report"][toolchain] + + if report["mbed_failure"]: + cur_report["failures"].append("mbed::%s" % (toolchain)) + elif report["library_failure"]: + for library in report["library_build_failures"]: + cur_report["failures"].append("Library::%s::%s" % (library, toolchain)) + else: + cur_report["successes"].append("All Libraries::%s" % (toolchain)) + + if len(report["test_build_failures"]) > 0: + for successful_test in report["test_build_successes"]: + cur_report["successes"].append("Test::%s::%s" % (toolchain, successful_test)) + + for failed_test in report["test_build_failures"]: + cur_report["failures"].append("Test::%s::%s" % (toolchain, failed_test)) + else: + cur_report["successes"].append("All Tests::%s" % (toolchain)) + + + build_report.append(cur_report) + if self.db_logger: self.db_logger.reconnect(); if self.db_logger.is_connected(): self.db_logger.update_build_id_info(self.db_logger_build_id, _status_fk=self.db_logger.BUILD_ID_STATUS_COMPLETED) self.db_logger.disconnect(); - return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext + return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext, build_report + + def get_valid_tests(self, test_map_keys, target, toolchain, test_ids): + valid_test_map_keys = [] + + for test_id in test_map_keys: + test = TEST_MAP[test_id] + if self.opts_test_by_names and test_id not in self.opts_test_by_names.split(','): + continue + + if test_ids and test_id not in test_ids: + continue + + if self.opts_test_only_peripheral and not test.peripherals: + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) + continue + + if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names.split(',')]): + # We will skip tests not forced with -p option + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) + continue + + if self.opts_test_only_common and test.peripherals: + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target)) + continue + + if test.automated and test.is_supported(target, toolchain): + if test.peripherals is None and self.opts_only_build_tests: + # When users are using 'build only flag' and test do not have + # specified peripherals we can allow test building by default + pass + elif self.opts_peripheral_by_names and test_id not in self.opts_peripheral_by_names.split(','): + # If we force peripheral with option -p we expect test + # to pass even if peripheral is not in MUTs file. + pass + elif not self.is_peripherals_available(target, test.peripherals): + if self.opts_verbose_skipped_tests: + if test.peripherals: + print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target)) + else: + print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target)) + continue + + # The test has made it through all the filters, so add it to the valid tests list + valid_test_map_keys.append(test_id) + + return valid_test_map_keys + + def get_skipped_tests(self, all_test_map_keys, valid_test_map_keys): + # NOTE: This will not preserve order + return list(set(all_test_map_keys) - set(valid_test_map_keys)) def generate_test_summary_by_target(self, test_summary, shuffle_seed=None): """ Prints well-formed summary with results (SQL table like) @@ -1314,7 +1403,7 @@ def singletest_in_cli_mode(single_test): """ start = time() # Execute tests depending on options and filter applied - test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext = single_test.execute() + test_summary, shuffle_seed, test_summary_ext, test_suite_properties_ext, build_report = single_test.execute() elapsed_time = time() - start # Human readable summary @@ -1333,9 +1422,12 @@ def singletest_in_cli_mode(single_test): report_exporter = ReportExporter(ResultExporterType.HTML) report_exporter.report_to_file(test_summary_ext, single_test.opts_report_html_file_name, test_suite_properties=test_suite_properties_ext) if single_test.opts_report_junit_file_name: - # Export results in form of HTML report to separate file + # Export results in form of JUnit XML report to separate file report_exporter = ReportExporter(ResultExporterType.JUNIT) report_exporter.report_to_file(test_summary_ext, single_test.opts_report_junit_file_name, test_suite_properties=test_suite_properties_ext) + if single_test.opts_report_jenkins_file_name: + # Export build results as Jenkins XML report ti sparate file + write_build_report(build_report, single_test.opts_report_jenkins_file_name) class TestLogger(): @@ -1706,6 +1798,10 @@ def get_default_test_options_parser(): dest='report_junit_file_name', help='You can log test suite results in form of JUnit compliant XML report') + parser.add_option("", "--report-jenkins", + dest="report_jenkins_file_name", + help="Output the build results to an xml file that is readable by Jenkins") + parser.add_option('', '--verbose-skipped', dest='verbose_skipped_tests', default=False, From a574e1f27ecc457cfa8d4e287ca9438f8454227e Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Wed, 1 Apr 2015 13:15:15 -0500 Subject: [PATCH 110/143] Broke apart some template stuff, added tests-build report --- workspace_tools/build_api.py | 8 +- .../library_build/build_report.html | 6 +- .../ci_templates/library_build/report.html | 62 ++----------- workspace_tools/ci_templates/scripts.js | 53 +++++++++++ .../tests_build/build_report.html | 26 ++++++ .../tests_build/build_report_table.html | 12 +++ .../ci_templates/tests_build/report.html | 11 +++ workspace_tools/test_api.py | 88 +++++++++++-------- 8 files changed, 165 insertions(+), 101 deletions(-) create mode 100644 workspace_tools/ci_templates/scripts.js create mode 100644 workspace_tools/ci_templates/tests_build/build_report.html create mode 100644 workspace_tools/ci_templates/tests_build/build_report_table.html create mode 100644 workspace_tools/ci_templates/tests_build/report.html diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 76875426f4..40e378ee9d 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -532,7 +532,7 @@ def print_build_results(result_list, build_name): result += "\n" return result -def write_build_report(build_report, filename): +def write_build_report(build_report, template_filename, filename): build_report_failing = [] build_report_passing = [] @@ -541,7 +541,7 @@ def write_build_report(build_report, filename): build_report_failing.append(report) else: build_report_passing.append(report) - + '''build_report_failing = [{ "target": "K64F", "passing": [ @@ -592,8 +592,8 @@ def write_build_report(build_report, filename): }]''' env = Environment(extensions=['jinja2.ext.with_']) - env.loader = FileSystemLoader('ci_templates/library_build') - template = env.get_template('report.html') + env.loader = FileSystemLoader('ci_templates') + template = env.get_template(template_filename) with open(filename, 'w+') as f: f.write(template.render(failing_builds=build_report_failing, passing_builds=build_report_passing)) diff --git a/workspace_tools/ci_templates/library_build/build_report.html b/workspace_tools/ci_templates/library_build/build_report.html index f3be3f74aa..24283125a3 100644 --- a/workspace_tools/ci_templates/library_build/build_report.html +++ b/workspace_tools/ci_templates/library_build/build_report.html @@ -5,7 +5,7 @@ {% if report.failing|length > 0 %} [FAIL] {% else %} - [OK] + [PASS] {% endif %} {{report.target}} - Passing: {{report.passing|length}}, Failing: {{report.failing|length}} @@ -15,12 +15,12 @@

    Failing

    {% with build = report.failing %} - {% include 'build_report_table.html' %} + {% include 'library_build/build_report_table.html' %} {% endwith %}

    Passing

    {% with build = report.passing %} - {% include 'build_report_table.html' %} + {% include 'library_build/build_report_table.html' %} {% endwith %}