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Merge tag 'mbed-os-5.15.7' into feature-wisun 

This is the mbed-os-5.15.7 release. For a full list of changes please refer to the release notes.

* tag 'mbed-os-5.15.7': (160 commits)
  Update Mbed version block
  Improve WisunInterface set_network_size docs
  Add integer overflow check to the malloc wrappers
  targets:evkbimxrt1050: Adjust the SEMC re-order rules
  targets:RT1050: Fix the flash erase and program issue for qspi nor flash.
  targets:RT1050: Fix the low speed switch issue
  targets:clock: Update the coreclock value
  targets: clock: change default core clock to 528M
  targets:uart: Add uart_3 support
  targets:lpspi: Update the lpspi driver and api
  targets:MIMXRT1050: Add LPSPI4 support
  targets:MIMXRT1050: Update link file for application
  targets:MIMXRT1050: Add QSPI Flash FLASHIAP support
  targets:TARGET_IMX: Fix the memset issue for FLASHIAP
  targets:TARGET_IMX: Fix the flash init risk
  targets:MIMXRT1050: Add QSPI Flash boot support
  MIMXRT1050: Update for deep sleep latency
  MXRT1050: Add bootloader support
  MIMXRT1050: Enable FlashIAP support
  MIMXRT1050: Reduce NOR size used by mbed-os
  ...
pull/14526/head
Arto Kinnunen 2021-04-08 16:39:12 +03:00
parent 62b57abd67 0be7685a27
commit e00a1febd1
278 changed files with 103096 additions and 1989 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.travis.yml
View File

@ -21,7 +21,7 @@ dist: xenial
env:
global:
- deps_url="https://mbed-os-ci.s3-eu-west-1.amazonaws.com/jenkins-ci/deps"
- deps_url="https://mbed-os-ci-public.s3-eu-west-1.amazonaws.com/jenkins-ci/deps"
- deps_dir="${HOME}/.cache/deps"
cache:
@ -77,7 +77,7 @@ matrix:
env: NAME=astyle
install:
- >-
curl -L0 https://mbed-os.s3-eu-west-1.amazonaws.com/builds/deps/astyle_3.1_linux.tar.gz --output astyle.tar.gz;
curl -L0 https://mbed-os-ci-public.s3-eu-west-1.amazonaws.com/jenkins-ci/deps/astyle_3.1_linux.tar.gz --output astyle.tar.gz;
mkdir -p BUILD && tar xf astyle.tar.gz -C BUILD;
cd BUILD/astyle/build/gcc;
make;

4
LICENSE.md
View File

@ -13,7 +13,9 @@ Folders containing files under different permissive license than Apache 2.0 are
- [features/lorawan](./features/lorawan) - Revised BSD
- [features/lwipstack](./features/lwipstack) - BSD-style, MIT-style
- [features/nanostack/sal-stack-nanostack](./features/nanostack/sal-stack-nanostack) - BSD-3-Clause
- [features/storage](./features/storage) - BSD-style, MIT
- [features/storage/blockdevice](./features/storage/blockdevice) - Apache 2.0, MIT
- [features/storage/filesystem/littlefs](./features/storage/filesystem/littlefs) - [BSD-3-Clause](https://github.com/ARMmbed/littlefs/blob/master/LICENSE.md)
- [features/storage/filesystem/fat/ChaN](.features/storage/filesystem/fat/ChaN) - BSD-style, 1 clause, [Copyright ChaN](http://www.elm-chan.org/fsw/ff/doc/appnote.html)
- [features/netsocket/emac-drivers](./features/netsocket/emac-drivers) - BSD-style
- [features/frameworks/unity/unity](./features/frameworks/unity/unity) - MIT
- [features/unsupported](./features/unsupported) - MIT-style, BSD-style

2
TESTS/netsocket/udp/udp_tests.h
View File

@ -43,7 +43,7 @@ namespace udp_global {
#ifdef MBED_GREENTEA_TEST_UDPSOCKET_TIMEOUT_S
static const int TESTS_TIMEOUT = MBED_GREENTEA_TEST_UDPSOCKET_TIMEOUT_S;
#else
static const int TESTS_TIMEOUT = 480;
static const int TESTS_TIMEOUT = (20 * 60);
#endif
static const int MAX_SEND_SIZE_IPV4 = 536;

8
components/TARGET_PSA/TARGET_MBED_SPM/COMPONENT_SPE/psa_setup.c
View File

@ -1006,7 +1006,7 @@ void smoke_tests_part1_init(spm_partition_t *partition)
/****************** SPM DB initialization *************************************/
spm_partition_t g_partitions[] = {
/* ATTEST_SRV */
/* ATTEST_SRV */
{
.partition_id = ATTEST_SRV_ID,
.thread_id = 0,
@ -1018,7 +1018,7 @@ spm_partition_t g_partitions[] = {
.irq_mapper = NULL,
},
/* CRYPTO_SRV */
/* CRYPTO_SRV */
{
.partition_id = CRYPTO_SRV_ID,
.thread_id = 0,
@ -1030,7 +1030,7 @@ spm_partition_t g_partitions[] = {
.irq_mapper = NULL,
},
/* PLATFORM */
/* PLATFORM */
{
.partition_id = PLATFORM_ID,
.thread_id = 0,
@ -1042,7 +1042,7 @@ spm_partition_t g_partitions[] = {
.irq_mapper = NULL,
},
/* ITS */
/* ITS */
{
.partition_id = ITS_ID,
.thread_id = 0,

138
components/wifi/esp8266-driver/ESP8266/ESP8266.cpp
View File

@ -58,6 +58,7 @@ ESP8266::ESP8266(PinName tx, PinName rx, bool debug, PinName rts, PinName cts)
_error(false),
_busy(false),
_reset_done(false),
_sock_sending_id(-1),
_conn_status(NSAPI_STATUS_DISCONNECTED)
{
_serial.set_baud(MBED_CONF_ESP8266_SERIAL_BAUDRATE);
@ -89,6 +90,10 @@ ESP8266::ESP8266(PinName tx, PinName rx, bool debug, PinName rts, PinName cts)
_parser.oob("busy ", callback(this, &ESP8266::_oob_busy));
// NOTE: documentation v3.0 says '+CIPRECVDATA:<data_len>,' but it's not how the FW responds...
_parser.oob("+CIPRECVDATA,", callback(this, &ESP8266::_oob_tcp_data_hdlr));
// Register 'SEND OK'/'SEND FAIL' oobs here. Don't get involved in oob management with send status
// because ESP8266 modem possibly doesn't reply these packets on error case.
_parser.oob("SEND OK", callback(this, &ESP8266::_oob_send_ok_received));
_parser.oob("SEND FAIL", callback(this, &ESP8266::_oob_send_fail_received));
for (int i = 0; i < SOCKET_COUNT; i++) {
_sock_i[i].open = false;
@ -96,6 +101,7 @@ ESP8266::ESP8266(PinName tx, PinName rx, bool debug, PinName rts, PinName cts)
_sock_i[i].tcp_data = NULL;
_sock_i[i].tcp_data_avbl = 0;
_sock_i[i].tcp_data_rcvd = 0;
_sock_i[i].send_fail = false;
}
_scan_r.res = NULL;
@ -288,6 +294,7 @@ bool ESP8266::reset(void)
tr_debug("reset(): Done: %s.", done ? "OK" : "FAIL");
_clear_socket_packets(ESP8266_ALL_SOCKET_IDS);
_sock_sending_id = -1;
set_timeout();
_smutex.unlock();
@ -511,9 +518,17 @@ nsapi_error_t ESP8266::open_udp(int id, const char *addr, int port, int local_po
// process OOB so that _sock_i reflects the correct state of the socket
_process_oob(ESP8266_SEND_TIMEOUT, true);
if (id >= SOCKET_COUNT || _sock_i[id].open) {
// Previous close() can fail with busy in sending. Usually, user will ignore the close()
// error code and cause 'spurious close', in which case user has closed the socket but ESP8266 modem
// hasn't yet. Because we don't know how long ESP8266 modem will trap in busy, enlarge retry count
// or timeout in close() isn't a nice way. Here, we actively re-call close() in open() to let the modem
// close the socket. User can re-try open() on failure. Without this active close(), open() can fail forever
// with previous 'spurious close', unless peer closes the socket and so ESP8266 modem closes it accordingly.
if (id >= SOCKET_COUNT) {
_smutex.unlock();
return NSAPI_ERROR_PARAMETER;
} else if (_sock_i[id].open) {
close(id);
}
for (int i = 0; i < 2; i++) {
@ -562,9 +577,12 @@ nsapi_error_t ESP8266::open_tcp(int id, const char *addr, int port, int keepaliv
// process OOB so that _sock_i reflects the correct state of the socket
_process_oob(ESP8266_SEND_TIMEOUT, true);
if (id >= SOCKET_COUNT || _sock_i[id].open) {
// See the reason above with close()
if (id >= SOCKET_COUNT) {
_smutex.unlock();
return NSAPI_ERROR_PARAMETER;
} else if (_sock_i[id].open) {
close(id);
}
for (int i = 0; i < 2; i++) {
@ -612,9 +630,24 @@ bool ESP8266::dns_lookup(const char *name, char *ip)
return done;
}
nsapi_error_t ESP8266::send(int id, const void *data, uint32_t amount)
nsapi_size_or_error_t ESP8266::send(int id, const void *data, uint32_t amount)
{
if (_sock_i[id].proto == NSAPI_TCP) {
if (_sock_sending_id >= 0 && _sock_sending_id < SOCKET_COUNT) {
if (!_sock_i[id].send_fail) {
tr_debug("send(): Previous packet (socket %d) was not yet ACK-ed with SEND OK.", _sock_sending_id);
return NSAPI_ERROR_WOULD_BLOCK;
} else {
tr_debug("send(): Previous packet (socket %d) failed.", id);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
}
nsapi_error_t ret = NSAPI_ERROR_DEVICE_ERROR;
int bytes_confirmed = 0;
constexpr unsigned int send_ack_retries = 3;
// +CIPSEND supports up to 2048 bytes at a time
// Data stream can be truncated
if (amount > 2048 && _sock_i[id].proto == NSAPI_TCP) {
@ -626,6 +659,10 @@ nsapi_error_t ESP8266::send(int id, const void *data, uint32_t amount)
}
_smutex.lock();
// Mark this socket is sending. We allow only one actively sending socket because:
// 1. ESP8266 AT packets 'SEND OK'/'SEND FAIL' are not associated with socket ID. No way to tell them.
// 2. In original implementation, ESP8266::send() is synchronous, which implies only one actively sending socket.
_sock_sending_id = id;
set_timeout(ESP8266_SEND_TIMEOUT);
_busy = false;
_error = false;
@ -635,37 +672,70 @@ nsapi_error_t ESP8266::send(int id, const void *data, uint32_t amount)
}
if (!_parser.recv(">")) {
// This means ESP8266 hasn't even started to receive data
tr_debug("send(): Didn't get \">\"");
ret = NSAPI_ERROR_WOULD_BLOCK;
if (_sock_i[id].proto == NSAPI_TCP) {
ret = NSAPI_ERROR_WOULD_BLOCK; // Not necessarily critical error.
} else if (_sock_i[id].proto == NSAPI_UDP) {
ret = NSAPI_ERROR_NO_MEMORY;
}
goto END;
}
if (_parser.write((char *)data, (int)amount) >= 0 && _parser.recv("SEND OK")) {
ret = NSAPI_ERROR_OK;
if (_parser.write((char *)data, (int)amount) < 0) {
tr_debug("send(): Failed to write serial data");
// Serial is not working, serious error, reset needed.
ret = NSAPI_ERROR_DEVICE_ERROR;
goto END;
}
// The "Recv X bytes" is not documented.
if (!_parser.recv("Recv %d bytes", &bytes_confirmed)) {
tr_debug("send(): Bytes not confirmed.");
if (_sock_i[id].proto == NSAPI_TCP) {
ret = NSAPI_ERROR_WOULD_BLOCK;
} else if (_sock_i[id].proto == NSAPI_UDP) {
ret = NSAPI_ERROR_NO_MEMORY;
}
} else if (bytes_confirmed != amount && _sock_i[id].proto == NSAPI_UDP) {
tr_debug("send(): Error: confirmed %d bytes, but expected %d.", bytes_confirmed, amount);
ret = NSAPI_ERROR_DEVICE_ERROR;
} else {
// TCP can accept partial writes (if they ever happen)
ret = bytes_confirmed;
}
END:
_process_oob(ESP8266_RECV_TIMEOUT, true); // Drain USART receive register to avoid data overrun
// error hierarchy, from low to high
if (_busy) {
// NOTE: We cannot return NSAPI_ERROR_WOULD_BLOCK when "Recv X bytes" has reached, otherwise duplicate data send.
if (_busy && ret < 0) {
ret = NSAPI_ERROR_WOULD_BLOCK;
tr_debug("send(): Modem busy. ");
}
if (ret == NSAPI_ERROR_DEVICE_ERROR) {
ret = NSAPI_ERROR_WOULD_BLOCK;
tr_debug("send(): Send failed.");
tr_debug("send(): Modem busy.");
}
if (_error) {
// FIXME: Not sure clear or not of _error. See it as device error and it can recover only via reset?
_sock_sending_id = -1;
ret = NSAPI_ERROR_CONNECTION_LOST;
tr_debug("send(): Connection disrupted.");
}
if (!_sock_i[id].open && ret != NSAPI_ERROR_OK) {
if (_sock_i[id].send_fail) {
_sock_sending_id = -1;
if (_sock_i[id].proto == NSAPI_TCP) {
ret = NSAPI_ERROR_DEVICE_ERROR;
} else {
ret = NSAPI_ERROR_NO_MEMORY;
}
tr_debug("send(): SEND FAIL received.");
}
if (!_sock_i[id].open && ret < 0) {
_sock_sending_id = -1;
ret = NSAPI_ERROR_CONNECTION_LOST;
tr_debug("send(): Socket closed abruptly.");
tr_debug("send(): Socket %d closed abruptly.", id);
}
set_timeout();
@ -938,6 +1008,14 @@ void ESP8266::_clear_socket_packets(int id)
}
}
void ESP8266::_clear_socket_sending(int id)
{
if (id == _sock_sending_id) {
_sock_sending_id = -1;
}
_sock_i[id].send_fail = false;
}
bool ESP8266::close(int id)
{
//May take a second try if device is busy
@ -949,20 +1027,27 @@ bool ESP8266::close(int id)
_closed = false;
_sock_i[id].open = false;
_clear_socket_packets(id);
// Closed, so this socket escapes from SEND FAIL status.
_clear_socket_sending(id);
_smutex.unlock();
// ESP8266 has a habit that it might close a socket on its own.
tr_debug("close(%d): socket close OK with UNLINK ERROR", id);
return true;
}
} else {
// _sock_i[id].open set to false with an OOB
_clear_socket_packets(id);
// Closed, so this socket escapes from SEND FAIL status
_clear_socket_sending(id);
_smutex.unlock();
tr_debug("close(%d): socket close OK with AT+CIPCLOSE OK", id);
return true;
}
}
_smutex.unlock();
}
tr_debug("close(%d): socket close FAIL'ed (spurious close)", id);
return false;
}
@ -1140,6 +1225,8 @@ void ESP8266::_oob_socket0_closed()
{
static const int id = 0;
_sock_i[id].open = false;
// Closed, so this socket escapes from SEND FAIL status
_clear_socket_sending(id);
tr_debug("_oob_socket0_closed(): Socket %d closed.", id);
}
@ -1147,6 +1234,8 @@ void ESP8266::_oob_socket1_closed()
{
static const int id = 1;
_sock_i[id].open = false;
// Closed, so this socket escapes from SEND FAIL status
_clear_socket_sending(id);
tr_debug("_oob_socket1_closed(): Socket %d closed.", id);
}
@ -1154,6 +1243,7 @@ void ESP8266::_oob_socket2_closed()
{
static const int id = 2;
_sock_i[id].open = false;
_clear_socket_sending(id);
tr_debug("_oob_socket2_closed(): Socket %d closed.", id);
}
@ -1161,6 +1251,7 @@ void ESP8266::_oob_socket3_closed()
{
static const int id = 3;
_sock_i[id].open = false;
_clear_socket_sending(id);
tr_debug("_oob_socket3_closed(): %d closed.", id);
}
@ -1168,6 +1259,8 @@ void ESP8266::_oob_socket4_closed()
{
static const int id = 4;
_sock_i[id].open = false;
// Closed, so this socket escapes from SEND FAIL status
_clear_socket_sending(id);
tr_debug("_oob_socket0_closed(): Socket %d closed.", id);
}
@ -1205,6 +1298,21 @@ void ESP8266::_oob_connection_status()
_conn_stat_cb();
}
void ESP8266::_oob_send_ok_received()
{
tr_debug("_oob_send_ok_received called for socket %d", _sock_sending_id);
_sock_sending_id = -1;
}
void ESP8266::_oob_send_fail_received()
{
tr_debug("_oob_send_fail_received called for socket %d", _sock_sending_id);
if (_sock_sending_id >= 0 && _sock_sending_id < SOCKET_COUNT) {
_sock_i[_sock_sending_id].send_fail = true;
}
_sock_sending_id = -1;
}
int8_t ESP8266::default_wifi_mode()
{
int8_t mode;

11
components/wifi/esp8266-driver/ESP8266/ESP8266.h
View File

@ -255,10 +255,10 @@ public:
*
* @param id id of socket to send to
* @param data data to be sent
* @param amount amount of data to be sent - max 1024
* @return NSAPI_ERROR_OK in success, negative error code in failure
* @param amount amount of data to be sent - max 2048
* @return number of bytes on success, negative error code in failure
*/
nsapi_error_t send(int id, const void *data, uint32_t amount);
nsapi_size_or_error_t send(int id, const void *data, uint32_t amount);
/**
* Receives datagram from an open UDP socket
@ -444,6 +444,7 @@ private:
// data follows
} *_packets, * *_packets_end;
void _clear_socket_packets(int id);
void _clear_socket_sending(int id);
int _sock_active_id;
// Memory statistics
@ -469,6 +470,8 @@ private:
void _oob_tcp_data_hdlr();
void _oob_ready();
void _oob_scan_results();
void _oob_send_ok_received();
void _oob_send_fail_received();
// OOB state variables
int _connect_error;
@ -479,6 +482,7 @@ private:
bool _error;
bool _busy;
bool _reset_done;
int _sock_sending_id;
// Modem's address info
char _ip_buffer[16];
@ -493,6 +497,7 @@ private:
char *tcp_data;
int32_t tcp_data_avbl; // Data waiting on modem
int32_t tcp_data_rcvd;
bool send_fail; // Received 'SEND FAIL'. Expect user will close the socket.
};
struct _sock_info _sock_i[SOCKET_COUNT];

27
components/wifi/esp8266-driver/ESP8266Interface.cpp
View File

@ -775,8 +775,27 @@ int ESP8266Interface::socket_close(void *handle)
return NSAPI_ERROR_NO_SOCKET;
}
if (socket->connected && !_esp.close(socket->id)) {
err = NSAPI_ERROR_DEVICE_ERROR;
// With send(...) changing to non-block, modem can be busy in
// sending previous data and 'busy' the current 'AT+CIPCLOSE'
// command. In blocking mode, add retries to avoid spurious
// close to some degree. This is required to pass GT netsocket-tcp/
// netsocket-tls tests which expect close(...) to be OK.
if (socket->connected) {
if (_if_blocking) {
err = NSAPI_ERROR_DEVICE_ERROR;
for (int i = 0; i < 10; i ++) {
if (_esp.close(socket->id)) {
err = 0;
break;
} else {
rtos::ThisThread::sleep_for(1000);
}
}
} else {
if (!_esp.close(socket->id)) {
err = NSAPI_ERROR_WOULD_BLOCK;
}
}
}
_cbs[socket->id].callback = NULL;
@ -849,7 +868,7 @@ int ESP8266Interface::socket_accept(void *server, void **socket, SocketAddress *
int ESP8266Interface::socket_send(void *handle, const void *data, unsigned size)
{
nsapi_error_t status;
nsapi_size_or_error_t status;
struct esp8266_socket *socket = (struct esp8266_socket *)handle;
uint8_t expect_false = false;
@ -881,7 +900,7 @@ int ESP8266Interface::socket_send(void *handle, const void *data, unsigned size)
status = NSAPI_ERROR_DEVICE_ERROR;
}
return status != NSAPI_ERROR_OK ? status : size;
return status;
}
int ESP8266Interface::socket_recv(void *handle, void *data, unsigned size)

4
features/frameworks/mbed-coap/CHANGELOG.md
View File

@ -1,5 +1,9 @@
# Change Log
## [v5.1.8](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.8)
- Fix to blockwise code. Now uses block size received in packet, not block size defined in code.
## [v5.1.7](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.7)
- Removed comparison of IP addresses when validating message resending. This avoids unnessary network errors due to load balancers causing frequent IP address changes.

13
features/frameworks/mbed-coap/source/sn_coap_protocol.c
View File

@ -59,7 +59,7 @@ static bool sn_coap_protocol_update_duplicate_package_data_all(
#if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* If Message blockwising is not enabled, this part of code will not be compiled */
static void sn_coap_protocol_linked_list_blockwise_msg_remove(struct coap_s *handle, coap_blockwise_msg_s *removed_msg_ptr);
static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *handle, sn_nsdl_addr_s *addr_ptr, uint16_t payload_len, uint8_t *payload_ptr, uint8_t *token_ptr, uint8_t token_len, uint32_t block_number, uint32_t size1);
static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *handle, sn_nsdl_addr_s *addr_ptr, uint16_t payload_len, uint8_t *payload_ptr, uint8_t *token_ptr, uint8_t token_len, uint32_t block_number, uint16_t block_size, uint32_t size1);
static uint8_t *sn_coap_protocol_linked_list_blockwise_payload_search(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, uint16_t *payload_length, const uint8_t *token_ptr, uint8_t token_len);
static coap_blockwise_payload_s *sn_coap_protocol_linked_list_blockwise_search(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, const uint8_t *token_ptr, uint8_t token_len);
static bool sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, const uint8_t *token_ptr, uint8_t token_len, uint32_t block_number);
@ -1253,6 +1253,7 @@ static void sn_coap_protocol_linked_list_blockwise_msg_remove(struct coap_s *han
* \param *token_ptr is pointer to stored token
* \param token_len is length of the stored token
* \param block_number Block number to be stored
* \param block_size Size on block to be stored
* \param size1 Size of the whole incoming message
*****************************************************************************/
@ -1262,6 +1263,7 @@ static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *
uint8_t *token_ptr,
uint8_t token_len,
uint32_t block_number,
uint16_t block_size,
uint32_t size1)
{
if (!addr_ptr || !payload_len || !payload_ptr) {
@ -1280,7 +1282,7 @@ static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *
coap_blockwise_payload_s *stored_blockwise_payload_ptr = sn_coap_protocol_linked_list_blockwise_search(handle, addr_ptr, token_ptr, token_len);
if (stored_blockwise_payload_ptr && stored_blockwise_payload_ptr->use_size1) {
memcpy(stored_blockwise_payload_ptr->payload_ptr + (block_number * handle->sn_coap_block_data_size), payload_ptr, payload_len);
memcpy(stored_blockwise_payload_ptr->payload_ptr + (block_number * block_size), payload_ptr, payload_len);
} else if (stored_blockwise_payload_ptr) {
uint16_t new_len = stored_blockwise_payload_ptr->payload_len + payload_len;
tr_debug("sn_coap_protocol_linked_list_blockwise_payload_store - reallocate from %d to %d", stored_blockwise_payload_ptr->payload_len, new_len);
@ -1967,6 +1969,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
// Store only in success case
if (src_coap_blockwise_ack_msg_ptr->msg_code != COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_INCOMPLETE &&
src_coap_blockwise_ack_msg_ptr->msg_code != COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE) {
uint16_t block_size = 1u << ((received_coap_msg_ptr->options_list_ptr->block1 & 0x07) + 4);
sn_coap_protocol_linked_list_blockwise_payload_store(handle,
src_addr_ptr,
received_coap_msg_ptr->payload_len,
@ -1974,6 +1977,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
received_coap_msg_ptr->token_ptr,
received_coap_msg_ptr->token_len,
block_number,
block_size,
received_coap_msg_ptr->options_list_ptr->size1);
}
@ -1989,7 +1993,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
/* * * This is the last block when whole Blockwise payload from received * * */
/* * * blockwise messages is gathered and returned to User * * */
uint16_t block_size = 1u << ((received_coap_msg_ptr->options_list_ptr->block1 & 0x07) + 4);
sn_coap_protocol_linked_list_blockwise_payload_store(handle,
src_addr_ptr,
received_coap_msg_ptr->payload_len,
@ -1997,6 +2001,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
received_coap_msg_ptr->token_ptr,
received_coap_msg_ptr->token_len,
block_number,
block_size,
received_coap_msg_ptr->options_list_ptr->size1);
if (!sn_coap_handle_last_blockwise(handle, src_addr_ptr, received_coap_msg_ptr)) {
@ -2018,6 +2023,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
uint32_t block_number = 0;
/* Store blockwise payload to Linked list */
//todo: add block number to stored values - just to make sure all packets are in order
uint16_t block_size = 1u << ((received_coap_msg_ptr->options_list_ptr->block1 & 0x07) + 4);
sn_coap_protocol_linked_list_blockwise_payload_store(handle,
src_addr_ptr,
received_coap_msg_ptr->payload_len,
@ -2025,6 +2031,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
received_coap_msg_ptr->token_ptr,
received_coap_msg_ptr->token_len,
received_coap_msg_ptr->options_list_ptr->block2 >> 4,
block_size,
received_coap_msg_ptr->options_list_ptr->size1);
/* If not last block (more value is set) */
if (received_coap_msg_ptr->options_list_ptr->block2 & 0x08) {

22
features/nanostack/coap-service/source/coap_connection_handler.c
View File

@ -66,7 +66,9 @@ static NS_LIST_DEFINE(socket_list, internal_socket_t, link);
static uint8_t max_handshakes = MAX_ONGOING_HANDSHAKES;
static uint8_t max_sessions = MAX_SECURE_SESSION_COUNT;
#ifdef COAP_SECURITY_AVAILABLE
static void timer_cb(void *param);
#endif
static void recv_sckt_msg(void *cb_res);
#ifdef COAP_SECURITY_AVAILABLE
@ -102,10 +104,13 @@ typedef struct secure_session {
} secure_session_t;
static NS_LIST_DEFINE(secure_session_list, secure_session_t, link);
#ifdef COAP_SECURITY_AVAILABLE
static int secure_session_sendto(int8_t socket_id, void *handle, const void *buf, size_t len);
static int secure_session_recvfrom(int8_t socket_id, unsigned char *buf, size_t len);
static void start_timer(int8_t timer_id, uint32_t int_ms, uint32_t fin_ms);
static int timer_status(int8_t timer_id);
#endif //COAP_SECURITY_AVAILABLE
static secure_session_t *secure_session_find_by_timer_id(int8_t timer_id)
{
@ -119,6 +124,7 @@ static secure_session_t *secure_session_find_by_timer_id(int8_t timer_id)
return this;
}
#ifdef COAP_SECURITY_AVAILABLE
static bool is_secure_session_valid(secure_session_t *session)
{
ns_list_foreach(secure_session_t, cur_ptr, &secure_session_list) {
@ -128,6 +134,7 @@ static bool is_secure_session_valid(secure_session_t *session)
}
return false;
}
#endif
static void secure_session_delete(secure_session_t *this)
{
@ -161,6 +168,7 @@ static int8_t virtual_socket_id_allocate()
static secure_session_t *secure_session_create(internal_socket_t *parent, const uint8_t *address_ptr, uint16_t port, SecureConnectionMode secure_mode)
{
(void) secure_mode;
uint8_t handshakes = 0;
if (!address_ptr) {
return NULL;
@ -237,7 +245,9 @@ static void clear_secure_sessions(internal_socket_t *this)
if (this) {
ns_list_foreach_safe(secure_session_t, cur_ptr, &secure_session_list) {
if (cur_ptr->parent == this) {
#ifdef COAP_SECURITY_AVAILABLE
coap_security_send_close_alert(cur_ptr->sec_handler);
#endif //COAP_SECURITY_AVAILABLE
secure_session_delete(cur_ptr);
}
}
@ -430,6 +440,7 @@ static int send_to_real_socket(int8_t socket_id, const ns_address_t *address, co
return socket_sendmsg(socket_id, &msghdr, 0);
}
#ifdef COAP_SECURITY_AVAILABLE
static int secure_session_sendto(int8_t socket_id, void *handle, const void *buf, size_t len)
{
secure_session_t *session = handle;
@ -462,7 +473,9 @@ static int secure_session_sendto(int8_t socket_id, void *handle, const void *buf
}
return len;
}
#endif //COAP_SECURITY_AVAILABLE
#ifdef COAP_SECURITY_AVAILABLE
static int secure_session_recvfrom(int8_t socket_id, unsigned char *buf, size_t len)
{
(void)len;
@ -477,6 +490,7 @@ static int secure_session_recvfrom(int8_t socket_id, unsigned char *buf, size_t
}
return MBEDTLS_ERR_SSL_WANT_READ;
}
#endif //COAP_SECURITY_AVAILABLE
/**
* Callback timer. Maybe called in interrupt context
@ -484,6 +498,7 @@ static int secure_session_recvfrom(int8_t socket_id, unsigned char *buf, size_t
* TODO - might be better to use an event timer in conjunction with
* CoAP tasklet
*/
#ifdef COAP_SECURITY_AVAILABLE
static void timer_cb(void *param)
{
secure_session_t *sec = param;
@ -515,7 +530,9 @@ static void timer_cb(void *param)
}
}
}
#endif
#ifdef COAP_SECURITY_AVAILABLE
static void start_timer(int8_t timer_id, uint32_t int_ms, uint32_t fin_ms)
{
secure_session_t *sec = secure_session_find_by_timer_id(timer_id);
@ -538,7 +555,9 @@ static void start_timer(int8_t timer_id, uint32_t int_ms, uint32_t fin_ms)
}
}
}
#endif //COAP_SECURITY_AVAILABLE
#ifdef COAP_SECURITY_AVAILABLE
static int timer_status(int8_t timer_id)
{
secure_session_t *sec = secure_session_find_by_timer_id(timer_id);
@ -547,6 +566,7 @@ static int timer_status(int8_t timer_id)
}
return TIMER_STATE_CANCELLED;
}
#endif //COAP_SECURITY_AVAILABLE
static int read_data(socket_callback_t *sckt_data, internal_socket_t *sock, ns_address_t *src_address, uint8_t dst_address[static 16])
{
@ -872,7 +892,9 @@ void connection_handler_close_secure_connection(coap_conn_handler_t *handler, ui
if (handler->socket && handler->socket->is_secure) {
secure_session_t *session = secure_session_find(handler->socket, destination_addr_ptr, port);
if (session) {
#ifdef COAP_SECURITY_AVAILABLE
coap_security_send_close_alert(session->sec_handler);
#endif //COAP_SECURITY_AVAILABLE
session->session_state = SECURE_SESSION_CLOSED;
session->last_contact_time = coap_service_get_internal_timer_ticks();
}

1
features/nanostack/coap-service/source/include/coap_security_handler.h
View File

@ -23,6 +23,7 @@
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
// cppcheck-suppress preprocessorErrorDirective
#include MBEDTLS_CONFIG_FILE
#endif

26
features/nanostack/mbed-mesh-api/mbed-mesh-api/WisunBorderRouter.h
View File

@ -272,19 +272,6 @@ public:
* */
mesh_error_t get_radius_shared_secret(uint16_t *shared_secret_len, uint8_t *shared_secret);
/**
* \brief Set DNS query result to Nanostack cache.
*
* Function sets DNS query result to Nanostack cache to get distributed to the devices in the Wi-SUN network.
* Function must be called for a running Wi-SUN Border Router instance.
*
* \param address resolved address of domain_name.
* \param domain_name name of the domain. Must be non-NULL.
* \return MESH_ERROR_NONE on success.
* \return error value in case of failure.
* */
mesh_error_t set_dns_query_result(SocketAddress *address, char *domain_name);
/**
* \brief Set Wi-SUN RADIUS timing parameters.
*
@ -320,6 +307,19 @@ public:
* */
mesh_error_t validate_radius_timing(ws_br_radius_timing_t *timing);
/**
* \brief Set DNS query result to Nanostack cache.
*
* Function sets DNS query result to Nanostack cache to get distributed to the devices in the Wi-SUN network.
* Function must be called for a running Wi-SUN Border Router instance.
*
* \param address resolved address of domain_name.
* \param domain_name name of the domain. Must be non-NULL.
* \return MESH_ERROR_NONE on success.
* \return error value in case of failure.
* */
mesh_error_t set_dns_query_result(SocketAddress *address, char *domain_name);
private:
mesh_error_t configure();
mesh_error_t apply_configuration(int8_t mesh_if_id);

2
features/nanostack/mbed-mesh-api/source/NanostackEMACInterface.cpp
View File

@ -27,7 +27,7 @@ private:
EMAC &emac;
uint8_t mac_addr[6];
int8_t device_id;
phy_device_driver_s phy;
phy_device_driver_s phy = {};
};
// GAH! no handles on the callback. Force a single interface

2
features/nanostack/mbed-mesh-api/source/NanostackPPPInterface.cpp
View File

@ -52,7 +52,7 @@ private:
bool active;
bool powered_up;
int8_t device_id;
phy_device_driver_s phy;
phy_device_driver_s phy = {};
};
nsapi_error_t Nanostack::PPPInterface::initialize()

34
features/nanostack/mbed-mesh-api/source/WisunBorderRouter.cpp
View File

@ -379,23 +379,6 @@ mesh_error_t WisunBorderRouter::get_radius_shared_secret(uint16_t *shared_secret
return MESH_ERROR_NONE;
}
mesh_error_t WisunBorderRouter::set_dns_query_result(SocketAddress *address, char *domain_name)
{
if (!domain_name || !address) {
return MESH_ERROR_PARAM;
}
if (_mesh_if_id < 0) {
return MESH_ERROR_STATE;
}
if (ws_bbr_dns_query_result_set(_mesh_if_id, (const uint8_t *)address->get_ip_bytes(), domain_name) >= 0) {
return MESH_ERROR_NONE;
}
return MESH_ERROR_UNKNOWN;
}
mesh_error_t WisunBorderRouter::set_radius_timing(ws_br_radius_timing_t *timing)
{
if (timing == NULL) {
@ -475,3 +458,20 @@ mesh_error_t WisunBorderRouter::validate_radius_timing(ws_br_radius_timing_t *ti
return MESH_ERROR_NONE;
}
mesh_error_t WisunBorderRouter::set_dns_query_result(SocketAddress *address, char *domain_name)
{
if (!domain_name || !address) {
return MESH_ERROR_PARAM;
}
if (_mesh_if_id < 0) {
return MESH_ERROR_STATE;
}
if (ws_bbr_dns_query_result_set(_mesh_if_id, (const uint8_t *)address->get_ip_bytes(), domain_name) >= 0) {
return MESH_ERROR_NONE;
}
return MESH_ERROR_UNKNOWN;
}

5
features/nanostack/nanostack-hal-mbed-cmsis-rtos/arm_hal_random.c
View File

@ -34,7 +34,10 @@ uint32_t arm_random_seed_get(void)
uint32_t result = 0;
#ifdef MBEDTLS_ENTROPY_HARDWARE_ALT
#if defined(MBEDTLS_PLATFORM_C)
mbedtls_platform_setup(NULL);
int ret = mbedtls_platform_setup(NULL);
if (ret != 0) {
return result;
}
#endif /* MBEDTLS_PLATFORM_C */
/* Grab a seed from a function we provide for mbedtls */
size_t len;

1
features/nanostack/nanostack-interface/Nanostack.h
View File

@ -112,6 +112,7 @@ protected:
*
* @param index Index of the DNS server, starts from zero
* @param address Destination for the host address
* @param interface_name Network interface name
* @return 0 on success, negative error code on failure
*/
virtual nsapi_error_t get_dns_server(int index, SocketAddress *address, const char *interface_name);

212
features/netsocket/emac-drivers/TARGET_NUVOTON_EMAC/TARGET_M480/m480_eth.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -16,24 +16,30 @@
*
* Description: M480 MAC driver source file
*/
#include <stdbool.h>
#include "m480_eth.h"
#include "mbed_toolchain.h"
//#define NU_TRACE
#include "numaker_eth_hal.h"
#define ETH_TRIGGER_RX() do{EMAC->RXST = 0;}while(0)
#define ETH_TRIGGER_TX() do{EMAC->TXST = 0;}while(0)
#define ETH_ENABLE_TX() do{EMAC->CTL |= EMAC_CTL_TXON;}while(0)
#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON;}while(0)
#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk;}while(0)
#define ETH_DISABLE_TX() do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON_Msk;}while(0)
#define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel))
#define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel))
MBED_ALIGN(4) struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
MBED_ALIGN(4) struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
__attribute__((section("EMAC_RAM")))
MBED_ALIGN(4) uint8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
__attribute__((section("EMAC_RAM")))
MBED_ALIGN(4) uint8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
eth_callback_t nu_eth_txrx_cb = NULL;
@ -41,6 +47,9 @@ void *nu_userData = NULL;
extern void ack_emac_rx_isr(void);
static bool isPhyReset = false;
static uint16_t phyLPAval = 0;
// PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
// Assume we want to set each tick to 100ns.
// Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
@ -65,7 +74,7 @@ static uint16_t mdio_read(uint8_t addr, uint8_t reg)
EMAC->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
return(EMAC->MIIMDAT);
return (EMAC->MIIMDAT);
}
static int reset_phy(void)
@ -78,15 +87,18 @@ static int reset_phy(void)
mdio_write(CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET);
delayCnt = 2000;
while(delayCnt-- > 0) {
if((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0)
while (delayCnt > 0) {
delayCnt--;
if ((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0) {
break;
}
}
if(delayCnt == 0) {
if (delayCnt == 0) {
NU_DEBUGF(("Reset phy failed\n"));
return(-1);
return (-1);
}
mdio_write(CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA |
@ -99,26 +111,30 @@ static int reset_phy(void)
mdio_write(CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART);
delayCnt = 200000;
while(delayCnt-- > 0) {
if((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
== (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
while (delayCnt > 0) {
delayCnt--;
if ((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
== (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
break;
}
}
if(delayCnt == 0) {
if (delayCnt == 0) {
NU_DEBUGF(("AN failed. Set to 100 FULL\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
return(-1);
return (-1);
} else {
reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
phyLPAval = reg;
if(reg & ADVERTISE_100FULL) {
if (reg & ADVERTISE_100FULL) {
NU_DEBUGF(("100 full\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
} else if(reg & ADVERTISE_100HALF) {
} else if (reg & ADVERTISE_100HALF) {
NU_DEBUGF(("100 half\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
} else if(reg & ADVERTISE_10FULL) {
} else if (reg & ADVERTISE_10FULL) {
NU_DEBUGF(("10 full\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
} else {
@ -126,10 +142,10 @@ static int reset_phy(void)
EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
}
}
printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
return(0);
return (0);
}
@ -140,7 +156,7 @@ static void init_tx_desc(void)
cur_tx_desc_ptr = fin_tx_desc_ptr = &tx_desc[0];
for(i = 0; i < TX_DESCRIPTOR_NUM; i++) {
for (i = 0; i < TX_DESCRIPTOR_NUM; i++) {
tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN;
tx_desc[i].buf = &tx_buf[i][0];
tx_desc[i].status2 = 0;
@ -158,11 +174,11 @@ static void init_rx_desc(void)
cur_rx_desc_ptr = &rx_desc[0];
for(i = 0; i < RX_DESCRIPTOR_NUM; i++) {
for (i = 0; i < RX_DESCRIPTOR_NUM; i++) {
rx_desc[i].status1 = OWNERSHIP_EMAC;
rx_desc[i].buf = &rx_buf[i][0];
rx_desc[i].status2 = 0;
rx_desc[i].next = &rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
rx_desc[i].next = &rx_desc[(i + 1) % RX_DESCRIPTOR_NUM];
}
EMAC->RXDSA = (unsigned int)&rx_desc[0];
return;
@ -189,13 +205,13 @@ static void __eth_clk_pin_init()
/* Enable IP clock */
CLK_EnableModuleClock(EMAC_MODULE);
// Configure MDC clock rate to HCLK / (127 + 1) = 1.25 MHz if system is running at 160 MH
CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
/* Update System Core Clock */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
@ -209,10 +225,10 @@ static void __eth_clk_pin_init()
SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE8MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk |
SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk);
SYS->GPE_MFPH |= SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC |
SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO |
SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 |
SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 |
SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN;
SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO |
SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 |
SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 |
SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN;
// Enable high slew rate on all RMII TX output pins
PE->SLEWCTL = (GPIO_SLEWCTL_HIGH << GPIO_SLEWCTL_HSREN10_Pos) |
@ -228,13 +244,13 @@ static void __eth_clk_pin_init()
void numaker_eth_init(uint8_t *mac_addr)
{
// init CLK & pins
__eth_clk_pin_init();
// init CLK & pins
__eth_clk_pin_init();
// Reset MAC
EMAC->CTL = EMAC_CTL_RST_Msk;
while(EMAC->CTL & EMAC_CTL_RST_Msk) {}
while (EMAC->CTL & EMAC_CTL_RST_Msk) {}
init_tx_desc();
init_rx_desc();
@ -260,10 +276,33 @@ void numaker_eth_init(uint8_t *mac_addr)
EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk |
EMAC_CAMCTL_AMP_Msk |
EMAC_CAMCTL_ABP_Msk;
EMAC->CAMEN = 1; // Enable CAM entry 0
EMAC->CAMEN = 1; // Enable CAM entry 0
/* Limit the max receive frame length to 1514 + 4 */
EMAC->MRFL = NU_ETH_MAX_FLEN;
/* Set RX FIFO threshold as 8 words */
EMAC->FIFOCTL = 0x00200100;
if (isPhyReset != true) {
if (!reset_phy()) {
isPhyReset = true;
}
} else {
if (phyLPAval & ADVERTISE_100FULL) {
NU_DEBUGF(("100 full\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
} else if (phyLPAval & ADVERTISE_100HALF) {
NU_DEBUGF(("100 half\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
} else if (phyLPAval & ADVERTISE_10FULL) {
NU_DEBUGF(("10 full\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
} else {
NU_DEBUGF(("10 half\n"));
EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
}
}
reset_phy();
EMAC_ENABLE_RX();
EMAC_ENABLE_TX();
@ -281,20 +320,26 @@ unsigned int m_status;
void EMAC_RX_IRQHandler(void)
{
// NU_DEBUGF(("%s ... nu_eth_txrx_cb=0x%x\r\n", __FUNCTION__, nu_eth_txrx_cb));
m_status = EMAC->INTSTS & 0xFFFF;
EMAC->INTSTS = m_status;
if (m_status & EMAC_INTSTS_RXBEIF_Msk) {
// Shouldn't goes here, unless descriptor corrupted
NU_DEBUGF(("RX descriptor corrupted \r\n"));
//return;
mbed_error_printf("### RX Bus error [0x%x]\r\n", m_status);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('B', nu_userData);
}
return;
}
EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('R', nu_userData);
}
if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('R', nu_userData);
}
void numaker_eth_trigger_rx(void)
{
EMAC_ENABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
ETH_TRIGGER_RX();
}
@ -303,25 +348,35 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf)
unsigned int cur_entry, status;
cur_entry = EMAC->CRXDSA;
if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk))) // cur_entry may equal to cur_rx_desc_ptr if RDU occures
return -1;
if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk))) { // cur_entry may equal to cur_rx_desc_ptr if RDU occures
return -1;
}
status = cur_rx_desc_ptr->status1;
if(status & OWNERSHIP_EMAC)
return -1;
if (status & OWNERSHIP_EMAC) {
return -1;
}
if (status & RXFD_RXGD) {
*buf = cur_rx_desc_ptr->buf;
*len = status & 0xFFFF;
// length of payload should be <= 1514
if (*len > (NU_ETH_MAX_FLEN - 4)) {
NU_DEBUGF(("%s... unexpected long packet length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
*len = 0; // Skip this unexpected long packet
}
if (*len == (NU_ETH_MAX_FLEN - 4)) {
NU_DEBUGF(("%s... length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
}
}
return 0;
}
}
void numaker_eth_rx_next(void)
{
cur_rx_desc_ptr->status1 = OWNERSHIP_EMAC;
cur_rx_desc_ptr = cur_rx_desc_ptr->next;
}
cur_rx_desc_ptr = cur_rx_desc_ptr->next;
}
void EMAC_TX_IRQHandler(void)
{
@ -329,8 +384,12 @@ void EMAC_TX_IRQHandler(void)
status = EMAC->INTSTS & 0xFFFF0000;
EMAC->INTSTS = status;
if(status & EMAC_INTSTS_TXBEIF_Msk) {
if (status & EMAC_INTSTS_TXBEIF_Msk) {
// Shouldn't goes here, unless descriptor corrupted
mbed_error_printf("### TX Bus error [0x%x]\r\n", status);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('B', nu_userData);
}
return;
}
@ -340,16 +399,19 @@ void EMAC_TX_IRQHandler(void)
fin_tx_desc_ptr = fin_tx_desc_ptr->next;
}
if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('T', nu_userData);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('T', nu_userData);
}
}
uint8_t *numaker_eth_get_tx_buf(void)
{
if(cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC)
return(NULL);
else
return(cur_tx_desc_ptr->buf);
if (cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC) {
return (NULL);
} else {
return (cur_tx_desc_ptr->buf);
}
}
void numaker_eth_trigger_tx(uint16_t length, void *p)
@ -366,11 +428,12 @@ void numaker_eth_trigger_tx(uint16_t length, void *p)
int numaker_eth_link_ok(void)
{
/* first, a dummy read to latch */
mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
if(mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS)
return 1;
return 0;
/* first, a dummy read to latch */
mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
if (mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS) {
return 1;
}
return 0;
}
void numaker_eth_set_cb(eth_callback_t eth_cb, void *userData)
@ -392,8 +455,7 @@ void mbed_mac_address(char *mac)
// http://en.wikipedia.org/wiki/MAC_address
uint32_t word1 = *(uint32_t *)0x7F800; // 2KB Data Flash at 0x7F800
if( word0 == 0xFFFFFFFF ) // Not burn any mac address at 1st 2 words of Data Flash
{
if (word0 == 0xFFFFFFFF) { // Not burn any mac address at 1st 2 words of Data Flash
// with a semi-unique MAC address from the UUID
/* Enable FMC ISP function */
SYS_UnlockReg();
@ -401,34 +463,36 @@ void mbed_mac_address(char *mac)
// = FMC_ReadUID(0);
uID1 = FMC_ReadUID(1);
word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8;
word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF)<<12) | (FMC_ReadUID(2) & 0xFFF);
word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF) << 12) | (FMC_ReadUID(2) & 0xFFF);
/* Disable FMC ISP function */
FMC_Close();
/* Lock protected registers */
SYS_LockReg();
}
}
word1 |= 0x00000200;
word1 &= 0x0000FEFF;
mac[0] = (word1 & 0x0000ff00) >> 8;
mac[0] = (word1 & 0x0000ff00) >> 8;
mac[1] = (word1 & 0x000000ff);
mac[2] = (word0 & 0xff000000) >> 24;
mac[3] = (word0 & 0x00ff0000) >> 16;
mac[4] = (word0 & 0x0000ff00) >> 8;
mac[5] = (word0 & 0x000000ff);
NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]));
NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
}
void numaker_eth_enable_interrupts(void) {
void numaker_eth_enable_interrupts(void)
{
EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
EMAC_INTEN_TXIEN_Msk ;
NVIC_EnableIRQ(EMAC_RX_IRQn);
NVIC_EnableIRQ(EMAC_TX_IRQn);
NVIC_EnableIRQ(EMAC_RX_IRQn);
NVIC_EnableIRQ(EMAC_TX_IRQn);
}
void numaker_eth_disable_interrupts(void) {
NVIC_DisableIRQ(EMAC_RX_IRQn);
NVIC_DisableIRQ(EMAC_TX_IRQn);
void numaker_eth_disable_interrupts(void)
{
NVIC_DisableIRQ(EMAC_RX_IRQn);
NVIC_DisableIRQ(EMAC_TX_IRQn);
}

221
features/netsocket/emac-drivers/TARGET_NUVOTON_EMAC/TARGET_NUC472/nuc472_eth.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -16,30 +16,38 @@
*
* Description: NUC472 MAC driver source file
*/
#include <stdbool.h>
#include "nuc472_eth.h"
#include "mbed_toolchain.h"
//#define NU_TRACE
#include "numaker_eth_hal.h"
#define ETH_TRIGGER_RX() do{EMAC->RXST = 0;}while(0)
#define ETH_TRIGGER_TX() do{EMAC->TXST = 0;}while(0)
#define ETH_ENABLE_TX() do{EMAC->CTL |= EMAC_CTL_TXON;}while(0)
#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON;}while(0)
#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk;}while(0)
#define ETH_DISABLE_TX() do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON_Msk;}while(0)
#define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel))
#define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel))
MBED_ALIGN(4) struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
MBED_ALIGN(4) struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
__attribute__((section("EMAC_RAM")))
MBED_ALIGN(4) uint8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
__attribute__((section("EMAC_RAM")))
MBED_ALIGN(4) uint8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
eth_callback_t nu_eth_txrx_cb = NULL;
void *nu_userData = NULL;
extern void ack_emac_rx_isr(void);
static bool isPhyReset = false;
static uint16_t phyLPAval = 0;
// PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
// Assume we want to set each tick to 100ns.
@ -65,7 +73,7 @@ static uint16_t mdio_read(uint8_t addr, uint8_t reg)
EMAC->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
return(EMAC->MIIMDAT);
return (EMAC->MIIMDAT);
}
static int reset_phy(void)
@ -78,15 +86,18 @@ static int reset_phy(void)
mdio_write(CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET);
delayCnt = 2000;
while(delayCnt-- > 0) {
if((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0)
while (delayCnt > 0) {
delayCnt--;
if ((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0) {
break;
}
}
if(delayCnt == 0) {
if (delayCnt == 0) {
NU_DEBUGF(("Reset phy failed\n"));
return(-1);
return (-1);
}
mdio_write(CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA |
@ -99,26 +110,30 @@ static int reset_phy(void)
mdio_write(CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART);
delayCnt = 200000;
while(delayCnt-- > 0) {
if((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
== (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
while (delayCnt > 0) {
delayCnt--;
if ((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
== (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
break;
}
}
if(delayCnt == 0) {
if (delayCnt == 0) {
NU_DEBUGF(("AN failed. Set to 100 FULL\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
return(-1);
return (-1);
} else {
reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
phyLPAval = reg;
if(reg & ADVERTISE_100FULL) {
if (reg & ADVERTISE_100FULL) {
NU_DEBUGF(("100 full\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
} else if(reg & ADVERTISE_100HALF) {
} else if (reg & ADVERTISE_100HALF) {
NU_DEBUGF(("100 half\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
} else if(reg & ADVERTISE_10FULL) {
} else if (reg & ADVERTISE_10FULL) {
NU_DEBUGF(("10 full\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
} else {
@ -126,10 +141,10 @@ static int reset_phy(void)
EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
}
}
printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
return(0);
return (0);
}
@ -140,7 +155,7 @@ static void init_tx_desc(void)
cur_tx_desc_ptr = fin_tx_desc_ptr = &tx_desc[0];
for(i = 0; i < TX_DESCRIPTOR_NUM; i++) {
for (i = 0; i < TX_DESCRIPTOR_NUM; i++) {
tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN;
tx_desc[i].buf = &tx_buf[i][0];
tx_desc[i].status2 = 0;
@ -158,11 +173,11 @@ static void init_rx_desc(void)
cur_rx_desc_ptr = &rx_desc[0];
for(i = 0; i < RX_DESCRIPTOR_NUM; i++) {
for (i = 0; i < RX_DESCRIPTOR_NUM; i++) {
rx_desc[i].status1 = OWNERSHIP_EMAC;
rx_desc[i].buf = &rx_buf[i][0];
rx_desc[i].status2 = 0;
rx_desc[i].next = &rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
rx_desc[i].next = &rx_desc[(i + 1) % (RX_DESCRIPTOR_NUM)];
}
EMAC->RXDSA = (unsigned int)&rx_desc[0];
return;
@ -186,24 +201,28 @@ void numaker_set_mac_addr(uint8_t *addr)
static void __eth_clk_pin_init()
{
/* Enable IP clock */
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable IP clock */
CLK_EnableModuleClock(EMAC_MODULE);
// Configure MDC clock rate to HCLK / (127 + 1) = 656 kHz if system is running at 84 MHz
CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
/* Update System Core Clock */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
// Configure RMII pins
SYS->GPC_MFPL &= ~( SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk |
SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk );
SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk |
SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk);
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK |
SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 |
SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 |
SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 |
SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 |
SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC8MFP_Msk;
SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
@ -214,21 +233,23 @@ static void __eth_clk_pin_init()
SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
SYS->GPB_MFPH |= SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
/* Lock protected registers */
SYS_LockReg();
}
void numaker_eth_init(uint8_t *mac_addr)
{
// init CLK & pins
__eth_clk_pin_init();
// init CLK & pins
__eth_clk_pin_init();
// Reset MAC
EMAC->CTL = EMAC_CTL_RST_Msk;
while (EMAC->CTL & EMAC_CTL_RST_Msk) {}
init_tx_desc();
init_rx_desc();
numaker_set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc...
reset_phy();
EMAC->CTL |= EMAC_CTL_STRIPCRC_Msk | EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk | EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
@ -239,7 +260,34 @@ void numaker_eth_init(uint8_t *mac_addr)
EMAC_INTEN_TXABTIEN_Msk |
EMAC_INTEN_TXCPIEN_Msk |
EMAC_INTEN_TXBEIEN_Msk;
EMAC->RXST = 0; // trigger Rx
/* Limit the max receive frame length to 1514 + 4 */
EMAC->MRFL = NU_ETH_MAX_FLEN;
/* Set RX FIFO threshold as 8 words */
if (isPhyReset != true) {
if (!reset_phy()) {
isPhyReset = true;
}
} else {
if (phyLPAval & ADVERTISE_100FULL) {
NU_DEBUGF(("100 full\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
} else if (phyLPAval & ADVERTISE_100HALF) {
NU_DEBUGF(("100 half\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
} else if (phyLPAval & ADVERTISE_10FULL) {
NU_DEBUGF(("10 full\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
} else {
NU_DEBUGF(("10 half\n"));
EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
}
}
EMAC_ENABLE_RX();
EMAC_ENABLE_TX();
}
@ -254,20 +302,26 @@ unsigned int m_status;
void EMAC_RX_IRQHandler(void)
{
// NU_DEBUGF(("%s ... nu_eth_txrx_cb=0x%x\r\n", __FUNCTION__, nu_eth_txrx_cb));
m_status = EMAC->INTSTS & 0xFFFF;
EMAC->INTSTS = m_status;
if (m_status & EMAC_INTSTS_RXBEIF_Msk) {
// Shouldn't goes here, unless descriptor corrupted
NU_DEBUGF(("RX descriptor corrupted \r\n"));
//return;
mbed_error_printf("### RX Bus error [0x%x]\r\n", m_status);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('B', nu_userData);
}
return;
}
EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('R', nu_userData);
}
if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('R', nu_userData);
}
void numaker_eth_trigger_rx(void)
{
EMAC_ENABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
ETH_TRIGGER_RX();
}
@ -276,25 +330,35 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf)
unsigned int cur_entry, status;
cur_entry = EMAC->CRXDSA;
if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk))) // cur_entry may equal to cur_rx_desc_ptr if RDU occures
return -1;
if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk))) { // cur_entry may equal to cur_rx_desc_ptr if RDU occures
return -1;
}
status = cur_rx_desc_ptr->status1;
if(status & OWNERSHIP_EMAC)
return -1;
if (status & OWNERSHIP_EMAC) {
return -1;
}
if (status & RXFD_RXGD) {
*buf = cur_rx_desc_ptr->buf;
*len = status & 0xFFFF;
// length of payload should be <= 1514
if (*len > (NU_ETH_MAX_FLEN - 4)) {
NU_DEBUGF(("%s... unexpected long packet length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
*len = 0; // Skip this unexpected long packet
}
if (*len == (NU_ETH_MAX_FLEN - 4)) {
NU_DEBUGF(("%s... length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
}
}
return 0;
}
}
void numaker_eth_rx_next(void)
{
cur_rx_desc_ptr->status1 = OWNERSHIP_EMAC;
cur_rx_desc_ptr = cur_rx_desc_ptr->next;
}
cur_rx_desc_ptr = cur_rx_desc_ptr->next;
}
void EMAC_TX_IRQHandler(void)
{
@ -302,8 +366,12 @@ void EMAC_TX_IRQHandler(void)
status = EMAC->INTSTS & 0xFFFF0000;
EMAC->INTSTS = status;
if(status & EMAC_INTSTS_TXBEIF_Msk) {
if (status & EMAC_INTSTS_TXBEIF_Msk) {
// Shouldn't goes here, unless descriptor corrupted
mbed_error_printf("### TX Bus error [0x%x]\r\n", status);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('B', nu_userData);
}
return;
}
@ -313,16 +381,19 @@ void EMAC_TX_IRQHandler(void)
fin_tx_desc_ptr = fin_tx_desc_ptr->next;
}
if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('T', nu_userData);
if (nu_eth_txrx_cb != NULL) {
nu_eth_txrx_cb('T', nu_userData);
}
}
uint8_t *numaker_eth_get_tx_buf(void)
{
if(cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC)
return(NULL);
else
return(cur_tx_desc_ptr->buf);
if (cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC) {
return (NULL);
} else {
return (cur_tx_desc_ptr->buf);
}
}
void numaker_eth_trigger_tx(uint16_t length, void *p)
@ -339,11 +410,12 @@ void numaker_eth_trigger_tx(uint16_t length, void *p)
int numaker_eth_link_ok(void)
{
/* first, a dummy read to latch */
mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
if(mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS)
return 1;
return 0;
/* first, a dummy read to latch */
mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
if (mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS) {
return 1;
}
return 0;
}
void numaker_eth_set_cb(eth_callback_t eth_cb, void *userData)
@ -365,8 +437,7 @@ void mbed_mac_address(char *mac)
// http://en.wikipedia.org/wiki/MAC_address
uint32_t word1 = *(uint32_t *)0x7F800; // 2KB Data Flash at 0x7F800
if( word0 == 0xFFFFFFFF ) // Not burn any mac address at 1st 2 words of Data Flash
{
if (word0 == 0xFFFFFFFF) { // Not burn any mac address at 1st 2 words of Data Flash
// with a semi-unique MAC address from the UUID
/* Enable FMC ISP function */
SYS_UnlockReg();
@ -374,34 +445,36 @@ void mbed_mac_address(char *mac)
// = FMC_ReadUID(0);
uID1 = FMC_ReadUID(1);
word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8;
word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF)<<12) | (FMC_ReadUID(2) & 0xFFF);
word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF) << 12) | (FMC_ReadUID(2) & 0xFFF);
/* Disable FMC ISP function */
FMC_Close();
/* Lock protected registers */
SYS_LockReg();
}
}
word1 |= 0x00000200;
word1 &= 0x0000FEFF;
mac[0] = (word1 & 0x0000ff00) >> 8;
mac[0] = (word1 & 0x0000ff00) >> 8;
mac[1] = (word1 & 0x000000ff);
mac[2] = (word0 & 0xff000000) >> 24;
mac[3] = (word0 & 0x00ff0000) >> 16;
mac[4] = (word0 & 0x0000ff00) >> 8;
mac[5] = (word0 & 0x000000ff);
NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]));
NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
}
void numaker_eth_enable_interrupts(void) {
void numaker_eth_enable_interrupts(void)
{
EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
EMAC_INTEN_TXIEN_Msk ;
NVIC_EnableIRQ(EMAC_RX_IRQn);
NVIC_EnableIRQ(EMAC_TX_IRQn);
NVIC_EnableIRQ(EMAC_RX_IRQn);
NVIC_EnableIRQ(EMAC_TX_IRQn);
}
void numaker_eth_disable_interrupts(void) {
NVIC_DisableIRQ(EMAC_RX_IRQn);
NVIC_DisableIRQ(EMAC_TX_IRQn);
void numaker_eth_disable_interrupts(void)
{
NVIC_DisableIRQ(EMAC_RX_IRQn);
NVIC_DisableIRQ(EMAC_TX_IRQn);
}

180
features/netsocket/emac-drivers/TARGET_NUVOTON_EMAC/numaker_emac.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 Nuvoton Technology Corp.
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -37,7 +37,7 @@
#include "numaker_eth_hal.h"
/********************************************************************************
*
*
********************************************************************************/
#define NU_BUFF_ALIGNMENT 4
#define PHY_LINKED_STATE 1
@ -48,6 +48,7 @@ extern "C" void numaker_eth_rx_next(void);
/* \brief Flags for worker thread */
#define FLAG_TX 1
#define FLAG_RX 2
#define FLAG_BUS_RESET 4
/** \brief Driver thread priority */
#define THREAD_PRIORITY (osPriorityNormal)
@ -82,24 +83,32 @@ void NUMAKER_EMAC::rx_isr()
}
}
void NUMAKER_EMAC::bus_isr()
{
if (thread) {
osThreadFlagsSet(thread, FLAG_BUS_RESET);
}
}
void NUMAKER_EMAC::tx_isr()
{
/* No-op at this stage */
}
/* No-op at this stage */
}
void NUMAKER_EMAC::ethernet_callback(char event, void *param)
{
NUMAKER_EMAC *enet = static_cast<NUMAKER_EMAC *>(param);
switch (event)
{
case 'R': //For RX event
enet->rx_isr();
break;
case 'T': //For TX event
enet->tx_isr();
break;
default:
break;
switch (event) {
case 'R': //For RX event
enet->rx_isr();
break;
case 'T': //For TX event
enet->tx_isr();
break;
case 'B': // For BUS event
enet->bus_isr();
default:
break;
}
}
@ -112,13 +121,13 @@ bool NUMAKER_EMAC::low_level_init_successful()
/* Init ETH */
mbed_mac_address((char *)hwaddr);
printf("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", hwaddr[0], hwaddr[1],hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]);
printf("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
/* Enable clock & set EMAC configuration */
/* Enable MAC and DMA transmission and reception */
numaker_eth_init(hwaddr);
numaker_eth_set_cb(&NUMAKER_EMAC::ethernet_callback, this);
return true;
}
@ -133,7 +142,7 @@ int NUMAKER_EMAC::low_level_input(emac_mem_buf_t **buf)
uint32_t payloadoffset = 0;
/* get received frame */
if ( numaker_eth_get_rx_buf(&len, &buffer) != 0) {
if (numaker_eth_get_rx_buf(&len, &buffer) != 0) {
return -1;
}
byteslefttocopy = len;
@ -148,10 +157,10 @@ int NUMAKER_EMAC::low_level_input(emac_mem_buf_t **buf)
for (q = *buf; q != NULL; q = memory_manager->get_next(q)) {
byteslefttocopy = memory_manager->get_len(q);
payloadoffset = 0;
NU_DEBUGF(("offset=[%d], bytes-to-copy[%d]\r\n",bufferoffset,byteslefttocopy));
NU_DEBUGF(("offset=[%d], bytes-to-copy[%d]\r\n", bufferoffset, byteslefttocopy));
/* Copy data in pbuf */
memcpy(static_cast<uint8_t *>(memory_manager->get_ptr(q)) + payloadoffset, static_cast<uint8_t *>(buffer) + bufferoffset, byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
}
}
@ -167,16 +176,20 @@ int NUMAKER_EMAC::low_level_input(emac_mem_buf_t **buf)
* \param[in] pvParameters pointer to the interface data
*/
void NUMAKER_EMAC::thread_function(void* pvParameters)
void NUMAKER_EMAC::thread_function(void *pvParameters)
{
static struct NUMAKER_EMAC *nu_enet = static_cast<NUMAKER_EMAC *>(pvParameters);
for (;;) {
uint32_t flags = osThreadFlagsWait(FLAG_RX, osFlagsWaitAny, osWaitForever);
uint32_t flags = osThreadFlagsWait(FLAG_RX | FLAG_BUS_RESET, osFlagsWaitAny, osWaitForever);
if (flags & FLAG_RX) {
nu_enet->packet_rx();
}
if (flags & FLAG_BUS_RESET) {
NU_DEBUGF(("BUS error and reset bus\r\n"));
nu_enet->bus_reset();
}
}
}
@ -187,20 +200,20 @@ void NUMAKER_EMAC::thread_function(void* pvParameters)
*/
void NUMAKER_EMAC::packet_rx()
{
/* move received packet into a new buf */
while (1) {
emac_mem_buf_t *p = NULL;
if (low_level_input(&p) < 0) {
break;
}
if (p) {
NU_DEBUGF(("%s ... p=0x%x\r\n",__FUNCTION__,p));
emac_link_input_cb(p);
}
numaker_eth_rx_next();
}
numaker_eth_trigger_rx();
/* move received packet into a new buf */
while (1) {
emac_mem_buf_t *p = NULL;
if (low_level_input(&p) < 0) {
break;
}
if (p) {
NU_DEBUGF(("%s ... p=0x%x\r\n", __FUNCTION__, p));
emac_link_input_cb(p);
}
numaker_eth_rx_next();
}
numaker_eth_trigger_rx();
}
@ -231,15 +244,17 @@ bool NUMAKER_EMAC::link_out(emac_mem_buf_t *buf)
/* Get exclusive access */
TXLockMutex.lock();
buffer = numaker_eth_get_tx_buf();
NU_DEBUGF(("%s ... buffer=0x%x\r\n",__FUNCTION__, buffer));
if( buffer == NULL ) goto error;
NU_DEBUGF(("%s ... buffer=0x%x\r\n", __FUNCTION__, buffer));
if (buffer == NULL) {
goto error;
}
/* copy frame from buf to driver buffers */
for (q = buf; q != NULL; q = memory_manager->get_next(q)) {
/* Get bytes in current lwIP buffer */
byteslefttocopy = memory_manager->get_len(q);
payloadoffset = 0;
NU_DEBUGF(("offset=%d, bytes-to-copy=%d\r\n",bufferoffset, byteslefttocopy));
NU_DEBUGF(("offset=%d, bytes-to-copy=%d\r\n", bufferoffset, byteslefttocopy));
/* Check if the length of data to copy is bigger than Tx buffer size*/
while ((byteslefttocopy + bufferoffset) > PACKET_BUFFER_SIZE) {
/* Copy data to Tx buffer*/
@ -248,20 +263,22 @@ bool NUMAKER_EMAC::link_out(emac_mem_buf_t *buf)
/* Point to next descriptor */
numaker_eth_trigger_tx(PACKET_BUFFER_SIZE, NULL);
buffer = numaker_eth_get_tx_buf();
if( buffer == NULL ) goto error;
if (buffer == NULL) {
goto error;
}
byteslefttocopy = byteslefttocopy - (PACKET_BUFFER_SIZE - bufferoffset);
payloadoffset = payloadoffset + (PACKET_BUFFER_SIZE - bufferoffset);
framelength = framelength + (PACKET_BUFFER_SIZE - bufferoffset);
bufferoffset = 0;
}
/* Copy the remaining bytes */
memcpy(static_cast<uint8_t *>(buffer) + bufferoffset, static_cast<uint8_t *>(memory_manager->get_ptr(q)) + payloadoffset, byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
framelength = framelength + byteslefttocopy;
}
/* Prepare transmit descriptors to give to DMA */
numaker_eth_trigger_tx(framelength, NULL);
@ -280,57 +297,72 @@ error:
void NUMAKER_EMAC::phy_task()
{
// Get current status
int state;
state = numaker_eth_link_ok();
if ((state & PHY_LINKED_STATE) && !(phy_state & PHY_LINKED_STATE)) {
NU_DEBUGF(("Link Up\r\n"));
if (emac_link_state_cb) emac_link_state_cb(true);
if (emac_link_state_cb) {
emac_link_state_cb(true);
}
} else if (!(state & PHY_LINKED_STATE) && (phy_state & PHY_LINKED_STATE)) {
NU_DEBUGF(("Link Down\r\n"));
if (emac_link_state_cb) emac_link_state_cb(false);
if (emac_link_state_cb) {
emac_link_state_cb(false);
}
}
phy_state = state;
phy_state = state;
}
bool NUMAKER_EMAC::power_up()
{
/* Initialize the hardware */
if (!low_level_init_successful())
return false;
/* Initialize the hardware */
if (!low_level_init_successful()) {
return false;
}
/* Worker thread */
thread = create_new_thread("numaker_emac_thread", &NUMAKER_EMAC::thread_function, this, THREAD_STACKSIZE, THREAD_PRIORITY, &thread_cb);
/* Worker thread */
thread = create_new_thread("numaker_emac_thread", &NUMAKER_EMAC::thread_function, this, THREAD_STACKSIZE * 2, THREAD_PRIORITY, &thread_cb);
/* PHY monitoring task */
phy_state = PHY_UNLINKED_STATE;
/* PHY monitoring task */
phy_state = PHY_UNLINKED_STATE;
phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD_MS, mbed::callback(this, &NUMAKER_EMAC::phy_task));
phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD_MS, mbed::callback(this, &NUMAKER_EMAC::phy_task));
/* Allow the PHY task to detect the initial link state and set up the proper flags */
osDelay(10);
numaker_eth_enable_interrupts();
return true;
/* Allow the PHY task to detect the initial link state and set up the proper flags */
osDelay(10);
numaker_eth_enable_interrupts();
return true;
}
bool NUMAKER_EMAC::bus_reset()
{
/* Initialize the hardware */
if (!low_level_init_successful()) {
return false;
}
numaker_eth_enable_interrupts();
return true;
}
uint32_t NUMAKER_EMAC::get_mtu_size() const
{
return NU_ETH_MTU_SIZE;
return NU_ETH_MTU_SIZE;
}
uint32_t NUMAKER_EMAC::get_align_preference() const
{
return NU_BUFF_ALIGNMENT;
return NU_BUFF_ALIGNMENT;
}
void NUMAKER_EMAC::get_ifname(char *name, uint8_t size) const
{
memcpy(name, NU_ETH_IF_NAME, (size < sizeof(NU_ETH_IF_NAME)) ? size : sizeof(NU_ETH_IF_NAME));
memcpy(name, NU_ETH_IF_NAME, (size < sizeof(NU_ETH_IF_NAME)) ? size : sizeof(NU_ETH_IF_NAME));
}
uint8_t NUMAKER_EMAC::get_hwaddr_size() const
@ -346,39 +378,39 @@ bool NUMAKER_EMAC::get_hwaddr(uint8_t *addr) const
void NUMAKER_EMAC::set_hwaddr(const uint8_t *addr)
{
memcpy(hwaddr, addr, sizeof hwaddr);
numaker_set_mac_addr(const_cast<uint8_t*>(addr));
memcpy(hwaddr, addr, sizeof hwaddr);
numaker_set_mac_addr(const_cast<uint8_t *>(addr));
}
void NUMAKER_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
{
emac_link_input_cb = input_cb;
emac_link_input_cb = input_cb;
}
void NUMAKER_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
{
emac_link_state_cb = state_cb;
emac_link_state_cb = state_cb;
}
void NUMAKER_EMAC::add_multicast_group(const uint8_t *addr)
{
/* No-op at this stage */
/* No-op at this stage */
}
void NUMAKER_EMAC::remove_multicast_group(const uint8_t *addr)
{
/* No-op at this stage */
/* No-op at this stage */
}
void NUMAKER_EMAC::set_all_multicast(bool all)
{
/* No-op at this stage */
/* No-op at this stage */
}
void NUMAKER_EMAC::power_down()
{
/* No-op at this stage */
/* No-op at this stage */
}
void NUMAKER_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
@ -387,13 +419,15 @@ void NUMAKER_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
}
NUMAKER_EMAC &NUMAKER_EMAC::get_instance() {
NUMAKER_EMAC &NUMAKER_EMAC::get_instance()
{
static NUMAKER_EMAC emac;
return emac;
}
// Weak so a module can override
MBED_WEAK EMAC &EMAC::get_default_instance() {
MBED_WEAK EMAC &EMAC::get_default_instance()
{
return NUMAKER_EMAC::get_instance();
}

4
features/netsocket/emac-drivers/TARGET_NUVOTON_EMAC/numaker_emac.h
View File

@ -151,9 +151,11 @@ private:
bool low_level_init_successful();
void tx_isr();
void rx_isr();
void bus_isr();
void packet_rx();
bool bus_reset();
int low_level_input(emac_mem_buf_t **buf);
static void thread_function(void* pvParameters);
static void thread_function(void *pvParameters);
void phy_task();
static void ethernet_callback(char event, void *param);

3
platform/mbed_lib.json
View File

@ -216,6 +216,9 @@
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true
},
"NU_M2354": {
"stdio-baud-rate": 115200
},
"NRF52840_DK": {
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true

2
platform/mbed_version.h
View File

@ -45,7 +45,7 @@
*
* @note 99 is default value for development version (master branch)
*/
#define MBED_PATCH_VERSION 4
#define MBED_PATCH_VERSION 7
#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))

10
platform/source/mbed_alloc_wrappers.cpp
View File

@ -105,7 +105,10 @@ extern "C" void *malloc_wrapper(struct _reent *r, size_t size, void *caller)
#endif
#ifdef MBED_HEAP_STATS_ENABLED
malloc_stats_mutex->lock();
alloc_info_t *alloc_info = (alloc_info_t *)__real__malloc_r(r, size + sizeof(alloc_info_t));
alloc_info_t *alloc_info = NULL;
if (size <= SIZE_MAX - sizeof(alloc_info_t)) {
alloc_info = (alloc_info_t *)__real__malloc_r(r, size + sizeof(alloc_info_t));
}
if (alloc_info != NULL) {
alloc_info->size = size;
alloc_info->signature = MBED_HEAP_STATS_SIGNATURE;
@ -292,7 +295,10 @@ extern "C" void *malloc_wrapper(size_t size, void *caller)
#endif
#ifdef MBED_HEAP_STATS_ENABLED
malloc_stats_mutex->lock();
alloc_info_t *alloc_info = (alloc_info_t *)SUPER_MALLOC(size + sizeof(alloc_info_t));
alloc_info_t *alloc_info = NULL;
if (size <= SIZE_MAX - sizeof(alloc_info_t)) {
alloc_info = (alloc_info_t *)SUPER_MALLOC(size + sizeof(alloc_info_t));
}
if (alloc_info != NULL) {
alloc_info->size = size;
alloc_info->signature = MBED_HEAP_STATS_SIGNATURE;

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/crypto_access_control.bin
View File

Binary file not shown.

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/spm_client.bin
View File

Binary file not shown.

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/spm_server.bin
View File

Binary file not shown.

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/spm_smoke.bin
View File

Binary file not shown.

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/tfm.bin
View File

Binary file not shown.

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_i2c.c
View File

@ -1327,7 +1327,7 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx
/* Read dummy to release bus. */
dummy = base->D;
result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag);
result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferNoStopFlag);
/* Switch to receive mode. */
base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);

2
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/gpio_api.c
View File

@ -19,6 +19,7 @@
#include "gpio_irq_api.h"
#include "pinmap.h"
#include "nrfx_gpiote.h"
#include <string.h>
#if defined(TARGET_MCU_NRF51822)
@ -125,6 +126,7 @@ static void gpio_apply_config(uint8_t pin)
|| (m_gpio_cfg[pin].used_as_irq)) {
//Configure as input.
nrfx_gpiote_in_config_t cfg;
memset(&cfg, 0, sizeof(cfg));
cfg.hi_accuracy = false;
cfg.is_watcher = false;

60
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_ARMC6/M2351.sct Normal file
View File

@ -0,0 +1,60 @@
#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)

212
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_GCC_ARM/M2351.ld Normal file
View File

@ -0,0 +1,212 @@
/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

64
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2351_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

72
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#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2351_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{
ER_IROM_NSC NU_TZ_NSC_START FIXED PADVALUE 0xFFFFFFFF NU_TZ_NSC_SIZE
{
*(Veneer$$CMSE)
}
}
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x4000)
/* Heap must be allocated in RAM. */
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))

234
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_GCC_ARM/M2351.ld Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../../../device/partition_M2351_mem.h"
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
FLASH_NSC (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
/* Veneer$$CMSE : */
.gnu.sgstubs NU_TZ_NSC_START :
{
. = ALIGN(32);
__sgstubs_start = .;
*(.gnu.sgstubs.*)
__sgstubs_end = .;
. = ALIGN(32);
} > FLASH_NSC
/* NOTE: __sgstubs_end is not updated with *(.gnu.sgstubs.*). __sgstubs_start and
* __sgstubs_end are the same. GCC bug? */
Image$$ER_IROM_NSC$$Base = ADDR(.gnu.sgstubs);
ASSERT(SIZEOF(.gnu.sgstubs) <= NU_TZ_NSC_SIZE, "Size of .gnu.sgstubs region cannot exceed NU_TZ_NSC_SIZE.")
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ASSERT(((__sgstubs_start % 32) == 0), "Requested by SAU, NSC region must start at 32 byte-aligned boundary.")
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

74
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_IAR/M2351.icf Normal file
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/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2351_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* FIXME: Check NSC area requirement */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
/* IAR has something wrong with "$$" in section/block name. So unlike other toolchains,
* we name "ER_IROM_NSC" instead of "Image$$ER_IROM_NSC". */
define block ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at address mem: NU_TZ_NSC_START { block ER_IROM_NSC };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };
define exported symbol Image$$ER_IROM_NSC$$Base = NU_TZ_NSC_START;

173
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARMC6/M2351.sct
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#! armclang -E
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../partition_M2351_mem.h"
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE (0x1000)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_NS
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_NS
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_NS
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_S
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_S
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_S
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#if defined(DOMAIN_NS) && DOMAIN_NS
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)
#else
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{
ER_IROM_NSC +0
{
*(Veneer$$CMSE)
}
ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
#endif

368
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
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/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2351 GCC linker script file
*/
#include "../partition_M2351_mem.h"
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE (0x1000)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_NS
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_NS
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_NS
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START NU_ROM_START_S
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE NU_ROM_SIZE_S
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START NU_RAM_START_S
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
#endif
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#endif
StackSize = MBED_BOOT_STACK_SIZE;
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
#ifndef NU_TZ_NSC_START
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#endif
#if defined(DOMAIN_NS) && DOMAIN_NS
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
#else
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_START - MBED_APP_START - 0x400
NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
#endif
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 102);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
/* ensure that uvisor bss is at the beginning of memory */
.uvisor.bss (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;
/* protected uvisor main bss */
. = ALIGN(32);
__uvisor_bss_main_start = .;
KEEP(*(.keep.uvisor.bss.main))
. = ALIGN(32);
__uvisor_bss_main_end = .;
/* protected uvisor secure boxes bss */
. = ALIGN(32);
__uvisor_bss_boxes_start = .;
KEEP(*(.keep.uvisor.bss.boxes))
. = ALIGN(32);
__uvisor_bss_boxes_end = .;
/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
. = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
__uvisor_bss_end = .;
} > RAM_INTERN
.text :
{
/* uVisor code and data */
. = ALIGN(8);
__uvisor_main_start = .;
*(.uvisor.main)
__uvisor_main_end = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS)
/* Veneer$$CMSE : */
.gnu.sgstubs :
{
__sgstubs_start = .;
*(.gnu.sgstubs.*)
__sgstubs_end = .;
} > NSC_FLASH
__nu_tz_nsc_start = NU_TZ_NSC_START;
__nu_tz_nsc_size = NU_TZ_NSC_SIZE;
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
#endif
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* .stack section doesn't contains any symbols. It is only
* used for linker to reserve space for the main stack section
* WARNING: .stack should come immediately after the last secure memory
* section. This provides stack overflow detection. */
.stack (NOLOAD):
{
__StackLimit = .;
*(.stack*);
. += StackSize - (. - __StackLimit);
} > RAM_INTERN
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ADDR(.stack) + SIZEOF(.stack);
__StackLimit = ADDR(.stack);
PROVIDE(__stack = __StackTop);
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
/* uvisor configuration data */
.uvisor.secure :
{
. = ALIGN(32);
__uvisor_secure_start = .;
/* uvisor secure boxes configuration tables */
. = ALIGN(32);
__uvisor_cfgtbl_start = .;
KEEP(*(.keep.uvisor.cfgtbl))
. = ALIGN(32);
__uvisor_cfgtbl_end = .;
/* pointers to uvisor secure boxes configuration tables */
/* note: no further alignment here, we need to have the exact list of pointers */
__uvisor_cfgtbl_ptr_start = .;
KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
KEEP(*(.keep.uvisor.cfgtbl_ptr))
__uvisor_cfgtbl_ptr_end = .;
/* the following symbols are kept for backward compatibility and will be soon
* deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
* will need to use uVisor 0.8.x or above, or the security assertions will halt the
* system */
/************************/
__uvisor_data_src = .;
__uvisor_data_start = .;
__uvisor_data_end = .;
/************************/
. = ALIGN(32);
__uvisor_secure_end = .;
} >FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM_INTERN
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
/* Provide physical memory boundaries for uVisor. */
__uvisor_flash_start = ORIGIN(VECTORS);
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
__uvisor_sram_start = ORIGIN(RAM_INTERN);
__uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}

138
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf
View File

@ -1,138 +0,0 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../partition_M2351_mem.icf";
if (! isdefinedsymbol(NU_TZ_NSC_SIZE)) {
define symbol NU_TZ_NSC_SIZE = 0x1000;
}
if (isdefinedsymbol(DOMAIN_NS)) {
if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = NU_ROM_START_NS;
}
if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = NU_ROM_SIZE_NS;
}
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = NU_RAM_START_NS;
}
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_NS;
}
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x8000;
} else {
if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = NU_ROM_START_S;
}
if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = NU_ROM_SIZE_S;
}
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = NU_RAM_START_S;
}
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_S;
}
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* Requirements for NSC location
*
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/
if (! isdefinedsymbol(NU_TZ_NSC_START)) {
define symbol NU_TZ_NSC_START = MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE;
}
define exported symbol __NU_TZ_NSC_start__ = NU_TZ_NSC_START;
define exported symbol __NU_TZ_NSC_size__ = NU_TZ_NSC_SIZE;
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NSCROM_start__ = NU_TZ_NSC_START;
define symbol __ICFEDIT_region_NSCROM_end__ = NU_TZ_NSC_START + NU_TZ_NSC_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x4000;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
if (! isdefinedsymbol(DOMAIN_NS)) {
place at address mem:__ICFEDIT_region_NSCROM_start__ { readonly section Veneer$$CMSE };
}
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

6
targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h
View File

@ -23,8 +23,8 @@
#include "partition_M2351.h"
/* Check relevant macro has been defined */
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#if (! defined(NU_ROM_SIZE_S))
#error("NU_ROM_SIZE_S not defined")
#endif
// Support linker-generated symbol as start of relocated vector table.
@ -38,7 +38,7 @@ extern uint32_t __start_vector_table__;
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (NS_OFFSET + NU_TZ_SECURE_FLASH_SIZE)
#define TZ_START_NS (NS_OFFSET + NU_ROM_SIZE_S)
#endif
#endif

53
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
View File

@ -21,48 +21,31 @@
#include "partition_M2351_mem.h"
#define NU_TZ_SECURE_FLASH_SIZE NU_ROM_SIZE_S
#define NU_TZ_SECURE_SRAM_SIZE NU_RAM_SIZE_S
#ifdef __cplusplus
extern "C"
{
#endif
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
extern int Load$$LR$$LR_IROM_NSC$$Base;
extern int Load$$LR$$LR_IROM_NSC$$Length;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Length)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#elif defined(__ICCARM__)
extern int __NU_TZ_NSC_start__;
extern int __NU_TZ_NSC_size__;
#define NU_TZ_NSC_REGION_START ((uint32_t) &__NU_TZ_NSC_start__)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__NU_TZ_NSC_size__)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#elif defined(__GNUC__)
extern int __nu_tz_nsc_start;
extern int __nu_tz_nsc_size;
#define NU_TZ_NSC_REGION_START ((uint32_t) &__nu_tz_nsc_start)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__nu_tz_nsc_size)
extern int Image$$ER_IROM_NSC$$Base;
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
#endif
/* Check relevant macros have been defined */
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#endif
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined")
#endif
#if (! defined(NU_TZ_NSC_REGION_START))
#error("NU_TZ_NSC_REGION_START not defined")
#endif
#if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined")
#endif
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
@ -88,7 +71,7 @@ extern int __nu_tz_nsc_size;
// <0x16000=> 88KB
// <0x18000=> 96KB
*/
#define SCU_SECURE_SRAM_SIZE NU_TZ_SECURE_SRAM_SIZE
#define SCU_SECURE_SRAM_SIZE NU_RAM_SIZE_S
#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
@ -103,7 +86,7 @@ extern int __nu_tz_nsc_size;
// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
*/
#define FMC_SECURE_ROM_SIZE NU_TZ_SECURE_FLASH_SIZE
#define FMC_SECURE_ROM_SIZE NU_ROM_SIZE_S
#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
@ -867,5 +850,9 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#ifdef __cplusplus
}
#endif
#endif /* PARTITION_M2351 */

126
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.h
View File

@ -19,12 +19,18 @@
#ifndef __PARTITION_M2351_MEM_H__
#define __PARTITION_M2351_MEM_H__
/* About partition_M2351_mem.h/partition_M2351_mem.icf
/* About partition_M2351_mem.h/partition_M2351_mem.icf.h
*
* 1. partition_M2351_mem.h is created for centralizing memory partition configuration. It will be
* included by C/C++ files and linker files (except IAR linker file).
* 2. IAR linker doesn't support preprocessor, so partition_M2351_mem.icf, duplicate of partition_M2351_mem.h
* 2. IAR linker doesn't support preprocessor, so partition_M2351_mem.icf.h, duplicate of partition_M2351_mem.h
* is created for IAR linker file.
* 3. To continue above, we name partition_M2351_mem.icf.h instead of partition_M2351_mem.icf because:
* (1) Mbed OS build tool may mis-regard partition_M2351_mem.icf as the main linker configuration file.
* (2) *.icf files may not be present in search directories for "include" directive. Per observation,
* the search directories are inconsistent among normal example build and test code build. To address
* it, we name partition_M2351_mem.icf.h instead because *.h files are always present in these builds
* (already there or via copy).
*/
/* Default flash/SRAM partition
@ -39,34 +45,38 @@
*/
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Default non-secure ROM layout */
/* Resolve non-secure ROM start */
#ifndef MBED_ROM_START
#define MBED_ROM_START (0x10040000)
#endif
/* Resolve non-secure ROM size */
#ifndef MBED_ROM_SIZE
#define MBED_ROM_SIZE (0x40000)
#endif
/* Default non-secure RAM layout */
/* Resolve non-secure RAM start */
#ifndef MBED_RAM_START
#define MBED_RAM_START (0x30008000)
#endif
/* Resolve non-secure RAM size */
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE (0x10000)
#endif
#else
/* Default secure ROM layout */
/* Resolve secure ROM start */
#ifndef MBED_ROM_START
#define MBED_ROM_START (0x0)
#endif
/* Resolve secure ROM size */
#ifndef MBED_ROM_SIZE
#define MBED_ROM_SIZE (0x40000)
#endif
/* Default secure RAM layout */
/* Resolve secure RAM start */
#ifndef MBED_RAM_START
#define MBED_RAM_START (0x20000000)
#endif
/* Resolve secure RAM size */
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE (0x8000)
#endif
@ -108,4 +118,108 @@
#endif
/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just
* MBED_APP_xxx macros to linker files even though they mean the same thing.
* Because this file is to include by both C/C++ files and linker files, we add
* these macros according to the others for consistency when they are missing
* in compile or link stage. */
#ifndef APPLICATION_ADDR
#ifdef MBED_APP_START
#define APPLICATION_ADDR MBED_APP_START
#else
#define APPLICATION_ADDR MBED_ROM_START
#endif
#endif
#ifndef APPLICATION_SIZE
#ifdef MBED_APP_SIZE
#define APPLICATION_SIZE MBED_APP_SIZE
#else
#define APPLICATION_SIZE MBED_ROM_SIZE
#endif
#endif
#ifndef APPLICATION_RAM_ADDR
#ifdef MBED_RAM_APP_START
#define APPLICATION_RAM_ADDR MBED_RAM_APP_START
#else
#define APPLICATION_RAM_ADDR MBED_RAM_START
#endif
#endif
#ifndef APPLICATION_RAM_SIZE
#ifdef MBED_RAM_APP_SIZE
#define APPLICATION_RAM_SIZE MBED_RAM_APP_SIZE
#else
#define APPLICATION_RAM_SIZE MBED_RAM_SIZE
#endif
#endif
#ifndef MBED_APP_START
#define MBED_APP_START APPLICATION_ADDR
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE APPLICATION_SIZE
#endif
#ifndef MBED_RAM_APP_START
#define MBED_RAM_APP_START APPLICATION_RAM_ADDR
#endif
#ifndef MBED_RAM_APP_SIZE
#define MBED_RAM_APP_SIZE APPLICATION_RAM_SIZE
#endif
#if (APPLICATION_ADDR != MBED_APP_START)
#error("APPLICATION_ADDR and MBED_APP_START are not the same!!!")
#endif
#if (APPLICATION_SIZE != MBED_APP_SIZE)
#error("APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!")
#endif
#if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START)
#error("APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!")
#endif
#if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE)
#error("APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!")
#endif
/* Determine NSC area
*
* Requirements for NSC area:
* 1. Requested by SAU, NSC area must start at 32 byte-aligned boundary.
* 2. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 3. Greentea flash IAP uses last 2 sectors for its test. Avoid this range.
* 4. Greentea NVSTORE uses last 2 sectors or 4 KiB x 2 for its test. Avoid this range.
* 5. KVStore uses last a few KiB. Avoid this range.
* 6. Due to TFM build process, TFM and its tests must generate the same cmse_lib.o.
* To this end, TZ NSC location must fix at a well-known location and cannot place
* arbitrarily.
*
* Configurable for NSC area:
* We cannot configure NSC location via configuration parameter because the generated
* configuration macros are just passed to C/C++ files but not to linker files. So
* we can only hardcode NSC location here as constants (to be included by linker file).
*
* Locate NSC area at end of secure flash:
* We decide to locate NSC area at end of secure flash. To avoid this area
* accidentally erased by flash IAP operation, flash IAP must configure to exclude
* this area.
*/
/* TZ NSC area defaults to from secure ROM end */
#define NU_TZ_NSC_START (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
/* TZ NSC area defaults to 4KiB. */
#define NU_TZ_NSC_SIZE 0x1000
/* Configuration of flash IAP area */
#define NU_FLASHIAP_SECURE_START NU_ROM_START_S
/* Exclude NSC area to avoid accidentally erased */
#define NU_FLASHIAP_SECURE_SIZE (NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
#define NU_FLASHIAP_NONSECURE_START NU_ROM_START_NS
#define NU_FLASHIAP_NONSECURE_SIZE NU_ROM_SIZE_NS
#endif /* __PARTITION_M2351_MEM_H__ */

100
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.icf
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@ -1,100 +0,0 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* See partition_M2351_mem.h for documentation */
/* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Default non-secure ROM layout */
if (! isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10040000;
}
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x40000;
}
/* Default non-secure RAM layout */
if (! isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x30008000;
}
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x10000;
}
#else
/* Default secure ROM layout */
if (! isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x0;
}
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x40000;
}
/* Default secure RAM layout */
if (! isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x20000000;
}
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x8000;
}
#endif
/* Resolved flash/SRAM partition */
#if defined(DOMAIN_NS) && DOMAIN_NS
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = 0x0;
define symbol NU_ROM_SIZE_S = (0x80000 - MBED_ROM_SIZE);
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = 0x20000000;
define symbol NU_RAM_SIZE_S = (0x18000 - MBED_RAM_SIZE);
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = MBED_ROM_START;
define symbol NU_ROM_SIZE_NS = MBED_ROM_SIZE;
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = MBED_RAM_START;
define symbol NU_RAM_SIZE_NS = MBED_RAM_SIZE;
#else
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = MBED_ROM_START;
define symbol NU_ROM_SIZE_S = MBED_ROM_SIZE;
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = MBED_RAM_START;
define symbol NU_RAM_SIZE_S = MBED_RAM_SIZE;
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = (0x10000000 + MBED_ROM_SIZE);
define symbol NU_ROM_SIZE_NS = (0x80000 - MBED_ROM_SIZE);
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = (0x30000000 + MBED_RAM_SIZE);
define symbol NU_RAM_SIZE_NS = (0x18000 - MBED_RAM_SIZE);
#endif

252
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351_mem.icf.h Normal file
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@ -0,0 +1,252 @@
/*
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* See partition_M2351_mem.h for documentation */
/* IAR doesn't support short-circuit evaluation in boolean operator and fails when
* evaluating undefined symbol. Define it explicitly. */
if (!isdefinedsymbol(DOMAIN_NS)) {
define symbol DOMAIN_NS = 0;
}
/* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
if (DOMAIN_NS) {
/* Resolve non-secure ROM start */
if (! isdefinedsymbol(MBED_ROM_START)) {
if (isdefinedsymbol(PSA_NON_SECURE_ROM_START)) {
define symbol MBED_ROM_START = PSA_NON_SECURE_ROM_START;
} else {
define symbol MBED_ROM_START = 0x10040000;
}
}
/* Resolve non-secure ROM size */
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
if (isdefinedsymbol(PSA_NON_SECURE_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = PSA_NON_SECURE_ROM_SIZE;
} else {
define symbol MBED_ROM_SIZE = 0x40000;
}
}
/* Resolve non-secure RAM start */
if (! isdefinedsymbol(MBED_RAM_START)) {
if (isdefinedsymbol(PSA_NON_SECURE_RAM_START)) {
define symbol MBED_RAM_START = PSA_NON_SECURE_RAM_START;
} else {
define symbol MBED_RAM_START = 0x30008000;
}
}
/* Resolve non-secure RAM size */
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
if (isdefinedsymbol(PSA_NON_SECURE_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = PSA_NON_SECURE_RAM_SIZE;
} else {
define symbol MBED_RAM_SIZE = 0x10000;
}
}
} else {
/* Resolve secure ROM start */
if (! isdefinedsymbol(MBED_ROM_START)) {
if (isdefinedsymbol(PSA_SECURE_ROM_START)) {
define symbol MBED_ROM_START = PSA_SECURE_ROM_START;
} else {
define symbol MBED_ROM_START = 0x0;
}
}
/* Resolve secure ROM size */
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
if (isdefinedsymbol(PSA_SECURE_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = PSA_SECURE_ROM_SIZE;
} else {
define symbol MBED_ROM_SIZE = 0x40000;
}
}
/* Resolve secure RAM start */
if (! isdefinedsymbol(MBED_RAM_START)) {
if (isdefinedsymbol(PSA_SECURE_RAM_START)) {
define symbol MBED_RAM_START = PSA_SECURE_RAM_START;
} else {
define symbol MBED_RAM_START = 0x20000000;
}
}
/* Resolve secure RAM size */
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
if (isdefinedsymbol(PSA_SECURE_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = PSA_SECURE_RAM_SIZE;
} else {
define symbol MBED_RAM_SIZE = 0x8000;
}
}
}
/* Resolved flash/SRAM partition */
if (DOMAIN_NS) {
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = 0x0;
define symbol NU_ROM_SIZE_S = (0x80000 - MBED_ROM_SIZE);
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = 0x20000000;
define symbol NU_RAM_SIZE_S = (0x18000 - MBED_RAM_SIZE);
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = MBED_ROM_START;
define symbol NU_ROM_SIZE_NS = MBED_ROM_SIZE;
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = MBED_RAM_START;
define symbol NU_RAM_SIZE_NS = MBED_RAM_SIZE;
} else {
/* Resolved secure ROM layout */
define symbol NU_ROM_START_S = MBED_ROM_START;
define symbol NU_ROM_SIZE_S = MBED_ROM_SIZE;
/* Resolved secure RAM layout */
define symbol NU_RAM_START_S = MBED_RAM_START;
define symbol NU_RAM_SIZE_S = MBED_RAM_SIZE;
/* Resolved non-secure ROM layout */
define symbol NU_ROM_START_NS = (0x10000000 + MBED_ROM_SIZE);
define symbol NU_ROM_SIZE_NS = (0x80000 - MBED_ROM_SIZE);
/* Resolved non-secure RAM layout */
define symbol NU_RAM_START_NS = (0x30000000 + MBED_RAM_SIZE);
define symbol NU_RAM_SIZE_NS = (0x18000 - MBED_RAM_SIZE);
}
/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just
* MBED_APP_xxx macros to linker files even though they mean the same thing.
* Because this file is to include by both C/C++ files and linker files, we add
* these macros according to the others for consistency when they are missing
* in compile or link stage. */
if (!isdefinedsymbol(APPLICATION_ADDR)) {
if (isdefinedsymbol(MBED_APP_START)) {
define symbol APPLICATION_ADDR = MBED_APP_START;
} else {
define symbol APPLICATION_ADDR = MBED_ROM_START;
}
}
if (!isdefinedsymbol(APPLICATION_SIZE)) {
if (isdefinedsymbol(MBED_APP_SIZE)) {
define symbol APPLICATION_SIZE = MBED_APP_SIZE;
} else {
define symbol APPLICATION_SIZE = MBED_ROM_SIZE;
}
}
if (!isdefinedsymbol(APPLICATION_RAM_ADDR)) {
if (isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol APPLICATION_RAM_ADDR = MBED_RAM_APP_START;
} else {
define symbol APPLICATION_RAM_ADDR = MBED_RAM_START;
}
}
if (!isdefinedsymbol(APPLICATION_RAM_SIZE)) {
if (isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol APPLICATION_RAM_SIZE = MBED_RAM_APP_SIZE;
} else {
define symbol APPLICATION_RAM_SIZE = MBED_RAM_SIZE;
}
}
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = APPLICATION_ADDR;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = APPLICATION_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_APP_START)) {
define symbol MBED_RAM_APP_START = APPLICATION_RAM_ADDR;
}
if (!isdefinedsymbol(MBED_RAM_APP_SIZE)) {
define symbol MBED_RAM_APP_SIZE = APPLICATION_RAM_SIZE;
}
if (APPLICATION_ADDR != MBED_APP_START) {
error "APPLICATION_ADDR and MBED_APP_START are not the same!!!";
}
if (APPLICATION_SIZE != MBED_APP_SIZE) {
error "APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!";
}
if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) {
error "APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!";
}
if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) {
error "APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!";
}
/* Determine NSC area
*
* Requirements for NSC area:
* 1. Requested by SAU, NSC area must start at 32 byte-aligned boundary.
* 2. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 3. Greentea flash IAP uses last 2 sectors for its test. Avoid this range.
* 4. Greentea NVSTORE uses last 2 sectors or 4 KiB x 2 for its test. Avoid this range.
* 5. KVStore uses last a few KiB. Avoid this range.
* 6. Due to TFM build process, TFM and its tests must generate the same cmse_lib.o.
* To this end, TZ NSC location must fix at a well-known location and cannot place
* arbitrarily.
*
* Configurable for NSC area:
* We cannot configure NSC location via configuration parameter because the generated
* configuration macros are just passed to C/C++ files but not to linker files. So
* we can only hardcode NSC location here as constants (to be included by linker file).
*
* Locate NSC area at end of secure flash:
* We decide to locate NSC area at end of secure flash. To avoid this area
* accidentally erased by flash IAP operation, flash IAP must configure to exclude
* this area.
*/
/* TZ NSC area defaults to 4KiB. */
define symbol NU_TZ_NSC_SIZE = 0x1000;
/* TZ NSC area defaults to from secure ROM end */
define symbol NU_TZ_NSC_START = (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE);
/* Configuration of flash IAP area */
define symbol NU_FLASHIAP_SECURE_START = NU_ROM_START_S;
/* Exclude NSC area to avoid accidentally erased */
define symbol NU_FLASHIAP_SECURE_SIZE = (NU_ROM_SIZE_S - NU_TZ_NSC_SIZE);
define symbol NU_FLASHIAP_NONSECURE_START = NU_ROM_START_NS;
define symbol NU_FLASHIAP_NONSECURE_SIZE = NU_ROM_SIZE_NS;

196
targets/TARGET_NUVOTON/TARGET_M2351/device/startup_M2351.c
View File

@ -1,27 +1,35 @@
/**************************************************************************//**
* @file startup_M2351.c
* @version V2.00
* $Revision: 9 $
* $Date: 16/08/27 12:33p $
* @brief Startup Source File
/*
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
******************************************************************************/
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "M2351.h"
/* Suppress warning messages */
#if defined(__CC_ARM)
// Suppress warning message: extended constant initialiser used
#if defined(__ARMCC_VERSION)
// Suppress warning message: extended constant initializer used
#pragma diag_suppress 1296
#elif defined(__ICCARM__)
// Suppress warning message Pe1665
#pragma diag_suppress=Pe1665
#elif defined(__GNUC__)
#endif
/* Macro Definitions */
#if defined(__CC_ARM)
#if defined(__ARMCC_VERSION)
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias(#f)))
@ -46,22 +54,22 @@ void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
#endif
/* Initialize segments */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern void __main(void);
#elif defined(__ICCARM__)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint32_t CSTACK$$Limit;
void __iar_program_start(void);
#elif defined(__GNUC__)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint32_t __StackTop;
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern void uvisor_init(void);
#if defined(TOOLCHAIN_GCC_ARM)
extern void _start(void);
#else
@ -87,7 +95,7 @@ WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail
// 5: Reserved
WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
@ -106,16 +114,16 @@ WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI1
WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24:
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28:
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
@ -124,7 +132,7 @@ WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0
WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1
WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0
WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC
WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 42: ADC0 interrupt source 0
WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 43: ADC0 interrupt source 1
@ -177,15 +185,14 @@ WEAK_ALIAS_FUNC(DSRC_IRQHandler, Default_Handler) // 97:
WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98:
WEAK_ALIAS_FUNC(SCU_IRQHandler, Default_Handler) // 99:
// 100: Reserved
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
/* Vector table */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section("RESET")))
#if defined(__ARMCC_VERSION)
__attribute__ ((section("RESET"), used))
const uint32_t __vector_handlers[] = {
#elif defined(__ICCARM__)
extern uint32_t CSTACK$$Limit;
const uint32_t __vector_table[] @ ".intvec" = {
#elif defined(__GNUC__)
__attribute__ ((section(".vector_table")))
@ -193,10 +200,9 @@ const uint32_t __vector_handlers[] = {
#endif
/* Configure Initial Stack Pointer, using linker-generated symbols */
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
#elif defined(__ICCARM__)
//(uint32_t) __sfe("CSTACK"),
(uint32_t) &CSTACK$$Limit,
#elif defined(__GNUC__)
(uint32_t) &__StackTop,
@ -323,12 +329,48 @@ const uint32_t __vector_handlers[] = {
(uint32_t) TRNG_IRQHandler, // 101:
};
/**
* \brief This is the code that gets called on processor reset.
/* Some reset handler code cannot implement in pure C. Implement it in inline/embedded assembly.
*
* Reset_Handler:
* For non-secure PSA/non-secure non-PSA/secure non-PSA, jump directly to Reset_Handler_1
* For secure PSA, switch from MSP to PSP, then jump to Reset_Handler_1
*
* Reset_Handler_1:
* Platform initialization
* C/C++ runtime initialization
*/
void Reset_Handler(void)
/* Forward declaration */
void Reset_Handler_1(void);
/* Add '__attribute__((naked))' here to make sure compiler does not generate prologue and
* epilogue sequences for Reset_Handler. We don't want MSP is updated by compiler-generated
* code during stack switch.
*
* Don't allow extended assembly in naked functions:
* The compiler only supports basic __asm statements in __attribute__((naked))
* functions. Using extended assembly, parameter references or mixing C code with
* __asm statements might not work reliably.
*/
__attribute__((naked)) void Reset_Handler(void)
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined(__GNUC__)
__asm(".syntax unified \n");
#endif
/* Jump to Reset_Handler_1 */
#if !defined(__ICCARM__)
__asm("movw r0, #:lower16:Reset_Handler_1 \n");
__asm("movt r0, #:upper16:Reset_Handler_1 \n");
#else
__asm("mov32 r0, Reset_Handler_1 \n");
#endif
__asm("bx r0 \n");
}
void Reset_Handler_1(void)
{
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Disable register write-protection function */
SYS_UnlockReg();
@ -339,38 +381,61 @@ void Reset_Handler(void)
SYS_LockReg();
#endif
/**
* SystemInit() must be called at the very start.
*/
/* SystemInit() must be called at the very start. */
SystemInit();
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#if defined(__ARMCC_VERSION)
__main();
#elif defined(__ICCARM__)
__iar_program_start();
#elif defined(__GNUC__)
uint32_t *src_ind = (uint32_t *) &__etext;
uint32_t *dst_ind = (uint32_t *) &__data_start__;
uint32_t *dst_end = (uint32_t *) &__data_end__;
/* Move (multiple) .data section(s) from ROM to RAM */
{
/* Struct of copy table entry which must match linker script */
typedef struct copy_table_entry_ {
uint32_t src; // Address to copy from
uint32_t dst; // Address to copy to
uint32_t size; // Copy size in bytes
} copy_table_entry;
/* Move .data section from ROM to RAM */
if (src_ind != dst_ind) {
for (; dst_ind < dst_end;) {
*dst_ind ++ = *src_ind ++;
copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__;
copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__;
for (; copy_table_ind != copy_table_end; copy_table_ind ++) {
uint32_t *src_ind = (uint32_t *) copy_table_ind->src;
uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size);
uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst;
if (src_ind != dst_ind) {
for (; src_ind < src_end;) {
*dst_ind ++ = *src_ind ++;
}
}
}
}
/* Initialize .bss section to zero */
dst_ind = (uint32_t *) &__bss_start__;
dst_end = (uint32_t *) &__bss_end__;
if (dst_ind != dst_end) {
for (; dst_ind < dst_end;) {
*dst_ind ++ = 0;
/* Initialize (multiple) .bss sections to zero */
{
/* Struct of zero table entry which must match linker script */
typedef struct zero_table_entry_ {
uint32_t start; // Address to start zero'ing
uint32_t size; // Zero size in bytes
} zero_table_entry;
zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__;
zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__;
for (; zero_table_ind != zero_table_end; zero_table_ind ++) {
uint32_t *dst_ind = (uint32_t *) zero_table_ind->start;
uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size);
for (; dst_ind < dst_end; ) {
*dst_ind ++ = 0;
}
}
}
_start();
#endif
@ -386,18 +451,3 @@ void Default_Handler(void)
{
while (1);
}
#if 0
#if defined(__CC_ARM)
uint32_t GetPC(void)
{
uint32_t val=0;
__asm {
MOV R0, #0 // dumy
//MOV R0, LR // Except R0~R12, SP/LR/PC cannot be read or directly modified in inline assembly code
MOV val, R0
}
return val;
}
#endif
#endif

12
targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c
View File

@ -87,7 +87,7 @@ static const flash_algo_t flash_algo_config = {
/* Secure flash */
static const sector_info_t sectors_info[] = {
{NU_ROM_START_S, 0x800}, // (start, sector size)
{NU_FLASHIAP_SECURE_START, 0x800}, // (start, sector size)
};
/* Secure flash */
@ -95,15 +95,15 @@ static const flash_target_config_t flash_target_config = {
.page_size = 4, // 4 bytes
// Here page_size is program unit, which is different
// than FMC definition.
.flash_start = NU_ROM_START_S,
.flash_size = NU_ROM_SIZE_S,
.flash_start = NU_FLASHIAP_SECURE_START,
.flash_size = NU_FLASHIAP_SECURE_SIZE,
.sectors = sectors_info,
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
};
/* Non-secure flash */
static const sector_info_t sectors_info_ns[] = {
{NU_ROM_START_NS, 0x800}, // (start, sector size)
{NU_FLASHIAP_NONSECURE_START, 0x800}, // (start, sector size)
};
/* Non-secure flash */
@ -111,8 +111,8 @@ static const flash_target_config_t flash_target_config_ns = {
.page_size = 4, // 4 bytes
// Here page_size is program unit, which is different
// than FMC definition.
.flash_start = NU_ROM_START_NS,
.flash_size = NU_ROM_SIZE_NS,
.flash_start = NU_FLASHIAP_NONSECURE_START,
.flash_size = NU_FLASHIAP_NONSECURE_SIZE,
.sectors = sectors_info_ns,
.sector_info_count = sizeof(sectors_info_ns) / sizeof(sector_info_t)
};

9
targets/TARGET_NUVOTON/TARGET_M2351/i2c_api.c
View File

@ -25,6 +25,7 @@
#include "nu_miscutil.h"
#include "nu_bitutil.h"
#include "mbed_critical.h"
#include "us_ticker_api.h"
struct nu_i2c_var {
i2c_t * obj;
@ -463,6 +464,8 @@ static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uin
{
uint32_t t1, t2, elapsed = 0;
int status_assert = 0;
const uint32_t bits = us_ticker_get_info()->bits;
const uint32_t mask = (1 << bits) - 1;
t1 = us_ticker_read();
while (1) {
@ -472,7 +475,7 @@ static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uin
}
t2 = us_ticker_read();
elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1);
if (elapsed >= timeout) {
break;
}
@ -487,6 +490,8 @@ static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
int tran_started;
char *tran_pos = NULL;
char *tran_pos2 = NULL;
const uint32_t bits = us_ticker_get_info()->bits;
const uint32_t mask = (1 << bits) - 1;
i2c_disable_int(obj);
tran_pos = obj->i2c.tran_pos;
@ -510,7 +515,7 @@ static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
continue;
}
elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1);
if (elapsed >= timeout) { // Transfer idle
break;
}

92
targets/TARGET_NUVOTON/TARGET_M2351/rtc_api.c
View File

@ -26,10 +26,13 @@
#include "partition_M2351.h"
#include "hal_secure.h"
/* NOTE: BSP RTC driver judges secure/non-secure RTC by PC. This implementation cannot support non-secure RTC
* controlled by secure executable. A better way would be that secure/non-secure RTC base is passed
* to RTC API as an argument like most other APIs. With BSP RTC driver unchanged, we must enforce
* secure RTC. */
/* Secure attribution of RTC
*
* We need RTC to be secure for security concern.
*
* On M2351, configured to secure
* On M2354, hard-wired to secure
*/
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 1))
#error("Limited by BSP/RTC, we can only support secure RTC.")
#endif
@ -67,7 +70,7 @@ void rtc_write(time_t t)
*
* NOTE: This dependents on real hardware.
*/
#define NU_RTCCLK_PER_SEC ((CLK->CLKSEL3 & CLK_CLKSEL3_SC0SEL_Msk) ? __LIRC : __LXT)
#define NU_RTCCLK_PER_SEC (__LXT)
/* Strategy for implementation of RTC HAL
*
@ -121,35 +124,37 @@ static time_t t_write = 0;
/* Convert date time from H/W RTC to struct TM */
static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
__NONSECURE_ENTRY
void rtc_init_s(void)
static void rtc_init_impl(void);
static void rtc_free_impl(void);
static int32_t rtc_isenabled_impl(void);
static int64_t rtc_read_impl(void);
static void rtc_write_impl(int64_t t);
static void rtc_init_impl(void)
{
if (rtc_isenabled()) {
if (rtc_isenabled_impl()) {
return;
}
RTC_Open(NULL);
/* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
rtc_write(0);
rtc_write_impl(0);
}
__NONSECURE_ENTRY
void rtc_free_s(void)
static void rtc_free_impl(void)
{
CLK_DisableModuleClock_S(rtc_modinit.clkidx);
}
__NONSECURE_ENTRY
int32_t rtc_isenabled_s(void)
static int32_t rtc_isenabled_impl(void)
{
// NOTE: To access (RTC) registers, clock must be enabled first.
if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
// Enable IP clock
CLK_EnableModuleClock_S(rtc_modinit.clkidx);
}
// To access (RTC) registers, clock must be enabled first.
// For TZ, with RTC being secure, we needn't call the secure gateway versions.
CLK_EnableModuleClock(rtc_modinit.clkidx);
CLK_SetModuleClock(rtc_modinit.clkidx, rtc_modinit.clksrc, rtc_modinit.clkdiv);
RTC_T *rtc_base = (RTC_T *) NU_MODBASE(rtc_modinit.modname);
@ -157,16 +162,15 @@ int32_t rtc_isenabled_s(void)
return !! (rtc_base->INIT & RTC_INIT_ACTIVE_Msk);
}
__NONSECURE_ENTRY
int64_t rtc_read_s(void)
static int64_t rtc_read_impl(void)
{
/* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
* RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
* NUC472/M453: Known issue
* M487: Fixed
*/
if (! rtc_isenabled()) {
rtc_init();
if (! rtc_isenabled_impl()) {
rtc_init_impl();
}
/* Used for intermediary between date time of H/W RTC and POSIX time */
@ -206,11 +210,10 @@ int64_t rtc_read_s(void)
return t_present;
}
__NONSECURE_ENTRY
void rtc_write_s(int64_t t)
static void rtc_write_impl(int64_t t)
{
if (! rtc_isenabled()) {
rtc_init();
if (! rtc_isenabled_impl()) {
rtc_init_impl();
}
t_write = t;
@ -255,4 +258,39 @@ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC
}
#endif
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY
void rtc_init_s(void)
{
rtc_init_impl();
}
__NONSECURE_ENTRY
void rtc_free_s(void)
{
rtc_free_impl();
}
__NONSECURE_ENTRY
int32_t rtc_isenabled_s(void)
{
return rtc_isenabled_impl();
}
__NONSECURE_ENTRY
int64_t rtc_read_s(void)
{
return rtc_read_impl();
}
__NONSECURE_ENTRY
void rtc_write_s(int64_t t)
{
rtc_write_impl(t);
}
#endif
#endif

362
targets/TARGET_NUVOTON/TARGET_M2354/PeripheralNames.h Normal file
View File

@ -0,0 +1,362 @@
/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "partition_M2354.h"
#ifdef __cplusplus
extern "C" {
#endif
// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
// which encodes module base address and module index/subindex.
#define NU_MODSUBINDEX_Pos 0
#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
#define NU_MODINDEX_Pos 20
#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
#if 0
typedef enum {
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 0))
GPIO_A = (int) NU_MODNAME(GPIOA_BASE + NS_OFFSET, 0, 0),
#else
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 1))
GPIO_B = (int) NU_MODNAME(GPIOB_BASE + NS_OFFSET, 1, 0),
#else
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 2))
GPIO_C = (int) NU_MODNAME(GPIOC_BASE + NS_OFFSET, 2, 0),
#else
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 3))
GPIO_D = (int) NU_MODNAME(GPIOD_BASE + NS_OFFSET, 3, 0),
#else
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 4))
GPIO_E = (int) NU_MODNAME(GPIOE_BASE + NS_OFFSET, 4, 0),
#else
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 5))
GPIO_F = (int) NU_MODNAME(GPIOF_BASE + NS_OFFSET, 5, 0),
#else
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 6))
GPIO_G = (int) NU_MODNAME(GPIOG_BASE + NS_OFFSET, 6, 0),
#else
GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 7))
GPIO_H = (int) NU_MODNAME(GPIOH_BASE + NS_OFFSET, 7, 0),
#else
GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0),
#endif
} GPIOName;
#endif
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 3))
ADC_0_0 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 15),
#else
ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC_BASE, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC_BASE, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC_BASE, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC_BASE, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC_BASE, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC_BASE, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC_BASE, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC_BASE, 0, 15),
#endif
} ADCName;
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 7))
DAC_0_0 = (int) NU_MODNAME(DAC0_BASE + NS_OFFSET, 0, 0),
DAC_1_0 = (int) NU_MODNAME(DAC1_BASE + NS_OFFSET, 1, 0),
#else
DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0),
DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0),
#endif
} DACName;
typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 16))
UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0),
#else
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 17))
UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0),
#else
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 18))
UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0),
#else
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 19))
UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0),
#else
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 20))
UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0),
#else
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 21))
UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0),
#else
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
#endif
// NOTE: board-specific
#if defined(MBED_CONF_TARGET_USB_UART)
USB_UART = MBED_CONF_TARGET_USB_UART,
#else
USB_UART = NC,
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART)
STDIO_UART = MBED_CONF_TARGET_STDIO_UART,
#else
STDIO_UART = USB_UART,
#endif
} UARTName;
typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 1))
SPI_0 = (int) NU_MODNAME(SPI0_BASE + NS_OFFSET, 0, 0),
#else
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 2))
SPI_1 = (int) NU_MODNAME(SPI1_BASE + NS_OFFSET, 1, 0),
#else
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 3))
SPI_2 = (int) NU_MODNAME(SPI2_BASE + NS_OFFSET, 2, 0),
#else
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
#endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 4))
SPI_3 = (int) NU_MODNAME(SPI3_BASE + NS_OFFSET, 3, 0),
#else
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0),
#endif
/* No SPI4 H/W, degrade QSPI0 H/W to SPI_4 for standard SPI usage */
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 0))
SPI_4 = (int) NU_MODNAME(QSPI0_BASE + NS_OFFSET, 4, 0),
#else
SPI_4 = (int) NU_MODNAME(QSPI0_BASE, 4, 0),
#endif
} SPIName;
typedef enum {
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 0))
I2C_0 = (int) NU_MODNAME(I2C0_BASE + NS_OFFSET, 0, 0),
#else
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
#endif
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 1))
I2C_1 = (int) NU_MODNAME(I2C1_BASE + NS_OFFSET, 1, 0),
#else
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0),
#endif
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 2))
I2C_2 = (int) NU_MODNAME(I2C2_BASE + NS_OFFSET, 2, 0),
#else
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0),
#endif
} I2CName;
typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 24))
PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 0),
PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 1),
PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 2),
PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 3),
PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 4),
PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 5),
#else
PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE, 0, 0),
PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE, 0, 1),
PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE, 0, 2),
PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE, 0, 3),
PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE, 0, 4),
PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE, 0, 5),
#endif
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 25))
PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 0),
PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 1),
PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 2),
PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 3),
PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 4),
PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 5),
#else
PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE, 1, 0),
PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE, 1, 1),
PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE, 1, 2),
PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE, 1, 3),
PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE, 1, 4),
PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE, 1, 5),
#endif
} PWMName;
typedef enum {
/* TMR0/1 are hard-wired to Secure mode */
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 17))
TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
#else
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0),
#endif
} TIMERName;
typedef enum {
/* RTC0 is hard-wired to Secure mode */
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0),
} RTCName;
typedef enum {
/* PDMA0 is hard-wired to Secure mode. */
DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0),
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 24))
DMA_1 = (int) NU_MODNAME(PDMA1_BASE + NS_OFFSET, 1, 0),
#else
DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0),
#endif
} DMAName;
typedef enum {
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 13))
SD_0 = (int) NU_MODNAME(SDH0_BASE + NS_OFFSET, 0, 0),
#else
SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0),
#endif
} SDName;
typedef enum {
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 0))
CAN_0 = (int) NU_MODNAME(CAN0_BASE + NS_OFFSET, 0, 0),
#else
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0),
#endif
} CANName;
typedef enum {
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 25))
TRNG_0 = (int) NU_MODNAME(TRNG_BASE + NS_OFFSET, 0, 0),
#else
TRNG_0 = (int) NU_MODNAME(TRNG_BASE, 0, 0),
#endif
} TRNGName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.c Normal file
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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
//*** ADC ***
const PinMap PinMap_ADC[] = {
{PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0},
{PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1},
{PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2},
{PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3},
{PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4},
{PB_5, ADC_0_5, SYS_GPB_MFPL_PB5MFP_EADC0_CH5},
{PB_6, ADC_0_6, SYS_GPB_MFPL_PB6MFP_EADC0_CH6},
{PB_7, ADC_0_7, SYS_GPB_MFPL_PB7MFP_EADC0_CH7},
{PB_8, ADC_0_8, SYS_GPB_MFPH_PB8MFP_EADC0_CH8},
{PB_9, ADC_0_9, SYS_GPB_MFPH_PB9MFP_EADC0_CH9},
{PB_10, ADC_0_10, SYS_GPB_MFPH_PB10MFP_EADC0_CH10},
{PB_11, ADC_0_11, SYS_GPB_MFPH_PB11MFP_EADC0_CH11},
{PB_12, ADC_0_12, SYS_GPB_MFPH_PB12MFP_EADC0_CH12},
{PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13},
{PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14},
{PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15},
{NC, NC, 0}
};
//*** DAC ***
const PinMap PinMap_DAC[] = {
{PB_12, DAC_0_0, SYS_GPB_MFPH_PB12MFP_DAC0_OUT},
{PB_13, DAC_1_0, SYS_GPB_MFPH_PB13MFP_DAC1_OUT},
{NC, NC, 0}
};
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
{PA_0, I2C_2, SYS_GPA_MFPL_PA0MFP_I2C2_SDA},
{PA_2, I2C_1, SYS_GPA_MFPL_PA2MFP_I2C1_SDA},
{PA_4, I2C_0, SYS_GPA_MFPL_PA4MFP_I2C0_SDA},
{PA_6, I2C_1, SYS_GPA_MFPL_PA6MFP_I2C1_SDA},
{PA_10, I2C_2, SYS_GPA_MFPH_PA10MFP_I2C2_SDA},
{PA_13, I2C_1, SYS_GPA_MFPH_PA13MFP_I2C1_SDA},
{PA_15, I2C_2, SYS_GPA_MFPH_PA15MFP_I2C2_SDA},
{PB_0, I2C_1, SYS_GPB_MFPL_PB0MFP_I2C1_SDA},
{PB_2, I2C_1, SYS_GPB_MFPL_PB2MFP_I2C1_SDA},
{PB_4, I2C_0, SYS_GPB_MFPL_PB4MFP_I2C0_SDA},
{PB_8, I2C_0, SYS_GPB_MFPH_PB8MFP_I2C0_SDA},
{PB_10, I2C_1, SYS_GPB_MFPH_PB10MFP_I2C1_SDA},
{PB_12, I2C_2, SYS_GPB_MFPH_PB12MFP_I2C2_SDA},
{PC_0, I2C_0, SYS_GPC_MFPL_PC0MFP_I2C0_SDA},
{PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SDA},
{PC_8, I2C_0, SYS_GPC_MFPH_PC8MFP_I2C0_SDA},
{PC_11, I2C_0, SYS_GPC_MFPH_PC11MFP_I2C0_SDA},
{PD_0, I2C_2, SYS_GPD_MFPL_PD0MFP_I2C2_SDA},
{PD_4, I2C_1, SYS_GPD_MFPL_PD4MFP_I2C1_SDA},
{PD_6, I2C_0, SYS_GPD_MFPL_PD6MFP_I2C0_SDA},
{PD_8, I2C_2, SYS_GPD_MFPH_PD8MFP_I2C2_SDA},
{PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
{PF_1, I2C_1, SYS_GPF_MFPL_PF1MFP_I2C1_SDA},
{PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA},
{PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA},
{PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PA_1, I2C_2, SYS_GPA_MFPL_PA1MFP_I2C2_SCL},
{PA_3, I2C_1, SYS_GPA_MFPL_PA3MFP_I2C1_SCL},
{PA_5, I2C_0, SYS_GPA_MFPL_PA5MFP_I2C0_SCL},
{PA_7, I2C_1, SYS_GPA_MFPL_PA7MFP_I2C1_SCL},
{PA_11, I2C_2, SYS_GPA_MFPH_PA11MFP_I2C2_SCL},
{PA_12, I2C_1, SYS_GPA_MFPH_PA12MFP_I2C1_SCL},
{PA_14, I2C_2, SYS_GPA_MFPH_PA14MFP_I2C2_SCL},
{PB_1, I2C_1, SYS_GPB_MFPL_PB1MFP_I2C1_SCL},
{PB_3, I2C_1, SYS_GPB_MFPL_PB3MFP_I2C1_SCL},
{PB_5, I2C_0, SYS_GPB_MFPL_PB5MFP_I2C0_SCL},
{PB_9, I2C_0, SYS_GPB_MFPH_PB9MFP_I2C0_SCL},
{PB_11, I2C_1, SYS_GPB_MFPH_PB11MFP_I2C1_SCL},
{PB_13, I2C_2, SYS_GPB_MFPH_PB13MFP_I2C2_SCL},
{PC_1, I2C_0, SYS_GPC_MFPL_PC1MFP_I2C0_SCL},
{PC_5, I2C_1, SYS_GPC_MFPL_PC5MFP_I2C1_SCL},
{PC_12, I2C_0, SYS_GPC_MFPH_PC12MFP_I2C0_SCL},
{PD_1, I2C_2, SYS_GPD_MFPL_PD1MFP_I2C2_SCL},
{PD_5, I2C_1, SYS_GPD_MFPL_PD5MFP_I2C1_SCL},
{PD_7, I2C_0, SYS_GPD_MFPL_PD7MFP_I2C0_SCL},
{PD_9, I2C_2, SYS_GPD_MFPH_PD9MFP_I2C2_SCL},
{PE_1, I2C_1, SYS_GPE_MFPL_PE1MFP_I2C1_SCL},
{PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SCL},
{PF_0, I2C_1, SYS_GPF_MFPL_PF0MFP_I2C1_SCL},
{PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL},
{PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL},
{PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL},
{NC, NC, 0}
};
//*** PWM ***
const PinMap PinMap_PWM[] = {
{PA_0, PWM_0_5, SYS_GPA_MFPL_PA0MFP_EPWM0_CH5},
{PA_1, PWM_0_4, SYS_GPA_MFPL_PA1MFP_EPWM0_CH4},
{PA_2, PWM_0_3, SYS_GPA_MFPL_PA2MFP_EPWM0_CH3},
{PA_3, PWM_0_2, SYS_GPA_MFPL_PA3MFP_EPWM0_CH2},
{PA_4, PWM_0_1, SYS_GPA_MFPL_PA4MFP_EPWM0_CH1},
{PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_EPWM0_CH0},
{PA_6, PWM_1_5, SYS_GPA_MFPL_PA6MFP_EPWM1_CH5},
{PA_7, PWM_1_4, SYS_GPA_MFPL_PA7MFP_EPWM1_CH4},
{PB_0, PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
{NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
{PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
{NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
{PB_1, PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
{NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
{PB_1, PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
{NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
{PB_2, PWM_0_3, SYS_GPB_MFPL_PB2MFP_EPWM0_CH3},
{PB_3, PWM_0_2, SYS_GPB_MFPL_PB3MFP_EPWM0_CH2},
{PB_4, PWM_0_1, SYS_GPB_MFPL_PB4MFP_EPWM0_CH1},
{PB_5, PWM_0_0, SYS_GPB_MFPL_PB5MFP_EPWM0_CH0},
{PB_6, PWM_1_5, SYS_GPB_MFPL_PB6MFP_EPWM1_CH5},
{PB_7, PWM_1_4, SYS_GPB_MFPL_PB7MFP_EPWM1_CH4},
{PB_12, PWM_1_3, SYS_GPB_MFPH_PB12MFP_EPWM1_CH3},
{PB_13, PWM_1_2, SYS_GPB_MFPH_PB13MFP_EPWM1_CH2},
{PB_14, PWM_1_1, SYS_GPB_MFPH_PB14MFP_EPWM1_CH1},
{PB_15, PWM_1_0, SYS_GPB_MFPH_PB15MFP_EPWM1_CH0},
{PC_0, PWM_1_5, SYS_GPC_MFPL_PC0MFP_EPWM1_CH5},
{PC_1, PWM_1_4, SYS_GPC_MFPL_PC1MFP_EPWM1_CH4},
{PC_2, PWM_1_3, SYS_GPC_MFPL_PC2MFP_EPWM1_CH3},
{PC_3, PWM_1_2, SYS_GPC_MFPL_PC3MFP_EPWM1_CH2},
{PC_4, PWM_1_1, SYS_GPC_MFPL_PC4MFP_EPWM1_CH1},
{PC_5, PWM_1_0, SYS_GPC_MFPL_PC5MFP_EPWM1_CH0},
{PC_6, PWM_1_3, SYS_GPC_MFPL_PC6MFP_EPWM1_CH3},
{PC_7, PWM_1_2, SYS_GPC_MFPL_PC7MFP_EPWM1_CH2},
{PC_8, PWM_1_1, SYS_GPC_MFPH_PC8MFP_EPWM1_CH1},
{PC_9, PWM_1_3, SYS_GPC_MFPH_PC9MFP_EPWM1_CH3},
{PC_10, PWM_1_2, SYS_GPC_MFPH_PC10MFP_EPWM1_CH2},
{PC_11, PWM_1_1, SYS_GPC_MFPH_PC11MFP_EPWM1_CH1},
{PC_12, PWM_1_0, SYS_GPC_MFPH_PC12MFP_EPWM1_CH0},
{PD_14, PWM_0_4, SYS_GPD_MFPH_PD14MFP_EPWM0_CH4},
{PE_2, PWM_0_5, SYS_GPE_MFPL_PE2MFP_EPWM0_CH5},
{PE_3, PWM_0_4, SYS_GPE_MFPL_PE3MFP_EPWM0_CH4},
{PE_4, PWM_0_3, SYS_GPE_MFPL_PE4MFP_EPWM0_CH3},
{PE_5, PWM_0_2, SYS_GPE_MFPL_PE5MFP_EPWM0_CH2},
{PE_6, PWM_0_1, SYS_GPE_MFPL_PE6MFP_EPWM0_CH1},
{PE_7, PWM_0_0, SYS_GPE_MFPL_PE7MFP_EPWM0_CH0},
{PE_8, PWM_0_0, SYS_GPE_MFPH_PE8MFP_EPWM0_CH0},
{PE_9, PWM_0_1, SYS_GPE_MFPH_PE9MFP_EPWM0_CH1},
{PE_10, PWM_0_2, SYS_GPE_MFPH_PE10MFP_EPWM0_CH2},
{PE_11, PWM_0_3, SYS_GPE_MFPH_PE11MFP_EPWM0_CH3},
{PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_EPWM0_CH4},
{PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
{NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
{PE_13, PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
{NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
{PF_4, PWM_0_1, SYS_GPF_MFPL_PF4MFP_EPWM0_CH1},
{PF_5, PWM_0_0, SYS_GPF_MFPL_PF5MFP_EPWM0_CH0},
{PH_11, PWM_0_5, SYS_GPH_MFPH_PH11MFP_EPWM0_CH5},
{NC, NC, 0}
};
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{PA_1, UART_0, SYS_GPA_MFPL_PA1MFP_UART0_TXD},
{PA_3, UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
{NU_PINNAME_BIND(PA_3, UART_1), UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
{PA_3, UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
{NU_PINNAME_BIND(PA_3, UART_4), UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
{PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_TXD},
{PA_5, UART_5, SYS_GPA_MFPL_PA5MFP_UART5_TXD},
{PA_7, UART_0, SYS_GPA_MFPL_PA7MFP_UART0_TXD},
{PA_9, UART_1, SYS_GPA_MFPH_PA9MFP_UART1_TXD},
{PA_12, UART_4, SYS_GPA_MFPH_PA12MFP_UART4_TXD},
{PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD},
{PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
{PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
{PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_TXD},
{PB_5, UART_5, SYS_GPB_MFPL_PB5MFP_UART5_TXD},
{PB_7, UART_1, SYS_GPB_MFPL_PB7MFP_UART1_TXD},
{PB_9, UART_0, SYS_GPB_MFPH_PB9MFP_UART0_TXD},
{PB_11, UART_4, SYS_GPB_MFPH_PB11MFP_UART4_TXD},
{PB_13, UART_0, SYS_GPB_MFPH_PB13MFP_UART0_TXD},
{PB_15, UART_3, SYS_GPB_MFPH_PB15MFP_UART3_TXD},
{PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_TXD},
{PC_3, UART_3, SYS_GPC_MFPL_PC3MFP_UART3_TXD},
{PC_5, UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
{NU_PINNAME_BIND(PC_5, UART_2), UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
{PC_5, UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
{NU_PINNAME_BIND(PC_5, UART_4), UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
{PC_7, UART_4, SYS_GPC_MFPL_PC7MFP_UART4_TXD},
{PC_10, UART_3, SYS_GPC_MFPH_PC10MFP_UART3_TXD},
{PC_12, UART_0, SYS_GPC_MFPH_PC12MFP_UART0_TXD},
{PC_13, UART_2, SYS_GPC_MFPH_PC13MFP_UART2_TXD},
{PD_1, UART_3, SYS_GPD_MFPL_PD1MFP_UART3_TXD},
{PD_3, UART_0, SYS_GPD_MFPL_PD3MFP_UART0_TXD},
{PD_7, UART_1, SYS_GPD_MFPL_PD7MFP_UART1_TXD},
{PD_11, UART_1, SYS_GPD_MFPH_PD11MFP_UART1_TXD},
{PE_1, UART_3, SYS_GPE_MFPL_PE1MFP_UART3_TXD},
{PE_7, UART_5, SYS_GPE_MFPL_PE7MFP_UART5_TXD},
{PE_8, UART_2, SYS_GPE_MFPH_PE8MFP_UART2_TXD},
{PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
{PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_TXD},
{PE_14, UART_2, SYS_GPE_MFPH_PE14MFP_UART2_TXD},
{PF_0, UART_0, SYS_GPF_MFPL_PF0MFP_UART0_TXD},
{PF_0, UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD},
{PF_3, UART_0, SYS_GPF_MFPL_PF3MFP_UART0_TXD},
{PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_TXD},
{PF_7, UART_4, SYS_GPF_MFPL_PF7MFP_UART4_TXD},
{PF_11, UART_5, SYS_GPF_MFPH_PF11MFP_UART5_TXD},
{PH_8, UART_1, SYS_GPH_MFPH_PH8MFP_UART1_TXD},
{PH_10, UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
{NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
{PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{PA_0, UART_0, SYS_GPA_MFPL_PA0MFP_UART0_RXD},
{PA_2, UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
{NU_PINNAME_BIND(PA_2, UART_1), UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
#if !COMPONENT_FPGA_CI_TEST_SHIELD || !TARGET_NU_M2354
/* Get around one pin-to-many peripherals issue to pass FPGA CI Test Shield tests */
{PA_2, UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
{NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
#endif
{PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_RXD},
{PA_4, UART_5, SYS_GPA_MFPL_PA4MFP_UART5_RXD},
{PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD},
{PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD},
{PA_13, UART_4, SYS_GPA_MFPH_PA13MFP_UART4_RXD},
{PA_15, UART_0, SYS_GPA_MFPH_PA15MFP_UART0_RXD},
{PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
{PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
{PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_RXD},
{PB_4, UART_5, SYS_GPB_MFPL_PB4MFP_UART5_RXD},
{PB_6, UART_1, SYS_GPB_MFPL_PB6MFP_UART1_RXD},
{PB_8, UART_0, SYS_GPB_MFPH_PB8MFP_UART0_RXD},
#if !COMPONENT_FPGA_CI_TEST_SHIELD || !TARGET_NU_M2354
/* Need NU_PINNAME_BIND(...) to pick up the correct peripheral on
* the TX part. Remove to pass FPGA CI Test Shield tests. */
{PB_10, UART_4, SYS_GPB_MFPH_PB10MFP_UART4_RXD},
#endif
{PB_12, UART_0, SYS_GPB_MFPH_PB12MFP_UART0_RXD},
{PB_14, UART_3, SYS_GPB_MFPH_PB14MFP_UART3_RXD},
{PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_RXD},
{PC_2, UART_3, SYS_GPC_MFPL_PC2MFP_UART3_RXD},
{PC_4, UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
{NU_PINNAME_BIND(PC_4, UART_2), UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
{PC_4, UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
{NU_PINNAME_BIND(PC_4, UART_4), UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
{PC_6, UART_4, SYS_GPC_MFPL_PC6MFP_UART4_RXD},
{PC_8, UART_1, SYS_GPC_MFPH_PC8MFP_UART1_RXD},
{PC_9, UART_3, SYS_GPC_MFPH_PC9MFP_UART3_RXD},
{PC_11, UART_0, SYS_GPC_MFPH_PC11MFP_UART0_RXD},
{PD_0, UART_3, SYS_GPD_MFPL_PD0MFP_UART3_RXD},
{PD_2, UART_0, SYS_GPD_MFPL_PD2MFP_UART0_RXD},
{PD_6, UART_1, SYS_GPD_MFPL_PD6MFP_UART1_RXD},
{PD_10, UART_1, SYS_GPD_MFPH_PD10MFP_UART1_RXD},
{PD_12, UART_2, SYS_GPD_MFPH_PD12MFP_UART2_RXD},
{PE_0, UART_3, SYS_GPE_MFPL_PE0MFP_UART3_RXD},
{PE_6, UART_5, SYS_GPE_MFPL_PE6MFP_UART5_RXD},
{PE_9, UART_2, SYS_GPE_MFPH_PE9MFP_UART2_RXD},
{PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
{PE_15, UART_2, SYS_GPE_MFPH_PE15MFP_UART2_RXD},
{PF_1, UART_0, SYS_GPF_MFPL_PF1MFP_UART0_RXD},
{PF_1, UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD},
{PF_2, UART_0, SYS_GPF_MFPL_PF2MFP_UART0_RXD},
{PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_RXD},
{PF_6, UART_4, SYS_GPF_MFPL_PF6MFP_UART4_RXD},
{PF_10, UART_5, SYS_GPF_MFPH_PF10MFP_UART5_RXD},
{PH_9, UART_1, SYS_GPH_MFPH_PH9MFP_UART1_RXD},
{PH_11, UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
{NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
{PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nRTS},
{PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_nRTS},
{PB_3, UART_5, SYS_GPB_MFPL_PB3MFP_UART5_nRTS},
{PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
{PB_10, UART_0, SYS_GPB_MFPH_PB10MFP_UART0_nRTS},
{PB_13, UART_3, SYS_GPB_MFPH_PB13MFP_UART3_nRTS},
{PB_14, UART_0, SYS_GPB_MFPH_PB14MFP_UART0_nRTS},
{PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_nRTS},
{PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_nRTS},
{PD_3, UART_3, SYS_GPD_MFPL_PD3MFP_UART3_nRTS},
{PD_8, UART_2, SYS_GPD_MFPH_PD8MFP_UART2_nRTS},
{PE_0, UART_4, SYS_GPE_MFPL_PE0MFP_UART4_nRTS},
{PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_nRTS},
{PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS},
{PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS},
{PF_9, UART_5, SYS_GPF_MFPH_PF9MFP_UART5_nRTS},
{PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nCTS},
{PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_nCTS},
{PB_2, UART_5, SYS_GPB_MFPL_PB2MFP_UART5_nCTS},
{PB_9, UART_1, SYS_GPB_MFPH_PB9MFP_UART1_nCTS},
{PB_11, UART_0, SYS_GPB_MFPH_PB11MFP_UART0_nCTS},
{PB_12, UART_3, SYS_GPB_MFPH_PB12MFP_UART3_nCTS},
{PB_15, UART_0, SYS_GPB_MFPH_PB15MFP_UART0_nCTS},
{PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_nCTS},
{PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_nCTS},
{PC_8, UART_4, SYS_GPC_MFPH_PC8MFP_UART4_nCTS},
{PD_2, UART_3, SYS_GPD_MFPL_PD2MFP_UART3_nCTS},
{PD_9, UART_2, SYS_GPD_MFPH_PD9MFP_UART2_nCTS},
{PE_1, UART_4, SYS_GPE_MFPL_PE1MFP_UART4_nCTS},
{PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS},
{PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS},
{PF_8, UART_5, SYS_GPF_MFPH_PF8MFP_UART5_nCTS},
{PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS},
{NC, NC, 0}
};
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{PA_0, SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0},
{NU_PINNAME_BIND(PA_0, SPI_4), SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0},
{PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI},
{NU_PINNAME_BIND(PA_0, SPI_0), SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI},
{PA_8, SPI_2, SYS_GPA_MFPH_PA8MFP_SPI2_MOSI},
{PA_15, SPI_2, SYS_GPA_MFPH_PA15MFP_SPI2_MOSI},
{PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_MOSI},
{PB_8, SPI_3, SYS_GPB_MFPH_PB8MFP_SPI3_MOSI},
{PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI},
{PC_0, SPI_4, SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0},
{PC_2, SPI_1, SYS_GPC_MFPL_PC2MFP_SPI1_MOSI},
{PC_6, SPI_1, SYS_GPC_MFPL_PC6MFP_SPI1_MOSI},
{PC_11, SPI_3, SYS_GPC_MFPH_PC11MFP_SPI3_MOSI},
{PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI},
{PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_MOSI},
{PE_0, SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0},
{NU_PINNAME_BIND(PE_0, SPI_4), SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0},
{PE_0, SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI},
{NU_PINNAME_BIND(PE_0, SPI_1), SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI},
{PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI},
{PE_10, SPI_2, SYS_GPE_MFPH_PE10MFP_SPI2_MOSI},
{PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI},
{PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI},
{PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PA_1, SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0},
{NU_PINNAME_BIND(PA_1, SPI_4), SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0},
{PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO},
{NU_PINNAME_BIND(PA_1, SPI_0), SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO},
{PA_9, SPI_2, SYS_GPA_MFPH_PA9MFP_SPI2_MISO},
{PA_14, SPI_2, SYS_GPA_MFPH_PA14MFP_SPI2_MISO},
{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MISO},
{PB_9, SPI_3, SYS_GPB_MFPH_PB9MFP_SPI3_MISO},
{PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO},
{PC_1, SPI_4, SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0},
{PC_3, SPI_1, SYS_GPC_MFPL_PC3MFP_SPI1_MISO},
{PC_7, SPI_1, SYS_GPC_MFPL_PC7MFP_SPI1_MISO},
{PC_12, SPI_3, SYS_GPC_MFPH_PC12MFP_SPI3_MISO},
{PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO},
{PD_7, SPI_1, SYS_GPD_MFPL_PD7MFP_SPI1_MISO},
{PE_1, SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0},
{NU_PINNAME_BIND(PE_1, SPI_4), SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0},
{PE_1, SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO},
{NU_PINNAME_BIND(PE_1, SPI_1), SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO},
{PE_3, SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO},
{PE_9, SPI_2, SYS_GPE_MFPH_PE9MFP_SPI2_MISO},
{PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO},
{PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO},
{PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{PA_2, SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK},
{NU_PINNAME_BIND(PA_2, SPI_4), SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK},
{PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
{NU_PINNAME_BIND(PA_2, SPI_0), SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
{PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
{PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK},
{PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK},
{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK},
{PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK},
{PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK},
{PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK},
{PC_2, SPI_4, SYS_GPC_MFPL_PC2MFP_QSPI0_CLK},
{PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK},
{PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK},
{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK},
{PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK},
{PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK},
{PF_2, SPI_4, SYS_GPF_MFPL_PF2MFP_QSPI0_CLK},
{PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK},
{PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK},
{PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK},
{PH_8, SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK},
{NU_PINNAME_BIND(PH_8, SPI_4), SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK},
{PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK},
{NU_PINNAME_BIND(PH_8, SPI_1), SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PA_3, SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS},
{NU_PINNAME_BIND(PA_3, SPI_4), SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS},
{PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
{NU_PINNAME_BIND(PA_3, SPI_0), SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_SS},
{PA_11, SPI_2, SYS_GPA_MFPH_PA11MFP_SPI2_SS},
{PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_SS},
{PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_SS},
{PB_10, SPI_3, SYS_GPB_MFPH_PB10MFP_SPI3_SS},
{PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS},
{PC_0, SPI_1, SYS_GPC_MFPL_PC0MFP_SPI1_SS},
{PC_3, SPI_4, SYS_GPC_MFPL_PC3MFP_QSPI0_SS},
{PC_9, SPI_3, SYS_GPC_MFPH_PC9MFP_SPI3_SS},
{PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS},
{PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_SS},
{PE_5, SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS},
{PE_11, SPI_2, SYS_GPE_MFPH_PE11MFP_SPI2_SS},
{PF_9, SPI_0, SYS_GPF_MFPH_PF9MFP_SPI0_SS},
{PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS},
{PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS},
{PH_9, SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS},
{NU_PINNAME_BIND(PH_9, SPI_4), SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS},
{PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS},
{NU_PINNAME_BIND(PH_9, SPI_1), SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS},
{NC, NC, 0}
};
//*** SD ***
const PinMap PinMap_SD_DAT0[] = {
{PB_2, SD_0, SYS_GPB_MFPL_PB2MFP_SD0_DAT0},
{PE_2, SD_0, SYS_GPE_MFPL_PE2MFP_SD0_DAT0},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT1[] = {
{PB_3, SD_0, SYS_GPB_MFPL_PB3MFP_SD0_DAT1},
{PE_3, SD_0, SYS_GPE_MFPL_PE3MFP_SD0_DAT1},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT2[] = {
{PB_4, SD_0, SYS_GPB_MFPL_PB4MFP_SD0_DAT2},
{PE_4, SD_0, SYS_GPE_MFPL_PE4MFP_SD0_DAT2},
{NC, NC, 0}
};
const PinMap PinMap_SD_DAT3[] = {
{PB_5, SD_0, SYS_GPB_MFPL_PB5MFP_SD0_DAT3},
{PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_DAT3},
{NC, NC, 0}
};
const PinMap PinMap_SD_CMD[] = {
{PB_0, SD_0, SYS_GPB_MFPL_PB0MFP_SD0_CMD},
{PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CMD},
{NC, NC, 0}
};
const PinMap PinMap_SD_CLK[] = {
{PB_1, SD_0, SYS_GPB_MFPL_PB1MFP_SD0_CLK},
{PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CLK},
{NC, NC, 0}
};
const PinMap PinMap_SD_CD[] = {
{PB_12, SD_0, SYS_GPB_MFPH_PB12MFP_SD0_nCD},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{PA_5, CAN_0, SYS_GPA_MFPL_PA5MFP_CAN0_TXD},
{PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
{PB_11, CAN_0, SYS_GPB_MFPH_PB11MFP_CAN0_TXD},
{PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD},
{PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD},
{PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD},
{NC, NC, 0}
};
const PinMap PinMap_CAN_RD[] = {
{PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD},
{PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
{PB_10, CAN_0, SYS_GPB_MFPH_PB10MFP_CAN0_RXD},
{PC_4, CAN_0, SYS_GPC_MFPL_PC4MFP_CAN0_RXD},
{PD_10, CAN_0, SYS_GPD_MFPH_PD10MFP_CAN0_RXD},
{PE_15, CAN_0, SYS_GPE_MFPH_PE15MFP_CAN0_RXD},
{NC, NC, 0}
};

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
#ifdef __cplusplus
extern "C" {
#endif
//*** GPIO ***
extern const PinMap PinMap_GPIO[];
//*** ADC ***
extern const PinMap PinMap_ADC[];
//*** DAC ***
extern const PinMap PinMap_DAC[];
//*** I2C ***
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
//*** PWM ***
extern const PinMap PinMap_PWM[];
//*** SERIAL ***
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_RTS[];
extern const PinMap PinMap_UART_CTS[];
//*** SPI ***
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];
//*** SD ***
extern const PinMap PinMap_SD_CD[];
extern const PinMap PinMap_SD_CMD[];
extern const PinMap PinMap_SD_CLK[];
extern const PinMap PinMap_SD_DAT0[];
extern const PinMap PinMap_SD_DAT1[];
extern const PinMap PinMap_SD_DAT2[];
extern const PinMap PinMap_SD_DAT3[];
//*** CAN ***
extern PinMap const PinMap_CAN_TD[];
extern PinMap const PinMap_CAN_RD[];
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __PIN_NAMES_COMMON_H__
#define __PIN_NAMES_COMMON_H__
#include "cmsis.h"
#include "partition_M2354.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NU_PININDEX_Pos 0
#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
#define NU_PINPORT_Pos 8
#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
#define NU_PIN_MODINDEX_Pos 12
#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
#define NU_PIN_BIND_Pos 16
#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
#define NU_PINNAME_BIND(PINNAME, modname) ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname))
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
/* Revise NU_PORT_BASE to be TrustZone-aware */
__STATIC_INLINE GPIO_T *NU_PORT_BASE(uint32_t PORT)
{
uint32_t port_base = ((uint32_t) GPIOA_BASE) + 0x40 * PORT;
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
port_base += NS_OFFSET;
}
#endif
return ((GPIO_T *) port_base);
}
#define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
/* TrustZone-aware version of GPIO_PIN_DATA to get GPIO pin data */
__STATIC_INLINE uint32_t NU_GET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN)
{
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
return GPIO_PIN_DATA_NS(PORT, PIN);
}
#endif
return GPIO_PIN_DATA_S(PORT, PIN);
}
/* TrustZone-aware version of GPIO_PIN_DATA to set GPIO pin data */
__STATIC_INLINE void NU_SET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN, uint32_t VALUE)
{
#if defined(SCU_INIT_IONSSET_VAL)
if (SCU_INIT_IONSSET_VAL & (1 << (PORT + 0))) {
GPIO_PIN_DATA_NS(PORT, PIN) = VALUE;
return;
}
#endif
GPIO_PIN_DATA_S(PORT, PIN) = VALUE;
}
// LEGACY
#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
/* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
/* I/O mode */
InputOnly,
PushPullOutput,
OpenDrain,
QuasiBidirectional,
/* Default input pull mode */
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif // __PIN_NAMES_COMMON_H__

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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The M2354 is a TrustZone target that requires two programs: secure and nonsecure.
Secure program runs first to set up the secure environment and then brings up the nonsecure program. `NuMaker-mbed-TZ-secure-example.hex` is the pre-built secure image, and `cmse_lib.o` is its accompanying secure gateway library, which exports secure functions to nonsecure program.
It is built from the [non-PSA secure program template](https://github.com/OpenNuvoton/NuMaker-mbed-TZ-secure-example). Because secure program and nonsecure program may start at an address other than `0x0`, we have chosen `.hex` rather than `.bin` as the output format.
## Hardware partition
On TrustZone targets, you need to partition the hardware first for secure program to run on secure world and nonsecure program to run on nonsecure world.
The pre-built secure program will set up the following hardware partition:
- Flash (1024KiB in total): 96KiB for secure and 928KiB for nonsecure.
- SRAM (256KiB in total): 48KiB for secure and 208KiB for nonsecure.
- Peripherals: Most are configured to nonsecure except the following, which are hardwired or reserved:
- **SYS/CLK** hardwired to secure. Accessible to nonsecure through a secure gateway.
- **FMC** hardwired to secure. Accessible to nonsecure through a secure gateway.
- **WDT** hardwired to secure. Accessible to nonsecure through a secure gateway.
- **RTC** configured to secure. Accessible to nonsecure through a secure gateway.
- **TMR0/1** hardwired to secure. TMR0 implements secure `us_ticker`, and TMR1 implements secure `lp_ticker`.
- **TMR2/3** configured to nonsecure. TMR2 implements nonsecure `us_ticker`, and TMR3 implements nonsecure `lp_ticker`.
- **PDMA0** hardwired to secure. Implements secure asynchronous transfer.
- **PDMA1** configured to nonsecure. Implements nonsecure asynchronous transfer.
- **TRNG** configured to secure. Accessible to nonsecure through a secure gateway.
In this memory partition, secure program is the most simplified.
Then non-secure program can make use of the most memory available for its large application like Pelion.
To regenerate the default secure program, in [non-PSA secure program template](https://github.com/OpenNuvoton/NuMaker-mbed-TZ-secure-example), run:
```sh
$ mbed compile -m NU_M2354_NPSA_S -t ARMC6 --profile release
```
## Pre-built secure program files
- NuMaker-mbed-TZ-secure-example.hex
Pre-built secure image generated in non-PSA secure target build and to combine with non-secure image in non-PSA non-secure target post-build
- cmse_lib.o
Pre-built secure gateway library generated in non-PSA secure target build and to link with non-secure program in non-PSA non-secure target build
## Reference
Please refer to the [non-PSA secure program template](https://github.com/OpenNuvoton/NuMaker-mbed-TZ-secure-example) for details.

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#! armclang -E
/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2354_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 116))
{
}
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2354 GCC linker script file
*/
#include "../../../device/partition_M2354_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 116);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/* Stack Pointer (SP) configuration with GCC_ARM
*
* SP would go through the following configuration sequence:
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
* (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization)
*
* S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack
* is assigned conditionally according to Secure PSA or not.
*/
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2354_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 116);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };

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#! armclang -E
/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../../device/partition_M2354_mem.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START
{
/* load address = execution address */
ER_IROM1 +0
{
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
/* Boot stack requirement
*
* Secure non-PSA/Non-secure non-PSA/Non-secure PSA requires just one boot stack (MSP).
* Secure PSA(TFM) requires two boot stacks (MSP/PSP).
*/
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
{
}
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 116))
{
}
/* 16 byte-aligned */
RW_IRAM1 AlignExpr(+0, 16)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{
}
}
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{
ER_IROM_NSC NU_TZ_NSC_START FIXED PADVALUE 0xFFFFFFFF NU_TZ_NSC_SIZE
{
*(Veneer$$CMSE)
}
}
/* By IDAU, 0~0x800 is secure. NSC can only locate in 0x800~0x10000000. */
ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x800)
/* Heap must be allocated in RAM. */
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Nuvoton M2354 GCC linker script file
*/
#include "../../../device/partition_M2354_mem.h"
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
StackSize = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
FLASH_NSC (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
}
/**
* Must match cmsis_nvic.h
*/
__vector_size = 4 * (16 + 116);
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(8);
} > VECTORS
.copy.table : ALIGN(4)
{
__copy_table_start__ = .;
LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data))
__copy_table_end__ = .;
} > FLASH
.zero.table : ALIGN(4)
{
__zero_table_start__ = .;
LONG (ADDR(.bss))
LONG (SIZEOF(.bss))
__zero_table_end__ = .;
} > FLASH
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/* Stack Pointer (SP) configuration with GCC_ARM
*
* SP would go through the following configuration sequence:
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
* (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization)
*
* S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack
* is assigned conditionally according to Secure PSA or not.
*/
.stack (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. += StackSize;
__StackTop = .;
} > RAM_INTERN
PROVIDE(__stack = __StackTop);
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > FLASH
/* Relocate vector table in SRAM */
.isr_vector.reloc (NOLOAD) :
{
. = ALIGN(1 << LOG2CEIL(__vector_size));
PROVIDE(__start_vector_table__ = .);
. += __vector_size;
PROVIDE(__end_vector_table__ = .);
} > RAM_INTERN
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
/* All data end */
. = ALIGN(32);
__data_end__ = .;
} >RAM_INTERN AT>FLASH
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM_INTERN
/* Veneer$$CMSE : */
.gnu.sgstubs NU_TZ_NSC_START :
{
. = ALIGN(32);
__sgstubs_start = .;
*(.gnu.sgstubs.*)
__sgstubs_end = .;
. = ALIGN(32);
} > FLASH_NSC
/* NOTE: __sgstubs_end is not updated with *(.gnu.sgstubs.*). __sgstubs_start and
* __sgstubs_end are the same. GCC bug? */
Image$$ER_IROM_NSC$$Base = ADDR(.gnu.sgstubs);
ASSERT(SIZEOF(.gnu.sgstubs) <= NU_TZ_NSC_SIZE, "Size of .gnu.sgstubs region cannot exceed NU_TZ_NSC_SIZE.")
/* By IDAU, 0~0x800 is secure. NSC can only locate in 0x800~0x10000000. */
ASSERT(((__sgstubs_start % 32) == 0), "Requested by SAU, NSC region must start at 32 byte-aligned boundary.")
ASSERT(__sgstubs_start >= 0x800, "By IDAU, 0~0x800 is secure. NSC can only locate in 0x800~0x10000000.")
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
end = __end__;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
} > RAM_INTERN
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
}

73
targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_S/device/TOOLCHAIN_IAR/M2354.icf Normal file
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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
include "../../../device/partition_M2354_mem.icf.h";
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* FIXME: Check NSC area requirement */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 116);
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
/* IAR has something wrong with "$$" in section/block name. So unlike other toolchains,
* we name "ER_IROM_NSC" instead of "Image$$ER_IROM_NSC". */
define block ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place at address mem: NU_TZ_NSC_START { block ER_IROM_NSC };
place at start of IRAM_region { block CSTACK };
place in IRAM_region { block IRAMVEC };
place in IRAM_region { readwrite };
place in IRAM_region { block HEAP };
define exported symbol Image$$ER_IROM_NSC$$Base = NU_TZ_NSC_START;

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesCommon.h"
#include "partition_M2354.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
// Not connected
NC = (int)0xFFFFFFFF,
// Generic naming
PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13,
PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_14 = PD_12 + 2,
PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15,
PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11,
PG_2 = NU_PORT_N_PIN_TO_PINNAME(6, 2), PG_3, PG_4, PG_9 = PG_4 + 5, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15,
PH_4 = NU_PORT_N_PIN_TO_PINNAME(7, 4), PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11,
// Arduino UNO naming
A0 = PB_11,
A1 = PB_10,
A2 = PB_9,
A3 = PB_8,
A4 = PB_7,
A5 = PB_6,
D0 = PA_8,
D1 = PA_9,
D2 = PC_1,
D3 = PC_0,
D4 = PE_7,
D5 = PE_6,
D6 = PC_12,
D7 = PC_11,
D8 = PC_9,
D9 = PC_10,
D10 = PA_3,
D11 = PA_0,
D12 = PA_1,
D13 = PA_2,
D14 = PG_3,
D15 = PG_2,
// Other board-specific naming
// UART naming
#if defined(MBED_CONF_TARGET_USB_UART_TX)
USBTX = MBED_CONF_TARGET_USB_UART_TX,
#else
USBTX = NC,
#endif
#if defined(MBED_CONF_TARGET_USB_UART_RX)
USBRX = MBED_CONF_TARGET_USB_UART_RX,
#else
USBRX = NC,
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART_TX)
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
STDIO_UART_TX = USBTX,
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART_RX)
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
STDIO_UART_RX = USBRX,
#endif
// I2C naming
I2C_SCL = D15,
I2C_SDA = D14,
// LED naming
LED1 = PD_2,
LED2 = PD_3,
// Button naming
SW2 = PF_11,
BUTTON1 = SW2,
// Force PinName to 32-bit required by NU_PINNAME_BIND(...)
FORCE_ENUM_PINNAME_32BIT = 0x7FFFFFFF,
} PinName;
#ifdef __cplusplus
}
#endif
#endif // MBED_PINNAMES_H

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#if DEVICE_ANALOGIN
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "gpio_api.h"
#include "nu_modutil.h"
static uint32_t eadc_modinit_mask = 0;
static const struct nu_modinit_s adc_modinit_tab[] = {
{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL},
};
void analogin_init(analogin_t *obj, PinName pin)
{
obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName) NC);
const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == (int) obj->adc);
obj->pin = pin;
// Wire pinout
pinmap_pinout(pin, PinMap_ADC);
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
if (! eadc_modinit_mask) {
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
}
uint32_t chn = NU_MODSUBINDEX(obj->adc);
// Configure the sample module Nmod for analog input channel Nch and software trigger source
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn);
eadc_modinit_mask |= 1 << chn;
}
void analogin_free(analogin_t *obj)
{
const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
MBED_ASSERT(modinit->modname == (int) obj->adc);
/* Module subindex (aka channel) */
uint32_t chn = NU_MODSUBINDEX(obj->adc);
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
/* Channel-level windup from here */
/* Mark channel free */
eadc_modinit_mask &= ~(1 << chn);
/* Module-level windup from here */
/* See analogin_init() for reason */
if (! eadc_modinit_mask) {
/* Disable EADC module */
EADC_Close(eadc_base);
/* Disable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(modinit->clkidx);
}
/* Free up pins */
gpio_set(obj->pin);
obj->pin = NC;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
uint32_t chn = NU_MODSUBINDEX(obj->adc);
EADC_START_CONV(eadc_base, 1 << chn);
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn)));
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
// Just 12 bits are effective. Convert to 16 bits.
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
// conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
return conv_res_16;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = analogin_read_u16(obj);
return (float) value * (1.0f / (float) 0xFFFF);
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}
#endif

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogout_api.h"
#if DEVICE_ANALOGOUT
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "gpio_api.h"
#include "nu_modutil.h"
/* Maximum DAC modules */
#define NU_DACMOD_MAXNUM 2
/* Maximum DAC channels per module */
#define NU_DACCHN_MAXNUM 1
static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM];
static const struct nu_modinit_s dac_modinit_tab[] = {
{DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL},
{DAC_1_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}
};
void analogout_init(dac_t *obj, PinName pin)
{
obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT(obj->dac != (DACName) NC);
const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->dac);
/* Module index */
uint32_t modidx = NU_MODINDEX(obj->dac);
MBED_ASSERT(modidx < NU_DACMOD_MAXNUM);
/* Module subindex (aka channel) */
uint32_t chn = NU_MODSUBINDEX(obj->dac);
MBED_ASSERT(chn < NU_DACCHN_MAXNUM);
obj->pin = pin;
/* Wire pinout */
pinmap_pinout(pin, PinMap_DAC);
DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac);
/* Module-level setup from here */
/* DAC0/DAC1 are designed to share the same RESET/clock/IRQ for group
* function. So we:
*
* 1. Go to setup flow (analogout_init()) only when none of DAC0/DAC1
* channels are activated.
* 2. Go to windup flow (analogout_free()) only when all DAC0/DAC1
* channels are deactivated.
*/
if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
/* Select IP clock source and clock divider
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
/* Reset IP
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
/* The conversion settling time is 8us when 12-bit input code transition from
* lowest code (0x000) to highest code (0xFFF). */
DAC_SetDelayTime(dac_base, 8);
/* Configure DAT data format to left-aligned
* Effective 12-bits are aligned to left of 16-bit DAC_DAT. */
DAC_ENABLE_LEFT_ALIGN(dac_base);
}
/* Channel-level setup from here: */
/* Set the software trigger, enable DAC event trigger mode and enable D/A converter */
DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER);
/* Mark channel allocated */
dac_modinit_mask[modidx] |= 1 << chn;
}
void analogout_free(dac_t *obj)
{
const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->dac);
/* Module index */
uint32_t modidx = NU_MODINDEX(obj->dac);
MBED_ASSERT(modidx < NU_DACMOD_MAXNUM);
/* Module subindex (aka channel) */
uint32_t chn = NU_MODSUBINDEX(obj->dac);
MBED_ASSERT(chn < NU_DACCHN_MAXNUM);
DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac);
/* Channel-level windup from here */
/* Mark channel free */
dac_modinit_mask[modidx] &= ~(1 << chn);
/* Close channel */
DAC_Close(dac_base, chn);
/* Module-level windup from here: */
/* See analogout_init() for reason */
if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
/* Disable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(modinit->clkidx);
}
/* Free up pin */
gpio_set(obj->pin);
obj->pin = NC;
}
void analogout_write(dac_t *obj, float value)
{
if (value <= 0.0f) {
analogout_write_u16(obj, 0);
} else if (value >= 1.0f) {
analogout_write_u16(obj, 0xFFFF);
} else {
analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF)));
}
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac);
uint32_t chn = NU_MODSUBINDEX(obj->dac);
/* We should have configured DAC data format to left-aligned */
MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk);
DAC_WRITE_DATA(dac_base, chn, value);
/* Clear the DAC conversion complete finish flag for safe */
DAC_CLR_INT_FLAG(dac_base, chn);
/* Start A/D conversion */
DAC_START_CONV(dac_base);
/* Wait for completed */
while (DAC_IS_BUSY(dac_base, chn));
}
float analogout_read(dac_t *obj)
{
uint32_t value = analogout_read_u16(obj);
return (float) value * (1.0f / (float) 0xFFFF);
}
uint16_t analogout_read_u16(dac_t *obj)
{
DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac);
uint32_t chn = NU_MODSUBINDEX(obj->dac);
/* We should have configured DAC data format to left-aligned */
MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk);
uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn);
/* Just 12 bits are effective. Convert to 16 bits.
*
* dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000
* dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
*/
uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12);
return dat16;
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}
#endif

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "mbed_assert.h"
#include "mbed_atomic.h"
#include "mbed_critical.h"
#include "mbed_error.h"
#include <limits.h>
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include "crypto-misc.h"
#include "platform/SingletonPtr.h"
#include "platform/PlatformMutex.h"
#if defined(MBEDTLS_CONFIG_HW_SUPPORT)
/* Consideration for choosing proper synchronization mechanism
*
* 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee:
* (1) No deadlock
* We just lock mutex for a short sequence of operations rather than the whole lifetime
* of crypto context.
* (2) No priority inversion
* Mutex supports priority inheritance and it is enabled.
* 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee:
* (1) No deadlock
* With SHA AC not supporting context save & restore, we provide SHA S/W fallback when
* SHA AC is not available.
* (2) No biting CPU
* Same reason as above.
*/
/* Mutex for crypto AES AC management */
static SingletonPtr<PlatformMutex> crypto_aes_mutex;
/* Mutex for crypto DES AC management */
static SingletonPtr<PlatformMutex> crypto_des_mutex;
/* Mutex for crypto ECC AC management */
static SingletonPtr<PlatformMutex> crypto_ecc_mutex;
/* Atomic flag for crypto SHA AC management */
static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT;
/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */
static uint16_t crypto_init_counter = 0U;
/* Crypto done flags */
#define CRYPTO_DONE_OK BIT0 /* Done with OK */
#define CRYPTO_DONE_ERR BIT1 /* Done with error */
/* Track if PRNG H/W operation is done */
static volatile uint16_t crypto_prng_done;
/* Track if AES H/W operation is done */
static volatile uint16_t crypto_aes_done;
/* Track if DES H/W operation is done */
static volatile uint16_t crypto_des_done;
/* Track if ECC H/W operation is done */
static volatile uint16_t crypto_ecc_done;
static void crypto_submodule_prestart(volatile uint16_t *submodule_done);
static bool crypto_submodule_wait(volatile uint16_t *submodule_done);
/* As crypto init counter changes from 0 to 1:
*
* 1. Enable crypto clock
* 2. Enable crypto interrupt
*/
void crypto_init(void)
{
core_util_critical_section_enter();
if (crypto_init_counter == USHRT_MAX) {
core_util_critical_section_exit();
error("Crypto clock enable counter would overflow (> USHRT_MAX)");
}
core_util_atomic_incr_u16(&crypto_init_counter, 1);
if (crypto_init_counter == 1) {
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(CRPT_MODULE);
NVIC_EnableIRQ(CRPT_IRQn);
}
core_util_critical_section_exit();
}
/* As crypto init counter changes from 1 to 0:
*
* 1. Disable crypto interrupt
* 2. Disable crypto clock
*/
void crypto_uninit(void)
{
core_util_critical_section_enter();
if (crypto_init_counter == 0) {
core_util_critical_section_exit();
error("Crypto clock enable counter would underflow (< 0)");
}
core_util_atomic_decr_u16(&crypto_init_counter, 1);
if (crypto_init_counter == 0) {
NVIC_DisableIRQ(CRPT_IRQn);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(CRPT_MODULE);
}
core_util_critical_section_exit();
}
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (volatile unsigned char*) v;
while (n--) {
*p++ = 0;
}
}
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize32(uint32_t *v, size_t n)
{
volatile uint32_t *p = (volatile uint32_t*) v;
while (n--) {
*p++ = 0;
}
}
void crypto_aes_acquire(void)
{
/* Don't check return code of Mutex::lock(void)
*
* This function treats RTOS errors as fatal system errors, so it can only return osOK.
* Use of the return value is deprecated, as the return is expected to become void in
* the future.
*/
crypto_aes_mutex->lock();
}
void crypto_aes_release(void)
{
crypto_aes_mutex->unlock();
}
void crypto_des_acquire(void)
{
/* Don't check return code of Mutex::lock(void) */
crypto_des_mutex->lock();
}
void crypto_des_release(void)
{
crypto_des_mutex->unlock();
}
void crypto_ecc_acquire(void)
{
/* Don't check return code of Mutex::lock(void) */
crypto_ecc_mutex->lock();
}
void crypto_ecc_release(void)
{
crypto_ecc_mutex->unlock();
}
bool crypto_sha_try_acquire(void)
{
return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag);
}
void crypto_sha_release(void)
{
core_util_atomic_flag_clear(&crypto_sha_atomic_flag);
}
void crypto_prng_prestart(void)
{
crypto_submodule_prestart(&crypto_prng_done);
}
bool crypto_prng_wait(void)
{
return crypto_submodule_wait(&crypto_prng_done);
}
void crypto_aes_prestart(void)
{
crypto_submodule_prestart(&crypto_aes_done);
}
bool crypto_aes_wait(void)
{
return crypto_submodule_wait(&crypto_aes_done);
}
void crypto_des_prestart(void)
{
crypto_submodule_prestart(&crypto_des_done);
}
bool crypto_des_wait(void)
{
return crypto_submodule_wait(&crypto_des_done);
}
void crypto_ecc_prestart(void)
{
crypto_submodule_prestart(&crypto_ecc_done);
}
bool crypto_ecc_wait(void)
{
return crypto_submodule_wait(&crypto_ecc_done);
}
bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to)
{
uint32_t buff_ = (uint32_t) buff;
return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */
((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */
(((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */
}
/* Overlap cases
*
* 1. in_buff in front of out_buff:
*
* in in_end
* | |
* ||||||||||||||||
* ||||||||||||||||
* | |
* out out_end
*
* 2. out_buff in front of in_buff:
*
* in in_end
* | |
* ||||||||||||||||
* ||||||||||||||||
* | |
* out out_end
*/
bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size)
{
uint32_t in = (uint32_t) in_buff;
uint32_t in_end = in + in_buff_size;
uint32_t out = (uint32_t) out_buff;
uint32_t out_end = out + out_buff_size;
bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end);
return overlap;
}
static void crypto_submodule_prestart(volatile uint16_t *submodule_done)
{
*submodule_done = 0;
/* Ensure memory accesses above are completed before DMA is started
*
* Replacing __DSB() with __DMB() is also OK in this case.
*
* Refer to "multi-master systems" section with DMA in:
* https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
*/
__DSB();
}
static bool crypto_submodule_wait(volatile uint16_t *submodule_done)
{
while (! *submodule_done);
/* Ensure while loop above and subsequent code are not reordered */
__DSB();
if ((*submodule_done & CRYPTO_DONE_OK)) {
/* Done with OK */
return true;
} else if ((*submodule_done & CRYPTO_DONE_ERR)) {
/* Done with error */
return false;
}
return false;
}
/* Crypto interrupt handler
*
* There's inconsistency in cryptography related naming, Crpt or Crypto. For example,
* cryptography IRQ handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override
* default cryptography IRQ handler, see device/startup_{CHIP}.c for its correct name
* or call NVIC_SetVector() in crypto_init() regardless of its name. */
extern "C" void CRPT_IRQHandler()
{
uint32_t intsts;
if ((intsts = PRNG_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_prng_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
PRNG_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = AES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_aes_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
AES_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = TDES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Done with OK */
crypto_des_done |= CRYPTO_DONE_OK;
/* Clear interrupt flag */
TDES_CLR_INT_FLAG(CRYPTO_MODBASE());
} else if ((intsts = ECC_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) {
/* Check interrupt flags */
if (intsts & CRPT_INTSTS_ECCIF_Msk) {
/* Done with OK */
crypto_ecc_done |= CRYPTO_DONE_OK;
} else if (intsts & CRPT_INTSTS_ECCEIF_Msk) {
/* Done with error */
crypto_ecc_done |= CRYPTO_DONE_ERR;
}
/* Clear interrupt flag */
ECC_CLR_INT_FLAG(CRYPTO_MODBASE());
}
}
#endif /* #if defined(MBEDTLS_CONFIG_HW_SUPPORT) */

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CRYPTO_MISC_H
#define MBED_CRYPTO_MISC_H
#include <stdbool.h>
#include "partition_M2354.h"
/* Policy for configuring secure attribute of CRYPTO/CRPT module:
*
* There's only one CRYPTO/CRPT module and we have the following policy for configuring its secure attribute:
*
* 1. mbedtls H/W support can be enabled on either secure target or non-secure target, but not both.
* 2. On secure target, if mbedtls H/W support is enabled, CRYPTO/CRPT must configure to secure.
* 3. On non-secure target, if mbedtls H/W support is enabled, CRYPTO/CRPT must configure to non-secure.
*/
#if defined(MBEDTLS_CONFIG_HW_SUPPORT)
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined(SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & (1 << 18))
#error("CRYPTO/CRPT must configure to secure for secure target which supports mbedtls H/W")
#endif
#else
#if (! defined(SCU_INIT_PNSSET1_VAL)) || (! (SCU_INIT_PNSSET1_VAL & (1 << 18)))
#error("CRYPTO/CRPT must configure to non-secure for non-secure target which supports mbedtls H/W")
#endif
#endif
#endif
#if defined(MBEDTLS_CONFIG_HW_SUPPORT)
#ifdef __cplusplus
extern "C" {
#endif
/* Get Crypto module base dependent on security state */
__STATIC_INLINE CRPT_T *CRYPTO_MODBASE(void)
{
#if defined(SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & (1<<18))
return CRPT_NS;
#else
return CRPT_S;
#endif
}
/* Init/Uninit crypto module */
void crypto_init(void);
void crypto_uninit(void);
/* Clear buffer to zero
* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n);
void crypto_zeroize32(uint32_t *v, size_t n);
/* Acquire/release ownership of crypto sub-module
*
* \note "acquire" is blocking until ownership is acquired
*
* \note "acquire"/"release" must be paired.
*
* \note Recursive "acquire" is allowed because the underlying synchronization
* primitive mutex supports it.
*/
void crypto_aes_acquire(void);
void crypto_aes_release(void);
void crypto_des_acquire(void);
void crypto_des_release(void);
void crypto_ecc_acquire(void);
void crypto_ecc_release(void);
/* Acquire/release ownership of crypto sub-module
*
* \return false if crytpo sub-module is held by another thread or
* another mbedtls context.
* true if successful
*
* \note Successful "try_acquire" and "release" must be paired.
*/
bool crypto_sha_try_acquire(void);
void crypto_sha_release(void);
/* Flow control between crypto/xxx start and crypto/xxx ISR
*
* crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR.
*
* crypto_xxx_prestart will also address synchronization issue with memory barrier instruction.
*
* On finish, return of crypto_xxx_wait indicates success or not:
* true if successful
* false if failed
*
* Example: Start AES H/W and wait for its finish
* crypto_aes_prestart();
* AES_Start();
* crypto_aes_wait();
*/
void crypto_prng_prestart(void);
bool crypto_prng_wait(void);
void crypto_aes_prestart(void);
bool crypto_aes_wait(void);
void crypto_des_prestart(void);
bool crypto_des_wait(void);
void crypto_ecc_prestart(void);
bool crypto_ecc_wait(void);
/* Check if buffer can be used for crypto DMA. It has the following requirements:
* (1) Word-aligned buffer base address
* (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power.
* (3) Located in 0x20000000-0x2FFFFFFF region
*/
bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to);
/* Check if input/output buffers are overlapped */
bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size);
#ifdef __cplusplus
}
#endif
#endif /* defined(MBEDTLS_CONFIG_HW_SUPPORT) */
#endif

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/*
* Copyright (c) 2020, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

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/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "M2354.h"
#endif /* __NUMICRO_H__ */
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file acmp_reg.h
* @version V1.00
* @brief ACMP register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_REG_H__
#define __ACMP_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Analog Comparator Controller -------------------------*/
/**
@addtogroup ACMP Analog Comparator Controller(ACMP)
Memory Mapped Structure for ACMP Controller
@{
*/
typedef struct
{
/**
* @var ACMP_T::CTL
* Offset: 0x00 Analog Comparator 0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator 0 Disabled.
* | | |1 = Comparator 0 Enabled.
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator 0 interrupt Disabled.
* | | |1 = Comparator 0 interrupt Enabled.
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* |[2] |HYSEN |Comparator Hysteresis Enable Bit
* | | |0 = Comparator 0 hysteresis Disabled.
* | | |1 = Comparator 0 hysteresis Enabled.
* | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
* | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV.
* |[3] |ACMPOINV |Comparator Output Inverse
* | | |0 = Comparator 0 output inverse Disabled.
* | | |1 = Comparator 0 output inverse Enabled.
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMP0_N pin.
* | | |01 = Internal comparator reference voltage (CRV).
* | | |10 = Band-gap voltage.
* | | |11 = DAC output.
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMP0_P0.
* | | |01 = Input from ACMP0_P1.
* | | |10 = Input from ACMP0_P2.
* | | |11 = Input from ACMP0_P3.
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
* |[16] |WKEN |Power-down Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* |[25:24] |HYSSEL |Hysteresis Mode Selection
* | | |00 = Hysteresis is 0mV.
* | | |01 = Hysteresis is 10mV.
* | | |10 = Hysteresis is 20mV.
* | | |11 = Hysteresis is 30mV.
* |[29:28] |MODESEL |Propagation Delay Mode Selection
* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
* @var ACMP_T::STATUS
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |ACMPO0 |Comparator 0 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[5] |ACMPO1 |Comparator 1 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |ACMPS0 |Comparator 0 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[13] |ACMPS1 |Comparator 1 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[16] |ACMPWO |Comparator Window Output
* | | |This bit shows the output status of window compare mode
* | | |0 = The positive input voltage is outside the window.
* | | |1 = The positive input voltage is in the window.
* @var ACMP_T::VREF
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
* |[6] |CRVSSEL |CRV Source Voltage Selection
* | | |0 = VDDA is selected as CRV source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
*/
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{
*/
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
/**@}*/ /* end of REGISTER group */
#endif /* __ACMP_REG_H__ */

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/**************************************************************************//**
* @file can_reg.h
* @version V1.00
* @brief CAN register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CAN_REG_H__
#define __CAN_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Controller Area Network Controller -------------------------*/
/**
@addtogroup CAN Controller Area Network Controller(CAN)
Memory Mapped Structure for CAN Controller
@{
*/
typedef struct
{
/**
* @var CAN_IF_T::CREQ
* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MessageNumber|Message Number
* | | |0x01-0x20: Valid Message Number, the Message Object in the Message
* | | |RAM is selected for data transfer.
* | | |0x00: Not a valid Message Number, interpreted as 0x20.
* | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
* |[15] |Busy |Busy Flag
* | | |0 = Read/write action has finished.
* | | |1 = Writing to the IFn Command Request Register is in progress.
* | | |This bit can only be read by the software.
* @var CAN_IF_T::CMASK
* Offset: 0x24, 0x84 IFn Command Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DAT_B |Access Data Bytes [7:4]
* | | |Write Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [7:4] unchanged.
* | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
* |[1] |DAT_A |Access Data Bytes [3:0]
* | | |Write Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to Message Object.
* | | |Read Operation:
* | | |0 = Data Bytes [3:0] unchanged.
* | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
* |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
* | | |0 = TxRqst bit unchanged.
* | | |1 = Set TxRqst bit.
* | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
* | | |Access New Data Bit when Read Operation.
* | | |0 = NewDat bit remains unchanged.
* | | |1 = Clear NewDat bit in the Message Object.
* | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
* | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
* |[3] |ClrIntPnd |Clear Interrupt Pending Bit
* | | |Write Operation:
* | | |When writing to a Message Object, this bit is ignored.
* | | |Read Operation:
* | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
* | | |1 = Clear IntPnd bit in the Message Object.
* |[4] |Control |Control Access Control Bits
* | | |Write Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to Message Object.
* | | |Read Operation:
* | | |0 = Control Bits unchanged.
* | | |1 = Transfer Control Bits to IFn Message Buffer Register.
* |[5] |Arb |Access Arbitration Bits
* | | |Write Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
* | | |Read Operation:
* | | |0 = Arbitration bits unchanged.
* | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
* |[6] |Mask |Access Mask Bits
* | | |Write Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
* | | |Read Operation:
* | | |0 = Mask bits unchanged.
* | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
* |[7] |WR_RD |Write / Read Mode
* | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
* | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
* @var CAN_IF_T::MASK1
* Offset: 0x28, 0x88 IFn Mask 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |Msk[15:0] |Identifier Mask 15-0
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* @var CAN_IF_T::MASK2
* Offset: 0x2C, 0x8C IFn Mask 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |Msk[28:16]|Identifier Mask 28-16
* | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
* | | |1 = The corresponding identifier bit is used for acceptance filtering.
* |[14] |MDir |Mask Message Direction
* | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
* | | |1 = The message direction bit (Dir) is used for acceptance filtering.
* |[15] |MXtd |Mask Extended Identifier
* | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
* | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
* | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
* | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
* @var CAN_IF_T::ARB1
* Offset: 0x30, 0x90 IFn Arbitration 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ID[15:0] |Message Identifier 15-0
* | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
* | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
* @var CAN_IF_T::ARB2
* Offset: 0x34, 0x94 IFn Arbitration 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |ID[28:16] |Message Identifier 28-16
* | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
* | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
* |[13] |Dir |Message Direction
* | | |0 = Direction is receive.
* | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
* | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
* | | |1 = Direction is transmit.
* | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
* | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
* |[14] |Xtd |Extended Identifier
* | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
* | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
* |[15] |MsgVal |Message Valid
* | | |0 = The Message Object is ignored by the Message Handler.
* | | |1 = The Message Object is configured and should be considered by the Message Handler.
* | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
* | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
* @var CAN_IF_T::MCON
* Offset: 0x38, 0x98 IFn Message Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DLC |Data Length Code
* | | |0-8: Data Frame has 0-8 data bytes.
* | | |9-15: Data Frame has 8 data bytes
* | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
* | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
* | | |Data 0: 1st data byte of a CAN Data Frame
* | | |Data 1: 2nd data byte of a CAN Data Frame
* | | |Data 2: 3rd data byte of a CAN Data Frame
* | | |Data 3: 4th data byte of a CAN Data Frame
* | | |Data 4: 5th data byte of a CAN Data Frame
* | | |Data 5: 6th data byte of a CAN Data Frame
* | | |Data 6: 7th data byte of a CAN Data Frame
* | | |Data 7 : 8th data byte of a CAN Data Frame
* | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
* | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
* | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
* |[7] |EoB |End Of Buffer
* | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
* | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
* | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
* | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
* |[8] |TxRqst |Transmit Request
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* |[9] |RmtEn |Remote Enable Control
* | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
* | | |1 = At the reception of a Remote Frame, TxRqst is set.
* |[10] |RxIE |Receive Interrupt Enable Control
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
* | | |1 = IntPnd will be set after a successful reception of a frame.
* |[11] |TxIE |Transmit Interrupt Enable Control
* | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
* | | |1 = IntPnd will be set after a successful transmission of a frame.
* |[12] |UMask |Use Acceptance Mask
* | | |0 = Mask ignored.
* | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
* | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
* |[13] |IntPnd |Interrupt Pending
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
* |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
* | | |0 = No message lost since last time this bit was reset by the CPU.
* | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
* |[15] |NewDat |New Data
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_IF_T::DAT_A1
* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data0 |Data Byte 0
* | | |1st data byte of a CAN Data Frame
* |[15:8] |Data1 |Data Byte 1
* | | |2nd data byte of a CAN Data Frame
* @var CAN_IF_T::DAT_A2
* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data2 |Data Byte 2
* | | |3rd data byte of CAN Data Frame
* |[15:8] |Data3 |Data Byte 3
* | | |4th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B1
* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data4 |Data Byte 4
* | | |5th data byte of CAN Data Frame
* |[15:8] |Data5 |Data Byte 5
* | | |6th data byte of CAN Data Frame
* @var CAN_IF_T::DAT_B2
* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |Data6 |Data Byte 6
* | | |7th data byte of CAN Data Frame.
* |[15:8] |Data7 |Data Byte 7
* | | |8th data byte of CAN Data Frame.
*/
__IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
__IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
__IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
__IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
__IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
__IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
__IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
__IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
__IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
__IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
__IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
__I uint32_t RESERVE0[13];
} CAN_IF_T;
typedef struct
{
/**
* @var CAN_T::CON
* Offset: 0x00 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |Init |Init Initialization
* | | |0 = Normal Operation.
* | | |1 = Initialization is started.
* |[1] |IE |Module Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |SIE |Status Change Interrupt Enable Control
* | | |0 = Disabled - No Status Change Interrupt will be generated.
* | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
* |[3] |EIE |Error Interrupt Enable Control
* | | |0 = Disabled - No Error Status Interrupt will be generated.
* | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
* |[5] |DAR |Automatic Re-Transmission Disable Control
* | | |0 = Automatic Retransmission of disturbed messages enabled.
* | | |1 = Automatic Retransmission disabled.
* |[6] |CCE |Configuration Change Enable Control
* | | |0 = No write access to the Bit Timing Register.
* | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
* |[7] |Test |Test Mode Enable Control
* | | |0 = Normal Operation.
* | | |1 = Test Mode.
* @var CAN_T::STATUS
* Offset: 0x04 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
* | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
* | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
* | | |The unused code '7' may be written by the CPU to check for updates.
* | | |The following table describes the error code.
* |[3] |TxOK |Transmitted A Message Successfully
* | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
* | | |This bit is never reset by the CAN Core.
* | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
* |[4] |RxOK |Received A Message Successfully
* | | |0 = No message has been successfully received since this bit was last reset by the CPU.
* | | |This bit is never reset by the CAN Core.
* | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
* |[5] |EPass |Error Passive (Read Only)
* | | |0 = The CAN Core is error active.
* | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
* |[6] |EWarn |Error Warning Status (Read Only)
* | | |0 = Both error counters are below the error warning limit of 96.
* | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
* |[7] |BOff |Bus-Off Status (Read Only)
* | | |0 = The CAN module is not in bus-off state.
* | | |1 = The CAN module is in bus-off state.
* @var CAN_T::ERR
* Offset: 0x08 Error Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TEC |Transmit Error Counter
* | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
* |[14:8] |REC |Receive Error Counter
* | | |Actual state of the Receive Error Counter. Values between 0 and 127.
* |[15] |RP |Receive Error Passive
* | | |0 = The Receive Error Counter is below the error passive level.
* | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
* @var CAN_T::BTIME
* Offset: 0x0C Bit Timing Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |BRP |Baud Rate Prescaler
* | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
* | | |The bit time is built up from a multiple of this quanta.
* | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[7:6] |SJW |(Re)Synchronization Jump Width
* | | |0x0-0x3: Valid programmed values are [0 ... 3].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
* | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
* |[14:12] |TSeg2 |Time Segment After Sample Point
* | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
* | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
* @var CAN_T::IIDR
* Offset: 0x10 Interrupt Identifier Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
* | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
* | | |An interrupt remains pending until the application software has cleared it.
* | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
* | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
* | | |The Status Interrupt has the highest priority.
* | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
* | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
* | | |The Status Interrupt is cleared by reading the Status Register.
* @var CAN_T::TEST
* Offset: 0x14 Test Register (Register Map Note 1)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |Res |Reserved
* | | |There are reserved bits.
* | | |These bits are always read as '0' and must always be written with '0'.
* |[2] |Basic |Basic Mode
* | | |0 = Basic Mode disabled.
* | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
* |[3] |Silent |Silent Mode
* | | |0 = Normal operation.
* | | |1 = The module is in Silent Mode.
* |[4] |LBack |Loop Back Mode Enable Control
* | | |0 = Loop Back Mode is disabled.
* | | |1 = Loop Back Mode is enabled.
* |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
* | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
* | | |01 = Sample Point can be monitored at CAN_TX pin.
* | | |10 = CAN_TX pin drives a dominant ('0') value.
* | | |11 = CAN_TX pin drives a recessive ('1') value.
* |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
* | | |0 = The CAN bus is dominant (CAN_RX = '0').
* | | |1 = The CAN bus is recessive (CAN_RX = '1').
* @var CAN_T::BRPE
* Offset: 0x18 Baud Rate Prescaler Extension Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
* | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
* | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
* @var CAN_T::IF
* Offset: 0x20~0xFC CAN Interface Registers
* ---------------------------------------------------------------------------------------------------
* CAN interface structure. Refer to \ref CAN_IF_T for detail information.
*
* @var CAN_T::TXREQ1
* Offset: 0x100 Transmission Request Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::TXREQ2
* Offset: 0x104 Transmission Request Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
* | | |0 = This Message Object is not waiting for transmission.
* | | |1 = The transmission of this Message Object is requested and is not yet done.
* | | |These bits are read only.
* @var CAN_T::NDAT1
* Offset: 0x120 New Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::NDAT2
* Offset: 0x124 New Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
* | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
* | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
* @var CAN_T::IPND1
* Offset: 0x140 Interrupt Pending Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::IPND2
* Offset: 0x144 Interrupt Pending Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
* | | |0 = This message object is not the source of an interrupt.
* | | |1 = This message object is the source of an interrupt.
* @var CAN_T::MVLD1
* Offset: 0x160 Message Valid Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex.
* | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
* | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
* @var CAN_T::MVLD2
* Offset: 0x164 Message Valid Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
* | | |0 = This Message Object is ignored by the Message Handler.
* | | |1 = This Message Object is configured and should be considered by the Message Handler.
* | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
* | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
* @var CAN_T::WU_EN
* Offset: 0x168 Wake-up Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_EN |Wake-Up Enable Control
* | | |0 = The wake-up function Disabled.
* | | |1 = The wake-up function Enabled.
* | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
* @var CAN_T::WU_STATUS
* Offset: 0x16C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WAKUP_STS |Wake-Up Status
* | | |0 = No wake-up event occurred.
* | | |1 = Wake-up event occurred.
* | | |Note: This bit can be cleared by writing '0'.
*/
__IO uint32_t CON; /* Offset: 0x00 Control Register */
__IO uint32_t STATUS; /* Offset: 0x04 Status Register */
__I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
__IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
__I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
__IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
__IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
__I uint32_t RESERVE0[1];
__IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
__I uint32_t RESERVE1[8];
__I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
__I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
__I uint32_t RESERVE3[6];
__I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
__I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
__I uint32_t RESERVE4[6];
__I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
__I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
__I uint32_t RESERVE5[6];
__I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
__I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
__IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
__IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
} CAN_T;
/**
@addtogroup CAN_CONST CAN Bit Field Definition
Constant Definitions for CAN Controller
@{
*/
/* CAN CON Bit Field Definitions */
#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
/* CAN STATUS Bit Field Definitions */
#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
/* CAN ERR Bit Field Definitions */
#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
/* CAN BTIME Bit Field Definitions */
#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
/* CAN IIDR Bit Field Definitions */
#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
/* CAN TEST Bit Field Definitions */
#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
/* CAN BPRE Bit Field Definitions */
#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
/* CAN IFn_CREQ Bit Field Definitions */
#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
/* CAN IFn_CMASK Bit Field Definitions */
#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
/* CAN IFn_MASK1 Bit Field Definitions */
#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
/* CAN IFn_MASK2 Bit Field Definitions */
#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
/* CAN IFn_ARB1 Bit Field Definitions */
#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
/* CAN IFn_ARB2 Bit Field Definitions */
#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
/* CAN IFn_MCON Bit Field Definitions */
#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
/* CAN IFn_DATA_A1 Bit Field Definitions */
#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
/* CAN IFn_DATA_A2 Bit Field Definitions */
#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
/* CAN IFn_DATA_B1 Bit Field Definitions */
#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
/* CAN IFn_DATA_B2 Bit Field Definitions */
#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
/* CAN IFn_TXRQST1 Bit Field Definitions */
#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
/* CAN IFn_TXRQST2 Bit Field Definitions */
#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
/* CAN IFn_NDAT1 Bit Field Definitions */
#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
/* CAN IFn_NDAT2 Bit Field Definitions */
#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
/* CAN IFn_IPND1 Bit Field Definitions */
#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
/* CAN IFn_IPND2 Bit Field Definitions */
#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
/* CAN IFn_MVLD1 Bit Field Definitions */
#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
/* CAN IFn_MVLD2 Bit Field Definitions */
#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
/* CAN WUEN Bit Field Definitions */
#define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
/* CAN WUSTATUS Bit Field Definitions */
#define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
/**@}*/ /* CAN_CONST */
/**@}*/ /* end of CAN register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CAN_REG_H__ */

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/**************************************************************************//**
* @file crc_reg.h
* @version V1.00
* @brief CRC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_REG_H__
#define __CRC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller
@{
*/
typedef struct
{
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Generator Enable Bit
* | | |Set this bit 1 to enable CRC generator for CRC operation.
* | | |0 = No effect.
* | | |1 = CRC operation generator is active.
* |[1] |CHKSINIT |Checksum Initialization
* | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
* | | |0 = No effect.
* | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value.
* | | |The others contents of CRC_CTL register will not be cleared.
* | | |Note1: This bit will be cleared automatically
* | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
* |[24] |DATREV |Write Data Bit Order Reverse Enable Bit
* | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register.
* | | |0 = Bit order reversed for CRC_DATA write data in Disabled.
* | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit
* | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
* | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled.
* | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement Enable Bit
* | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
* | | |0 = 1's complement for CRC_DATA writes data in Disabled.
* | | |1 = 1's complement for CRC_DATA writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement Enable Bit
* | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register.
* | | |0 = 1's complement for CRC CHECKSUM Disabled.
* | | |1 = 1's complement for CRC CHECKSUMCRC Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |00 = CRC-CCITT Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1.
* | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
* | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{
*/
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CLK_REG_H__ */

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/**************************************************************************//**
* @file dac_reg.h
* @version V1.00
* @brief DAC register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_REG_H__
#define __DAC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Digital to Analog Converter -------------------------*/
/**
@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller
@{
*/
typedef struct
{
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA under-run interrupt Disabled.
* | | |1 = DMA under-run interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC0_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |110 = EPWM0 trigger.
* | | |111 = EPWM1 trigger.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* |[16] |GRPEN |DAC Group Mode Enable Bit
* | | |0 = DAC0 and DAC1 are not grouped.
* | | |1 = DAC0 and DAC1 are grouped.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
* | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits.
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET.
* | | |It is cleared to 0 when DAC starts a new conversion.
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{
*/
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __DAC_REG_H__ */

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/**************************************************************************//**
* @file ebi_reg.h
* @version V1.00
* @brief EBI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{
*/
typedef struct
{
/**
* @var EBI_T::CTL0
* Offset: 0x00 External Bus Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL0
* Offset: 0x04 External Bus Interface Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC+1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD+1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{
*/
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __EBI_REG_H__ */

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targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ecap_reg.h Normal file
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/**************************************************************************//**
* @file ecap_reg.h
* @version V1.00
* @brief ECAP register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ECAP_REG_H__
#define __ECAP_REG_H__
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Enhanced Input Capture Timer -------------------------*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{
*/
typedef struct
{
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{
*/
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
/**@}*/ /* end of REGISTER group */
#endif /* __ECAP_REG_H__ */

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/**************************************************************************//**
* @file ewdt_reg.h
* @version V1.00
* @brief EWDT register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EWDT_REG_H__
#define __EWDT_REG_H__
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Extra Watch Dog Timer Controller -------------------------*/
/**
@addtogroup EWDT Extra Watch Dog Timer Controller(EWDT)
Memory Mapped Structure for EWDT Controller
@{
*/
typedef struct
{
/**
* @var EWDT_T::CTL
* Offset: 0x00 EWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RSTEN |EWDT Time-out Reset Enable Control (Write Protect)
* | | |Setting this bit will enable the EWDT time-out reset system function If the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires.
* | | |0 = EWDT time-out reset system function Disabled.
* | | |1 = EWDT time-out reset system function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |RSTF |EWDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by EWDT time-out reset system event or not.
* | | |0 = EWDT time-out reset system event did not occur.
* | | |1 = EWDT time-out reset system event has been occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |EWDT Time-out Interrupt Flag
* | | |This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval
* | | |0 = EWDT time-out interrupt event interrupt did not occur.
* | | |1 = EWDT time-out interrupt interrupt event occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |EWDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip.
* | | |0 = Trigger Wake-up trigger event function Disabled if EWDT time-out interrupt signal generated.
* | | |1 = Trigger Wake-up trigger event function Enabled if EWDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Chip can be woken-up by while EWDT time-out interrupt signal generated only if EWDT clock source is selected to LIRC or LXT (32 kHz).
* |[5] |WKF |EWDT Time-out Wake-up Flag (Write Protect)
* | | |This bit indicates the EWDT time-out event has triggered interrupt chip wake-up or not.flag status of EWDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
* | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |WDTEN |WDT Enable Control (Write Protect)
* | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also).
* | | |1 = Set WDT counter start Enabled.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not.
* | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
* | | |Note3: This bit disabled needs 2 * WDT_CLK.
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These three bits select the time-out interval period after for the WDT starts counting.
* | | |000 = 2^4 * WDT_CLK.
* | | |001 = 2^6 * WDT_CLK.
* | | |010 = 2^8 * WDT_CLK.
* | | |011 = 2^10 * WDT_CLK.
* | | |100 = 2^12 * WDT_CLK.
* | | |101 = 2^14 * WDT_CLK.
* | | |110 = 2^16 * WDT_CLK.
* | | |111 = 2^18 * WDT_CLK.
* | | |111 = 2^20 * WDT_CLK.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only)
* | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not..
* | | |SYNC delay is
* | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion.
* | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet..
* | | |Note: Perform enable or disable WDTEN bit
* | | |This bit enabled needs 2 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
* | | |0 = ICE debug mode acknowledgment affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgment Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var EWDT_T::ALTCTL
* Offset: 0x04 EWDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect)
* | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened
* | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened.
* @var EWDT_T::RSTCNT
* Offset: 0x08 EWDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0.
* | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected.
* | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
*/
__IO uint32_t CTL; /*!< [0x0000] EWDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] EWDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] EWDT Reset Counter Register */
} EWDT_T;
/**
@addtogroup EWDT_CONST WDT Bit Field Definition
Constant Definitions for EWDT Controller
@{
*/
#define EWDT_CTL_RSTEN_Pos (1) /*!< EWDT_T::CTL: RSTEN Position */
#define EWDT_CTL_RSTEN_Msk (0x1ul << EWDT_CTL_RSTEN_Pos) /*!< EWDT_T::CTL: RSTEN Mask */
#define EWDT_CTL_RSTF_Pos (2) /*!< EWDT_T::CTL: RSTF Position */
#define EWDT_CTL_RSTF_Msk (0x1ul << EWDT_CTL_RSTF_Pos) /*!< EWDT_T::CTL: RSTF Mask */
#define EWDT_CTL_IF_Pos (3) /*!< EWDT_T::CTL: IF Position */
#define EWDT_CTL_IF_Msk (0x1ul << EWDT_CTL_IF_Pos) /*!< EWDT_T::CTL: IF Mask */
#define EWDT_CTL_WKEN_Pos (4) /*!< EWDT_T::CTL: WKEN Position */
#define EWDT_CTL_WKEN_Msk (0x1ul << EWDT_CTL_WKEN_Pos) /*!< EWDT_T::CTL: WKEN Mask */
#define EWDT_CTL_WKF_Pos (5) /*!< EWDT_T::CTL: WKF Position */
#define EWDT_CTL_WKF_Msk (0x1ul << EWDT_CTL_WKF_Pos) /*!< EWDT_T::CTL: WKF Mask */
#define EWDT_CTL_INTEN_Pos (6) /*!< EWDT_T::CTL: INTEN Position */
#define EWDT_CTL_INTEN_Msk (0x1ul << EWDT_CTL_INTEN_Pos) /*!< EWDT_T::CTL: INTEN Mask */
#define EWDT_CTL_WDTEN_Pos (7) /*!< EWDT_T::CTL: WDTEN Position */
#define EWDT_CTL_WDTEN_Msk (0x1ul << EWDT_CTL_WDTEN_Pos) /*!< EWDT_T::CTL: WDTEN Mask */
#define EWDT_CTL_TOUTSEL_Pos (8) /*!< EWDT_T::CTL: TOUTSEL Position */
#define EWDT_CTL_TOUTSEL_Msk (0xful << EWDT_CTL_TOUTSEL_Pos) /*!< EWDT_T::CTL: TOUTSEL Mask */
#define EWDT_CTL_SYNC_Pos (30) /*!< EWDT_T::CTL: SYNC Position */
#define EWDT_CTL_SYNC_Msk (0x1ul << EWDT_CTL_SYNC_Pos) /*!< EWDT_T::CTL: SYNC Mask */
#define EWDT_CTL_ICEDEBUG_Pos (31) /*!< EWDT_T::CTL: ICEDEBUG Position */
#define EWDT_CTL_ICEDEBUG_Msk (0x1ul << EWDT_CTL_ICEDEBUG_Pos) /*!< EWDT_T::CTL: ICEDEBUG Mask */
#define EWDT_ALTCTL_RSTDSEL_Pos (0) /*!< EWDT_T::ALTCTL: RSTDSEL Position */
#define EWDT_ALTCTL_RSTDSEL_Msk (0x3ul << EWDT_ALTCTL_RSTDSEL_Pos) /*!< EWDT_T::ALTCTL: RSTDSEL Mask */
#define EWDT_RSTCNT_RSTCNT_Pos (0) /*!< EWDT_T::RSTCNT: RSTCNT Position */
#define EWDT_RSTCNT_RSTCNT_Msk (0xfffffffful << EWDT_RSTCNT_RSTCNT_Pos) /*!< EWDT_T::RSTCNT: RSTCNT Mask */
/**@}*/ /* EWDT_CONST */
/**@}*/ /* end of EWDT register group */
/**@}*/ /* end of REGISTER group */
#endif /* __EWDT_REG_H__ */

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/**************************************************************************//**
* @file ewwdt_reg.h
* @version V1.00
* @brief EWWDT register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EWWDT_REG_H__
#define __EWWDT_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Extra Window Watchdog Timer -------------------------*/
/**
@addtogroup EWWDT Extra Window Watchdog Timer(EWWDT)
Memory Mapped Structure for EWWDT Controller
@{
*/
typedef struct
{
/**
* @var EWWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16])
* | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately.
* | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
* @var EWWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Control Bit
* | | |Set this bit to enable start WWDT counter counting.
* | | |0 = WWDT counter is stopped.
* | | |1 = WWDT counter is starting counting.
* |[1] |INTEN |WWDT Interrupt Enable Control Bit
* | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare Register Value
* | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT
* | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
* | | |0 = ICE debug mode acknowledgment effects WWDT counter counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgment Disabled.
* | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not.
* @var EWWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset System Flag
* | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not.
* | | |0 = WWDT time-out reset system event did not occur.
* | | |1 = WWDT time-out reset system event occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var EWWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] EWWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] EWWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] EWWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] EWWDT Counter Value Register */
} EWWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{
*/
#define EWWDT_RLDCNT_RLDCNT_Pos (0) /*!< EWWDT_T::RLDCNT: RLDCNT Position */
#define EWWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << EWWDT_RLDCNT_RLDCNT_Pos) /*!< EWWDT_T::RLDCNT: RLDCNT Mask */
#define EWWDT_CTL_WWDTEN_Pos (0) /*!< EWWDT_T::CTL: WWDTEN Position */
#define EWWDT_CTL_WWDTEN_Msk (0x1ul << EWWDT_CTL_WWDTEN_Pos) /*!< EWWDT_T::CTL: WWDTEN Mask */
#define EWWDT_CTL_INTEN_Pos (1) /*!< EWWDT_T::CTL: INTEN Position */
#define EWWDT_CTL_INTEN_Msk (0x1ul << EWWDT_CTL_INTEN_Pos) /*!< EWWDT_T::CTL: INTEN Mask */
#define EWWDT_CTL_PSCSEL_Pos (8) /*!< EWWDT_T::CTL: PSCSEL Position */
#define EWWDT_CTL_PSCSEL_Msk (0xful << EWWDT_CTL_PSCSEL_Pos) /*!< EWWDT_T::CTL: PSCSEL Mask */
#define EWWDT_CTL_CMPDAT_Pos (16) /*!< EWWDT_T::CTL: CMPDAT Position */
#define EWWDT_CTL_CMPDAT_Msk (0x3ful << EWWDT_CTL_CMPDAT_Pos) /*!< EWWDT_T::CTL: CMPDAT Mask */
#define EWWDT_CTL_ICEDEBUG_Pos (31) /*!< EWWDT_T::CTL: ICEDEBUG Position */
#define EWWDT_CTL_ICEDEBUG_Msk (0x1ul << EWWDT_CTL_ICEDEBUG_Pos) /*!< EWWDT_T::CTL: ICEDEBUG Mask */
#define EWWDT_STATUS_WWDTIF_Pos (0) /*!< EWWDT_T::STATUS: WWDTIF Position */
#define EWWDT_STATUS_WWDTIF_Msk (0x1ul << EWWDT_STATUS_WWDTIF_Pos) /*!< EWWDT_T::STATUS: WWDTIF Mask */
#define EWWDT_STATUS_WWDTRF_Pos (1) /*!< EWWDT_T::STATUS: WWDTRF Position */
#define EWWDT_STATUS_WWDTRF_Msk (0x1ul << EWWDT_STATUS_WWDTRF_Pos) /*!< EWWDT_T::STATUS: WWDTRF Mask */
#define EWWDT_CNT_CNTDAT_Pos (0) /*!< EWWDT_T::CNT: CNTDAT Position */
#define EWWDT_CNT_CNTDAT_Msk (0x3ful << EWWDT_CNT_CNTDAT_Pos) /*!< EWWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* EWWDT_CONST */
/**@}*/ /* end of EWWDT register group */
/**@}*/ /* end of REGISTER group */
#endif /* __EWWDT_REG_H__ */

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/**************************************************************************//**
* @file fmc_reg.h
* @version V1.00
* @brief FMC register definition header file
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __FMC_REG_H__
#define __FMC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Flash Memory Controller -------------------------*/
/**
@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller
@{
*/
typedef struct
{
/**
* @var FMC_T::ISPCTL
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Bit (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |BS |Boot Select (Write Protect)
* | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
* | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
* | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
* | | |0 = APROM cannot be updated when the chip runs in APROM.
* | | |1 = APROM can be updated when the chip runs in APROM.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
* | | |0 = CONFIG cannot be updated.
* | | |1 = CONFIG can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
* | | |LDROM update enable bit.
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |This bit needs to be cleared by writing 1 to it.
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
* | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0
* | | |(12) Read any content of boot loader with ICE connection
* | | |(13) The address of block erase and bank erase is not in APROM
* | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(15) The wrong setting of page erase ISP CMD in XOM
* | | |(16) Violate XOM setting one time protection
* | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
* | | |(18) Mass erase when MERASE (CFG0[13]) is disable
* | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |BL |Boot Loader Booting (Write Protect)
* | | |This bit is initiated with the inverses value of MBS (CONFIG0[5])
* | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
* | | |This bit is used to check chip boot from Boot Loader or not
* | | |User should keep original value of this bit when updating FMC_ISPCTL register.
* | | |0 = Booting from APROM or LDROM.
* | | |1 = Booting from Boot Loader.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[24] |INTEN |Interrupt Enable (Write Protect)
* | | |0 = ISP INT Disabled.
* | | |1 = ISP INT Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
* @var FMC_T::ISPADDR
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADDR |ISP Address
* | | |The NuMicro M2355 series is equipped with embedded flash
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
* | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.
* | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
* | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
* @var FMC_T::ISPDAT
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation.
* | | |Read data from this register after ISP read operation.
* | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment
* | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
* | | |For XOM page erase function, , ISPDAT = 0x0055_aa03.
* @var FMC_T::ISPCMD
* Offset: 0x0C ISP Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CMD |ISP Command
* | | |ISP command table is shown below:
* | | |0x00= FLASH Read.
* | | |0x04= Read Unique ID.
* | | |0x08= Read Flash All-One Result.
* | | |0x0B= Read Company ID.
* | | |0x0C= Read Device ID.
* | | |0x0D= Read Checksum.
* | | |0x21= FLASH 32-bit Program.
* | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
* | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
* | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..
* | | |0x27= FLASH Multi-Word Program.
* | | |0x28= Run Flash All-One Verification.
* | | |0x2D= Run Checksum Calculation.
* | | |0x2E= Vector Remap.
* | | |0x40= FLASH 64-bit Read.
* | | |0x61= FLASH 64-bit Program.
* | | |The other commands are invalid.
* @var FMC_T::ISPTRG
* Offset: 0x10 ISP Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger (Write Protect)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished
* | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0
* | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPSTS
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* |[2] |CBS |Boot Selection of CONFIG (Read Only)
* | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
* | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
* | | |0 = LDROM with IAP mode.
* | | |1 = APROM with IAP mode.
* |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
* | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from Boot Loader.
* | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
* |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
* | | |This bit is set if flash access cycle auto-tuning function is disabled
* | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
* | | |0 = Flash access cycle auto-tuning is Enabled.
* | | |1 = Flash access cycle auto-tuning is Disabled.
* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
* | | |This bit is set if data is mismatched at ISP programming verification
* | | |This bit is clear by performing ISP flash erase or ISP read CID operation
* | | |0 = Flash Program is success.
* | | |1 = Flash Program is fail. Program data is different with data in the flash memory
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
* | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.
* | | |(12) Read any content of boot loader with ICE connection
* | | |(13) The address of block erase and bank erase is not in APROM
* | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(15) The wrong setting of page erase ISP CMD in XOM
* | | |(16) Violate XOM setting one time protection
* | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
* | | |(18) Mass erase when MERASE (CFG0[13]) is disable
* | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |ALLONE |Flash All-one Verification Flag
* | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1
* | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete.
* | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.
* |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
* |[24] |INTFLAG |Interrupt Flag
* | | |0 = ISP is not finish.
* | | |1 = ISP done or ISPFF set.
* @var FMC_T::CYCCTL
* Offset: 0x4C Flash Access Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).
* | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.
* | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
* | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.
* | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.
* | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.
* | | |Others = Reserved.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
* | | |Set this bit to disable flash access cycle auto-tuning function
* | | |0 = Flash access cycle auto-tuning is enabled.
* | | |1 = Flash access cycle auto-tuning is disabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::MPDAT0
* Offset: 0x80 ISP Data0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT0 |ISP Data 0
* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
* @var FMC_T::MPDAT1
* Offset: 0x84 ISP Data1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT1 |ISP Data 1
* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
* @var FMC_T::MPDAT2
* Offset: 0x88 ISP Data2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT2 |ISP Data 2
* | | |This register is the third 32-bit data for multi-word programming.
* @var FMC_T::MPDAT3
* Offset: 0x8C ISP Data3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT3 |ISP Data 3
* | | |This register is the fourth 32-bit data for multi-word programming.
* @var FMC_T::MPSTS
* Offset: 0xC0 ISP Multi-Program Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP Multi-Word program operation is finished.
* | | |1 = ISP Multi-Word program operation is progressed.
* |[1] |PPGO |ISP Multi-program Status (Read Only)
* | | |0 = ISP multi-word program operation is not active.
* | | |1 = ISP multi-word program operation is in progress.
* |[2] |ISPFF |ISP Fail Flag (Read Only)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* |[4] |D0 |ISP DATA 0 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
* | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
* |[5] |D1 |ISP DATA 1 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
* | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
* |[6] |D2 |ISP DATA 2 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
* | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
* |[7] |D3 |ISP DATA 3 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
* | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
* @var FMC_T::MPADDR
* Offset: 0xC4 ISP Multi-Program Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |MPADDR |ISP Multi-word Program Address
* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
* @var FMC_T::XOMR0STS
* Offset: 0xD0 XOM Region 0 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 0.
* |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 0.
* @var FMC_T::XOMR1STS
* Offset: 0xD4 XOM Region 1 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 1.
* |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 1.
* @var FMC_T::XOMR2STS
* Offset: 0xD8 XOM Region 2 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 2.
* |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 2.
* @var FMC_T::XOMR3STS
* Offset: 0xDC XOM Region 3 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 3.
* |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 3.
* @var FMC_T::XOMSTS
* Offset: 0xE0 XOM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |XOMR0ON |XOM Region 0 On
* | | |XOM Region 0 active status.
* | | |0 = No active.
* | | |1 = XOM region 0 is active.
* |[1] |XOMR1ON |XOM Region 1 On
* | | |XOM Region 1 active status.
* | | |0 = No active.
* | | |1 = XOM region 1 is active.
* |[2] |XOMR2ON |XOM Region 2 On
* | | |XOM Region 2 active status.
* | | |0 = No active.
* | | |1 = XOM region 2 is active.
* |[3] |XOMR3ON |XOM Region 3 On
* | | |XOM Region 3 active status.
* | | |0 = No active.
* | | |1 = XOM region 3 is active.
* |[4] |XOMPEF |XOM Page Erase Function Fail
* | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
* | | |0 = Success.
* | | |1 = Fail.
*/
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
__I uint32_t RESERVE0[11];
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
__I uint32_t RESERVE2[12];
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
__I uint32_t RESERVE3[12];
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
__I uint32_t RESERVE4[2];
__I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */
__I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */
__I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */
__I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */
__I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
__I uint32_t RESERVE5[7];
__IO uint32_t DFCTL; /*!< [0x0100] Data Flash Function Control Register */
__I uint32_t RESERVE6;
__IO uint32_t DFSTS; /*!< [0x0108] Data Flash Status Register */
__O uint32_t SCRKEY; /*!< [0x010c] Data Flash Scrambling Key Register */
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{
*/
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */
#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */
#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */
#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */
#define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */
#define FMC_ISPSTS_ISPCERR_Msk (0x1ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Mask */
#define FMC_ISPSTS_MIRBOUND_Pos (29) /*!< FMC_T::ISPSTS: MIRBOUND Position */
#define FMC_ISPSTS_MIRBOUND_Msk (0x1ul << FMC_ISPSTS_MIRBOUND_Pos) /*!< FMC_T::ISPSTS: MIRBOUND Mask */
#define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */
#define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Mask */
#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */
#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */
#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */
#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */
#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */
#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */
#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */
#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */
#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */
#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */
#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */
#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */
#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */
#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */
#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */
#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */
#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */
#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */
#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */
#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */
#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */
#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */
#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */
#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */
#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */
#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */
#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */
#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */
#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
#define FMC_DFCTL_SCRAMEN_Pos (0) /*!< FMC_T::DFCTL: SCRAMEN Position */
#define FMC_DFCTL_SCRAMEN_Msk (0x1ul << FMC_DFCTL_SCRAMEN_Pos) /*!< FMC_T::DFCTL: SCRAMEN Mask */
#define FMC_DFCTL_SILENTEN_Pos (1) /*!< FMC_T::DFCTL: SILENTEN Position */
#define FMC_DFCTL_SILENTEN_Msk (0x1ul << FMC_DFCTL_SILENTEN_Pos) /*!< FMC_T::DFCTL: SILENTEN Mask */
#define FMC_DFSTS_TMPCLRDONE_Pos (0) /*!< FMC_T::DFSTS: TMPCLRDONE Position */
#define FMC_DFSTS_TMPCLRDONE_Msk (0x1ul << FMC_DFSTS_TMPCLRDONE_Pos) /*!< FMC_T::DFSTS: TMPCLRDONE Mask */
#define FMC_DFSTS_TMPCLRBUSY_Pos (1) /*!< FMC_T::DFSTS: TMPCLRBUSY Position */
#define FMC_DFSTS_TMPCLRBUSY_Msk (0x1ul << FMC_DFSTS_TMPCLRBUSY_Pos) /*!< FMC_T::DFSTS: TMPCLRBUSY Mask */
#define FMC_SCRKEY_SCRKEY_Pos (0) /*!< FMC_T::SCRKEY: SCRKEY Position */
#define FMC_SCRKEY_SCRKEY_Msk (0xfffffffful << FMC_SCRKEY_SCRKEY_Pos) /*!< FMC_T::SCRKEY: SCRKEY Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __FMC_REG_H__ */

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/**************************************************************************//**
* @file gpio_reg.h
* @version V1.00
* @brief GPIO register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __GPIO_REG_H__
#define __GPIO_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- General Purpose Input/Output Controller -------------------------*/
/**
@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller
@{
*/
typedef struct
{
/**
* @var GPIO_T::MODE
* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 PA-H I/O Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control
* | | |Determine each I/O mode of Px.n pins.
* | | |00 = Px.n is in Input mode.
* | | |01 = Px.n is in Push-pull Output mode.
* | | |10 = Px.n is in Open-drain Output mode.
* | | |11 = Px.n is in Quasi-bidirectional mode.
* | | |Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
* | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
* | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
* | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::DINOFF
* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 PA-H Digital Input Path Disable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
* | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
* | | |0 = Px.n digital input path Enabled.
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::DOUT
* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 PA-H Data Output Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DOUTn |Port A-H Pin[n] Output Value
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::DATMSK
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC PA-H Data Output Write Mask
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
* | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
* | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
* | | |Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
* | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::PIN
* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 PA-H Pin Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |PINn |Port A-H Pin[n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin.
* | | |0 = The corresponding pin status is low.
* | | |1 = The corresponding pin status is high.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::DBEN
* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 PA-H De-Bounce Enable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
* | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
* | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::INTTYPE
* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 PA-H Interrupt Trigger Type Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
* | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::INTEN
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC PA-H Interrupt Enable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
* | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
* | | |0 = Px.n level low or high to low interrupt Disabled.
* | | |1 = Px.n level low or high to low interrupt Enabled.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
* | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
* | | |0 = Px.n level high or low to high interrupt Disabled.
* | | |1 = Px.n level high or low to high interrupt Enabled.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::INTSRC
* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 PA-H Interrupt Source Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag
* | | |Write Operation :
* | | |0 = No action.
* | | |1 = Clear the corresponding pending interrupt.
* | | |Read Operation :
* | | |0 = No interrupt at Px.n.
* | | |1 = Px.n generates an interrupt.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::SMTEN
* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 PA-H Input Schmitt Trigger Enable
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
* | | |0 = Px.n input Schmitt trigger function Disabled.
* | | |1 = Px.n input Schmitt trigger function Enabled.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::SLEWCTL
* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 PA-H High Slew Rate Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control
* | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
* | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
* | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
* | | |11 = Reserved.
* | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::PUSEL
* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 PA-H Pull-up and Pull-down Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register
* | | |Determine each I/O Pull-up/pull-down of Px.n pins.
* | | |00 = Px.n pull-up and pull-down disabled.
* | | |01 = Px.n pull-up enabled.
* | | |10 = Px.n pull-down enabled.
* | | |11 = Px.n pull-up and pull-down disabled.
* | | |Note 1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode.
* | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode.
* | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
* @var GPIO_T::DBCTL
* Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4 PA-H Interrupt De-bounce Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection
* | | |0000 = Sample interrupt input once per 1 clocks.
* | | |0001 = Sample interrupt input once per 2 clocks.
* | | |0010 = Sample interrupt input once per 4 clocks.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 2*256 clocks.
* | | |1010 = Sample interrupt input once per 4*256 clocks.
* | | |1011 = Sample interrupt input once per 8*256 clocks.
* | | |1100 = Sample interrupt input once per 16*256 clocks.
* | | |1101 = Sample interrupt input once per 32*256 clocks.
* | | |1110 = Sample interrupt input once per 64*256 clocks.
* | | |1111 = Sample interrupt input once per 128*256 clocks.
* |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection
* | | |0 = De-bounce counter clock source is the HCLK.
* | | |1 = De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC).
* |[5] |ICLKON |Interrupt Clock on Mode
* | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
* | | |1 = All I/O pins edge detection circuit is always active after reset.
* | | |Note: It is recommended to disable this bit to save system power if no special application concern.
*/
__IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control */
__IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */
__IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value */
__IO uint32_t DATMSK; /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask */
__I uint32_t PIN; /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value */
__IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control */
__IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control */
__IO uint32_t INTEN; /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control */
__IO uint32_t INTSRC; /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag */
__IO uint32_t SMTEN; /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable */
__IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control */
__I uint32_t RESERVE0[1];
__IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */
__IO uint32_t DBCTL; /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control */
} GPIO_T;
/**
@addtogroup GPIO_CONST GPIO Bit Field Definition
Constant Definitions for GPIO Controller
@{
*/
#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
/**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */
/**@}*/ /* end of REGISTER group */
#endif /* __GPIO_REG_H__ */

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/**************************************************************************//**
* @file hdiv_reg.h
* @version V1.00
* @brief HDIV register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HDIV_REG_H__
#define __HDIV_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Hardware Divider --------------------------------*/
/**
@addtogroup HDIV Hardware Divider(HDIV)
Memory Mapped Structure for HDIV Controller
@{
*/
typedef struct
{
/**
* @var HDIV_T::DIVIDEND
* Offset: 0x00 Dividend Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DIVIDEND |Dividend Source
* | | |This register is given the dividend of divider before calculation starting.
* @var HDIV_T::DIVISOR
* Offset: 0x04 Divisor Source Resister
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DIVISOR |Divisor Source
* | | |This register is given the divisor of divider before calculation starts.
* | | |Note: When this register is written, hardware divider will start calculate.
* @var HDIV_T::DIVQUO
* Offset: 0x08 Quotient Result Resister
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |QUOTIENT |Quotient Result
* | | |This register holds the quotient result of divider after calculation complete.
* @var HDIV_T::DIVREM
* Offset: 0x0C Remainder Result Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |REMAINDER |Remainder Result
* | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
* | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
* | | |This register holds the remainder result of divider after calculation complete.
* @var HDIV_T::DIVSTS
* Offset: 0x10 Divider Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |Division Finish Flag
* | | |0 = Under Calculation.
* | | |1 = Calculation finished.
* | | |The flag will become low when the divider is in calculation.
* | | |The flag will go back to high once the calculation finished.
* |[1] |DIV0 |Divisor Zero Warning
* | | |0 = The divisor is not 0.
* | | |1 = The divisor is 0.
* | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
* | | |This register is read only.
*/
__IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */
__IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */
__IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */
__IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */
__I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */
} HDIV_T;
/**
@addtogroup HDIV_CONST HDIV Bit Field Definition
Constant Definitions for HDIV Controller
@{
*/
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */
#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */
#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */
#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */
#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */
#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */
#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */
#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */
/**@}*/ /* HDIV_CONST */
/**@}*/ /* end of HDIV register group */
/**@}*/ /* end of REGISTER group */
#endif /* __HDIV_REG_H__ */

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/**************************************************************************//**
* @file i2c_reg.h
* @version V1.00
* @brief I2C register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{
*/
typedef struct
{
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* @var I2C_T::ADDR0
* Offset: 0x04 I2C Slave Address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS0 values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When Enabled, The time-out period is extend 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear
* | | |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR1
* Offset: 0x18 I2C Slave Address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDR2
* Offset: 0x1C I2C Slave Address Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDR3
* Offset: 0x20 I2C Slave Address Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* @var I2C_T::ADDRMSK0
* Offset: 0x24 I2C Slave Address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK1
* Offset: 0x28 I2C Slave Address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK2
* Offset: 0x2C I2C Slave Address Mask Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK3
* Offset: 0x30 I2C Slave Address Mask Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1= I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C don't hold bus after wake-up disable.
* | | |1= I2C don't hold bus after wake-up enable.
* | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function disable.
* | | |1 = Transmit PDMA function enable.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function disable.
* | | |1 = Receive PDMA function enable.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable
* | | |0 = Address match 10-bit function is disabled.
* | | |1 = Address match 10-bit function is enabled.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status Register
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status Register
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[8] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected.
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* | | |Note:This bit is read only.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
* @var I2C_T::BUSCTL
* Offset: 0x50 I2C Bus Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACKMEN |Acknowledge Control by Manual
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
* | | |0 = Slave byte control Disabled.
* | | |1 = Slave byte control Enabled
* | | |The 9th bit can response the ACK or NACK according the received data by user
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
* | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
* | | |0 = Packet Error Checking Calculation Disabled.
* | | |1 = Packet Error Checking Calculation Enabled.
* | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
* | | |0 = Device default address Disable
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
* | | |1 = Device default address Enabled
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
* |[3] |BMHEN |Bus Management Host Enable Bit
* | | |0 = Host function Disabled.
* | | |1 = Host function Enabled.
* |[4] |ALERTEN |Bus Management Alert Enable Bit
* | | |Device Mode (BMHEN =0).
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
* | | |Host Mode (BMHEN =1).
* | | |0 = BM_ALERT pin not supported.
* | | |1 = BM_ALERT pin supported.
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
* | | |0 = The output of SUSCON pin is low.
* | | |1 = The output of SUSCON pin is high.
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
* | | |0 = The SUSCON pin in input.
* | | |1 = The output enable is active on the SUSCON pin.
* |[7] |BUSEN |BUS Enable Bit
* | | |0 = The system management function is Disabled.
* | | |1 = The system management function is Enable.
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
* | | |0 = No PEC transfer.
* | | |1 = PEC transmission is requested.
* | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
* |[9] |TIDLE |Timer Check in Idle State
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
* | | |This bit is used to define which condition is enabled.
* | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
* | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
* |[10] |PECCLR |PEC Clear at Repeat Start
* | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
* | | |0 = The PEC calculation is cleared by Repeat Start function is Disabled.
* | | |1 = The PEC calculation is cleared by Repeat Start function is Enabled.
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
* | | |0 = Indicates the byte count done interrupt is Disabled.
* | | |1 = Indicates the byte count done interrupt is Enabled.
* | | |Note: This bit is used in PECEN =1.
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
* | | |0 = Indicates the PEC transfer done interrupt is Disabled.
* | | |1 = Indicates the PEC transfer done interrupt is Enabled.
* | | |Note: This bit is used in PECEN =1.
* @var I2C_T::BUSTCTL
* Offset: 0x54 I2C Bus Management Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSTOEN |Bus Time Out Enable Bit
* | | |0 = Indicates the bus clock low time-out detection is Disabled.
* | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1)
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
* | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
* | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
* | | |For Master, it calculates the period from START to ACK
* | | |For Slave, it calculates the period from START to STOP
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
* | | |BUSY =1.
* | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
* | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
* | | |BUSY =0.
* | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
* | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
* | | |0 = Indicates the clock time out interrupt is Disabled.
* | | |1 = Indicates the clock time out interrupt is Enabled.
* |[4] |TORSTEN |Time Out Reset Enable Bit
* | | |0 = Indicates the I2C state machine reset is Disable.
* | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
* @var I2C_T::BUSSTS
* Offset: 0x58 I2C Bus Management Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[1] |BCDONE |Byte Count Transmission/Receive Done
* | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* |[2] |PECERR |PEC Error in Reception
* | | |0 = Indicates the PEC value equal the received PEC data packet.
* | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
* | | |Note: Software can write 1 to clear this bit.
* |[3] |ALERT |SMBus Alert Status
* | | |Device Mode (BMHEN =0).
* | | |0 = Indicates SMBALERT pin state is low.
* | | |1 = Indicates SMBALERT pin state is high.
* | | |Host Mode (BMHEN =1).
* | | |0 = No SMBALERT event.
* | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
* | | |Note: 1
* | | |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
* | | |2
* | | |Software can write 1 to clear this bit.
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status
* | | |0 = The input status of SUSCON pin is 0.
* | | |1 = The input status of SUSCON pin is 1.
* |[5] |BUSTO |Bus Time-out Status
* | | |0 = Indicates that there is no any time-out or external clock time-out.
* | | |1 = Indicates that a time-out or external clock time-out occurred.
* | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[6] |CLKTO |Clock Low Accumulate Time-out Status
* | | |0 = Indicates that the cumulative clock low is no any time-out.
* | | |1 = Indicates that the cumulative clock low time-out occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
* | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* @var I2C_T::PKTSIZE
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |PLDSIZE |Transfer Byte Number
* | | |The transmission or receive byte number in one transaction when the PECEN is set
* | | |The maximum transaction or receive byte is 256 Bytes.
* | | |Notice: The byte number counting includes address, command code, and data frame.
* @var I2C_T::PKTCRC
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PECCRC |Packet Error Checking Byte Value
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
* | | |It is read only.
* @var I2C_T::BUSTOUT
* Offset: 0x64 I2C Bus Management Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |BUSTO |Bus Management Time-out Value
* | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
* @var I2C_T::CLKTOUT
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKTO |Bus Clock Low Timer
* | | |The field is used to configure the cumulative clock extension time-out.
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
__I uint32_t RESERVE0[2];
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{
*/
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/**@}*/ /* end of REGISTER group */
#endif /* __I2C_REG_H__ */

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/**************************************************************************//**
* @file i2s_reg.h
* @version V1.00
* @brief I2S register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- I2S Interface Controller -------------------------*/
/**
@addtogroup I2S I2S Interface Controller(I2S)
Memory Mapped Structure for I2S Controller
@{
*/
typedef struct
{
/**
* @var I2S_T::CTL0
* Offset: 0x00 I2S Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Control
* | | |0 = I2S controller Disabled.
* | | |1 = I2S controller Enabled.
* |[1] |TXEN |Transmit Enable Control
* | | |0 = Data transmission Disabled.
* | | |1 = Data transmission Enabled.
* |[2] |RXEN |Receive Enable Control
* | | |0 = Data receiving Disabled.
* | | |1 = Data receiving Enabled.
* |[3] |MUTE |Transmit Mute Enable Control
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Send zero on transmit channel.
* |[5:4] |DATWIDTH |Data Width
* | | |This bit field is used to define the bit-width of data word in each audio channel
* | | |00 = The bit-width of data word is 8-bit.
* | | |01 = The bit-width of data word is 16-bit.
* | | |10 = The bit-width of data word is 24-bit.
* | | |11 = The bit-width of data word is 32-bit.
* |[6] |MONO |Monaural Data Control
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
* | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
* | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
* | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
* | | |1 = Even channel data at low byte.
* | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
* |[8] |SLAVE |Slave Mode Enable Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* | | |Note: I2S can operate as master or slave
* | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
* | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
* |[15] |MCLKEN |Master Clock Enable Control
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[18] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear TX FIFO.
* | | |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
* | | |Note 2: This bit is clear by hardware automatically, read it return zero.
* |[19] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear RX FIFO.
* | | |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
* | | |Note 2: This bit is cleared by hardware automatically, read it return zero.
* |[20] |TXPDMAEN |Transmit PDMA Enable Control
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[21] |RXPDMAEN |Receive PDMA Enable Control
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Control
* | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
* | | |0 = Receives channel1 data in MONO mode.
* | | |1 = Receives channel0 data in MONO mode.
* |[26:24] |FORMAT |Data Format Selection
* | | |000 = I2S standard data format.
* | | |001 = I2S with MSB justified.
* | | |010 = I2S with LSB justified.
* | | |011 = Reserved.
* | | |100 = PCM standard data format.
* | | |101 = PCM with MSB justified.
* | | |110 = PCM with LSB justified.
* | | |111 = Reserved.
* |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
* | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol.
* | | |0 = One BCLK period.
* | | |1 = One channel period.
* | | |Note: This bit is only available in master mode.
* |[29:28] |CHWIDTH |Channel Width
* | | |This bit fields are used to define the length of audio channel
* | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
* | | |00 = The bit-width of each audio channel is 8-bit.
* | | |01 = The bit-width of each audio channel is 16-bit.
* | | |10 = The bit-width of each audio channel is 24-bit.
* | | |11 = The bit-width of each audio channel is 32-bit.
* |[31:30] |TDMCHNUM |TDM Channel Number
* | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
* | | |00 = 2 channels in audio frame.
* | | |01 = 4 channels in audio frame.
* | | |10 = 6 channels in audio frame.
* | | |11 = 8 channels in audio frame.
* @var I2S_T::CLKDIV
* Offset: 0x04 I2S Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MCLKDIV |Master Clock Divider
* | | |If chip external crystal frequency is (2 x MCLKDIV) x 256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
* | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
* | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
* | | |F_MCLK = F_I2SCLK/(2 x MCLKDIV) (When MCLKDIV is >= 1 ).
* | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
* | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK.
* |[16:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |Software can program these bit fields to generate sampling rate clock frequency.
* | | |F_BCLK= F_I2SCLK / (2 x (BCLKDIV + 1)).
* | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK.
* @var I2S_T::IEN
* Offset: 0x08 I2S Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
* |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1.
* |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
* | | |If RXTHIEN bit is enabled, interrupt occur.
* |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
* |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1.
* |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
* |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross.
* | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross.
* | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* @var I2S_T::STATUS0
* Offset: 0x0C I2S Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SINT |I2S Interrupt Flag (Read Only)
* | | |0 = No I2S interrupt.
* | | |1 = I2S interrupt.
* | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
* |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
* | | |0 = No receive interrupt.
* | | |1 = Receive interrupt.
* |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
* | | |0 = No transmit interrupt.
* | | |1 = Transmit interrupt.
* |[5:3] |DATACH |Transmission Data Channel (Read Only)
* | | |This bit fields are used to indicate which audio channel is current transmit data belong.
* | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
* | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
* | | |010 = channel2 (available while 4-channel TDM PCM mode).
* | | |011 = channel3 (available while 4-channel TDM PCM mode).
* | | |100 = channel4 (available while 6-channel TDM PCM mode).
* | | |101 = channel5 (available while 6-channel TDM PCM mode).
* | | |110 = channel6 (available while 8-channel TDM PCM mode).
* | | |111 = channel7 (available while 8-channel TDM PCM mode).
* |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
* | | |0 = No underflow occur.
* | | |1 = Underflow occur.
* | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again
* | | |This bit will be set to 1, and it indicates underflow situation occurs.
* | | |Note 2: Write 1 to clear this bit to zero
* |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
* | | |0 = No overflow occur.
* | | |1 = Overflow occur.
* | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
* | | |Note 2: Write 1 to clear this bit to 0.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is not higher than threshold level.
* | | |1 = Data word(s) in FIFO is higher than threshold level.
* | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
* | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
* |[11] |RXFULL |Receive FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in receive FIFO is 16.
* |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in receive FIFO is 0.
* |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
* | | |0 = No underflow.
* | | |1 = Underflow.
* | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
* | | |Note 2: Write 1 to clear this bit to 0.
* |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
* | | |0 = No overflow.
* | | |1 = Overflow.
* | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1.
* | | |Note 2: Write 1 to clear this bit to 0.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is higher than threshold level.
* | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
* | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
* | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
* |[19] |TXFULL |Transmit FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in transmit FIFO is 16.
* |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in transmit FIFO is 0.
* |[21] |TXBUSY |Transmit Busy (Read Only)
* | | |0 = Transmit shift buffer is empty.
* | | |1 = Transmit shift buffer is busy.
* | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
* | | |And set to 1 when 1st data is load to shift buffer
* @var I2S_T::TXFIFO
* Offset: 0x10 I2S Transmit FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXFIFO |Transmit FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data transmit
* | | |Write data to this register to prepare data for transmit
* | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
* @var I2S_T::RXFIFO
* Offset: 0x14 I2S Receive FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXFIFO |Receive FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data receive
* | | |Read this register to get data in FIFO
* | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
* @var I2S_T::CTL1
* Offset: 0x20 I2S Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control
* | | |0 = channel0 zero-cross detect Disabled.
* | | |1 = channel0 zero-cross detect Enabled.
* | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
* | | |Note 3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
* |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control
* | | |0 = channel1 zero-cross detect Disabled.
* | | |1 = channel1 zero-cross detect Enabled.
* | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
* | | |Note 3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
* |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control
* | | |0 = channel2 zero-cross detect Disabled.
* | | |1 = channel2 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
* | | |Note 3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
* |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control
* | | |0 = channel3 zero-cross detect Disabled.
* | | |1 = channel3 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
* | | |Note 3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
* |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control
* | | |0 = channel4 zero-cross detect Disabled.
* | | |1 = channel4 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
* | | |Note 3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
* |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control
* | | |0 = channel5 zero-cross detect Disabled.
* | | |1 = channel5 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
* | | |Note 3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
* |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control
* | | |0 = channel6 zero-cross detect Disabled.
* | | |1 = channel6 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
* | | |Note 3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
* |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control
* | | |0 = channel7 zero-cross detect Disabled.
* | | |1 = channel7 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
* | | |Note 3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
* |[11:8] |TXTH |Transmit FIFO Threshold Level
* | | |0000 = 0 data word in transmit FIFO.
* | | |0001 = 1 data word in transmit FIFO.
* | | |0010 = 2 data words in transmit FIFO.
* | | |...
* | | |1110 = 14 data words in transmit FIFO.
* | | |1111 = 15 data words in transmit FIFO.
* | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
* |[19:16] |RXTH |Receive FIFO Threshold Level
* | | |0000 = 1 data word in receive FIFO.
* | | |0001 = 2 data words in receive FIFO.
* | | |0010 = 3 data words in receive FIFO.
* | | |...
* | | |1110 = 15 data words in receive FIFO.
* | | |1111 = 16 data words in receive FIFO.
* | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
* |[24] |PBWIDTH |Peripheral Bus Data Width Selection
* | | |This bit is used to choice the available data width of APB bus
* | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
* | | |0 = 32 bits data width.
* | | |1 = 16 bits data width.
* | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
* | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
* | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
* |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
* | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
* | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
* | | |0 = Low 16-bit read/write access first.
* | | |1 = High 16-bit read/write access first.
* | | |Note: This bit is available while PBWIDTH = 1.
* @var I2S_T::STATUS1
* Offset: 0x24 I2S Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
* | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel0.
* | | |1 = Channel0 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
* | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel1.
* | | |1 = Channel1 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
* | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel2.
* | | |1 = Channel2 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
* | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel3.
* | | |1 = Channel3 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
* | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel4.
* | | |1 = Channel4 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
* | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel5.
* | | |1 = Channel5 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
* | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel6.
* | | |1 = Channel6 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
* | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel7.
* | | |1 = Channel7 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in transmit FIFO.
* | | |00000 = No data.
* | | |00001 = 1 word in transmit FIFO.
* | | |00010 = 2 words in transmit FIFO.
* | | |...
* | | |01110 = 14 words in transmit FIFO.
* | | |01111 = 15 words in transmit FIFO.
* | | |10000 = 16 words in transmit FIFO.
* | | |Others are reserved.
* |[20:16] |RXCNT |Receive FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in receive FIFO.
* | | |00000 = No data.
* | | |00001 = 1 word in receive FIFO.
* | | |00010 = 2 words in receive FIFO.
* | | |...
* | | |01110 = 14 words in receive FIFO.
* | | |01111 = 15 words in receive FIFO.
* | | |10000 = 16 words in receive FIFO.
* | | |Others are reserved.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
__IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
__IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
__O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
__I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
} I2S_T;
/**
@addtogroup I2S_CONST I2S Bit Field Definition
Constant Definitions for I2S Controller
@{
*/
#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
/**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */
/**@}*/ /* end of REGISTER group */
#endif /* __I2S_REG_H__ */

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/**************************************************************************//**
* @file keystore_reg.h
* @version V1.00
* @brief Key store register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __KEYSTORE_REG_H__
#define __KEYSTORE_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Key Store -------------------------*/
/**
@addtogroup KS Key Store(KS)
Memory Mapped Structure for KS Controller
@{
*/
typedef struct
{
/**
* @var KS_T::CTL
* Offset: 0x00 Key Store Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |Key Store Start Control Bit
* | | |0 = No operation.
* | | |1 = Start the setted operation.
* |[3:1] |OPMODE |Key Store Operation Mode
* | | |000 = Read operation.
* | | |001 = Create operation.
* | | |010 = Erase one key operation (only for key is in SRAM).
* | | |011 = Erase all keys operation (only for SRAM and Flash).
* | | |100 = Revoke key operation.
* | | |101 = Data Remanence prevention opertation (only for SRAM).
* | | |Others = reserved.
* |[7] |CONT |Read/Write Key Continue Bit
* | | |0 = Read/Write key operation is not continuous to previous operation.
* | | |1 = Read/Write key operation is continuous to previous operation.
* |[8] |INIT |Key Store Initialization
* | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized.
* | | |After KeyStore is initialized, INIT will be cleared.
* | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00.
* |[10] |SILENT |Silent Access Enable Bit
* | | |0 = Silent Access Disabled.
* | | |1 = Silent Access Enabled.
* |[11] |SCMB |Data Scramble Enable Bit
* | | |0 = Data Scramble Disabled.
* | | |1 = Data Scramble Enabled.
* |[15] |IEN |Key Store Interrupt Enable Bit
* | | |0 = Key Store Interrupt Disabled.
* | | |1 = Key Store Interrupt Enabled.
* @var KS_T::METADATA
* Offset: 0x04 Key Store Metadata Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEC |Secure Key Selection Bit
* | | |0 = Set key as the non-secure key.
* | | |1 = Set key as the secure key.
* |[1] |PRIV |Privilege Key Selection Bit
* | | |0 = Set key as the non-privilege key.
* | | |1 = Set key as the privilege key.
* |[2] |READABLE |Key Readable Control Bit
* | | |0 = key is un-readable.
* | | |1 = key is readable.
* |[3] |RVK |Key Revoke Control Bit
* | | |0 = Key current selected will not be changed.
* | | |1 = key current selected will be change to revoked state.
* |[4] |BS |Booting State Selection Bit
* | | |0 = Set key used at all state.
* | | |1 = Set key used at boot loader state 1 (BL1 state).
* |[12:8] |SIZE |Key Size Selection Bits
* | | |00000 = 128 bits.
* | | |00001 = 163 bits.
* | | |00010 = 192 bits.
* | | |00011 = 224 bits.
* | | |00100 = 233 bits.
* | | |00101 = 255 bits.
* | | |00110 = 256 bits.
* | | |00111 = 283 bits.
* | | |01000 = 384 bits.
* | | |01001 = 409 bits.
* | | |01010 = 512 bits.
* | | |01011 = 521 bits.
* | | |01100 = 571 bits.
* | | |10000 = 1024 bits.
* | | |10001 = 1536 bits.
* | | |10010 = 2048 bits.
* | | |10011 = 3072 bits.
* | | |10100 = 4096 bits.
* | | |Others = reserved.
* |[18:16] |OWNER |Key Owner Selection Bits
* | | |000 = Only for AES used.
* | | |001 = Only for HMAC engine used.
* | | |010 = Only for RSA engine exponential used (private key).
* | | |011 = Only for RSA engine middle data used.
* | | |100 = Only for ECC engine used.
* | | |101 = Only for CPU engine use.
* | | |Others = reserved.
* |[25:20] |NUMBER |Key Number
* | | |Before read or erase one key operation starts, user should write the key number to be operated
* | | |When create operation is finished, user can read these bits to get its key number.
* |[31:30] |DST |Key Location Selection Bits
* | | |00 = Key is in SRAM.
* | | |01 = Key is in Flash.
* | | |10 = Key is in OTP.
* | | |Others = reserved.
* @var KS_T::STS
* Offset: 0x08 Key Store Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IF |Key Store Finish Interrupt Flag
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store interrupt.
* | | |1 = Key Store operation done interrupt.
* |[1] |EIF |Key Store Error Flag
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store error.
* | | |1 = Key Store error interrupt.
* |[2] |BUSY |Key Store Busy Flag (RO)
* | | |0 = KeyStore is idle or finished.
* | | |1 = KeyStore is busy.
* |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (RO)
* | | |0 = Key Storage at SRAM is not full.
* | | |1 = Key Storage at SRAM is full.
* |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (RO)
* | | |0 = Key Storage at Flash is not full.
* | | |1 = Key Storage at Flash is full.
* |[7] |INITDONE |Key Store Initialization Done Status (RO)
* | | |0 = Key Store is un-initialized.
* | | |1 = Key Store is initialized.
* |[8] |RAMINV |Key Store SRAM Invert Status (RO)
* | | |0 = Key Store key in SRAM is normal.
* | | |1 = Key Store key in SRAM is inverted.
* @var KS_T::REMAIN
* Offset: 0x0C Key Store Remaining Space Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |RRMNG |Key Store SRAM Remaining Space
* | | |The RRMNG shows the remaining byte count space for SRAM.
* |[27:16] |FRMNG |Key Store Flash Remaining Space
* | | |The FRMNG shows the remaining byte count space for Flash.
* @var KS_T::SCMBKEY
* Offset: 0x10-0x1C Key Store Scramble Key Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCMBKEY |Key Store Scramble Key
* | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
* | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
* @var KS_T::KEY
* Offset: 0x20-0x3C Key Store Entry Key Word Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::OTPSTS
* Offset: 0x40 Key Store OTP Keys Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KEY0 |OTP Key 0 Used Status
* | | |0 = OTP key 0 is unused.
* | | |1 = OTP key 0 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[1] |KEY1 |OTP Key 1 Used Status
* | | |0 = OTP key 1 is unused.
* | | |1 = OTP key 1 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[2] |KEY2 |OTP Key 2 Used Status
* | | |0 = OTP key 2 is unused.
* | | |1 = OTP key 2 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[3] |KEY3 |OTP Key 3 Used Status
* | | |0 = OTP key 3 is unused.
* | | |1 = OTP key 3 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[4] |KEY4 |OTP Key 4 Used Status
* | | |0 = OTP key 4 is unused.
* | | |1 = OTP key 4 is used.
* | | |Note: If chip is changed to RMA stage, existing key will be revoked after initialization.
* |[5] |KEY5 |OTP Key 5 Used Status
* | | |0 = OTP key 5 is unused.
* | | |1 = OTP key 5 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[6] |KEY6 |OTP Key 6 Used Status
* | | |0 = OTP key 6 is unused.
* | | |1 = OTP key 6 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[7] |KEY7 |OTP Key 7 Used Status
* | | |0 = OTP key 7 is unused.
* | | |1 = OTP key 7 is used.
* | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* @var KS_T::REMKCNT
* Offset: 0x44 Key Store Remaining Key Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count
* | | |The RRMKCNT shows the remaining key count for SRAM.
* |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count
* | | |The FRMKCNT shows the remaining key count for Flash.
*/
__IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */
__IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */
__IO uint32_t STS; /*!< [0x0008] Key Store Status Register */
__I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */
__IO uint32_t SCMBKEY[4]; /*!< [0x0010 ~ 0x001c] Key Store Scramble Key Word 0 Register */
__IO uint32_t KEY[8]; /*!< [0x0020 ~ 0x003c] Key Store Entry Key Word 0 Register */
__I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */
__I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */
} KS_T;
/**
@addtogroup KS_CONST KS Bit Field Definition
Constant Definitions for KS Controller
@{
*/
#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */
#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */
#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */
#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */
#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */
#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */
#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */
#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */
#define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */
#define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */
#define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */
#define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */
#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */
#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */
#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */
#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */
#define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */
#define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */
#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */
#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */
#define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */
#define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */
#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */
#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */
#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */
#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */
#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */
#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */
#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */
#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */
#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */
#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */
#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */
#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */
#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */
#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */
#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */
#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */
#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */
#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */
#define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */
#define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */
#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */
#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */
#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */
#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */
#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */
#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */
#define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */
#define KS_REMAIN_FRMNG_Msk (0xffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */
#define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */
#define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */
#define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */
#define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */
#define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */
#define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */
#define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */
#define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */
#define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */
#define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */
#define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */
#define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */
#define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */
#define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */
#define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */
#define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */
#define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */
#define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */
#define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */
#define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */
#define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */
#define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */
#define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */
#define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */
#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */
#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */
#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */
#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */
#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */
#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */
#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */
#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */
#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */
#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */
#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */
#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */
#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */
#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */
#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */
#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */
#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */
#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */
#define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */
#define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */
/**@}*/ /* KS_CONST */
/**@}*/ /* end of KS register group */
/**@}*/ /* end of REGISTER group */
#endif /* __KEYSTORE_REG_H__ */

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/**************************************************************************//**
* @file otg_reg.h
* @version V1.00
* @brief OTG register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OTG_REG_H__
#define __OTG_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- USB On-The-Go Controller -------------------------*/
/**
@addtogroup OTG USB On-The-Go Controller(OTG)
Memory Mapped Structure for OTG Controller
@{
*/
typedef struct
{
/**
* @var OTG_T::CTL
* Offset: 0x00 OTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame is not configured as OTG device, this bit must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var OTG_T::PHYCTL
* Offset: 0x04 OTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable Bit
* | | |When USB frame is configured as OTG device or ID dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG device nor ID dependent , this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var OTG_T::INTEN
* Offset: 0x08 OTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var OTG_T::INTSTS
* Offset: 0x0C OTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var OTG_T::STATUS
* Offset: 0x10 OTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |Over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V, this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
} OTG_T;
/**
@addtogroup OTG_CONST OTG Bit Field Definition
Constant Definitions for OTG Controller
@{
*/
#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
/**@}*/ /* OTG_CONST */
/**@}*/ /* end of OTG register group */
/**@}*/ /* end of REGISTER group */
#endif /* __OTG_REG_H__ */

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/**************************************************************************//**
* @file pdma_reg.h
* @version V1.00
* @brief PDMA register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PDMA_REG_H__
#define __PDMA_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
/**
@addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
Memory Mapped Structure for PDMA Controller
@{
*/
typedef struct
{
/**
* @var DSCT_T::CTL
* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE |PDMA Operation Mode Selection
* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
* | | |01 = Basic mode: The descriptor table only has one task
* | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted.
* | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute.
* | | |11 = Reserved.
* | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
* |[2] |TXTYPE |Transfer Type
* | | |0 = Burst transfer type.
* | | |1 = Single transfer type.
* |[6:4] |BURSIZE |Burst Size
* | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
* | | |000 = 128 Transfers.
* | | |001 = 64 Transfers.
* | | |010 = 32 Transfers.
* | | |011 = 16 Transfers.
* | | |100 = 8 Transfers.
* | | |101 = 4 Transfers.
* | | |110 = 2 Transfers.
* | | |111 = 1 Transfers.
* | | |Note: This field is only useful in burst transfer type.
* |[7] |TBINTDIS |Table Interrupt Disable Bit
* | | |This field can be used to decide whether to enable table interrupt or not
* | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
* | | |0 = Table interrupt Enabled.
* | | |1 = Table interrupt Disabled.
* | | |Note: If this bit set to 1, the TEMPTYF will not be set.
* |[9:8] |SAINC |Source Address Increment
* | | |This field is used to set the source address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[11:10] |DAINC |Destination Address Increment
* | | |This field is used to set the destination address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[13:12] |TXWIDTH |Transfer Width Selection
* | | |This field is used for transfer width.
* | | |00 = One byte (8 bit) is transferred for every operation.
* | | |01 = One half-word (16 bit) is transferred for every operation.
* | | |10 = One word (32-bit) is transferred for every operation.
* | | |11 = Reserved.
* | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
* | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment
* | | |The source address is aligned when TXWIDTH is byte or half-word transfer.
* |[14] |TXACK |Transfer Acknowledge Selection
* | | |0 = transfer ack when transfer done.
* | | |1 = transfer ack when PDMA get transfer data.
* |[15] |STRIDEEN |Stride Mode Enable Bit
* | | |0 = Stride transfer mode Disabled.
* | | |1 = Stride transfer mode Enabled.
* |[31:16] |TXCNT |Transfer Count
* | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
* | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
* @var DSCT_T::SA
* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SA |PDMA Transfer Source Address Register
* | | |This field indicates a 32-bit source address of PDMA controller.
* | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
* @var DSCT_T::DA
* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DA |PDMA Transfer Destination Address Register
* | | |This field indicates a 32-bit destination address of PDMA controller.
* | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
* @var DSCT_T::NEXT
* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FIRST |PDMA First Descriptor Table Offset
* | | |This field indicates the offset of the first descriptor table address in system memory.
* | | |Write Operation:
* | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
* | | |Read Operation:
* | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
* | | |Note1: The first descriptor table address must be word boundary.
* | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
* |[31:16] |NEXT |PDMA Next Descriptor Table Offset
* | | |This field indicates the offset of next descriptor table address in system memory.
* | | |Note: write operation is useless in this field.
*/
__IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */
__IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */
__IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */
__IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */
} DSCT_T;
typedef struct
{
/**
* @var STRIDE_T::STCR
* Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |STC |PDMA Stride Transfer Count
* | | |The 16-bit register defines the stride transfer count of each row.
* @var STRIDE_T::ASOCR
* Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SASOL |VDMA Source Address Stride Offset Length
* | | |The 16-bit register defines the source address stride transfer offset count of each row.
* |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
* | | |The 16-bit register defines the destination address stride transfer offset count of each row.
*/
__IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */
__IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */
} STRIDE_T;
typedef struct
{
/**
* @var REPEAT_T::AICTL
* Offset: 0x600 Address Interval Control Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SAICNT |PDMA Source Address Interval Count
* | | |The 16-bit register defines the source address interval count of each row.
* |[31:16] |DAICNT |PDMA Destination Address Interval Count
* | | |The 16-bit register defines the destination address interval count of each row.
* @var REPEAT_T::RCNT
* Offset: 0x604 Repeat Count Register of PDMA Channe n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCNT |PDMA Repeat Count
* | | |The 16-bit register defines the repeat times of block transfer.
*/
__IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */
__IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */
} REPEAT_T;
typedef struct
{
/**
* @var PDMA_T::CURSCAT
* Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
* | | |This field indicates a 32-bit current external description address of PDMA controller.
* | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
* @var PDMA_T::CHCTL
* Offset: 0x400 PDMA Channel Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHENn |PDMA Channel Enable Bit
* | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
* | | |0 = PDMA channel [n] Disabled.
* | | |1 = PDMA channel [n] Enabled.
* | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
* @var PDMA_T::PAUSE
* Offset: 0x404 PDMA Transfer Pause Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)
* | | |User can set PAUSEn bit field to pause the PDMA transfer
* | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
* | | |If re-enable the paused channel again, the remaining transfers will be processed.
* | | |0 = No effect.
* | | |1 = Pause PDMA channel n transfer.
* @var PDMA_T::SWREQ
* Offset: 0x408 PDMA Software Request Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SWREQn |PDMA Software Request Register (Write Only)
* | | |Set this bit to 1 to generate a software request to PDMA [n].
* | | |0 = No effect.
* | | |1 = Generate a software request.
* | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
* | | |Active flag may be triggered by software request or peripheral request.
* | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
* @var PDMA_T::TRGSTS
* Offset: 0x40C PDMA Channel Request Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)
* | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
* | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
* | | |0 = PDMA Channel n has no request.
* | | |1 = PDMA Channel n has a request.
* | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
* @var PDMA_T::PRISET
* Offset: 0x410 PDMA Fixed Priority Setting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register
* | | |Set this bit to 1 to enable fixed priority level.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set PDMA channel [n] to fixed priority channel.
* | | |Read Operation:
* | | |0 = Corresponding PDMA channel is round-robin priority.
* | | |1 = Corresponding PDMA channel is fixed priority.
* | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
* @var PDMA_T::PRICLR
* Offset: 0x414 PDMA Fixed Priority Clear Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
* | | |Set this bit to 1 to clear fixed priority level.
* | | |0 = No effect.
* | | |1 = Clear PDMA channel [n] fixed priority setting.
* | | |Note: User can read PDMA_PRISET register to know the channel priority.
* @var PDMA_T::INTEN
* Offset: 0x418 PDMA Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |INTENn |PDMA Interrupt Enable Register
* | | |This field is used for enabling PDMA channel[n] interrupt.
* | | |0 = PDMA channel n interrupt Disabled.
* | | |1 = PDMA channel n interrupt Enabled.
* @var PDMA_T::INTSTS
* Offset: 0x41C PDMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
* | | |0 = No AHB bus ERROR response received.
* | | |1 = AHB bus ERROR response received.
* |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
* | | |0 = Not finished yet.
* | | |1 = PDMA channel has finished transmission.
* |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* |[8] |REQTOF0 |Request Time-out Flag for Channel 0
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* |[9] |REQTOF1 |Request Time-out Flag for Channel 1
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* @var PDMA_T::ABTSTS
* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
* | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
* | | |0 = No AHB bus ERROR response received when channel n transfer.
* | | |1 = AHB bus ERROR response received when channel n transfer.
* @var PDMA_T::TDSTS
* Offset: 0x424 PDMA Channel Transfer Done Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TDIFn |Transfer Done Flag Register
* | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
* | | |0 = PDMA channel transfer has not finished.
* | | |1 = PDMA channel has finished transmission.
* @var PDMA_T::ALIGN
* Offset: 0x428 PDMA Transfer Alignment Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ALIGNn |Transfer Alignment Flag Register
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* @var PDMA_T::TACTSTS
* Offset: 0x42C PDMA Transfer Active Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)
* | | |This bit indicates which PDMA channel is in active.
* | | |0 = PDMA channel is not finished.
* | | |1 = PDMA channel is active.
* @var PDMA_T::TOUTPSC
* Offset: 0x430 PDMA Time-out Prescaler Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8.
* | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9.
* | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10.
* | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11.
* | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12.
* | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13.
* | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14.
* | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15.
* |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8.
* | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9.
* | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10.
* | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11.
* | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12.
* | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13.
* | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14.
* | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15.
* @var PDMA_T::TOUTEN
* Offset: 0x434 PDMA Time-out Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit
* | | |0 = PDMA Channel 0 time-out function Disable.
* | | |1 = PDMA Channel 0 time-out function Enable.
* |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit
* | | |0 = PDMA Channel 1 time-out function Disable.
* | | |1 = PDMA Channel 1 time-out function Enable.
* @var PDMA_T::TOUTIEN
* Offset: 0x438 PDMA Time-out Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit
* | | |0 = PDMA Channel 0 time-out interrupt Disable.
* | | |1 = PDMA Channel 0 time-out interrupt Enable.
* |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit
* | | |0 = PDMA Channel 1 time-out interrupt Disable.
* | | |1 = PDMA Channel 1 time-out interrupt Enable.
* @var PDMA_T::SCATBA
* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register
* | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
* | | |The next link address equation is
* | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
* | | |Note: Only useful in Scatter-Gather mode.
* @var PDMA_T::TOC0_1
* Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TOC0 |Time-out Counter for Channel 0
* | | |This controls the period of time-out function for channel 0
* | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
* | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1.
* |[31:16] |TOC1 |Time-out Counter for Channel 1
* | | |This controls the period of time-out function for channel 1
* | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock
* | | |The example of time-out period can refer TOC0 bit description.
* @var PDMA_T::CHRST
* Offset: 0x460 PDMA Channel Reset Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHnRST |Channel N Reset
* | | |0 = corresponding channel n not reset.
* | | |1 = corresponding channel n is reset.
* @var PDMA_T::REQSEL0_3
* Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC0 |Channel 0 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 0
* | | |User can configure the peripheral by setting REQSRC0.
* | | |0 = Disable PDMA.
* | | |1 = Reserved.
* | | |2 = Channel connects to USB_TX.
* | | |3 = Channel connects to USB_RX.
* | | |4 = Channel connects to UART0_TX.
* | | |5 = Channel connects to UART0_RX.
* | | |6 = Channel connects to UART1_TX.
* | | |7 = Channel connects to UART1_RX.
* | | |8 = Channel connects to UART2_TX.
* | | |9 = Channel connects to UART2_RX.
* | | |10 = Channel connects to UART3_TX.
* | | |11 = Channel connects to UART3_RX.
* | | |12 = Channel connects to UART4_TX.
* | | |13 = Channel connects to UART4_RX.
* | | |14 = Channel connects to UART5_TX.
* | | |15 = Channel connects to UART5_RX.
* | | |16 = Channel connects to USCI0_TX.
* | | |17 = Channel connects to USCI0_RX.
* | | |18 = Channel connects to USCI1_TX.
* | | |19 = Channel connects to USCI1_RX.
* | | |20 = Channel connects to QSPI0_TX.
* | | |21 = Channel connects to QSPI0_RX.
* | | |22 = Channel connects to SPI0_TX.
* | | |23 = Channel connects to SPI0_RX.
* | | |24 = Channel connects to SPI1_TX.
* | | |25 = Channel connects to SPI1_RX.
* | | |26 = Channel connects to SPI2_TX.
* | | |27 = Channel connects to SPI2_RX.
* | | |28 = Channel connects to SPI3_TX.
* | | |29 = Channel connects to SPI3_RX.
* | | |30 = Channel connects to ADC_RX.
* | | |32 = Channel connects to EPWM0_P1_RX.
* | | |33 = Channel connects to EPWM0_P2_RX.
* | | |34 = Channel connects to EPWM0_P3_RX.
* | | |35 = Channel connects to EPWM1_P1_RX.
* | | |36 = Channel connects to EPWM1_P2_RX.
* | | |37 = Channel connects to EPWM1_P3_RX.
* | | |38 = Channel connects to I2C0_TX.
* | | |39 = Channel connects to I2C0_RX.
* | | |40 = Channel connects to I2C1_TX.
* | | |41 = Channel connects to I2C1_RX.
* | | |42 = Channel connects to I2C2_TX.
* | | |43 = Channel connects to I2C2_RX.
* | | |44 = Channel connects to I2S0_TX.
* | | |45 = Channel connects to I2S0_RX.
* | | |46 = Channel connects to TMR0.
* | | |47 = Channel connects to TMR1.
* | | |48 = Channel connects to TMR2.
* | | |49 = Channel connects to TMR3.
* | | |50 = Channel connects to TMR4.
* | | |51 = Channel connects to TMR5.
* | | |52 = Channel connects to DAC0_TX.
* | | |53 = Channel connects to DAC1_TX.
* | | |54 = Channel connects to EPWM0_CH0_TX.
* | | |55 = Channel connects to EPWM0_CH1_TX.
* | | |56 = Channel connects to EPWM0_CH2_TX.
* | | |57 = Channel connects to EPWM0_CH3_TX.
* | | |58 = Channel connects to EPWM0_CH4_TX.
* | | |59 = Channel connects to EPWM0_CH5_TX.
* | | |60 = Channel connects to EPWM1_CH0_TX.
* | | |61 = Channel connects to EPWM1_CH1_TX.
* | | |62 = Channel connects to EPWM1_CH2_TX.
* | | |63 = Channel connects to EPWM1_CH3_TX.
* | | |64 = Channel connects to EPWM1_CH4_TX.
* | | |65 = Channel connects to EPWM1_CH5_TX.
* | | |Others = Reserved.
* | | |Note 1: A request source cannot assign to two channels at the same time.
* | | |Note 2: This field is useless when transfer between memory and memory.
* |[14:8] |REQSRC1 |Channel 1 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 1
* | | |User can configure the peripheral setting by REQSRC1.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC2 |Channel 2 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 2
* | | |User can configure the peripheral setting by REQSRC2.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC3 |Channel 3 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 3
* | | |User can configure the peripheral setting by REQSRC3.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL4_7
* Offset: 0x484 PDMA Request Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC4 |Channel 4 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 4
* | | |User can configure the peripheral setting by REQSRC4.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC5 |Channel 5 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 5
* | | |User can configure the peripheral setting by REQSRC5.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC6 |Channel 6 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 6
* | | |User can configure the peripheral setting by REQSRC6.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC7 |Channel 7 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 7
* | | |User can configure the peripheral setting by REQSRC7.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
*/
DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */
__I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */
__I uint32_t RESERVE0[216];
__IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
__O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
__O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
__I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
__IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
__O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
__IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
__IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
__IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
__IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
__I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
__IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
__IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
__IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
__IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */
__IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */
__I uint32_t RESERVE1[7];
__IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
__I uint32_t RESERVE2[7];
__IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */
__IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */
__I uint32_t RESERVE4[30];
STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */
__IO uint32_t RESERVE5[52];
REPEAT_T REPEAT[2]; /*!< [0x0600 ~ 0x060C] Repeat Count Function Control Register of PDMA Channel 0 ~ 1 */
} PDMA_T;
/**
@addtogroup PDMA_CONST PDMA Bit Field Definition
Constant Definitions for PDMA Controller
@{
*/
#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */
#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */
#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */
#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */
#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */
#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */
#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */
#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */
#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */
#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */
#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */
#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */
#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */
#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */
#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */
#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */
#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */
#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */
#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */
#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */
#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */
#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */
#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */
#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */
#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */
#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */
#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */
#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */
#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */
#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */
#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */
#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */
#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */
#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */
#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */
#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */
#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */
#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */
#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */
#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */
#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */
#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */
/**@}*/ /* PDMA_CONST */
/**@}*/ /* end of PDMA register group */
/**@}*/ /* end of REGISTER group */
#endif /* __PDMA_REG_H__ */

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/**************************************************************************//**
* @file qei_reg.h
* @version V1.00
* @brief QEI register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QEI_REG_H__
#define __QEI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Quadrature Encoder Interface -------------------------*/
/**
@addtogroup QEI Quadrature Encoder Interface(QEI)
Memory Mapped Structure for QEI Controller
@{
*/
typedef struct
{
/**
* @var QEI_T::CNT
* Offset: 0x00 QEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
* | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
* | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.
* @var QEI_T::CNTHOLD
* Offset: 0x04 QEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
* @var QEI_T::CNTLATCH
* Offset: 0x08 QEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
* @var QEI_T::CNTCMP
* Offset: 0x0C QEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var QEI_T::CNTMAX
* Offset: 0x14 QEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
* @var QEI_T::CTL
* Offset: 0x18 QEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = QEI_CLK.
* | | |001 = QEI_CLK/2.
* | | |010 = QEI_CLK/4.
* | | |011 = QEI_CLK/16.
* | | |100 = QEI_CLK/32.
* | | |101 = QEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of QEI controller Enabled.
* | | |1 = The noise filter of QEI controller Disabled.
* |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
* | | |0 = QEA input to QEI Controller Disabled.
* | | |1 = QEA input to QEI Controller Enabled.
* |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
* | | |0 = QEB input to QEI Controller Disabled.
* | | |1 = QEB input to QEI Controller Enabled.
* |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
* | | |0 = IDX input to QEI Controller Disabled.
* | | |1 = IDX input to QEI Controller Enabled.
* |[9:8] |MODE |QEI Counting Mode Selection
* | | |There are four quadrature encoder pulse counter operation modes.
* | | |00 = X4 Free-counting Mode.
* | | |01 = X2 Free-counting Mode.
* | | |10 = X4 Compare-counting Mode.
* | | |11 = X2 Compare-counting Mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inverse to QEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inverse to QEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inverse to QEI controller.
* |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
* | | |0 = CMPF can trigger QEI controller interrupt Disabled.
* | | |1 = CMPF can trigger QEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger QEI interrupt Disabled.
* | | |1 = The IDXF can trigger QEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold QEI_CNT Control
* | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
* | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
* |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
* | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
* | | |0 = The index signal latch QEI counter function Disabled.
* | | |1 = The index signal latch QEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).
* | | |0 = Reload function Disabled.
* | | |1 = QEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |the Compare Function Enable Bit
* | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
* | | |0 = QEI controller function Disabled.
* | | |1 = QEI controller function Enabled.
* @var QEI_T::STATUS
* Offset: 0x2C QEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
* | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
* | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in QEI counter.
* | | |1 = QEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while QEI counter counting direction is changed
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in QEI counter counting direction.
* | | |1 = QEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = QEI Counter is in down-counting.
* | | |1 = QEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
*/
__IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
__I uint32_t RESERVE0[1];
__IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
__I uint32_t RESERVE1[4];
__IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
} QEI_T;
/**
@addtogroup QEI_CONST QEI Bit Field Definition
Constant Definitions for QEI Controller
@{
*/
#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
/**@}*/ /* QEI_CONST */
/**@}*/ /* end of QEI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __QEI_REG_H__ */

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/**************************************************************************//**
* @file qspi_reg.h
* @version V1.00
* @brief QSPI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_REG_H__
#define __QSPI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI)
Memory Mapped Structure for QSPI Controller
@{
*/
typedef struct
{
/**
* @var QSPI_T::CTL
* Offset: 0x00 QSPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |QSPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
* | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]).
* |[3] |CLKPOL |Clock Polarity
* | | |0 = QSPI bus clock is idle low.
* | | |1 = QSPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
* | | |Note: In TX DTR mode, SUSPITV equals to 0x0.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = QSPI operates in full-duplex transfer.
* | | |1 = QSPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit
* | | |0 = 2-Bit Transfer mode Disabled.
* | | |1 = 2-Bit Transfer mode Enabled.
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = QSPI unit transfer interrupt Disabled.
* | | |1 = QSPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = QSPI data is input direction.
* | | |1 = QSPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit
* | | |0 = TX DTR mode Disabled.
* | | |1 = TX DTR mode Enabled.
* | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode.
* @var QSPI_T::CLKDIV
* Offset: 0x04 QSPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
* @var QSPI_T::SSCTL
* Offset: 0x08 QSPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = Set the QSPIx_SS line to inactive state.
* | | |1 = Set the QSPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS line at inactive state.
* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
* | | |Note: Master mode only.
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
* | | |0 = The slave selection signal QSPIx_SS is active low.
* | | |1 = The slave selection signal QSPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* | | |Note: Master mode only.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var QSPI_T::PDMACTL
* Offset: 0x0C QSPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
* @var QSPI_T::FIFOCTL
* Offset: 0x10 QSPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode.
* | | |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
* | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode.
* | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode
* | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
* | | |Note: Slave mode only.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
* @var QSPI_T::STATUS
* Offset: 0x14 QSPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = QSPI controller is in idle state.
* | | |1 = QSPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
* | | |e.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* | | |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF
* | | |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = QSPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag
* | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |QSPI Enable Status (Read Only)
* | | |0 = The QSPI controller is disabled.
* | | |1 = The QSPI controller is enabled.
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var QSPI_T::STATUS2
* Offset: 0x18 QSPI Status2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data
* | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode
* | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled.
* | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]).
* | | |Note 2: Slave mode only.
* @var QSPI_T::TX
* Offset: 0x20 QSPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.
* | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var QSPI_T::RX
* Offset: 0x30 QSPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register (Read Only)
* | | |There are 8-level FIFO buffers in this controller.
* | | |The data receive register holds the data received from QSPI data input pin.
* | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
*/
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
__I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */
__I uint32_t RESERVE0[1];
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
} QSPI_T;
/**
@addtogroup QSPI_CONST QSPI Bit Field Definition
Constant Definitions for QSPI Controller
@{
*/
#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */
#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
#define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */
#define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */
#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */
#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */
#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
/**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __QSPI_REG_H__ */

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/**************************************************************************//**
* @file sc_reg.h
* @version V1.00
* @brief SC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SC_REG_H__
#define __SC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Smart Card Host Interface Controller -------------------------*/
/**
@addtogroup SC Smart Card Host Interface Controller(SC)
Memory Mapped Structure for SC Controller
@{
*/
typedef struct
{
/**
* @var SC_T::DAT
* Offset: 0x00 SC Receive/Transmit Holding Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Receive/Transmit Holding Buffer
* | | |Write Operation:
* | | |By writing data to DAT, the SC will send out an 8-bit data.
* | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
* | | |Read Operation:
* | | |By reading DAT, the SC will return an 8-bit received data.
* @var SC_T::CTL
* Offset: 0x04 SC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SCEN |SC Controller Enable Bit
* | | |Set this bit to 1 to enable SC operation.
* | | |0 = SC will force all transition to IDLE state.
* | | |1 = SC controller is enabled and all function can work correctly.
* | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
* |[1] |RXOFF |RX Transition Disable Control Bit
* | | |This bit is used for disable Rx transition function.
* | | |0 = The receiver Enabled.
* | | |1 = The receiver Disabled.
* | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[2] |TXOFF |TX Transition Disable Control Bit
* | | |This bit is used for disable Tx transition function.
* | | |0 = The transceiver Enabled.
* | | |1 = The transceiver Disabled.
* |[3] |AUTOCEN |Auto Convention Enable Bit
* | | |This bit is used for enable auto convention function.
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F
* | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
* | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
* |[5:4] |CONSEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[7:6] |RXTRGLV |Rx Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
* | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
* | | |00 = Rx Buffer Trigger Level with 01 bytes.
* | | |01 = Rx Buffer Trigger Level with 02 bytes.
* | | |10 = Rx Buffer Trigger Level with 03 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time (BGT)
* | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions
* | | |This field indicates the counter for the bit length of block guard time
* | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMRSEL |Timer Channel Selection
* | | |00 = All internal timer function Disabled.
* | | |.
* | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
* | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
* | | |Other configurations are reserve
* |[15] |NSB |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode).
* | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode).
* | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
* | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
* |[18:16] |RXRTY |RX Error Retry Count Number
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
* | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when RXRTYEN enabled
* | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
* |[19] |RXRTYEN |RX Error Retry Enable Bit
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill in the RXRTY value before enabling this bit.
* |[22:20] |TXRTY |TX Error Retry Count Number
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
* | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when TXRTYEN enabled
* | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
* |[23] |TXRTYEN |TX Error Retry Enable Bit
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* |[25:24] |CDDBSEL |Card Detect De-bounce Selection
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.
* | | |Other configurations are reserved.
* |[26] |CDLV |Card Detect Level Selection
* | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
* | | |Note: User must select card detect level before Smart Card controller enabled.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
* | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
* | | |1 = Last value is synchronizing.
* @var SC_T::ALTCTL
* Offset: 0x08 SC Alternate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXRST |TX Software Reset
* | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[1] |RXRST |Rx Software Reset
* | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the Rx internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by deactivation sequence.
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[3] |ACTEN |Activation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by activation sequence.
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data
* | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
* |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by warm reset sequence.
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
* | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
* |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
* | | |This bit enables Timer 0 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed
* |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
* | | |This bit enables Timer 1 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
* | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
* | | |This bit enables Timer 2 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
* | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[9:8] |INITSEL |Initial Timing Selection
* | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
* | | |The unit of initial timing is SC module clock.
* | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence.
* | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence.
* | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence.
* | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
* |[11] |ADACEN |Auto Deactivation When Card Removal
* | | |This bit is used for enable hardware auto deactivation when smart card is removed.
* | | |0 = Auto deactivation Disabled.
* | | |1 = Auto deactivation Enabled.
* | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set
* | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
* |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
* | | |This bit enables the receiver block guard time function.
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
* |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
* |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
* | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::EGT
* Offset: 0x0C SC Extra Guard Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extra Guard Time
* | | |This field indicates the extra guard time value.
* | | |Note: The extra guard time unit is ETU base.
* @var SC_T::RXTOUT
* Offset: 0x10 SC Receive Buffer Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
* | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
* | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.
* | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
* | | |Note2: Filling in all 0 to this field indicates to disable this function.
* @var SC_T::ETUCTL
* Offset: 0x14 SC Element Time Unit Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETURDIV |ETU Rate Divider
* | | |The field is used for ETU clock rate divider.
* | | |The real ETU is ETURDIV + 1.
* | | |Note: User can configure this field, but this field must be greater than 0x04.
* @var SC_T::INTEN
* Offset: 0x18 SC Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
* | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
* | | |0 = Receive data reach trigger level interrupt Disabled.
* | | |1 = Receive data reach trigger level interrupt Enabled.
* |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
* | | |This field is used to enable transmit buffer empty interrupt.
* | | |0 = Transmit buffer empty interrupt Disabled.
* | | |1 = Transmit buffer empty interrupt Enabled.
* |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
* | | |This field is used to enable transfer error interrupt
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt Disabled.
* | | |1 = Transfer error interrupt Enabled.
* |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
* | | |This field is used to enable Timer0 interrupt function.
* | | |0 = Timer0 interrupt Disabled.
* | | |1 = Timer0 interrupt Enabled.
* |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
* | | |This field is used to enable the Timer1 interrupt function.
* | | |0 = Timer1 interrupt Disabled.
* | | |1 = Timer1 interrupt Enabled.
* |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
* | | |This field is used to enable Timer2 interrupt function.
* | | |0 = Timer2 interrupt Disabled.
* | | |1 = Timer2 interrupt Enabled.
* |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
* | | |This field is used to enable block guard time interrupt in receive direction.
* | | |0 = Block guard time interrupt Disabled.
* | | |1 = Block guard time interrupt Enabled.
* | | |Note: This bit is valid only for receive receive direction block guard time.
* |[7] |CDIEN |Card Detect Interrupt Enable Bit
* | | |This field is used to enable card detect interrupt
* | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
* | | |0 = Card detect interrupt Disabled.
* | | |1 = Card detect interrupt Enabled.
* |[8] |INITIEN |Initial End Interrupt Enable Bit
* | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
* | | |0 = Initial end interrupt Disabled.
* | | |1 = Initial end interrupt Enabled.
* |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
* | | |This field is used to enable receiver buffer time-out interrupt.
* | | |0 = Receiver buffer time-out interrupt Disabled.
* | | |1 = Receiver buffer time-out interrupt Enabled.
* |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
* | | |This field is used to enable auto-convention error interrupt.
* | | |0 = Auto-convention error interrupt Disabled.
* | | |1 = Auto-convention error interrupt Enabled.
* @var SC_T::INTSTS
* Offset: 0x1C SC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
* | | |0 = Number of receive buffer is less than RXTRGLV setting.
* | | |1 = Number of receive buffer data equals the RXTRGLV setting.
* | | |Note: This bit is read only
* | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
* |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* | | |Note: This bit is read only
* | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
* |[2] |TERRIF |Transfer Error Interrupt Status Flag
* | | |This field is used for transfer error interrupt status flag
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt did not occur.
* | | |1 = Transfer error interrupt occurred.
* | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[3] |TMR0IF |Timer0 Interrupt Status Flag
* | | |This field is used for Timer0 interrupt status flag.
* | | |0 = Timer0 interrupt did not occur.
* | | |1 = Timer0 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[4] |TMR1IF |Timer1 Interrupt Status Flag
* | | |This field is used for Timer1 interrupt status flag.
* | | |0 = Timer1 interrupt did not occur.
* | | |1 = Timer1 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[5] |TMR2IF |Timer2 Interrupt Status Flag
* | | |This field is used for Timer2 interrupt status flag.
* | | |0 = Timer2 interrupt did not occur.
* | | |1 = Timer2 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[6] |BGTIF |Block Guard Time Interrupt Status Flag
* | | |This field is used for indicate block guard time interrupt status flag in receive direction.
* | | |0 = Block guard time interrupt did not occur.
* | | |1 = Block guard time interrupt occurred.
* | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag
* | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
* | | |0 = Card detect event did not occur.
* | | |1 = Card detect event occurred.
* | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
* |[8] |INITIF |Initial End Interrupt Status Flag
* | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
* | | |0 = Initial sequence is not complete.
* | | |1 = Initial sequence is completed.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
* | | |This field is used for indicate receive buffer time-out interrupt status flag.
* | | |0 = Receive buffer time-out interrupt did not occur.
* | | |1 = Receive buffer time-out interrupt occurred.
* | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
* |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
* | | |This field indicates auto convention sequence error.
* | | |0 = Received TS at ATR state is 0x3B or 0x3F.
* | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
* | | |Note: This bit can be cleared by writing 1 to it.
* @var SC_T::STATUS
* Offset: 0x20 SC Transfer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOV |Receive Overflow Error Status Flag
* | | |This bit is set when Rx buffer overflow.
* | | |0 = Rx buffer is not overflow.
* | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
* | | |This bit indicates Rx buffer empty or not.
* | | |0 = Rx buffer is not empty.
* | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
* |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
* | | |This bit indicates Rx buffer full or not.
* | | |0 = Rx buffer count is less than 4.
* | | |1 = Rx buffer count equals to 4.
* |[4] |PEF |Receiver Parity Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
* | | |0 = Receiver parity error flag did not occur.
* | | |1 = Receiver parity error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[5] |FEF |Receiver Frame Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = Receiver frame error flag did not occur.
* | | |1 = Receiver frame error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[6] |BEF |Receiver Break Error Status Flag
* | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).
* | | |0 = Receiver break error flag did not occur.
* | | |1 = Receiver break error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
* | | |This bit is set when Tx buffer overflow.
* | | |0 = Tx buffer is not overflow.
* | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |0 = Tx buffer is not empty.
* | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register.
* | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
* |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates Tx buffer full or not.
* | | |0 = Tx buffer count is less than 4.
* | | |1 = Tx buffer count equals to 4.
* |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card removed.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
* |[12] |CINSERT |Card Insert Status of SCn_CD Pin
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
* |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
* | | |This bit is the pin status of SCn_CD.
* | | |0 = The SCn_CD pin state at low.
* | | |1 = The SCn_CD pin state at high.
* |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
* | | |This field indicates the Rx buffer pointer status
* | | |When SC controller receives one byte from external device, RXPOINT increases one
* | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
* |[21] |RXRERR |Receiver Retry Error
* | | |This bit is used for receiver error retry and set by hardware.
* | | |0 = No Rx retry transfer.
* | | |1 = Rx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
* | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[22] |RXOVERR |Receiver over Retry Error
* | | |This bit is used for receiver retry counts over than retry number limitation.
* | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[23] |RXACT |Receiver in Active Status Flag (Read Only)
* | | |This bit indicates Rx transfer status.
* | | |0 = This bit is cleared automatically when Rx transfer is finished.
* | | |1 = This bit is set by hardware when Rx transfer is in active.
* | | |Note: This bit is read only.
* | | |Note2:
* |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
* | | |This field indicates the Tx buffer pointer status
* | | |When CPU writes data into SCn_DAT, TXPOINT increases one
* | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
* |[29] |TXRERR |Transmitter Retry Error
* | | |This bit is used for indicate transmitter error retry and set by hardware..
* | | |0 = No Tx retry transfer.
* | | |1 = Tx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.
* |[30] |TXOVERR |Transmitter over Retry Error
* | | |This bit is used for transmitter retry counts over than retry number limitation.
* | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[31] |TXACT |Transmit in Active Status Flag (Read Only)
* | | |This bit indicates Tx transmit status.
* | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
* | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted.
* | | |Note: This bit is read only.
* @var SC_T::PINCTL
* Offset: 0x24 SC Pin Control State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWREN |SCn_PWR Pin Signal
* | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
* | | |Write this field to drive SCn_PWR pin
* | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
* | | |Read this field to get SCn_PWR signal status.
* | | |0 = SCn_PWR signal status is low.
* | | |1 = SCn_PWR signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[1] |RSTEN |SCn_RST Pin Signal
* | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
* | | |Write this field to drive SCn_RST pin.
* | | |0 = Drive SCn_RST pin to low.
* | | |1 = Drive SCn_RST pin to high.
* | | |Read this field to get SCn_RST signal status.
* | | |0 = SCn_RST signal status is low.
* | | |1 = SCn_RST signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[5] |CSTOPLV |SCn_CLK Pin Stop Level
* | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode.
* | | |0 = SCn_CLK pin keeps at low when SC clock stopped.
* | | |1 = SCn_CLK pin keeps at high when SC clock stopped.
* |[6] |CLKKEEP |SC Clock Enable Bit
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[9] |SCDATA |SCn_DATA Pin Signal
* | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
* | | |0 = Drive SCn_DATA pin to low.
* | | |1 = Drive SCn_DATA pin to high.
* | | |Read this field to get SCn_DATA signal status.
* | | |0 = SCn_DATA signal status is low.
* | | |1 = SCn_DATA signal status is high.
* | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when SC is in these modes.
* |[11] |PWRINV |SCn_PWR Pin Inverse
* | | |This bit is used for inverse the SCn_PWR pin.
* | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
* | | |0 = SCn_PWR pin inverse Disabled
* | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0.
* | | |1 = SCn_PWR pin inverse Enabled
* | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1.
* | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
* |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
* | | |This bit is the pin status of SCn_DATA.
* | | |0 = The SCn_DATA pin status is low.
* | | |1 = The SCn_DATA pin status is high.
* | | |Note:
* |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
* | | |This bit is the pin status of SCn_PWR.
* | | |0 = SCn_PWR pin to low.
* | | |1 = SCn_PWR pin to high.
* |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
* | | |This bit is the pin status of SCn_RST.
* | | |0 = SCn_RST pin is low.
* | | |1 = SCn_RST pin is high.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL0
* Offset: 0x28 SC Internal Timer0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer0 Counter Value
* | | |This field indicates the internal Timer0 counter values.
* | | |Note: Unit of Timer0 counter is ETU base.
* |[27:24] |OPMODE |Timer0 Operation Mode Selection
* | | |This field indicates the internal 24-bit Timer0 operation selection.
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL1
* Offset: 0x2C SC Internal Timer1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value
* | | |This field indicates the internal Timer1 counter values.
* | | |Note: Unit of Timer1 counter is ETU base.
* |[27:24] |OPMODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer1 operation selection.
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL2
* Offset: 0x30 SC Internal Timer2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value
* | | |This field indicates the internal Timer2 counter values.
* | | |Note: Unit of Timer2 counter is ETU base.
* |[27:24] |OPMODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer2 operation selection
* | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::UARTCTL
* Offset: 0x34 SC UART Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UARTEN |UART Mode Enable Bit
* | | |Sets this bit to enable UART mode function.
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
* | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
* | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
* |[5:4] |WLS |Word Length Selection
* | | |This field is used for select UART data length.
* | | |00 = Word length is 8 bits.
* | | |01 = Word length is 7 bits.
* | | |10 = Word length is 6 bits.
* | | |11 = Word length is 5 bits.
* | | |Note: In smart card mode, this WLS must be u201800'.
* |[6] |PBOFF |Parity Bit Disable Control
* | | |Sets this bit is used for disable parity check function.
* | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit).
* |[7] |OPE |Odd Parity Enable Bit
* | | |This is used for odd/even parity selection.
* | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBOFF bit is u20180'.
* @var SC_T::ACTCTL
* Offset: 0x4C SC Activation Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
* | | |This field provide the configurable cycles to extend the activation time T1 period.
* | | |The cycle scaling factor is 2048.
* | | |Extend cycles = (filled value * 2048) cycles.
* | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence.
* | | |For example,
* | | |SCLK = 4MHz, each cycle = 0.25us,.
* | | |Filled 20 to this field
* | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
* | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
*/
__IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
__IO uint32_t CTL; /*!< [0x0004] SC Control Register */
__IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
__IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
__IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
__IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
__IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
__IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
__IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
__IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
__IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
__IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
__IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
__I uint32_t RESERVE0[5];
__IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{
*/
#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */
#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SC_REG_H__ */

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/**************************************************************************//**
* @file sdh_reg.h
* @version V1.00
* @brief SDH register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SDH_REG_H__
#define __SDH_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- SD Card Host Interface -------------------------*/
/**
@addtogroup SDH SD Card Host Interface(SDH)
Memory Mapped Structure for SDH Controller
@{
*/
typedef struct
{
/**
* @var SDH_T::FB
* Offset: 0x00~0x7C Shared Buffer (FIFO)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BUFFER |Shared Buffer
* | | |Buffer for DMA transfer
* @var SDH_T::DMACTL
* Offset: 0x400 DMA Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMAEN |DMA Engine Enable Bit
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers
* | | |The contents of control register will not be cleared
* | | |This bit will auto be cleared after few clock cycles.
* | | |Note: The software reset DMA related registers.
* |[3] |SGEN |Scatter-gather Function Enable Bit
* | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
* | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
* | | |The format of these Pads' will be described later).
* |[9] |DMABUSY |DMA Transfer Is in Progress
* | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
* | | |0 = DMA transfer is not in progress.
* | | |1 = DMA transfer is in progress.
* @var SDH_T::DMASA
* Offset: 0x408 DMA Transfer Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order
* | | |0 = PAD table is fetched in order.
* | | |1 = PAD table is fetched out of order.
* | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
* |[31:1] |DMASA |DMA Transfer Starting Address
* | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
* | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
* | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
* @var SDH_T::DMABCNT
* Offset: 0x40C DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)
* | | |This field indicates the remained byte count of DMA transfer
* | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
* @var SDH_T::DMAINTEN
* Offset: 0x410 DMA Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit
* | | |0 = Target abort interrupt generation Disabled during DMA transfer.
* | | |1 = Target abort interrupt generation Enabled during DMA transfer.
* |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit
* | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
* | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
* @var SDH_T::DMAINTSTS
* Offset: 0x414 DMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note1: This bit is read only, but can be cleared by writing '1' to it.
* | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
* | | |DMA will stop transfer and respond this event and then go to IDLE state
* | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
* |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
* | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
* | | |0 = No EOT encountered before DMA transfer finished.
* | | |1 = EOT encountered before DMA transfer finished.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::GCTL
* Offset: 0x800 Global Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset SD host
* | | |The contents of control register will not be cleared
* | | |This bit will auto cleared after reset complete.
* |[1] |SDEN |Secure Digital Functionality Enable Bit
* | | |0 = SD functionality disabled.
* | | |1 = SD functionality enabled.
* @var SDH_T::GINTEN
* Offset: 0x804 Global Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit
* | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
* | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
* @var SDH_T::GINTSTS
* Offset: 0x808 Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::CTL
* Offset: 0x820 SD Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |COEN |Command Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output a command to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[1] |RIEN |Response Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[2] |DIEN |Data Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[3] |DOEN |Data Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[4] |R2EN |Response R2 Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 8 clock cycles.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0
* | | |0 = SD host decided when to output clock and when to disable clock output automatically.
* | | |1 = SD clock always keeps free running.
* |[13:8] |CMDCODE |SD Command Code
* | | |This register contains the SD command code (0x00 ~ 0x3F).
* |[14] |CTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset the internal state machine and counters
* | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared)
* | | |This bit will be auto cleared after few clock cycles.
* |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)
* | | |0 = Data bus width is 1-bit.
* | | |1 = Data bus width is 4-bit.
* |[23:16] |BLKCNT |Block Counts to Be Transferred or Received
* | | |This field contains the block counts for data-in and data-out transfer
* | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
* | | |Don't fill 0x0 to this field.
* | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
* |[27:24] |SDNWR |NWR Parameter for Block Write Operation
* | | |This value indicates the NWR parameter for data block write operation in SD clock counts
* | | |The actual clock cycle will be SDNWR+1.
* @var SDH_T::CMDARG
* Offset: 0x824 SD Command Argument Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ARGUMENT |SD Command Argument
* | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
* | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
* @var SDH_T::INTEN
* Offset: 0x828 SD Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit
* | | |0 = SD host will not generate interrupt when data-in (out) transfer done.
* | | |1 = SD host will generate interrupt when data-in (out) transfer done.
* |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
* | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
* | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
* |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
* | | |0 = SD card detection interrupt Disabled.
* | | |1 = SD card detection interrupt Enabled.
* |[12] |RTOIEN |Response Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = Response time-out interrupt Disabled.
* | | |1 = Response time-out interrupt Enabled.
* |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when data input time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = Data input time-out interrupt Disabled.
* | | |1 = Data input time-out interrupt Enabled.
* |[14] |WKIEN |Wake-up Signal Generating Enable Bit
* | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
* | | |0 = Wake-up signal generating Disabled.
* | | |1 = Wake-up signal generating Enabled.
* |[30] |CDSRC0 |SD0 Card Detect Source Selection
* | | |0 = From SD0 card's DAT3 pin.
* | | |Host need clock to got data on pin DAT3
* | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
* | | |1 = From GPIO pin.
* @var SDH_T::INTSTS
* Offset: 0x82C SD Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has finished all data-in or data-out block transfer
* | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error is occurred, software should reset SD engine
* | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in
* | | |If that response does not contain CRC7 information (ex
* | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
* | | |0 = Fault.
* | | |1 = OK.
* |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)
* | | |SD host will check CRC16 correctness after data-in transfer.
* | | |0 = Fault.
* | | |1 = OK.
* |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)
* | | |SD host will record CRC status of data-out transfer
* | | |Software could use this value to identify what type of error is during data-out transfer.
* | | |010 = Positive CRC status.
* | | |101 = Negative CRC status.
* | | |111 = SD card programming error occurs.
* |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)
* | | |This bit is the DAT0 pin status of current selected SD port.
* |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only)
* | | |This bit indicates that SD card 0 is inserted or removed
* | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
* | | |0 = No card is inserted or removed.
* | | |1 = There is a card inserted in or removed from SD0.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Response time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Data input time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only)
* | | |This bit indicates the card detect pin status of SD0, and is used for card detection
* | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
* | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
* | | |0 = Card removed.
* | | |1 = Card inserted.
* | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
* | | |0 = Card inserted.
* | | |1 = Card removed.
* |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)
* | | |This bit indicates the DAT1 pin status of SD port.
* @var SDH_T::RESP0
* Offset: 0x830 SD Receiving Response Token Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RESPTK0 |SD Receiving Response Token 0
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This field contains response bit 47-16 of the response token.
* @var SDH_T::RESP1
* Offset: 0x834 SD Receiving Response Token Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RESPTK1 |SD Receiving Response Token 1
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This register contains the bit 15-8 of the response token.
* @var SDH_T::BLEN
* Offset: 0x838 SD Block Length Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit
* | | |An 11-bit value specifies the SD transfer byte count of a block
* | | |The actual byte count is equal to BLKLEN+1.
* | | |Note: The default SD block length is 512 bytes
* @var SDH_T::TOUT
* Offset: 0x83C SD Response/Data-in Time-out Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TOUT |SD Response/Data-in Time-out Value
* | | |A 24-bit value specifies the time-out counts of response and data input
* | | |SD host controller will wait start bit of response or data-in until this value reached
* | | |The time period depends on SD engine clock frequency
* | | |Do not write a small number into this field, or you may never get response or data due to time-out.
* | | |Note: Filling 0x0 into this field will disable hardware time-out function.
*/
__IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */
__I uint32_t RESERVE0[224];
__IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */
__I uint32_t RESERVE1[1];
__IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */
__I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */
__IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */
__IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */
__I uint32_t RESERVE2[250];
__IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */
__IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */
__IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */
__I uint32_t RESERVE3[5];
__IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */
__IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */
__IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */
__IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */
__I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */
__I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */
__IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
__IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
} SDH_T;
/**
@addtogroup SDH_CONST SDH Bit Field Definition
Constant Definitions for SDH Controller
@{
*/
#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */
#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */
#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */
#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */
#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */
#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */
#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */
#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */
#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */
#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */
#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */
#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */
#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */
#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */
#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */
#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */
#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */
#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */
#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */
#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */
#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */
#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */
#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */
#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */
#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */
#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */
#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */
#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */
#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */
#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */
#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */
#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */
#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */
#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */
#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */
#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */
#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */
#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */
#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */
#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */
#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */
#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */
#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */
#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */
#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */
#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */
#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */
#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */
#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */
#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */
#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */
#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */
#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */
#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */
#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */
#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */
#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */
#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */
#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */
#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */
#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */
#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */
#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */
#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */
#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */
#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */
#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */
#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */
#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */
#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */
#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */
#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */
#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */
#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */
#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */
#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */
#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */
#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */
#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */
#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */
#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */
#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */
#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */
#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */
#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */
#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */
#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */
#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */
#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */
#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */
#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */
#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */
#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */
#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */
#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
/**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SDH_REG_H__ */

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