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M487: Adjust placement of SYS_UnlockReg in WDT reset from PD patch 

This adjustment has two purposes:
1.  Avoid misleading placement of SYS_UnlockReg for WDT clock setting
2.  Safer for power-down
pull/14524/head
Chun-Chieh Li 2021-04-08 17:18:38 +08:00
parent 9bbc8c914c
commit df4f1a3387
1 changed files with 6 additions and 2 deletions
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8
targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c
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@ -94,6 +94,9 @@ void mbed_sdk_init(void)
* start of boot process on detecting WDT reset. * start of boot process on detecting WDT reset.
*/ */
if (SYS_IS_WDT_RST()) { if (SYS_IS_WDT_RST()) {
/* Re-unlock to highlight WDT clock setting is protected */
SYS_UnlockReg();
/* Enable IP module clock */ /* Enable IP module clock */
CLK_EnableModuleClock(WDT_MODULE); CLK_EnableModuleClock(WDT_MODULE);
@ -108,8 +111,6 @@ void mbed_sdk_init(void)
*/ */
NVIC_EnableIRQ(WDT_IRQn); NVIC_EnableIRQ(WDT_IRQn);
SYS_UnlockReg();
/* Configure/Enable WDT */ /* Configure/Enable WDT */
WDT->CTL = WDT_TIMEOUT_2POW4 | // Timeout interval of 2^4 LIRC clocks WDT->CTL = WDT_TIMEOUT_2POW4 | // Timeout interval of 2^4 LIRC clocks
WDT_CTL_WDTEN_Msk | // Enable watchdog timer WDT_CTL_WDTEN_Msk | // Enable watchdog timer
@ -123,6 +124,9 @@ void mbed_sdk_init(void)
CLK_PowerDown(); CLK_PowerDown();
/* Re-unlock for safe */
SYS_UnlockReg();
/* Clear all flags & Disable WDT/INT/WK/RST */ /* Clear all flags & Disable WDT/INT/WK/RST */
WDT->CTL = (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_RSTCNT_Msk); WDT->CTL = (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_RSTCNT_Msk);