mirror of https://github.com/ARMmbed/mbed-os.git
[MAXWSNENV] Fixing comments in startup file for ARM compiler.
Kevin Gillespie
Jeremy Brodt
parent
5a81e89daa
commit
de73e4574a
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@ -1,35 +1,34 @@
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/*******************************************************************************
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* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*******************************************************************************
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*/
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;*******************************************************************************
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; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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;
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; Permission is hereby granted, free of charge, to any person obtaining a
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; copy of this software and associated documentation files (the "Software"),
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; to deal in the Software without restriction, including without limitation
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; the rights to use, copy, modify, merge, publish, distribute, sublicense,
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; and/or sell copies of the Software, and to permit persons to whom the
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; Software is furnished to do so, subject to the following conditions:
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;
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; The above copyright notice and this permission notice shall be included
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; in all copies or substantial portions of the Software.
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;
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; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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; OTHER DEALINGS IN THE SOFTWARE.
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;
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; Except as contained in this notice, the name of Maxim Integrated
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; Products, Inc. shall not be used except as stated in the Maxim Integrated
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; Products, Inc. Branding Policy.
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;
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; The mere transfer of this software does not imply any licenses
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; of trade secrets, proprietary technology, copyrights, patents,
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; trademarks, maskwork rights, or any other form of intellectual
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; property whatsoever. Maxim Integrated Products, Inc. retains all
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; ownership rights.
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;*******************************************************************************
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__initial_sp EQU 0x20008000 ; Top of RAM
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@ -44,71 +43,71 @@ __initial_sp EQU 0x20008000 ; Top of RAM
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp /* Top of Stack */
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DCD Reset_Handler /* Reset Handler */
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DCD NMI_Handler /* NMI Handler */
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DCD HardFault_Handler /* Hard Fault Handler */
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DCD DefaultIRQ_Handler /* MPU Fault Handler */
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DCD DefaultIRQ_Handler /* Bus Fault Handler */
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DCD DefaultIRQ_Handler /* Usage Fault Handler */
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DCD 0 /* Reserved */
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DCD 0 /* Reserved */
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DCD 0 /* Reserved */
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DCD 0 /* Reserved */
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DCD DefaultIRQ_Handler /* SVCall Handler */
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DCD DebugMon_Handler /* Debug Monitor Handler */
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DCD 0 /* Reserved */
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DCD DefaultIRQ_Handler /* PendSV Handler */
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DCD SysTick_IRQHandler /* SysTick Handler */
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD DefaultIRQ_Handler ; MPU Fault Handler
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DCD DefaultIRQ_Handler ; Bus Fault Handler
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DCD DefaultIRQ_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DefaultIRQ_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD DefaultIRQ_Handler ; PendSV Handler
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DCD SysTick_IRQHandler ; SysTick Handler
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/* Maxim 32610 Externals interrupts */
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DCD UART0_IRQHandler /* 16: 1 UART0 */
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DCD UART1_IRQHandler /* 17: 2 UART1 */
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DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
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DCD I2CS_IRQHandler /* 19: 4 I2C Slave */
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DCD USB_IRQHandler /* 20: 5 USB */
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DCD PMU_IRQHandler /* 21: 6 DMA */
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DCD AFE_IRQHandler /* 22: 7 AFE */
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DCD MAA_IRQHandler /* 23: 8 MAA */
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DCD AES_IRQHandler /* 24: 9 AES */
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DCD SPI0_IRQHandler /* 25:10 SPI0 */
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DCD SPI1_IRQHandler /* 26:11 SPI1 */
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DCD SPI2_IRQHandler /* 27:12 SPI2 */
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DCD TMR0_IRQHandler /* 28:13 Timer32-0 */
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DCD TMR1_IRQHandler /* 29:14 Timer32-1 */
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DCD TMR2_IRQHandler /* 30:15 Timer32-1 */
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DCD TMR3_IRQHandler /* 31:16 Timer32-2 */
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DCD RSVD0_IRQHandler /* 32:17 RSVD */
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DCD RSVD1_IRQHandler /* 33:18 RSVD */
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DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
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DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
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DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
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DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
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DCD ADC_IRQHandler /* 38:23 ADC */
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DCD FLC_IRQHandler /* 39:24 Flash Controller */
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DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */
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DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */
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DCD RTC0_IRQHandler /* 42:27 RTC INT0 */
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DCD RTC1_IRQHandler /* 43:28 RTC INT1 */
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DCD RTC2_IRQHandler /* 44:29 RTC INT2 */
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DCD RTC3_IRQHandler /* 45:30 RTC INT3 */
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DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */
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DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
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DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */
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DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
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DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
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DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
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DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
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DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
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DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
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DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
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DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
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DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
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DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
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DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
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DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
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DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
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DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */
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; Maxim 32610 Externals interrupts
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DCD UART0_IRQHandler ; 16: 1 UART0
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DCD UART1_IRQHandler ; 17: 2 UART1
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DCD I2CM0_IRQHandler ; 18: 3 I2C Master 0
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DCD I2CS_IRQHandler ; 19: 4 I2C Slave
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DCD USB_IRQHandler ; 20: 5 USB
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DCD PMU_IRQHandler ; 21: 6 DMA
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DCD AFE_IRQHandler ; 22: 7 AFE
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DCD MAA_IRQHandler ; 23: 8 MAA
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DCD AES_IRQHandler ; 24: 9 AES
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DCD SPI0_IRQHandler ; 25:10 SPI0
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DCD SPI1_IRQHandler ; 26:11 SPI1
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DCD SPI2_IRQHandler ; 27:12 SPI2
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DCD TMR0_IRQHandler ; 28:13 Timer32-0
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DCD TMR1_IRQHandler ; 29:14 Timer32-1
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DCD TMR2_IRQHandler ; 30:15 Timer32-1
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DCD TMR3_IRQHandler ; 31:16 Timer32-2
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DCD RSVD0_IRQHandler ; 32:17 RSVD
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DCD RSVD1_IRQHandler ; 33:18 RSVD
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DCD DAC0_IRQHandler ; 34:19 DAC0 (12-bit DAC)
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DCD DAC1_IRQHandler ; 35:20 DAC1 (12-bit DAC)
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DCD DAC2_IRQHandler ; 36:21 DAC2 (8-bit DAC)
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DCD DAC3_IRQHandler ; 37:22 DAC3 (8-bit DAC)
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DCD ADC_IRQHandler ; 38:23 ADC
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DCD FLC_IRQHandler ; 39:24 Flash Controller
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DCD PWRMAN_IRQHandler ; 40:25 PWRMAN
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DCD CLKMAN_IRQHandler ; 41:26 CLKMAN
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DCD RTC0_IRQHandler ; 42:27 RTC INT0
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DCD RTC1_IRQHandler ; 43:28 RTC INT1
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DCD RTC2_IRQHandler ; 44:29 RTC INT2
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DCD RTC3_IRQHandler ; 45:30 RTC INT3
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DCD WDT0_IRQHandler ; 46:31 WATCHDOG0
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DCD WDT0_P_IRQHandler ; 47:32 WATCHDOG0 PRE-WINDOW
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DCD WDT1_IRQHandler ; 48:33 WATCHDOG1
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DCD WDT1_P_IRQHandler ; 49:34 WATCHDOG1 PRE-WINDOW
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DCD GPIO_P0_IRQHandler ; 50:35 GPIO Port 0
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DCD GPIO_P1_IRQHandler ; 51:36 GPIO Port 1
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DCD GPIO_P2_IRQHandler ; 52:37 GPIO Port 2
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DCD GPIO_P3_IRQHandler ; 53:38 GPIO Port 3
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DCD GPIO_P4_IRQHandler ; 54:39 GPIO Port 4
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DCD GPIO_P5_IRQHandler ; 55:40 GPIO Port 5
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DCD GPIO_P6_IRQHandler ; 56:41 GPIO Port 6
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DCD GPIO_P7_IRQHandler ; 57:42 GPIO Port 7
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DCD TMR16_0_IRQHandler ; 58:43 Timer16-s0
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DCD TMR16_1_IRQHandler ; 59:44 Timer16-s1
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DCD TMR16_2_IRQHandler ; 60:45 Timer16-s2
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DCD TMR16_3_IRQHandler ; 61:46 Timer16-s3
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DCD I2CM1_IRQHandler ; 62:47 I2C Master 1
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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