From 6086c5123426434346167784bd1d5245a09bf588 Mon Sep 17 00:00:00 2001
From: jeromecoutant <jerome.coutant@st.com>
Date: Thu, 18 Jan 2018 17:48:06 +0100
Subject: [PATCH] STM32LX : HAL_RCC_OscConfig update in PLL configuration

check PLL settings before retuuning error
---
 .../TARGET_STM32L0/device/stm32l0xx_hal_rcc.c | 14 +++++++++-
 .../TARGET_STM32L1/device/stm32l1xx_hal_rcc.c | 15 +++++++++--
 .../TARGET_STM32L4/device/stm32l4xx_hal_rcc.c | 26 ++++++++++++++++++-
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c
index 91bff130e3..cf1597aa1b 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c
@@ -709,7 +709,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      return HAL_ERROR;
+      /* MBED patch - ST internal ticket 42806 */
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) {
+        return HAL_ERROR;
+      }
+      /* MBED patch - ST internal ticket 42806 */
     }
   }
   return HAL_OK;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c
index 4217e0bd16..c9c8f0e020 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c
@@ -713,10 +713,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      return HAL_ERROR;
+      /* MBED patch - ST internal ticket 42806 */
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) {
+        return HAL_ERROR;
+      }
+      /* MBED patch - ST internal ticket 42806 */
     }
   }
-  
   return HAL_OK;
 }
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c
index 06a9b26658..50e2470772 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c
@@ -877,7 +877,31 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      return HAL_ERROR;
+      /* MBED patch - ST internal ticket 42806 */
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) {
+        return HAL_ERROR;
+      }
+
+      if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR) {
+        return HAL_ERROR;
+      }
+      /* MBED patch - ST internal ticket 42806 */
     }
   }
   return HAL_OK;