mirror of https://github.com/ARMmbed/mbed-os.git
Update system_stm32l4xx.c with latest version
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43a31557dc
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dda34ea206
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file system_stm32l4xx.c
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* @author MCD Application Team
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* @version V1.3.1
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* @date 21-April-2017
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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@ -110,15 +108,15 @@
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#include "stm32l4xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (MSI_VALUE)
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#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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@ -167,12 +165,12 @@
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 4000000;
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uint32_t SystemCoreClock = 4000000U;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
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4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
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4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
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/**
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* @}
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*/
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@ -189,6 +187,7 @@
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* @{
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*/
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// Removed from MBED PR #4740
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/*+ MBED */
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#if 0
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/*- MBED */
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@ -205,24 +204,25 @@ void SystemInit(void)
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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RCC->CFGR = 0x00000000U;
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/* Reset HSEON, CSSON , HSION, and PLLON bits */
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RCC->CR &= (uint32_t)0xEAF6FFFF;
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RCC->CR &= 0xEAF6FFFFU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x00001000;
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RCC->PLLCFGR = 0x00001000U;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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RCC->CIER = 0x00000000U;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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@ -280,16 +280,16 @@ void SystemInit(void)
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
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uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
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/* Get MSI Range frequency--------------------------------------------------*/
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if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
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{ /* MSISRANGE from RCC_CSR applies */
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msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
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msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
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}
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else
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{ /* MSIRANGE from RCC_CR applies */
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msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
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msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
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}
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/*MSI frequency range in HZ*/
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msirange = MSIRangeTable[msirange];
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@ -314,7 +314,7 @@ void SystemCoreClockUpdate(void)
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
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switch (pllsource)
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{
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@ -330,8 +330,8 @@ void SystemCoreClockUpdate(void)
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pllvco = (msirange / pllm);
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break;
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
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SystemCoreClock = pllvco/pllr;
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break;
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@ -341,7 +341,7 @@ void SystemCoreClockUpdate(void)
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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