From dd88e97e0bb13f45f8cf4c8f7f95900b34ae78e5 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 14 Dec 2016 10:03:02 +0100 Subject: [PATCH] STM32F4 : correct ST HAL API call - RCC init: one PLL parameter was missing - GPIO: mode was not allowed by ST HAL API --- .../TARGET_DISCO_F469NI/device/system_stm32f4xx.c | 4 ++++ .../TARGET_NUCLEO_F410RB/device/system_stm32f4xx.c | 1 + targets/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c | 4 ++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device/system_stm32f4xx.c index d3cdb0fa83..de41ad36b2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device/system_stm32f4xx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device/system_stm32f4xx.c @@ -808,6 +808,8 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; // I2S clocks + HAL_RCC_OscConfig(&RCC_OscInitStruct); RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 @@ -843,6 +845,8 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 360; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; // I2S clocks + HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_PWREx_ActivateOverDrive(); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device/system_stm32f4xx.c index 5e05224363..46e1822b70 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device/system_stm32f4xx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device/system_stm32f4xx.c @@ -840,6 +840,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + RCC_OscInitStruct.PLL.PLLR = 2; // I2S clocks if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL diff --git a/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c b/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c index cf8fed9402..c595b98ba6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c @@ -304,7 +304,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) mode = STM_MODE_IT_FALLING; obj->event = EDGE_FALL; } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; + mode = STM_MODE_INPUT; obj->event = EDGE_NONE; } } @@ -313,7 +313,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) mode = STM_MODE_IT_RISING; obj->event = EDGE_RISE; } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; + mode = STM_MODE_INPUT; obj->event = EDGE_NONE; } }