From dd7fd76758fceda3676f8a38126616e1b2dfa1df Mon Sep 17 00:00:00 2001 From: ccli8 Date: Wed, 28 Mar 2018 17:29:56 +0800 Subject: [PATCH] [M2351] Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader --- .../device/TOOLCHAIN_ARM_MICRO/M2351.sct | 84 +++++++++++++------ .../TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h | 23 +++++ .../device/TOOLCHAIN_ARM_STD/M2351.sct | 84 +++++++++++++------ .../TOOLCHAIN_ARM_STD/partition_M2351_sub.h | 23 +++++ .../device/TOOLCHAIN_GCC_ARM/M2351.ld | 55 +++++++++--- .../TOOLCHAIN_GCC_ARM/partition_M2351_sub.h | 23 +++++ .../TARGET_M2351/device/cmsis.h | 8 +- .../TARGET_M2351/device/partition_M2351.h | 44 +++++++++- 8 files changed, 273 insertions(+), 71 deletions(-) create mode 100644 targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/partition_M2351_sub.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/partition_M2351_sub.h diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct index bb52ec578d..a85969c79d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct @@ -1,18 +1,39 @@ #! armcc -E +#include "partition_M2351_sub.h" + +/* Check relevant macros have been defined */ +#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) +#error("NU_TZ_SECURE_FLASH_SIZE not defined") +#endif +#if (! defined(NU_TZ_SECURE_SRAM_SIZE)) +#error("NU_TZ_SECURE_SRAM_SIZE not defined") +#endif +#if (! defined(NU_TZ_NSC_REGION_SIZE)) +#error("NU_TZ_NSC_REGION_SIZE not defined") +#endif + /* Requirements for NSC location * * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. */ -#define NSC_REGION_BASE 0x0003D000 -#define NSC_REGION_SIZE 0x00001000 +#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) #if defined(__DOMAIN_NS) && __DOMAIN_NS -LR_IROM1 0x10040000 ; load address = execution address -{ +#if (! defined(MBED_APP_START)) +#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE) +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE) +#endif + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ ER_IROM1 +0 { *(RESET, +First) @@ -20,35 +41,43 @@ LR_IROM1 0x10040000 ; load address = executi .ANY (+RO) } - ARM_LIB_STACK 0x30006000 EMPTY 0x800 + ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY 0x800 { } - ER_IRAMVEC 0x30006800 EMPTY (4*(16 + 102)) ; Reserve for vectors + /* Reserve for vectors */ + ER_IRAMVEC 0x30000800 + NU_TZ_SECURE_SRAM_SIZE EMPTY (4*(16 + 102)) { } - RW_IRAM1 AlignExpr(+0, 16) ; 16 byte-aligned - { + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30006000 + 0x12000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } } -; Total 512 KB APROM: 256 KB for secure + NSC + reserved, 256 KB for non-secure -ScatterAssert(LoadLimit(LR_IROM1) <= 0x10080000) - -; Total 96 KB SRAM: 24 KB for secure, 72 KB for non-secure +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000) #else -LR_IROM1 0x00000000 +#if (! defined(MBED_APP_START)) +#define MBED_APP_START 0 +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE +#endif + +LR_IROM1 MBED_APP_START { - ER_IROM1 +0 ; load address = execution address + /* load address = execution address */ + ER_IROM1 +0 { *(RESET, +First) *(InRoot$$Sections) @@ -59,33 +88,34 @@ LR_IROM1 0x00000000 { } - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) ; Reserve for vectors + /* Reserve for vectors */ + ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) { } - RW_IRAM1 AlignExpr(+0, 16) ; 16 byte-aligned - { + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x6000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } } -LR_IROM2 NSC_REGION_BASE +LR_IROM2 NU_TZ_NSC_REGION_BASE { - NSC_ROM +0 NSC_REGION_SIZE + NSC_ROM +0 NU_TZ_NSC_REGION_SIZE { *(Veneer$$CMSE) } } -; Total 512 KB APROM: 256 KB for secure + NSC + reserved, 256 KB for non-secure -ScatterAssert(LoadLimit(LR_IROM1) <= NSC_REGION_BASE) -ScatterAssert(LoadLimit(LR_IROM2) <= (NSC_REGION_BASE + NSC_REGION_SIZE)) - -; Total 96 KB SRAM: 24 KB for secure, 72 KB for non-secure -ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20006000) +ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE) +ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE)) +/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */ +ScatterAssert(LoadBase(LR_IROM2) >= 0x4000) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE)) #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h new file mode 100644 index 0000000000..ffe2057d64 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h @@ -0,0 +1,23 @@ +/**************************************************************************//** + * @file partition_M2351_sub.c + * @version V3.00 + * @brief SAU configuration for secure/nonsecure region settings. + * + * @note + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + +#ifndef PARTITION_M2351_SUB +#define PARTITION_M2351_SUB + +/* Secure flash size: 256 KB */ +#define NU_TZ_SECURE_FLASH_SIZE 0x40000 + +/* Secure SRAM size: 24 KB */ +#define NU_TZ_SECURE_SRAM_SIZE 0x6000 + +/* NSC region size: 4 KB */ +#define NU_TZ_NSC_REGION_SIZE 0x1000 + +#endif /* PARTITION_M2351_SUB */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct index bb52ec578d..a85969c79d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct @@ -1,18 +1,39 @@ #! armcc -E +#include "partition_M2351_sub.h" + +/* Check relevant macros have been defined */ +#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) +#error("NU_TZ_SECURE_FLASH_SIZE not defined") +#endif +#if (! defined(NU_TZ_SECURE_SRAM_SIZE)) +#error("NU_TZ_SECURE_SRAM_SIZE not defined") +#endif +#if (! defined(NU_TZ_NSC_REGION_SIZE)) +#error("NU_TZ_NSC_REGION_SIZE not defined") +#endif + /* Requirements for NSC location * * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. */ -#define NSC_REGION_BASE 0x0003D000 -#define NSC_REGION_SIZE 0x00001000 +#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) #if defined(__DOMAIN_NS) && __DOMAIN_NS -LR_IROM1 0x10040000 ; load address = execution address -{ +#if (! defined(MBED_APP_START)) +#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE) +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE) +#endif + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ ER_IROM1 +0 { *(RESET, +First) @@ -20,35 +41,43 @@ LR_IROM1 0x10040000 ; load address = executi .ANY (+RO) } - ARM_LIB_STACK 0x30006000 EMPTY 0x800 + ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY 0x800 { } - ER_IRAMVEC 0x30006800 EMPTY (4*(16 + 102)) ; Reserve for vectors + /* Reserve for vectors */ + ER_IRAMVEC 0x30000800 + NU_TZ_SECURE_SRAM_SIZE EMPTY (4*(16 + 102)) { } - RW_IRAM1 AlignExpr(+0, 16) ; 16 byte-aligned - { + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30006000 + 0x12000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } } -; Total 512 KB APROM: 256 KB for secure + NSC + reserved, 256 KB for non-secure -ScatterAssert(LoadLimit(LR_IROM1) <= 0x10080000) - -; Total 96 KB SRAM: 24 KB for secure, 72 KB for non-secure +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000) #else -LR_IROM1 0x00000000 +#if (! defined(MBED_APP_START)) +#define MBED_APP_START 0 +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE +#endif + +LR_IROM1 MBED_APP_START { - ER_IROM1 +0 ; load address = execution address + /* load address = execution address */ + ER_IROM1 +0 { *(RESET, +First) *(InRoot$$Sections) @@ -59,33 +88,34 @@ LR_IROM1 0x00000000 { } - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) ; Reserve for vectors + /* Reserve for vectors */ + ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) { } - RW_IRAM1 AlignExpr(+0, 16) ; 16 byte-aligned - { + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x6000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } } -LR_IROM2 NSC_REGION_BASE +LR_IROM2 NU_TZ_NSC_REGION_BASE { - NSC_ROM +0 NSC_REGION_SIZE + NSC_ROM +0 NU_TZ_NSC_REGION_SIZE { *(Veneer$$CMSE) } } -; Total 512 KB APROM: 256 KB for secure + NSC + reserved, 256 KB for non-secure -ScatterAssert(LoadLimit(LR_IROM1) <= NSC_REGION_BASE) -ScatterAssert(LoadLimit(LR_IROM2) <= (NSC_REGION_BASE + NSC_REGION_SIZE)) - -; Total 96 KB SRAM: 24 KB for secure, 72 KB for non-secure -ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20006000) +ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE) +ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE)) +/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */ +ScatterAssert(LoadBase(LR_IROM2) >= 0x4000) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE)) #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/partition_M2351_sub.h b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/partition_M2351_sub.h new file mode 100644 index 0000000000..ffe2057d64 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/partition_M2351_sub.h @@ -0,0 +1,23 @@ +/**************************************************************************//** + * @file partition_M2351_sub.c + * @version V3.00 + * @brief SAU configuration for secure/nonsecure region settings. + * + * @note + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + +#ifndef PARTITION_M2351_SUB +#define PARTITION_M2351_SUB + +/* Secure flash size: 256 KB */ +#define NU_TZ_SECURE_FLASH_SIZE 0x40000 + +/* Secure SRAM size: 24 KB */ +#define NU_TZ_SECURE_SRAM_SIZE 0x6000 + +/* NSC region size: 4 KB */ +#define NU_TZ_NSC_REGION_SIZE 0x1000 + +#endif /* PARTITION_M2351_SUB */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld index fec4775a6e..42f1717ed8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld @@ -1,35 +1,63 @@ /* * Nuvoton M2351 GCC linker script file */ - + StackSize = 0x800; +#include "partition_M2351_sub.h" + +/* Check relevant macros have been defined */ +#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) +#error("NU_TZ_SECURE_FLASH_SIZE not defined") +#endif +#if (! defined(NU_TZ_SECURE_SRAM_SIZE)) +#error("NU_TZ_SECURE_SRAM_SIZE not defined") +#endif +#if (! defined(NU_TZ_NSC_REGION_SIZE)) +#error("NU_TZ_NSC_REGION_SIZE not defined") +#endif + /* Requirements for NSC location * * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. */ -#define NSC_REGION_BASE 0x0003D000 -#define NSC_REGION_SIZE 0x00001000 - +#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) + #if defined(__DOMAIN_NS) && __DOMAIN_NS +#if (! defined(MBED_APP_START)) +#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE) +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE) +#endif + MEMORY { - VECTORS (rx) : ORIGIN = 0x10040000, LENGTH = 0x00000400 - FLASH (rx) : ORIGIN = 0x10040400, LENGTH = 0x00040000 - 0x00000400 - RAM_INTERN (rwx) : ORIGIN = 0x30006000, LENGTH = 0x00018000 - 0x00006000 + VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 + RAM_INTERN (rwx) : ORIGIN = 0x30000000 + NU_TZ_SECURE_SRAM_SIZE, LENGTH = 0x00018000 - NU_TZ_SECURE_SRAM_SIZE } #else +#if (! defined(MBED_APP_START)) +#define MBED_APP_START 0 +#endif + +#if (! defined(MBED_APP_SIZE)) +#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE +#endif + MEMORY { - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH (rx) : ORIGIN = 0x00000400, LENGTH = NSC_REGION_BASE - 0x00000400 - NSC_FLASH (rx) : ORIGIN = NSC_REGION_BASE, LENGTH = NSC_REGION_SIZE - RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 - 0x00000000 + VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_REGION_BASE - MBED_APP_START - 0x400 + NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_REGION_BASE, LENGTH = NU_TZ_NSC_REGION_SIZE + RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = NU_TZ_SECURE_SRAM_SIZE } #endif @@ -141,7 +169,10 @@ SECTIONS __sgstubs_start = .; *(.gnu.sgstubs.*) __sgstubs_end = .; - } > NSC_FLASH + } > NSC_FLASH + + /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */ + ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.") #endif .ARM.extab : { diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/partition_M2351_sub.h b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/partition_M2351_sub.h new file mode 100644 index 0000000000..ffe2057d64 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/partition_M2351_sub.h @@ -0,0 +1,23 @@ +/**************************************************************************//** + * @file partition_M2351_sub.c + * @version V3.00 + * @brief SAU configuration for secure/nonsecure region settings. + * + * @note + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + +#ifndef PARTITION_M2351_SUB +#define PARTITION_M2351_SUB + +/* Secure flash size: 256 KB */ +#define NU_TZ_SECURE_FLASH_SIZE 0x40000 + +/* Secure SRAM size: 24 KB */ +#define NU_TZ_SECURE_SRAM_SIZE 0x6000 + +/* NSC region size: 4 KB */ +#define NU_TZ_NSC_REGION_SIZE 0x1000 + +#endif /* PARTITION_M2351_SUB */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h b/targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h index f3f56fe231..59ce2f8d59 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/cmsis.h @@ -20,6 +20,12 @@ #include "M2351.h" #include "m2351_stddriver_sup.h" #include "cmsis_nvic.h" +#include "partition_M2351.h" + +/* Check relevant macro has been defined */ +#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) +#error("NU_TZ_SECURE_FLASH_SIZE not defined") +#endif // Support linker-generated symbol as start of relocated vector table. #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) @@ -32,7 +38,7 @@ extern uint32_t __start_vector_table__; /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS -#define TZ_START_NS (0x10040000U) +#define TZ_START_NS (NS_OFFSET + NU_TZ_SECURE_FLASH_SIZE) #endif #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h b/targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h index 095ff2a826..ae9d0b1711 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h @@ -11,6 +11,42 @@ #ifndef PARTITION_M2351 #define PARTITION_M2351 +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +#include "partition_M2351_sub.h" + +extern int Image$$NSC_ROM$$Base; + +#define NU_TZ_NSC_REGION_BASE ((uint32_t) &Image$$NSC_ROM$$Base) + +#elif defined(__ICCARM__) + +#error ("TODO: Support IAR") + +#elif defined(__GNUC__) + +#include "partition_M2351_sub.h" + +extern int __sgstubs_start; + +#define NU_TZ_NSC_REGION_BASE ((uint32_t) &__sgstubs_start) + +#endif + +/* Check relevant macros have been defined */ +#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) +#error("NU_TZ_SECURE_FLASH_SIZE not defined") +#endif +#if (! defined(NU_TZ_SECURE_SRAM_SIZE)) +#error("NU_TZ_SECURE_SRAM_SIZE not defined") +#endif +#if (! defined(NU_TZ_NSC_REGION_BASE)) +#error("NU_TZ_NSC_REGION_BASE not defined") +#endif +#if (! defined(NU_TZ_NSC_REGION_SIZE)) +#error("NU_TZ_NSC_REGION_SIZE not defined") +#endif + /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ @@ -35,7 +71,7 @@ // <0x16000=> 88KB // <0x18000=> 96KB */ -#define SCU_SECURE_SRAM_SIZE 0x6000 +#define SCU_SECURE_SRAM_SIZE NU_TZ_SECURE_SRAM_SIZE #define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE) @@ -50,7 +86,7 @@ // Secure Flash ROM Size <0x800-0x7FFFF:0x800> */ -#define FMC_SECURE_ROM_SIZE 0x40000 +#define FMC_SECURE_ROM_SIZE NU_TZ_SECURE_FLASH_SIZE #define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE) @@ -387,11 +423,11 @@ __STATIC_INLINE void SCU_Setup(void) /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x3D000 +#define SAU_INIT_START3 NU_TZ_NSC_REGION_BASE /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x3DFFF +#define SAU_INIT_END3 (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE - 1) /* // Region is // <0=>Non-Secure