From 10b90edea311f6d89e6ce6a639a3a227b7ffd738 Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Fri, 29 Jun 2018 13:33:45 -0700 Subject: [PATCH 1/2] Fix ITM on NRF52 series The ITM must be initialized before the SoftDevice, but due to the lazy initialization in C++ on (at least) GCC the ITM init call might happen too late. This commit moves the initialization code into the NRF52 system startup file. --- .../TARGET_MCU_NRF52832/device/system_nrf52.c | 31 +++++++++-- .../device/system_nrf52840.c | 55 +++++++++++++------ .../TARGET_NRF5x/TARGET_NRF52/itm_api.c | 22 +------- 3 files changed, 69 insertions(+), 39 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c index 4980feb918..5af1757695 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c @@ -79,13 +79,13 @@ void SystemInit(void) NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); #endif - + /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_12()){ *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; } - + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_16()){ @@ -154,7 +154,7 @@ void SystemInit(void) if (errata_108()){ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; } - + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_136()){ @@ -162,7 +162,7 @@ void SystemInit(void) NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; } } - + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ @@ -216,6 +216,29 @@ void SystemInit(void) while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { // Do nothing. } + + /** + * Mbed HAL specific code section. + * + * The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API. + */ + #if defined (DEVICE_ITM) + /* Enable SWO trace functionality */ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + + /* set SWO clock speed to 4 MHz */ + NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) | + (CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos); + + /* set SWO pin */ + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | + (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + /* set prescaler */ + TPI->ACPR = 0; + #endif } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c index 55b171bf2d..4b73b3972b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ - + #include #include #include "nrf.h" @@ -76,7 +76,7 @@ void SystemInit(void) NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); #endif - + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_36()){ @@ -84,7 +84,7 @@ void SystemInit(void) NRF_CLOCK->EVENTS_CTTO = 0; NRF_CLOCK->CTIV = 0; } - + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_66()){ @@ -106,31 +106,31 @@ void SystemInit(void) NRF_TEMP->T3 = NRF_FICR->TEMP.T3; NRF_TEMP->T4 = NRF_FICR->TEMP.T4; } - + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_98()){ *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; } - + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_103()){ NRF_CCM->MAXPACKETSIZE = 0xFBul; } - + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_115()){ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); } - + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_120()){ *(volatile uint32_t *)0x40029640ul = 0x200ul; } - + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_136()){ @@ -138,7 +138,7 @@ void SystemInit(void) NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; } } - + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ @@ -192,6 +192,29 @@ void SystemInit(void) while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { // Do nothing. } + + /** + * Mbed HAL specific code section. + * + * The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API. + */ + #if defined (DEVICE_ITM) + /* Enable SWO trace functionality */ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + + /* set SWO clock speed to 4 MHz */ + NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) | + (CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos); + + /* set SWO pin */ + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | + (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + /* set prescaler */ + TPI->ACPR = 0; + #endif } @@ -200,7 +223,7 @@ static bool errata_36(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -210,7 +233,7 @@ static bool errata_66(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -220,7 +243,7 @@ static bool errata_98(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -230,7 +253,7 @@ static bool errata_103(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -240,7 +263,7 @@ static bool errata_115(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -250,7 +273,7 @@ static bool errata_120(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -260,7 +283,7 @@ static bool errata_136(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c index 593ef6b6f9..ff390a3cf0 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c @@ -18,27 +18,11 @@ #include "hal/itm_api.h" -#include "nrf.h" -#include "nrf5x_lf_clk_helper.h" - -/* SWO frequency: 4000 kHz */ void itm_init(void) { - /* Enable SWO trace functionality */ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; - - /* set SWO clock speed to 4 MHz */ - NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) | - (CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos); - - /* set SWO pin */ - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - - /* set prescaler */ - TPI->ACPR = 0; + /** + * Initialization moved to system_nrf52840.c due to SoftDevice incompatibility. + */ } #endif From 0198481f8f159bca91c76893eb8d242e6fd5886a Mon Sep 17 00:00:00 2001 From: RFulchiero Date: Thu, 12 Jul 2018 13:24:46 -0500 Subject: [PATCH 2/2] Improved formatting for preprocessor conditionals. --- .../TARGET_MCU_NRF52832/device/system_nrf52.c | 32 +++++------ .../device/system_nrf52840.c | 55 ++++++++++--------- 2 files changed, 44 insertions(+), 43 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c index 5af1757695..edb28370ec 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c @@ -62,15 +62,15 @@ void SystemInit(void) { /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product Specification to see which one). */ - #if defined (ENABLE_SWO) +#if defined (ENABLE_SWO) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif +#endif /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product Specification to see which ones). */ - #if defined (ENABLE_TRACE) +#if defined (ENABLE_TRACE) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); @@ -78,14 +78,14 @@ void SystemInit(void) NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - +#endif + /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_12()){ *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; } - + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_16()){ @@ -154,7 +154,7 @@ void SystemInit(void) if (errata_108()){ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; } - + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_136()){ @@ -162,20 +162,20 @@ void SystemInit(void) NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; } } - + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ - #if (__FPU_USED == 1) +#if (__FPU_USED == 1) SCB->CPACR |= (3UL << 20) | (3UL << 22); __DSB(); __ISB(); - #endif +#endif /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) +#if defined (CONFIG_NFCT_PINS_AS_GPIOS) if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} @@ -185,12 +185,12 @@ void SystemInit(void) while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} NVIC_SystemReset(); } - #endif +#endif /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) +#if defined (CONFIG_GPIO_AS_PINRESET) if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; @@ -203,7 +203,7 @@ void SystemInit(void) while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} NVIC_SystemReset(); } - #endif +#endif SystemCoreClockUpdate(); @@ -222,7 +222,7 @@ void SystemInit(void) * * The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API. */ - #if defined (DEVICE_ITM) +#if defined (DEVICE_ITM) /* Enable SWO trace functionality */ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; @@ -238,7 +238,7 @@ void SystemInit(void) /* set prescaler */ TPI->ACPR = 0; - #endif +#endif } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c index 4b73b3972b..242cee7da5 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ - + #include #include #include "nrf.h" @@ -59,15 +59,15 @@ void SystemInit(void) { /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product Specification to see which one). */ - #if defined (ENABLE_SWO) +#if defined (ENABLE_SWO) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif +#endif /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product Specification to see which ones). */ - #if defined (ENABLE_TRACE) +#if defined (ENABLE_TRACE) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); @@ -75,7 +75,7 @@ void SystemInit(void) NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif +#endif /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ @@ -84,7 +84,7 @@ void SystemInit(void) NRF_CLOCK->EVENTS_CTTO = 0; NRF_CLOCK->CTIV = 0; } - + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_66()){ @@ -106,31 +106,31 @@ void SystemInit(void) NRF_TEMP->T3 = NRF_FICR->TEMP.T3; NRF_TEMP->T4 = NRF_FICR->TEMP.T4; } - + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_98()){ *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; } - + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_103()){ NRF_CCM->MAXPACKETSIZE = 0xFBul; } - + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_115()){ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); } - + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_120()){ *(volatile uint32_t *)0x40029640ul = 0x200ul; } - + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://infocenter.nordicsemi.com/ */ if (errata_136()){ @@ -138,20 +138,20 @@ void SystemInit(void) NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; } } - + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ - #if (__FPU_USED == 1) +#if (__FPU_USED == 1) SCB->CPACR |= (3UL << 20) | (3UL << 22); __DSB(); __ISB(); - #endif +#endif /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) +#if defined (CONFIG_NFCT_PINS_AS_GPIOS) if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} @@ -161,12 +161,12 @@ void SystemInit(void) while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} NVIC_SystemReset(); } - #endif +#endif /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) +#if defined (CONFIG_GPIO_AS_PINRESET) if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; @@ -179,7 +179,7 @@ void SystemInit(void) while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} NVIC_SystemReset(); } - #endif +#endif SystemCoreClockUpdate(); @@ -198,7 +198,7 @@ void SystemInit(void) * * The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API. */ - #if defined (DEVICE_ITM) +#if defined (DEVICE_ITM) /* Enable SWO trace functionality */ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; @@ -214,7 +214,8 @@ void SystemInit(void) /* set prescaler */ TPI->ACPR = 0; - #endif +#endif + } @@ -223,7 +224,7 @@ static bool errata_36(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -233,7 +234,7 @@ static bool errata_66(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -243,7 +244,7 @@ static bool errata_98(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -253,7 +254,7 @@ static bool errata_103(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -263,7 +264,7 @@ static bool errata_115(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -273,7 +274,7 @@ static bool errata_120(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; } @@ -283,7 +284,7 @@ static bool errata_136(void) if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ return true; } - + return false; }