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Merge pull request #5720 from kjbracey-arm/STM32F7_DMB 

Add memory barriers to STM32F7xx Ethernet
pull/5682/head
Martin Kojtal 2017-12-22 11:07:46 +00:00 committed by GitHub
parent 1ae20c5659 05e2ae7a70
commit dd5bd73a88
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 0 deletions
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7
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c
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@ -717,6 +717,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
/* Set frame size */ /* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN; heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* Point to next descriptor */ /* Point to next descriptor */
@ -746,6 +748,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
} }
/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN; heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* point to next descriptor */ /* point to next descriptor */
@ -753,6 +757,9 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
} }
} }
/* Ensure all descriptors are written to RAM before checking transmitter status */
__DMB();
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
{ {