Merge remote-tracking branch 'upstream/master'

libraries/mbed/api/mbed.h

@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 88
+#define MBED_LIBRARY_VERSION 89
 
 #include "platform.h"
 

libraries/mbed/common/RawSerial.cpp

@@ -47,13 +47,6 @@ int RawSerial::puts(const char *str) {
 int RawSerial::printf(const char *format, ...) {
     std::va_list arg;
     va_start(arg, format);
-#if defined(__MICROLIB) && defined(__ARMCC_VERSION) // with microlib and ARM compiler
-    char *temp;
-    temp = (char*)alloca(STRING_STACK_LIMIT);
-    vsprintf(temp, format, arg);
-    puts(temp);
-    int len = strlen(temp);
-#else
     int len = vsnprintf(NULL, 0, format, arg);
     if (len < STRING_STACK_LIMIT) {
         char temp[STRING_STACK_LIMIT];
@@ -65,7 +58,6 @@ int RawSerial::printf(const char *format, ...) {
         puts(temp);
         delete[] temp;
     }
-#endif
     va_end(arg);
     return len;
 }

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct

@@ -6,7 +6,7 @@ LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
   ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
-   *.o (+RO-CODE)                    ; forces all CODE to IFLASH
+   *.o (+RO-CODE)                    ; prioritizes CODE in IFLASH before SPIFI
    .ANY2 (+RO-DATA)                  ; prioritizes DATA in IFLASH before SPIFI
    .ANY (+RO)                        ; remaining RO
   }
@@ -25,6 +25,7 @@ LR_IROM2 0x28000000 0x01000000  {
   ER_IROM2 0x28000000 0x01000000  {  ; load address = execution address
     .ANY1 (+RO-DATA)                 ; all DATA not fitting in IFLASH
     .ANY (SPIFI_MEM)                 ; DATA tagged as SPIFI_MEM
+    *.o (SPIFI_MEM)                  ; CODE tagged as SPIFI_MEM
   }
 }
 

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct

@@ -0,0 +1,22 @@
+
+LR_IROM1 0x1A000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x1A000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+;  ER_IROM2 0x1B000000 0x00080000  {  ; load address = execution address
+;   .ANY (+RO)
+;  }
+
+  ; 8_byte_aligned(69 vect * 4 bytes) =  8_byte_aligned(0x0114) = 0x0118
+  RW_IRAM1 0x10000000+0x118 0x8000-0x118  {
+   .ANY (+RW +ZI)
+  }
+;  RW_IRAM2 0x10080000 0xA000 {  ; RW data
+;   .ANY (IRAM2)
+;  }
+;  RW_IRAM3 0x20000000 0x10000 {  ; RW data
+;   .ANY (AHBSRAM)
+;  }
+}

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.s

@@ -0,0 +1,291 @@
+;/***********************************************************************
+; * @brief: LPC18xx/43xx M3/M4 startup code
+; *
+; * @note
+; * Copyright(C) NXP Semiconductors, 2012
+; * All rights reserved.
+; *
+; * @par
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * LPC products.  This software is supplied "AS IS" without any warranties of
+; * any kind, and NXP Semiconductors and its licensor disclaim any and
+; * all warranties, express or implied, including all implied warranties of
+; * merchantability, fitness for a particular purpose and non-infringement of
+; * intellectual property rights.  NXP Semiconductors assumes no responsibility
+; * or liability for the use of the software, conveys no license or rights under any
+; * patent, copyright, mask work right, or any other intellectual property rights in
+; * or to any products. NXP Semiconductors reserves the right to make changes
+; * in the software without notification. NXP Semiconductors also makes no
+; * representation or warranty that such application will be suitable for the
+; * specified use without further testing or modification.
+; *
+; * @par
+; * Permission to use, copy, modify, and distribute this software and its
+; * documentation is hereby granted, under NXP Semiconductors' and its
+; * licensor's relevant copyrights in the software, without fee, provided that it
+; * is used in conjunction with NXP Semiconductors microcontrollers.  This
+; * copyright, permission, and disclaimer notice must appear in all copies of
+; * this code.
+; */
+
+;__initial_sp    EQU     0x1008A000  ; Top of 2nd RAM segment for LPC4337
+__initial_sp    EQU     0x10008000  ; Top of 1st RAM segment for LPC4337
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors   DCD __initial_sp                ; 0 Top of Stack
+            DCD Reset_Handler               ; 1 Reset Handler
+            DCD NMI_Handler                 ; 2 NMI Handler
+            DCD HardFault_Handler           ; 3 Hard Fault Handler
+            DCD MemManage_Handler           ; 4 MPU Fault Handler
+            DCD BusFault_Handler            ; 5 Bus Fault Handler
+            DCD UsageFault_Handler          ; 6 Usage Fault Handler
+            DCD Sign_Value                  ; 7 Reserved
+            DCD UnHandled_Vector            ; 8 Reserved
+            DCD UnHandled_Vector            ; 9 Reserved
+            DCD UnHandled_Vector            ; 10 Reserved
+            DCD SVC_Handler                 ; 11 SVCall Handler
+            DCD DebugMon_Handler            ; 12 Debug Monitor Handler
+            DCD UnHandled_Vector            ; 13 Reserved
+            DCD PendSV_Handler              ; 14 PendSV Handler
+            DCD SysTick_Handler             ; 15 SysTick Handler
+
+        ; External Interrupts
+            DCD DAC_IRQHandler              ; 16 D/A Converter
+            DCD MX_CORE_IRQHandler          ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
+            DCD DMA_IRQHandler              ; 18 General Purpose DMA
+            DCD UnHandled_Vector            ; 19 Reserved
+            DCD FLASHEEPROM_IRQHandler      ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
+            DCD ETH_IRQHandler              ; 21 Ethernet
+            DCD SDIO_IRQHandler             ; 22 SD/MMC
+            DCD LCD_IRQHandler              ; 23 LCD
+            DCD USB0_IRQHandler             ; 24 USB0
+            DCD USB1_IRQHandler             ; 25 USB1
+            DCD SCT_IRQHandler              ; 26 State Configurable Timer
+            DCD RIT_IRQHandler              ; 27 Repetitive Interrupt Timer
+            DCD TIMER0_IRQHandler           ; 28 Timer0
+            DCD TIMER1_IRQHandler           ; 29 Timer1
+            DCD TIMER2_IRQHandler           ; 30 Timer2
+            DCD TIMER3_IRQHandler           ; 31 Timer3
+            DCD MCPWM_IRQHandler            ; 32 Motor Control PWM
+            DCD ADC0_IRQHandler             ; 33 A/D Converter 0
+            DCD I2C0_IRQHandler             ; 34 I2C0
+            DCD I2C1_IRQHandler             ; 35 I2C1
+            DCD SPI_IRQHandler              ; 36 SPI (LPC43XX ONLY)
+            DCD ADC1_IRQHandler             ; 37 A/D Converter 1
+            DCD SSP0_IRQHandler             ; 38 SSP0
+            DCD SSP1_IRQHandler             ; 39 SSP1
+            DCD UART0_IRQHandler            ; 40 UART0
+            DCD UART1_IRQHandler            ; 41 UART1
+            DCD UART2_IRQHandler            ; 42 UART2
+            DCD UART3_IRQHandler            ; 43 UART3
+            DCD I2S0_IRQHandler             ; 44 I2S0
+            DCD I2S1_IRQHandler             ; 45 I2S1
+            DCD SPIFI_IRQHandler            ; 46 SPI Flash Interface
+            DCD SGPIO_IRQHandler            ; 47 SGPIO (LPC43XX ONLY)
+            DCD GPIO0_IRQHandler            ; 48 GPIO0
+            DCD GPIO1_IRQHandler            ; 49 GPIO1
+            DCD GPIO2_IRQHandler            ; 50 GPIO2
+            DCD GPIO3_IRQHandler            ; 51 GPIO3
+            DCD GPIO4_IRQHandler            ; 52 GPIO4
+            DCD GPIO5_IRQHandler            ; 53 GPIO5
+            DCD GPIO6_IRQHandler            ; 54 GPIO6
+            DCD GPIO7_IRQHandler            ; 55 GPIO7
+            DCD GINT0_IRQHandler            ; 56 GINT0
+            DCD GINT1_IRQHandler            ; 57 GINT1
+            DCD EVRT_IRQHandler             ; 58 Event Router
+            DCD CAN1_IRQHandler             ; 59 C_CAN1
+            DCD UnHandled_Vector            ; 60 Reserved
+            DCD VADC_IRQHandler             ; 61 VADC
+            DCD ATIMER_IRQHandler           ; 62 ATIMER
+            DCD RTC_IRQHandler              ; 63 RTC
+            DCD UnHandled_Vector            ; 64 Reserved
+            DCD WDT_IRQHandler              ; 65 WDT
+            DCD UnHandled_Vector            ; 66 M0s
+            DCD CAN0_IRQHandler             ; 67 C_CAN0
+            DCD QEI_IRQHandler              ; 68 QEI
+
+;                IF      :LNOT::DEF:NO_CRP
+;                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+;CRP_Key         DCD     0xFFFFFFFF
+;                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+UnHandled_Vector    PROC
+                EXPORT  UnHandled_Vector        [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT DAC_IRQHandler           [WEAK]
+                EXPORT MX_CORE_IRQHandler       [WEAK]
+                EXPORT DMA_IRQHandler           [WEAK]
+                EXPORT FLASHEEPROM_IRQHandler   [WEAK]
+                EXPORT ETH_IRQHandler           [WEAK]
+                EXPORT SDIO_IRQHandler          [WEAK]
+                EXPORT LCD_IRQHandler           [WEAK]
+                EXPORT USB0_IRQHandler          [WEAK]
+                EXPORT USB1_IRQHandler          [WEAK]
+                EXPORT SCT_IRQHandler           [WEAK]
+                EXPORT RIT_IRQHandler           [WEAK]
+                EXPORT TIMER0_IRQHandler        [WEAK]
+                EXPORT TIMER1_IRQHandler        [WEAK]
+                EXPORT TIMER2_IRQHandler        [WEAK]
+                EXPORT TIMER3_IRQHandler        [WEAK]
+                EXPORT MCPWM_IRQHandler         [WEAK]
+                EXPORT ADC0_IRQHandler          [WEAK]
+                EXPORT I2C0_IRQHandler          [WEAK]
+                EXPORT I2C1_IRQHandler          [WEAK]
+                EXPORT SPI_IRQHandler           [WEAK]
+                EXPORT ADC1_IRQHandler          [WEAK]
+                EXPORT SSP0_IRQHandler          [WEAK]
+                EXPORT SSP1_IRQHandler          [WEAK]
+                EXPORT UART0_IRQHandler         [WEAK]
+                EXPORT UART1_IRQHandler         [WEAK]
+                EXPORT UART2_IRQHandler         [WEAK]
+                EXPORT UART3_IRQHandler         [WEAK]
+                EXPORT I2S0_IRQHandler          [WEAK]
+                EXPORT I2S1_IRQHandler          [WEAK]
+                EXPORT SPIFI_IRQHandler         [WEAK]
+                EXPORT SGPIO_IRQHandler         [WEAK]
+                EXPORT GPIO0_IRQHandler         [WEAK]
+                EXPORT GPIO1_IRQHandler         [WEAK]
+                EXPORT GPIO2_IRQHandler         [WEAK]
+                EXPORT GPIO3_IRQHandler         [WEAK]
+                EXPORT GPIO4_IRQHandler         [WEAK]
+                EXPORT GPIO5_IRQHandler         [WEAK]
+                EXPORT GPIO6_IRQHandler         [WEAK]
+                EXPORT GPIO7_IRQHandler         [WEAK]
+                EXPORT GINT0_IRQHandler         [WEAK]
+                EXPORT GINT1_IRQHandler         [WEAK]
+                EXPORT EVRT_IRQHandler          [WEAK]
+                EXPORT CAN1_IRQHandler          [WEAK]
+                EXPORT VADC_IRQHandler          [WEAK]
+                EXPORT ATIMER_IRQHandler        [WEAK]
+                EXPORT RTC_IRQHandler           [WEAK]
+                EXPORT WDT_IRQHandler           [WEAK]
+                EXPORT CAN0_IRQHandler          [WEAK]
+                EXPORT QEI_IRQHandler           [WEAK]
+
+DAC_IRQHandler
+MX_CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030.s

@@ -54,7 +54,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.s

@@ -66,7 +66,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f10x_md.s

@@ -54,7 +54,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.s

@@ -56,7 +56,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.s

@@ -66,7 +66,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.s

@@ -66,7 +66,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.s

@@ -66,7 +66,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld

@@ -0,0 +1,151 @@
+/* Linker script for STM32F411 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+/*  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
+  RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/startup_STM32F41x.s

@@ -0,0 +1,297 @@
+/* File: startup_STM32F40x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ *   GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv7-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x400
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long     WWDG_IRQHandler               /* Window WatchDog */
+    .long     PVD_IRQHandler                /* PVD through EXTI Line detection */
+    .long     TAMP_STAMP_IRQHandler         /* Tamper and TimeStamps through the EXTI line */
+    .long     RTC_WKUP_IRQHandler           /* RTC Wakeup through the EXTI line */
+    .long     FLASH_IRQHandler              /* FLASH */
+    .long     RCC_IRQHandler                /* RCC */
+    .long     EXTI0_IRQHandler              /* EXTI Line0 */
+    .long     EXTI1_IRQHandler              /* EXTI Line1 */
+    .long     EXTI2_IRQHandler              /* EXTI Line2 */
+    .long     EXTI3_IRQHandler              /* EXTI Line3 */
+    .long     EXTI4_IRQHandler              /* EXTI Line4 */
+    .long     DMA1_Stream0_IRQHandler       /* DMA1 Stream 0 */
+    .long     DMA1_Stream1_IRQHandler       /* DMA1 Stream 1 */
+    .long     DMA1_Stream2_IRQHandler       /* DMA1 Stream 2 */
+    .long     DMA1_Stream3_IRQHandler       /* DMA1 Stream 3 */
+    .long     DMA1_Stream4_IRQHandler       /* DMA1 Stream 4 */
+    .long     DMA1_Stream5_IRQHandler       /* DMA1 Stream 5 */
+    .long     DMA1_Stream6_IRQHandler       /* DMA1 Stream 6 */
+    .long     ADC_IRQHandler                /* ADC1, ADC2 and ADC3s */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long     EXTI9_5_IRQHandler            /* External Line[9:5]s */
+    .long     TIM1_BRK_TIM9_IRQHandler      /* TIM1 Break and TIM9 */
+    .long     TIM1_UP_TIM10_IRQHandler      /* TIM1 Update and TIM10 */
+    .long     TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+    .long     TIM1_CC_IRQHandler            /* TIM1 Capture Compare */
+    .long     TIM2_IRQHandler               /* TIM2 */
+    .long     TIM3_IRQHandler               /* TIM3 */
+    .long     TIM4_IRQHandler               /* TIM4 */
+    .long     I2C1_EV_IRQHandler            /* I2C1 Event */
+    .long     I2C1_ER_IRQHandler            /* I2C1 Error */
+    .long     I2C2_EV_IRQHandler            /* I2C2 Event */
+    .long     I2C2_ER_IRQHandler            /* I2C2 Error */
+    .long     SPI1_IRQHandler               /* SPI1 */
+    .long     SPI2_IRQHandler               /* SPI2 */
+    .long     USART1_IRQHandler             /* USART1 */
+    .long     USART2_IRQHandler             /* USART2 */
+    .long    0                     /* Reserved */
+    .long     EXTI15_10_IRQHandler          /* External Line[15:10]s */
+    .long     RTC_Alarm_IRQHandler          /* RTC Alarm (A and B) through EXTI Line */
+    .long     OTG_FS_WKUP_IRQHandler        /* USB OTG FS Wakeup through EXTI line */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long     DMA1_Stream7_IRQHandler       /* DMA1 Stream7 */
+    .long    0                     /* Reserved */
+    .long     SDIO_IRQHandler               /* SDIO */
+    .long     TIM5_IRQHandler               /* TIM5 */
+    .long     SPI3_IRQHandler               /* SPI3 */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long     DMA2_Stream0_IRQHandler       /* DMA2 Stream 0 */
+    .long     DMA2_Stream1_IRQHandler       /* DMA2 Stream 1 */
+    .long     DMA2_Stream2_IRQHandler       /* DMA2 Stream 2 */
+    .long     DMA2_Stream3_IRQHandler       /* DMA2 Stream 3 */
+    .long     DMA2_Stream4_IRQHandler       /* DMA2 Stream 4 */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long     OTG_FS_IRQHandler             /* USB OTG FS */
+    .long     DMA2_Stream5_IRQHandler       /* DMA2 Stream 5 */
+    .long     DMA2_Stream6_IRQHandler       /* DMA2 Stream 6 */
+    .long     DMA2_Stream7_IRQHandler       /* DMA2 Stream 7 */
+    .long     USART6_IRQHandler             /* USART6 */
+    .long     I2C3_EV_IRQHandler            /* I2C3 event */
+    .long     I2C3_ER_IRQHandler            /* I2C3 error */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long     FPU_IRQHandler                /* FPU */
+    .long     SPI4_IRQHandler                   /* SPI4 */ 
+    .long     SPI5_IRQHandler                   /* SPI5 */ 
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx     r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+
+    def_irq_default_handler     WWDG_IRQHandler
+    def_irq_default_handler     PVD_IRQHandler
+    def_irq_default_handler     TAMP_STAMP_IRQHandler
+    def_irq_default_handler     RTC_WKUP_IRQHandler
+    def_irq_default_handler     FLASH_IRQHandler
+    def_irq_default_handler     RCC_IRQHandler
+    def_irq_default_handler     EXTI0_IRQHandler
+    def_irq_default_handler     EXTI1_IRQHandler
+    def_irq_default_handler     EXTI2_IRQHandler
+    def_irq_default_handler     EXTI3_IRQHandler
+    def_irq_default_handler     EXTI4_IRQHandler
+    def_irq_default_handler     DMA1_Stream0_IRQHandler
+    def_irq_default_handler     DMA1_Stream1_IRQHandler
+    def_irq_default_handler     DMA1_Stream2_IRQHandler
+    def_irq_default_handler     DMA1_Stream3_IRQHandler
+    def_irq_default_handler     DMA1_Stream4_IRQHandler
+    def_irq_default_handler     DMA1_Stream5_IRQHandler
+    def_irq_default_handler     DMA1_Stream6_IRQHandler
+    def_irq_default_handler     ADC_IRQHandler
+    def_irq_default_handler     EXTI9_5_IRQHandler
+    def_irq_default_handler     TIM1_BRK_TIM9_IRQHandler
+    def_irq_default_handler     TIM1_UP_TIM10_IRQHandler
+    def_irq_default_handler     TIM1_TRG_COM_TIM11_IRQHandler
+    def_irq_default_handler     TIM1_CC_IRQHandler
+    def_irq_default_handler     TIM2_IRQHandler
+    def_irq_default_handler     TIM3_IRQHandler
+    def_irq_default_handler     TIM4_IRQHandler
+    def_irq_default_handler     I2C1_EV_IRQHandler
+    def_irq_default_handler     I2C1_ER_IRQHandler
+    def_irq_default_handler     I2C2_EV_IRQHandler
+    def_irq_default_handler     I2C2_ER_IRQHandler
+    def_irq_default_handler     SPI1_IRQHandler
+    def_irq_default_handler     SPI2_IRQHandler
+    def_irq_default_handler     USART1_IRQHandler
+    def_irq_default_handler     USART2_IRQHandler
+    def_irq_default_handler     EXTI15_10_IRQHandler
+    def_irq_default_handler     RTC_Alarm_IRQHandler
+    def_irq_default_handler     OTG_FS_WKUP_IRQHandler
+    def_irq_default_handler     DMA1_Stream7_IRQHandler
+    def_irq_default_handler     SDIO_IRQHandler
+    def_irq_default_handler     TIM5_IRQHandler
+    def_irq_default_handler     SPI3_IRQHandler
+    def_irq_default_handler     DMA2_Stream0_IRQHandler
+    def_irq_default_handler     DMA2_Stream1_IRQHandler
+    def_irq_default_handler     DMA2_Stream2_IRQHandler
+    def_irq_default_handler     DMA2_Stream3_IRQHandler
+    def_irq_default_handler     DMA2_Stream4_IRQHandler
+    def_irq_default_handler     OTG_FS_IRQHandler
+    def_irq_default_handler     DMA2_Stream5_IRQHandler
+    def_irq_default_handler     DMA2_Stream6_IRQHandler
+    def_irq_default_handler     DMA2_Stream7_IRQHandler
+    def_irq_default_handler     USART6_IRQHandler
+    def_irq_default_handler     I2C3_EV_IRQHandler
+    def_irq_default_handler     I2C3_ER_IRQHandler
+    def_irq_default_handler     FPU_IRQHandler
+    def_irq_default_handler     SPI4_IRQHandler
+    def_irq_default_handler     SPI5_IRQHandler
+    def_irq_default_handler     DEF_IRQHandler
+
+    .end

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.s

@@ -66,7 +66,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l1xx_hd.s

@@ -54,7 +54,7 @@ Heap_Size       EQU     0x00000400
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.s

@@ -48,7 +48,7 @@ __initial_sp    EQU     0x20004000 ; Top of RAM
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Heap_Size       EQU     0x00000000
+Heap_Size       EQU     0x00000400
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
                 EXPORT  __heap_base
@@ -56,7 +56,7 @@ Heap_Size       EQU     0x00000000
                 
 __heap_base
 Heap_Mem        SPACE   Heap_Size
-__heap_limit
+__heap_limit    EQU (__initial_sp - Stack_Size)
 
                 PRESERVE8
                 THUMB

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/device.h

@@ -37,7 +37,7 @@
 
 #define DEVICE_RTC              1
 
-#define DEVICE_ETHERNET         1
+#define DEVICE_ETHERNET         0
 
 #define DEVICE_PWMOUT           0