mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #2159 from jeromecoutant/PR_dev_NUCLEO_F207ZG
New STM32 board : NUCLEO_F207ZGpull/2098/head
Martin Kojtal
GitHub
commit
dd010097ba
|
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@ -689,6 +689,18 @@
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"default_build": "small",
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"release": true
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},
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"NUCLEO_F207ZG": {
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"supported_form_factors": ["ARDUINO", "MORPHO"],
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"core": "Cortex-M3",
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"default_toolchain": "ARM",
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"extra_labels": ["STM", "STM32F2", "STM32F207ZG"],
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"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
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"inherits": ["Target"],
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"progen": {"target": "nucleo-f207zg"},
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"detect_code": ["0835"],
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"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
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"release": true
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},
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"NUCLEO_F302R8": {
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"supported_form_factors": ["ARDUINO", "MORPHO"],
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"core": "Cortex-M4F",
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File diff suppressed because one or more lines are too long
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@ -0,0 +1,415 @@
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******************* (C) COPYRIGHT 2016 STMicroelectronics ********************
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;* File Name : startup_stm32f207xx.s
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;* Author : MCD Application Team
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;* Version : V2.1.1
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;* Date : 20-November-2015
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;* Description : STM32F207xx devices vector table for MDK-ARM_MICRO toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM3 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;*******************************************************************************
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;
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||||
;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
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||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20020000 ; Top of RAM
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit EQU (__initial_sp - Stack_Size)
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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DCD CAN1_TX_IRQHandler ; CAN1 TX
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DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
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DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
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DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD FSMC_IRQHandler ; FSMC
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DCD SDIO_IRQHandler ; SDIO
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD ETH_IRQHandler ; Ethernet
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DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
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DCD CAN2_TX_IRQHandler ; CAN2 TX
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DCD CAN2_RX0_IRQHandler ; CAN2 RX0
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DCD CAN2_RX1_IRQHandler ; CAN2 RX1
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DCD CAN2_SCE_IRQHandler ; CAN2 SCE
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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||||
DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
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||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
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||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
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DCD OTG_HS_IRQHandler ; USB OTG HS
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||||
DCD DCMI_IRQHandler ; DCMI
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DCD 0 ; Reserved
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DCD HASH_RNG_IRQHandler ; Hash and Rng
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|
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
|
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|
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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||||
UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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||||
ENDP
|
||||
SVC_Handler PROC
|
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EXPORT SVC_Handler [WEAK]
|
||||
B .
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||||
ENDP
|
||||
DebugMon_Handler\
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PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
|
||||
SysTick_Handler PROC
|
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EXPORT SysTick_Handler [WEAK]
|
||||
B .
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||||
ENDP
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||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
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EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FSMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FSMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
; Scatter-Loading Description File
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Copyright (c) 2016, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; 97 vectors * 4 bytes = 388 bytes to reserve (0x184)
|
||||
RW_IRAM1 (0x20000000+0x184) (0x00020000-0x184) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,436 @@
|
|||
******************* (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f207xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.1
|
||||
;* Date : 20-November-2015
|
||||
;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x20020000
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FSMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FSMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
; Scatter-Loading Description File
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Copyright (c) 2016, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; 97 vectors * 4 bytes = 388 bytes to reserve (0x184)
|
||||
RW_IRAM1 (0x20000000+0x184) (0x00020000-0x184) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
/* 97 vectors * 4 bytes = 388 bytes to reserve (0x184) */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
|
||||
RAM (rwx) : ORIGIN = 0x20000184, LENGTH = 128K - 0x184
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* _estack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f207xx.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.1
|
||||
* @date 20-November-2015
|
||||
* @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
//bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
//bl main
|
||||
// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
|
||||
// and when existing hardware_init_hook() and software_init_hook() before
|
||||
// starting main(). software_init_hook() is available and has to be called due
|
||||
// to initializsation when using rtos.
|
||||
bl _start
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word 0 /* CRYP crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,633 @@
|
|||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f207xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.1
|
||||
;* Date : 20-November-2015
|
||||
;* Description : STM32F20x/21x devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_RNG_IRQHandler ; Hash and RNG
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PVD_IRQHandler
|
||||
B PVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TAMP_STAMP_IRQHandler
|
||||
B TAMP_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream0_IRQHandler
|
||||
B DMA1_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream1_IRQHandler
|
||||
B DMA1_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream2_IRQHandler
|
||||
B DMA1_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream3_IRQHandler
|
||||
B DMA1_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream4_IRQHandler
|
||||
B DMA1_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream5_IRQHandler
|
||||
B DMA1_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream6_IRQHandler
|
||||
B DMA1_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_SCE_IRQHandler
|
||||
B CAN1_SCE_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
B TIM1_BRK_TIM9_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
B TIM1_UP_TIM10_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
B OTG_FS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_TIM12_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
B TIM8_BRK_TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_TIM13_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
B TIM8_UP_TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
B TIM8_TRG_COM_TIM14_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream7_IRQHandler
|
||||
B DMA1_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK FSMC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FSMC_IRQHandler
|
||||
B FSMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream0_IRQHandler
|
||||
B DMA2_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream1_IRQHandler
|
||||
B DMA2_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream2_IRQHandler
|
||||
B DMA2_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream3_IRQHandler
|
||||
B DMA2_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream4_IRQHandler
|
||||
B DMA2_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_SCE_IRQHandler
|
||||
B CAN2_SCE_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream5_IRQHandler
|
||||
B DMA2_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream6_IRQHandler
|
||||
B DMA2_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream7_IRQHandler
|
||||
B DMA2_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
B OTG_HS_EP1_OUT_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_IN_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
B OTG_HS_EP1_IN_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
B OTG_HS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_IRQHandler
|
||||
B OTG_HS_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DCMI_IRQHandler
|
||||
B DCMI_IRQHandler
|
||||
|
||||
PUBWEAK HASH_RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HASH_RNG_IRQHandler
|
||||
B HASH_RNG_IRQHandler
|
||||
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20020000;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* mbed Microcontroller Library
|
||||
* A generic CMSIS include header
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "stm32f2xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
|
||||
// MCU Peripherals: 81 vectors
|
||||
// Total: 388 bytes to be reserved in RAM (see scatter file)
|
||||
#define NVIC_NUM_VECTORS 97
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file hal_tick.c
|
||||
* @author MCD Application Team
|
||||
* @brief Initialization of HAL tick
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "hal_tick.h"
|
||||
|
||||
TIM_HandleTypeDef TimMasterHandle;
|
||||
uint32_t PreviousVal = 0;
|
||||
|
||||
void us_ticker_irq_handler(void);
|
||||
|
||||
void timer_irq_handler(void)
|
||||
{
|
||||
// Channel 1 for mbed timeout
|
||||
if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
|
||||
if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
|
||||
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
|
||||
us_ticker_irq_handler();
|
||||
}
|
||||
}
|
||||
|
||||
// Channel 2 for HAL tick
|
||||
if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
|
||||
if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) {
|
||||
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
|
||||
// Increment HAL variable
|
||||
HAL_IncTick();
|
||||
// Prepare next interrupt
|
||||
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
|
||||
PreviousVal = val;
|
||||
#if 0 // For DEBUG only
|
||||
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Reconfigure the HAL tick using a standard timer instead of systick.
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
uint32_t PclkFreq;
|
||||
|
||||
// Get clock configuration
|
||||
// Note: PclkFreq contains here the Latency (not used after)
|
||||
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
|
||||
|
||||
// Get TIM5 clock value
|
||||
PclkFreq = HAL_RCC_GetPCLK1Freq();
|
||||
|
||||
// Enable timer clock
|
||||
TIM_MST_RCC;
|
||||
|
||||
// Reset timer
|
||||
TIM_MST_RESET_ON;
|
||||
TIM_MST_RESET_OFF;
|
||||
|
||||
// Configure time base
|
||||
TimMasterHandle.Instance = TIM_MST;
|
||||
TimMasterHandle.Init.Period = 0xFFFFFFFF;
|
||||
|
||||
// TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
|
||||
if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1)
|
||||
TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick
|
||||
else
|
||||
TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick
|
||||
|
||||
TimMasterHandle.Init.ClockDivision = 0;
|
||||
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
TimMasterHandle.Init.RepetitionCounter = 0;
|
||||
HAL_TIM_OC_Init(&TimMasterHandle);
|
||||
|
||||
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
|
||||
NVIC_EnableIRQ(TIM_MST_IRQ);
|
||||
|
||||
// Channel 1 for mbed timeout
|
||||
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
|
||||
|
||||
// Channel 2 for HAL tick
|
||||
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
|
||||
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
|
||||
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||
|
||||
#if 0 // For DEBUG only
|
||||
__GPIOB_CLK_ENABLE();
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
#endif
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file hal_tick.h
|
||||
* @author MCD Application Team
|
||||
* @brief Initialization of HAL tick
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_TICK_H
|
||||
#define __HAL_TICK_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32f2xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define TIM_MST TIM5
|
||||
#define TIM_MST_IRQ TIM5_IRQn
|
||||
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
|
||||
|
||||
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
|
||||
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
|
||||
|
||||
#define HAL_TICK_DELAY (1000) // 1 ms
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __HAL_TICK_H
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,206 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.2
|
||||
* @date 29-June-2016
|
||||
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F2xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f2xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F2xx_H
|
||||
#define __STM32F2xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F2)
|
||||
#define STM32F2
|
||||
#endif /* STM32F2 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx)
|
||||
|
||||
/* #define STM32F205xx */ /*!< STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF,
|
||||
STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC,
|
||||
STM32F205RB and STM32F205VB Devices */
|
||||
/* #define STM32F215xx */ /*!< STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE and STM32F215ZE Devices */
|
||||
#define STM32F207xx /*!< STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF,
|
||||
STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */
|
||||
/* #define STM32F217xx */ /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */
|
||||
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
#define USE_HAL_DRIVER
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.1.2
|
||||
*/
|
||||
#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F2xx_CMSIS_VERSION))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F205xx)
|
||||
#include "stm32f205xx.h"
|
||||
#elif defined(STM32F215xx)
|
||||
#include "stm32f215xx.h"
|
||||
#elif defined(STM32F207xx)
|
||||
#include "stm32f207xx.h"
|
||||
#elif defined(STM32F217xx)
|
||||
#include "stm32f217xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F2xx device used in your application (in stm32f2xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum {
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum {
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f2xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F2xx_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,460 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f2xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.2
|
||||
* @date 29-June-2016
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f2xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
|
||||
* | (external 25MHz xtal) | (internal 16MHz clock)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 120 | 96
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 120 | 96
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 30 | 12
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 60 | 24
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB capable | YES | NO
|
||||
* with 48 MHz precise clock | |
|
||||
*-----------------------------------------------------------------------------
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f2xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f2xx.h"
|
||||
#include "hal_tick.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on STM322xG_EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* This variable can be updated in Three ways :
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 120000000;
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
SystemCoreClock = 120000000;
|
||||
#else
|
||||
SystemCoreClock = 96000000;
|
||||
#endif
|
||||
HAL_Init();
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings */
|
||||
SetSysClock();
|
||||
|
||||
/* Reset the timer to avoid issues after the RAM initialization */
|
||||
TIM_MST_RESET_ON;
|
||||
TIM_MST_RESET_OFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f2xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM322xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00;
|
||||
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR |= 0x00000078;
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
|
||||
(void)(tmp);
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00CCC0CC;
|
||||
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xAAAA0A8A;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xFFFF0FCF;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00CC0CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA828A;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00CCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCC0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA000AAA;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xFF000FFF;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00CCCCCC;
|
||||
GPIOG->AFR[1] = 0x000000C0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00085AAA;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000CAFFF;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*--FSMC Configuration -------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FSMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI() == 0) {
|
||||
while (1) {
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 // SYSCLK can be map to PC_9
|
||||
HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_2);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
|
||||
}
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 8;
|
||||
RCC_OscInitStruct.PLL.PLLN = 240;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 5;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = 16;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 8;
|
||||
RCC_OscInitStruct.PLL.PLLN = 192;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 8;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
||||
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f2xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.2
|
||||
* @date 29-June-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f2xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F2XX_H
|
||||
#define __SYSTEM_STM32F2XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F2xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
extern void SetSysClock(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F2XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,498 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs' categories:
|
||||
(+) Common HAL APIs
|
||||
(+) Services HAL APIs
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F2xx HAL Driver version number V1.1.3
|
||||
*/
|
||||
#define __STM32F2xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F2xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F2xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F2xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|(__STM32F2xx_HAL_VERSION_SUB2 << 8U) \
|
||||
|(__STM32F2xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
|
||||
|
||||
/* ------------ RCC registers bit address in the alias region ----------- */
|
||||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
|
||||
/* --- MEMRMP Register ---*/
|
||||
/* Alias word address of UFB_MODE bit */
|
||||
#define MEMRMP_OFFSET SYSCFG_OFFSET
|
||||
#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
|
||||
#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
|
||||
|
||||
/* --- CMPCR Register ---*/
|
||||
/* Alias word address of CMP_PD bit */
|
||||
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
|
||||
#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
|
||||
#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) Systick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is used to initialize the HAL Library; it must be the first
|
||||
* instruction to be executed in the main program (before to call any other
|
||||
* HAL function), it performs the following:
|
||||
* Configure the Flash prefetch, instruction and Data caches.
|
||||
* Configures the SysTick to generate an interrupt each 1 millisecond,
|
||||
* which is clocked by the HSI (at this stage, the clock is not yet
|
||||
* configured and thus the system is running from the internal HSI at 16 MHz).
|
||||
* Set NVIC Group Priority to 4.
|
||||
* Calls the HAL_MspInit() callback function defined in user file
|
||||
* "stm32f2xx_hal_msp.c" to do the global low level hardware initialization
|
||||
*
|
||||
* @note SysTick is used as time base for the HAL_Delay() function, the application
|
||||
* need to ensure that the SysTick time base is always set to 1 millisecond
|
||||
* to have correct HAL operation.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache */
|
||||
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
||||
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
||||
#endif /* INSTRUCTION_CACHE_ENABLE */
|
||||
|
||||
#if (DATA_CACHE_ENABLE != 0U)
|
||||
__HAL_FLASH_DATA_CACHE_ENABLE();
|
||||
#endif /* DATA_CACHE_ENABLE */
|
||||
|
||||
#if (PREFETCH_ENABLE != 0U)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the systick.
|
||||
* This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB1_FORCE_RESET();
|
||||
__HAL_RCC_AHB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB2_FORCE_RESET();
|
||||
__HAL_RCC_AHB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB3_FORCE_RESET();
|
||||
__HAL_RCC_AHB3_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority: Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
HAL_SYSTICK_Config(SystemCoreClock/1000U);
|
||||
|
||||
/*Configure the SysTick IRQ priority */
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in Systick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay: specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(__IO uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
tickstart = HAL_GetTick();
|
||||
while((HAL_GetTick() - tickstart) < Delay)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F2xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableCompensationCell(void)
|
||||
{
|
||||
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power-down the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableCompensationCell(void)
|
||||
{
|
||||
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_H
|
||||
#define __STM32F2xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
|
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
|
||||
}while(0);
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
|
||||
}while(0);
|
||||
|
||||
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
|
||||
}while(0);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(__IO uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
void HAL_EnableCompensationCell(void);
|
||||
void HAL_DisableCompensationCell(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,854 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of ADC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_ADC_H
|
||||
#define __STM32F2xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC and regular group initialization
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
|
||||
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
|
||||
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
|
||||
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
|
||||
all the ADCs.
|
||||
This parameter can be a value of @ref ADC_ClockPrescaler */
|
||||
uint32_t Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
|
||||
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
|
||||
This parameter can be a value of @ref ADC_Data_align */
|
||||
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
|
||||
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
|
||||
Scan direction is upward: from rank1 to rank 'n'.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
|
||||
This parameter can be a value of @ref ADC_EOCSelection.
|
||||
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
|
||||
Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
|
||||
or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
|
||||
Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
|
||||
If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
|
||||
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
|
||||
after the selected trigger occurred (software start or external trigger).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
|
||||
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
|
||||
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
|
||||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
|
||||
uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge by default.
|
||||
This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
|
||||
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
|
||||
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
|
||||
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
|
||||
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
|
||||
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
|
||||
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC channel for regular group
|
||||
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
|
||||
* ADC can be either disabled or enabled without conversion on going on regular group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_selection */
|
||||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
|
||||
This parameter has an effect only if watchdog mode is configured on single channel
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
|
||||
is interrupt mode or in polling mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_AnalogWDGConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC states definition (bitfields)
|
||||
*/
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
|
||||
|
||||
/* States of ADC analog watchdogs */
|
||||
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
ADC_InitTypeDef Init; /*!< ADC required parameters */
|
||||
|
||||
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
|
||||
__IO uint32_t State; /*!< ADC communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
}ADC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Error_Code ADC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
|
||||
enable/disable, erroneous state */
|
||||
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
|
||||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
|
||||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Resolution ADC Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
|
||||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
|
||||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
|
||||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
||||
* @{
|
||||
*/
|
||||
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
|
||||
/* compatibility with other STM32 devices. */
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
|
||||
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Data_align ADC Data Align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
|
||||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels ADC Common Channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
|
||||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
|
||||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
|
||||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
|
||||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
|
||||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
|
||||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
|
||||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
|
||||
|
||||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
|
||||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_times ADC Sampling Times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
|
||||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
||||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
||||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
|
||||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
||||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
|
||||
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
|
||||
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Event_type ADC Event Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
||||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
||||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
||||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
||||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition ADC Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
||||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
||||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
||||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
||||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
||||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels_type ADC Channels Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
|
||||
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||||
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset ADC handle state
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC peripheral.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC peripheral.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: ADC Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: ADC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: specifies the ADC interrupt source to check.
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the ADC's pending flags.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __FLAG__: ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Get the selected ADC's flag status.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __FLAG__: ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include ADC HAL Extension module */
|
||||
#include "stm32f2xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ***************************************************/
|
||||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Delay for ADC stabilization time. */
|
||||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
||||
/* Unit: us */
|
||||
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in
|
||||
code of final user */
|
||||
|
||||
/**
|
||||
* @brief Verification of ADC state: enabled or disabled
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
||||
*/
|
||||
#define ADC_IS_ENABLE(__HANDLE__) \
|
||||
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
|
||||
) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of regular group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Simultaneously clears and sets specific bits of the handle State
|
||||
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||||
* the first parameter is the ADC handle State, the second parameter is the
|
||||
* bit field to clear, the third and last parameter is the bit field to set.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_STATE_CLR_SET MODIFY_REG
|
||||
|
||||
/**
|
||||
* @brief Clear ADC error code (set it to error code: "no error")
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
||||
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||||
|
||||
|
||||
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
|
||||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_10B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_8B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_6B))
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
|
||||
((ALIGN) == ADC_DATAALIGN_LEFT))
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_15CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_28CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_56CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_84CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_112CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_144CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_480CYCLES))
|
||||
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
|
||||
((EOCSelection) == ADC_EOC_SEQ_CONV) || \
|
||||
((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
|
||||
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
|
||||
((EVENT) == ADC_OVR_EVENT))
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
|
||||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
|
||||
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
|
||||
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
|
||||
|
||||
/**
|
||||
* @brief Set ADC Regular channel sequence length.
|
||||
* @param _NbrOfConversion_: Regular channel sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
||||
* @param _SAMPLETIME_: Sample time parameter.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
||||
* @param _SAMPLETIME_: Sample time parameter.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
|
||||
|
||||
/**
|
||||
* @brief Enable ADC continuous conversion mode.
|
||||
* @param _CONTINUOUS_MODE_: Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
|
||||
|
||||
/**
|
||||
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
||||
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
|
||||
|
||||
/**
|
||||
* @brief Enable ADC scan mode.
|
||||
* @param _SCANCONV_MODE_: Scan conversion mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion selection.
|
||||
* @param _EOCSelection_MODE_: End of conversion selection mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC DMA continuous request.
|
||||
* @param _DMAContReq_MODE_: DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
|
||||
|
||||
/**
|
||||
* @brief Return resolution bits in CR1 register.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F2xx_ADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,378 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of ADC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_ADC_EX_H
|
||||
#define __STM32F2xx_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration injected Channel structure definition
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
|
||||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
|
||||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||
This parameter can be a value of @ref ADC_channels
|
||||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
|
||||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||
This parameter must be a value of @ref ADCEx_injected_rank
|
||||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
|
||||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
|
||||
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
}ADC_InjectionConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||
This parameter can be a value of @ref ADCEx_Common_mode */
|
||||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
|
||||
}ADC_MultiModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Common_mode ADC Common Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
|
||||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
|
||||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
|
||||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
|
||||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_injected_rank ADC Injected Rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
|
||||
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
|
||||
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
|
||||
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_channels ADC Specific Channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_INTERL) || \
|
||||
((MODE) == ADC_DUALMODE_ALTERTRIG) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
|
||||
((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_INTERL) || \
|
||||
((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_1) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_2) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_3))
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
|
||||
((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @param _JSQR_JL_: Sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F2xx_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,771 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_CAN_H
|
||||
#define __STM32F2xx_HAL_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
|
||||
|
||||
}HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
}CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t BankNumber; /*!< Select the start slave bank filter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
|
||||
|
||||
}CAN_FilterConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
}CanTxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
|
||||
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
|
||||
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
|
||||
|
||||
}CanRxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
|
||||
|
||||
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
|
||||
}CAN_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */
|
||||
#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */
|
||||
#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */
|
||||
#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */
|
||||
#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */
|
||||
#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */
|
||||
#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */
|
||||
#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */
|
||||
#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus CAN InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Identifier_Type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
|
||||
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __INTERRUPT__: CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __INTERRUPT__: CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03U)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__: CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
|
||||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the DBG Freeze for CAN.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ***************************************************/
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
|
||||
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Functions CAN Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,400 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f2xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_CONF_H
|
||||
#define __STM32F2xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCCARD_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x0010U) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x0011U) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x0012U) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f2xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M3 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
|
||||
(#) please refer to programing manual for details in how to configure priority.
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest preemption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32f2xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (preemption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup: The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @param PreemptPriority: The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority: the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != RESET)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00U;
|
||||
MPU->RASR = 0x00U;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn: External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @param PriorityGroup: the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,467 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_CORTEX_H
|
||||
#define __STM32F2xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
|
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
|
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
|
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
|
||||
* @brief CORTEX private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Disables the MPU
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Disable fault exceptions */
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Disable the MPU */
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU
|
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Enable fault exceptions */
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,349 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The CRC HAL driver can be used as follows:
|
||||
|
||||
(#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
|
||||
|
||||
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of
|
||||
a 32-bit data buffer using combination of the previous CRC value
|
||||
and the new one.
|
||||
|
||||
(#) Use HAL_CRC_Calculate() function to compute the CRC Value of
|
||||
a new 32-bit data buffer. This function resets the CRC computation
|
||||
unit before starting the computation to avoid getting wrong CRC values.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP
|
||||
(+) DeInitialize CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and creates the associated handle.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if(hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcrc->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC peripheral.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if(hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CRC MSP.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Functions_Group2
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||
using combination of the previous CRC value and the new one.
|
||||
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of 32-bit data buffer using combination
|
||||
* of the previous CRC value and the new one.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of 32-bit data buffer independently
|
||||
* of the previous CRC value.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @param pBuffer: Pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: Length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Enter Data to the CRC calculator */
|
||||
for(index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRC_Exported_Functions_Group3
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC state.
|
||||
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||
* the configuration information for CRC
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_CRC_H
|
||||
#define __STM32F2xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
|
||||
}HAL_CRC_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
}CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Resets CRC handle state
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Resets CRC Data Register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @param __VALUE__: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Types CRC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Defines CRC Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Variables CRC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Constants CRC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,536 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_CRYP_H
|
||||
#define __STM32F2xx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
|
||||
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
|
||||
This parameter can be a value of @ref CRYP_Key_Size */
|
||||
|
||||
uint8_t* pKey; /*!< The key used for encryption/decryption */
|
||||
|
||||
uint8_t* pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
|
||||
uint8_t IVSize; /*!< The size of initialization vector.
|
||||
This parameter (called nonce size in CCM) is used only
|
||||
in AES-128/192/256 encryption/decryption CCM mode */
|
||||
|
||||
uint8_t TagSize; /*!< The size of returned authentication TAG.
|
||||
This parameter is used only in AES-128/192/256
|
||||
encryption/decryption CCM mode */
|
||||
|
||||
uint8_t* Header; /*!< The header used in GCM and CCM modes */
|
||||
|
||||
uint32_t HeaderSize; /*!< The size of header buffer in bytes */
|
||||
|
||||
uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
|
||||
This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
|
||||
}CRYP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
|
||||
HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
|
||||
HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
|
||||
}HAL_CRYP_STATETypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
|
||||
HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
|
||||
HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase
|
||||
This is relevant only with CCM and GCM modes */
|
||||
}HAL_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
CRYP_TypeDef *Instance; /*!< CRYP registers base address */
|
||||
|
||||
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of inputed data */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
|
||||
|
||||
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
}CRYP_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000U)
|
||||
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
|
||||
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U)
|
||||
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003CU)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000CU)
|
||||
#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010U)
|
||||
#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014U)
|
||||
#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018U)
|
||||
#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001CU)
|
||||
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020U)
|
||||
#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024U)
|
||||
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028U)
|
||||
#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002CU)
|
||||
#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030U)
|
||||
#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
|
||||
#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010U) /*!< The CRYP core is currently
|
||||
processing a block of data
|
||||
or a key preparation (for
|
||||
AES decryption). */
|
||||
#define CRYP_FLAG_IFEM ((uint32_t)0x00000001U) /*!< Input FIFO is empty */
|
||||
#define CRYP_FLAG_IFNF ((uint32_t)0x00000002U) /*!< Input FIFO is not Full */
|
||||
#define CRYP_FLAG_OFNE ((uint32_t)0x00000004U) /*!< Output FIFO is not empty */
|
||||
#define CRYP_FLAG_OFFU ((uint32_t)0x00000008U) /*!< Output FIFO is Full */
|
||||
#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U) /*!< Output FIFO service raw
|
||||
interrupt status */
|
||||
#define CRYP_FLAG_INRIS ((uint32_t)0x01000001U) /*!< Input FIFO service raw
|
||||
interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
|
||||
|
||||
/**
|
||||
* @brief Flush the data FIFO.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
|
||||
|
||||
/**
|
||||
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param MODE: The algorithm mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
|
||||
|
||||
/** @brief Check whether the specified CRYP flag is set or not.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption).
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24U)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: CRYP Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* AES encryption/decryption using polling ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
|
||||
/* AES encryption/decryption using interrupt *********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/* AES encryption/decryption using DMA ***************************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* DES encryption/decryption using polling ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
|
||||
/* DES encryption/decryption using interrupt *********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/* DES encryption/decryption using DMA ***************************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* TDES encryption/decryption using polling **********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
|
||||
/* TDES encryption/decryption using interrupt ********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/* TDES encryption/decryption using DMA **************************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Types CRYP Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_FLAG_MASK ((uint32_t)0x0000001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
|
||||
((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
|
||||
((__KEYSIZE__) == CRYP_KEYSIZE_256B))
|
||||
|
||||
|
||||
#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_16B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_8B) || \
|
||||
((__DATATYPE__) == CRYP_DATATYPE_1B))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F215xx || STM32F217xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_CRYP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,959 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital to Analog Converter (DAC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State and Errors functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** DAC Channels ***
|
||||
====================
|
||||
[..]
|
||||
The device integrates two 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC channel1 with DAC_OUT1 (PA4) as output
|
||||
(#) DAC channel2 with DAC_OUT2 (PA5) as output
|
||||
|
||||
*** DAC Triggers ***
|
||||
====================
|
||||
[..]
|
||||
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
|
||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
|
||||
[..]
|
||||
Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
|
||||
(DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
|
||||
|
||||
(#) Software using DAC_TRIGGER_SOFTWARE
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
|
||||
[..]
|
||||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC wave generation feature ***
|
||||
===================================
|
||||
[..]
|
||||
Both DAC channels can be used to generate
|
||||
(#) Noise wave
|
||||
(#) Triangle wave
|
||||
|
||||
*** DAC data format ***
|
||||
=======================
|
||||
[..]
|
||||
The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_ALIGN_8B_R
|
||||
(#) 12-bit left alignment using DAC_ALIGN_12B_L
|
||||
(#) 12-bit right alignment using DAC_ALIGN_12B_R
|
||||
|
||||
*** DAC data value to voltage correspondence ***
|
||||
================================================
|
||||
[..]
|
||||
The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
*** DMA requests ***
|
||||
=====================
|
||||
[..]
|
||||
A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
HAL_DAC_Start_DMA()
|
||||
[..]
|
||||
DMA1 requests are mapped as following:
|
||||
(#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
|
||||
already configured
|
||||
(#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
|
||||
already configured
|
||||
|
||||
-@- For Dual mode and specific signal (Triangle and noise) generation please
|
||||
refer to Extension Features Driver description
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC
|
||||
registers using HAL_DAC_Init()
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
|
||||
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start()
|
||||
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop()
|
||||
|
||||
*** DMA mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
|
||||
of data to be transferred at each end of conversion
|
||||
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
|
||||
function is executed and user can add his own code by customization of function pointer
|
||||
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
|
||||
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
|
||||
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DAC HAL driver.
|
||||
|
||||
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
|
||||
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
|
||||
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
|
||||
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DAC.
|
||||
(+) De-initialize the DAC.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||
* in the DAC_InitStruct.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
if(hdac->State == HAL_DAC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdac->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_DAC_MspInit(hdac);
|
||||
}
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Initialize the DAC state*/
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
if(hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DAC_MspDeInit(hdac);
|
||||
|
||||
/* Set DAC error code to none */
|
||||
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DAC MSP.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, Channel);
|
||||
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
|
||||
tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
|
||||
/* Check if software trigger enabled */
|
||||
if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
|
||||
{
|
||||
/* Enable the selected DAC software conversion */
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
|
||||
tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
|
||||
/* Check if software trigger enabled */
|
||||
if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
|
||||
{
|
||||
/* Enable the selected DAC software conversion*/
|
||||
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param pData: The destination peripheral Buffer address.
|
||||
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||
* @param Alignment: Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
|
||||
{
|
||||
uint32_t tmpreg = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel1 */
|
||||
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||
|
||||
/* Set the DMA error callback for channel1 */
|
||||
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||
|
||||
/* Enable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN1;
|
||||
|
||||
/* Case of use of channel 1 */
|
||||
switch(Alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||
|
||||
/* Set the DMA half transfer complete callback for channel2 */
|
||||
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||
|
||||
/* Set the DMA error callback for channel2 */
|
||||
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||
|
||||
/* Enable the selected DAC channel2 DMA request */
|
||||
hdac->Instance->CR |= DAC_CR_DMAEN2;
|
||||
|
||||
/* Case of use of channel 2 */
|
||||
switch(Alignment)
|
||||
{
|
||||
case DAC_ALIGN_12B_R:
|
||||
/* Get DHR12R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||
break;
|
||||
case DAC_ALIGN_12B_L:
|
||||
/* Get DHR12L2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
/* Get DHR8R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DAC_ENABLE(hdac, Channel);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables DAC and stop conversion of channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, Channel);
|
||||
|
||||
/* Disable the DMA Channel */
|
||||
/* Channel1 is used */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||
}
|
||||
else /* Channel2 is used for */
|
||||
{
|
||||
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||
}
|
||||
|
||||
/* Check if DMA Channel effectively disabled */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Update DAC state machine to error */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
return hdac->Instance->DOR1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return hdac->Instance->DOR2;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DAC interrupt request
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Check underrun channel 1 flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to channel1 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||
}
|
||||
/* Check underrun channel 2 flag */
|
||||
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to channel2 DMA underrun error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
|
||||
|
||||
/* Error callback */
|
||||
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel1.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure channels.
|
||||
(+) Set the specified data holding register value for DAC channel.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param sConfig: DAC configuration structure.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
|
||||
{
|
||||
uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = hdac->Instance->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << Channel;
|
||||
/* Write to DAC CR */
|
||||
hdac->Instance->CR = tmpreg1;
|
||||
/* Disable wave generation */
|
||||
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param Alignment: Specifies the data alignment.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param Data: Data to be loaded in the selected data holding register.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)hdac->Instance;
|
||||
if(Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
|
||||
}
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DAC state.
|
||||
(+) Check the DAC Errors.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the DAC state
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Return DAC state */
|
||||
return hdac->State;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the DAC error code
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval DAC Error Code
|
||||
*/
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
return hdac->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DAC_ConvCpltCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DAC_ErrorCallbackCh1(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,405 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DAC_H
|
||||
#define __STM32F2xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_ChannelConfTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC Output Buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC Data Alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT Definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
|
||||
/** @brief Enable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __DAC_Channel__: specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/** @brief Disable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __DAC_Channel__: specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/** @brief Enable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: DAC handle
|
||||
* @param __INTERRUPT__: DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
#include "stm32f2xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions *********************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @brief Set DHR12R1 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12R2 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12RD alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F2xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,382 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of DAC extension peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
|
||||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx DACEx
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Extended features functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start conversion.
|
||||
(+) Stop conversion.
|
||||
(+) Start conversion and enable DMA transfer.
|
||||
(+) Stop conversion and disable DMA transfer.
|
||||
(+) Get result of conversion.
|
||||
(+) Get result of dual mode conversion.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
tmp |= hdac->Instance->DOR1;
|
||||
|
||||
tmp |= hdac->Instance->DOR2 << 16U;
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||
* @param Amplitude: Select max triangle amplitude.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
|
||||
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
|
||||
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_BUSY;
|
||||
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @param Alignment: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||
* DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||
* DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||
{
|
||||
uint32_t data = 0U, tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (Alignment == DAC_ALIGN_8B_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8U) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16U) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)hdac->Instance;
|
||||
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DAC callback for Channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA underrun DAC callback for channel2.
|
||||
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdac);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA half transfer complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
/* Conversion complete callback */
|
||||
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Set DAC error code to DMA error */
|
||||
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||
|
||||
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||
|
||||
hdac->State= HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DAC_EX_H
|
||||
#define __STM32F2xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F2xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,884 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dcmi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief DCMI HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital Camera Interface (DCMI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State and Error functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The sequence below describes how to use this driver to capture image
|
||||
from a camera module connected to the DCMI Interface.
|
||||
This sequence does not take into account the configuration of the
|
||||
camera module, which should be made before to configure and enable
|
||||
the DCMI to capture images.
|
||||
|
||||
(#) Program the required configuration through following parameters:
|
||||
horizontal and vertical polarity, pixel clock polarity, Capture Rate,
|
||||
Synchronization Mode, code of the frame delimiter and data width
|
||||
using HAL_DCMI_Init() function.
|
||||
|
||||
(#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
|
||||
register to the destination memory buffer.
|
||||
|
||||
(#) Program the required configuration through following parameters:
|
||||
DCMI mode, destination memory Buffer address and the data length
|
||||
and enable capture using HAL_DCMI_Start_DMA() function.
|
||||
|
||||
(#) Optionally, configure and Enable the CROP feature to select a rectangular
|
||||
window from the received image using HAL_DCMI_ConfigCrop()
|
||||
and HAL_DCMI_EnableCROP() functions
|
||||
|
||||
(#) The capture can be stopped using HAL_DCMI_Stop() function.
|
||||
|
||||
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
|
||||
|
||||
*** DCMI HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DCMI HAL driver.
|
||||
|
||||
(+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
|
||||
(+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
|
||||
(+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
|
||||
(+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
|
||||
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
|
||||
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
|
||||
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DCMI HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMI DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)14U) /* Set timeout to 1s */
|
||||
|
||||
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
|
||||
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
|
||||
|
||||
#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
|
||||
#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
|
||||
#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
|
||||
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize and configure the DCMI
|
||||
(+) De-initialize the DCMI
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the DCMI according to the specified
|
||||
* parameters in the DCMI_InitTypeDef and create the associated handle.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Check the DCMI peripheral state */
|
||||
if(hdcmi == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
|
||||
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
|
||||
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
|
||||
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
|
||||
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
|
||||
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
|
||||
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
|
||||
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
|
||||
|
||||
if(hdcmi->State == HAL_DCMI_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdcmi->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_DCMI_MspInit(hdcmi);
|
||||
}
|
||||
|
||||
/* Change the DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Set DCMI parameters */
|
||||
/* Configures the HS, VS, DE and PC polarity */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
|
||||
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
|
||||
DCMI_CR_ESS);
|
||||
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
|
||||
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
|
||||
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
|
||||
hdcmi->Init.JPEGMode);
|
||||
|
||||
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
|
||||
{
|
||||
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
|
||||
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|
|
||||
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |
|
||||
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
|
||||
}
|
||||
|
||||
/* Enable the Line, Vsync, Error and Overrun interrupts */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DCMI peripheral registers to their default reset
|
||||
* values.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* DeInit the low level hardware */
|
||||
HAL_DCMI_MspDeInit(hdcmi);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DCMI MSP.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DCMI MSP.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure destination address and data length and
|
||||
Enables DCMI DMA request and enables DCMI capture
|
||||
(+) Stop the DCMI capture.
|
||||
(+) Handles DCMI interrupt request.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables DCMI DMA request and enables DCMI capture
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
|
||||
* @param pData: The destination memory Buffer address (LCD Frame buffer).
|
||||
* @param Length: The length of capture to be transferred.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
|
||||
{
|
||||
/* Initialize the second memory address */
|
||||
uint32_t SecondMemAddress = 0U;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Enable DCMI by setting DCMIEN bit */
|
||||
__HAL_DCMI_ENABLE(hdcmi);
|
||||
|
||||
/* Configure the DCMI Mode */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
|
||||
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
|
||||
|
||||
/* Set the DMA memory0 conversion complete callback */
|
||||
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
|
||||
|
||||
/* Set the DMA error callback */
|
||||
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
|
||||
|
||||
/* Set the dma abort callback */
|
||||
hdcmi->DMA_Handle->XferAbortCallback = NULL;
|
||||
|
||||
/* Reset transfer counters value */
|
||||
hdcmi->XferCount = 0;
|
||||
hdcmi->XferTransferNumber = 0;
|
||||
|
||||
if(Length <= 0xFFFFU)
|
||||
{
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
|
||||
}
|
||||
else /* DCMI_DOUBLE_BUFFER Mode */
|
||||
{
|
||||
/* Set the DMA memory1 conversion complete callback */
|
||||
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
|
||||
|
||||
/* Initialize transfer parameters */
|
||||
hdcmi->XferCount = 1U;
|
||||
hdcmi->XferSize = Length;
|
||||
hdcmi->pBuffPtr = pData;
|
||||
|
||||
/* Get the number of buffer */
|
||||
while(hdcmi->XferSize > 0xFFFFU)
|
||||
{
|
||||
hdcmi->XferSize = (hdcmi->XferSize/2U);
|
||||
hdcmi->XferCount = hdcmi->XferCount*2U;
|
||||
}
|
||||
|
||||
/* Update DCMI counter and transfer number*/
|
||||
hdcmi->XferCount = (hdcmi->XferCount - 2U);
|
||||
hdcmi->XferTransferNumber = hdcmi->XferCount;
|
||||
|
||||
/* Update second memory address */
|
||||
SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
|
||||
|
||||
/* Start DMA multi buffer transfer */
|
||||
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
|
||||
}
|
||||
|
||||
/* Enable Capture */
|
||||
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DCMI DMA request and Disable DCMI capture
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
__IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Disable Capture */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
|
||||
|
||||
/* Check if the DCMI capture effectively disabled */
|
||||
do
|
||||
{
|
||||
if (count-- == 0)
|
||||
{
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
|
||||
|
||||
status = HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
|
||||
|
||||
/* Disable the DCMI */
|
||||
__HAL_DCMI_DISABLE(hdcmi);
|
||||
|
||||
/* Disable the DMA */
|
||||
HAL_DMA_Abort(hdcmi->DMA_Handle);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
__IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
if(hdcmi->State == HAL_DCMI_STATE_BUSY)
|
||||
{
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
|
||||
|
||||
/* Disable Capture */
|
||||
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
|
||||
|
||||
/* Check if the DCMI capture effectively disabled */
|
||||
do
|
||||
{
|
||||
if (count-- == 0)
|
||||
{
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
status = HAL_TIMEOUT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
|
||||
}
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume DCMI capture
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
|
||||
{
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Disable Capture */
|
||||
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
|
||||
}
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DCMI interrupt request.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for the DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
|
||||
|
||||
/* Synchronization error interrupt management *******************************/
|
||||
if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
|
||||
{
|
||||
/* Clear the Synchronization error flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_ERROR;
|
||||
|
||||
/* Set the synchronization error callback */
|
||||
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
|
||||
|
||||
/* Abort the DMA Transfer */
|
||||
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
|
||||
}
|
||||
/* Overflow interrupt management ********************************************/
|
||||
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
|
||||
{
|
||||
/* Clear the Overflow flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
|
||||
|
||||
/* Update error code */
|
||||
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
|
||||
|
||||
/* Change DCMI state */
|
||||
hdcmi->State = HAL_DCMI_STATE_ERROR;
|
||||
|
||||
/* Set the overflow callback */
|
||||
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
|
||||
|
||||
/* Abort the DMA Transfer */
|
||||
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
|
||||
}
|
||||
/* Line Interrupt management ************************************************/
|
||||
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
|
||||
{
|
||||
/* Clear the Line interrupt flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
|
||||
|
||||
/* Line interrupt Callback */
|
||||
HAL_DCMI_LineEventCallback(hdcmi);
|
||||
}
|
||||
/* VSYNC interrupt management ***********************************************/
|
||||
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
|
||||
{
|
||||
/* Clear the VSYNC flag */
|
||||
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
|
||||
|
||||
/* VSYNC Callback */
|
||||
HAL_DCMI_VsyncEventCallback(hdcmi);
|
||||
}
|
||||
/* FRAME interrupt management ***********************************************/
|
||||
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
|
||||
{
|
||||
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
|
||||
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
|
||||
{
|
||||
/* Disable the Line, Vsync, Error and Overrun interrupts */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
|
||||
}
|
||||
|
||||
/* Disable the Frame interrupt */
|
||||
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
|
||||
|
||||
/* Frame Callback */
|
||||
HAL_DCMI_FrameEventCallback(hdcmi);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Error DCMI callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_ErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Line Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_LineEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VSYNC Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Frame Event callback.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdcmi);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_DCMI_FrameEventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the CROP feature.
|
||||
(+) Enable/Disable the CROP feature.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure the DCMI CROP coordinate.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @param X0: DCMI window X offset
|
||||
* @param Y0: DCMI window Y offset
|
||||
* @param XSize: DCMI Pixel per line
|
||||
* @param YSize: DCMI Line number
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
|
||||
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
|
||||
assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
|
||||
|
||||
/* Configure CROP */
|
||||
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
|
||||
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
|
||||
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Crop feature.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Disable DCMI Crop feature */
|
||||
hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
|
||||
|
||||
/* Change the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Crop feature.
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdcmi);
|
||||
|
||||
/* Lock the DCMI peripheral state */
|
||||
hdcmi->State = HAL_DCMI_STATE_BUSY;
|
||||
|
||||
/* Enable DCMI Crop feature */
|
||||
hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
|
||||
|
||||
/* Change the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdcmi);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DCMI state.
|
||||
(+) Get the specific DCMI error flag.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the DCMI state
|
||||
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
return hdcmi->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DCMI error code
|
||||
* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
|
||||
* the configuration information for DCMI.
|
||||
* @retval DCMI Error Code
|
||||
*/
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
|
||||
{
|
||||
return hdcmi->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Functions DCMI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
if(hdcmi->XferCount != 0)
|
||||
{
|
||||
/* Update memory 0 address location */
|
||||
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
|
||||
if(((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
|
||||
{
|
||||
tmp = hdcmi->DMA_Handle->Instance->M0AR;
|
||||
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY0);
|
||||
hdcmi->XferCount--;
|
||||
}
|
||||
/* Update memory 1 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
|
||||
{
|
||||
tmp = hdcmi->DMA_Handle->Instance->M1AR;
|
||||
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY1);
|
||||
hdcmi->XferCount--;
|
||||
}
|
||||
}
|
||||
/* Update memory 0 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0U)
|
||||
{
|
||||
hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
|
||||
}
|
||||
/* Update memory 1 address location */
|
||||
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
|
||||
{
|
||||
tmp = hdcmi->pBuffPtr;
|
||||
hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4U*hdcmi->XferSize));
|
||||
hdcmi->XferCount = hdcmi->XferTransferNumber;
|
||||
}
|
||||
|
||||
/* Check if the frame is transferred */
|
||||
if(hdcmi->XferCount == hdcmi->XferTransferNumber)
|
||||
{
|
||||
/* Enable the Frame interrupt */
|
||||
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
|
||||
|
||||
/* When snapshot mode, set dcmi state to ready */
|
||||
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
|
||||
{
|
||||
hdcmi->State= HAL_DCMI_STATE_READY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA error callback
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
|
||||
{
|
||||
/* Initialize the DCMI state*/
|
||||
hdcmi->State = HAL_DCMI_STATE_READY;
|
||||
}
|
||||
|
||||
/* DCMI error Callback */
|
||||
HAL_DCMI_ErrorCallback(hdcmi);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,572 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of DCMI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DCMI_H
|
||||
#define __STM32F2xx_HAL_DCMI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Types DCMI Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
}DCMI_CodesInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMI_Synchronization_Mode */
|
||||
|
||||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
|
||||
|
||||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
|
||||
|
||||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
|
||||
|
||||
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
||||
This parameter can be a value of @ref DCMI_Capture_Rate */
|
||||
|
||||
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
||||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
|
||||
|
||||
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
|
||||
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
|
||||
This parameter can be a value of @ref DCMI_MODE_JPEG */
|
||||
|
||||
}DCMI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
|
||||
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
|
||||
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
|
||||
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
|
||||
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
|
||||
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
|
||||
}HAL_DCMI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
|
||||
|
||||
DCMI_InitTypeDef Init; /*!< DCMI parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DCMI locking object */
|
||||
|
||||
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
|
||||
|
||||
__IO uint32_t XferCount; /*!< DMA transfer counter */
|
||||
|
||||
__IO uint32_t XferSize; /*!< DMA transfer size */
|
||||
|
||||
uint32_t XferTransferNumber; /*!< DMA transfer number */
|
||||
|
||||
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DCMI Error code */
|
||||
|
||||
}DCMI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame through the DMA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
|
||||
synchronization codes embedded in the data flow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
|
||||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
|
||||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
|
||||
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
|
||||
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
|
||||
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
|
||||
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
|
||||
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Flags DCMI Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
|
||||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
|
||||
/**
|
||||
* @brief DCMI RIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
|
||||
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
|
||||
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
|
||||
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
|
||||
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
|
||||
/**
|
||||
* @brief DCMI MIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
|
||||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
|
||||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
|
||||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
|
||||
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DCMI handle state
|
||||
* @param __HANDLE__: specifies the DCMI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the DCMI.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable the DCMI.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DCMI pending flag.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be one of the following values (no combination allowed)
|
||||
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
|
||||
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
|
||||
* @arg DCMI_FLAG_FNE: FIFO empty flag
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
|
||||
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
|
||||
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
|
||||
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
|
||||
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMI pending flags.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DCMI interrupts.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DCMI interrupts.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DCMI interrupt has occurred or not.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval The state of INTERRUPT.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MIS_INDEX ((uint32_t)0x1000U) /*!< DCMI MIS register index */
|
||||
#define DCMI_SR_INDEX ((uint32_t)0x2000U) /*!< DCMI SR register index */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Macros DCMI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
|
||||
((MODE) == DCMI_MODE_SNAPSHOT))
|
||||
|
||||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
|
||||
((MODE) == DCMI_SYNCHRO_EMBEDDED))
|
||||
|
||||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
|
||||
((POLARITY) == DCMI_PCKPOLARITY_RISING))
|
||||
|
||||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_VSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_HSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
|
||||
((JPEG_MODE) == DCMI_JPEG_ENABLE))
|
||||
|
||||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
|
||||
|
||||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_10B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_12B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_14B))
|
||||
|
||||
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
|
||||
|
||||
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DEF
|
||||
#define __STM32F2xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx.h"
|
||||
#include "stm32_hal_legacy.h"
|
||||
#include <stdio.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
|
||||
(__DMA_HANDLE_).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F2xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,793 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DMA_H
|
||||
#define __STM32F2xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @brief DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_Channel_selection */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_FIFO_direct_mode
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_FIFO_threshold_level */
|
||||
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Memory_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Peripheral_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
|
||||
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
|
||||
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
|
||||
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Stream_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
|
||||
|
||||
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
|
||||
|
||||
uint32_t StreamIndex; /*!< DMA Stream Index */
|
||||
|
||||
}DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @brief DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
|
||||
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
|
||||
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Channel_selection DMA Channel selection
|
||||
* @brief DMA channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
|
||||
#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
|
||||
#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
|
||||
#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
|
||||
#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
|
||||
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
|
||||
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
|
||||
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @brief DMA data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @brief DMA peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
|
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @brief DMA memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
|
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @brief DMA peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @brief DMA memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @brief DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
|
||||
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @brief DMA priority levels
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
|
||||
* @brief DMA FIFO direct mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
|
||||
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
|
||||
* @brief DMA FIFO level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_burst DMA Memory burst
|
||||
* @brief DMA memory burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
|
||||
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
|
||||
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
|
||||
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
|
||||
* @brief DMA peripheral burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
|
||||
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
|
||||
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
|
||||
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @brief DMA interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
|
||||
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
|
||||
#define DMA_IT_FE ((uint32_t)0x00000080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @brief DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
|
||||
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
|
||||
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
|
||||
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
|
||||
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
|
||||
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
|
||||
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
|
||||
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
|
||||
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
|
||||
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
|
||||
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
|
||||
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
|
||||
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
|
||||
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
|
||||
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
|
||||
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
|
||||
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
|
||||
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
|
||||
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
|
||||
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: specifies the DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO filled level.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The FIFO filling state.
|
||||
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
|
||||
* and not empty.
|
||||
* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
|
||||
* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
|
||||
* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
|
||||
* - DMA_FIFOStatus_Empty: when FIFO is empty
|
||||
* - DMA_FIFOStatus_Full: when FIFO is full
|
||||
*/
|
||||
#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
DMA_FLAG_TCIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
DMA_FLAG_HTIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
DMA_FLAG_TEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified FIFO error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
DMA_FLAG_FEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream direct mode error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified direct mode error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
DMA_FLAG_DMEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Stream pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Stream pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval The state of DMA_IT.
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
|
||||
((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Writes the number of data units to be transferred on the DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
|
||||
* Number of data items depends only on the Peripheral data format.
|
||||
*
|
||||
* @note If Peripheral data format is Bytes: number of data units is equal
|
||||
* to total number of bytes to be transferred.
|
||||
*
|
||||
* @note If Peripheral data format is Half-Word: number of data units is
|
||||
* equal to total number of bytes to be transferred / 2.
|
||||
*
|
||||
* @note If Peripheral data format is Word: number of data units is equal
|
||||
* to total number of bytes to be transferred / 4.
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMAy Streamx transfer.
|
||||
*/
|
||||
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
|
||||
* @param __HANDLE__: DMA handle
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMA Stream transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
|
||||
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f2xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @brief DMA Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private Constants -------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Constants DMA Private Constants
|
||||
* @brief DMA private defines and constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @brief DMA private macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7))
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR) || \
|
||||
((MODE) == DMA_PFCTRL))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
|
||||
((STATE) == DMA_FIFOMODE_ENABLE))
|
||||
|
||||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
|
||||
|
||||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
|
||||
((BURST) == DMA_MBURST_INC4) || \
|
||||
((BURST) == DMA_MBURST_INC8) || \
|
||||
((BURST) == DMA_MBURST_INC16))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
|
||||
((BURST) == DMA_PBURST_INC4) || \
|
||||
((BURST) == DMA_PBURST_INC8) || \
|
||||
((BURST) == DMA_PBURST_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @brief DMA private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,333 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dma_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief DMA Extension HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the DMA Extension peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The DMA Extension HAL driver can be used as follows:
|
||||
(#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
|
||||
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
|
||||
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
|
||||
-@- In Multi (Double) buffer mode, it is possible to update the base address for
|
||||
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private Constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer with interrupt
|
||||
(+) Change on the fly the memory0 or memory1 address.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Enable the double buffer mode */
|
||||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M1AR = SecondMemAddress;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return error status */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check callback functions */
|
||||
if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Initialize the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Enable the Double buffer mode */
|
||||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M1AR = SecondMemAddress;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Enable Common interrupts*/
|
||||
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
||||
hdma->Instance->FCR |= DMA_IT_FE;
|
||||
|
||||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
||||
{
|
||||
hdma->Instance->CR |= DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change the memory0 or memory1 address on the fly.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param Address: The new address
|
||||
* @param memory: the memory to be changed, This parameter can be one of
|
||||
* the following values:
|
||||
* MEMORY0 /
|
||||
* MEMORY1
|
||||
* @note The MEMORY0 address can be changed only when the current transfer use
|
||||
* MEMORY1 and the MEMORY1 address can be changed only when the current
|
||||
* transfer use MEMORY0.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
|
||||
{
|
||||
if(memory == MEMORY0)
|
||||
{
|
||||
/* change the memory0 address */
|
||||
hdma->Instance->M0AR = Address;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* change the memory1 address */
|
||||
hdma->Instance->M1AR = Address;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameter.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Configure DMA Stream data length */
|
||||
hdma->Instance->NDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->PAR = DstAddress;
|
||||
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->M0AR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->PAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M0AR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_DMA_EX_H
|
||||
#define __STM32F2xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Memory definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
MEMORY0 = 0x00U, /*!< Memory 0 */
|
||||
MEMORY1 = 0x01U /*!< Memory 1 */
|
||||
}HAL_DMA_MemoryTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,768 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch and cache lines.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) 64 cache lines of 128 bits on I-Code
|
||||
(+) 8 cache lines of 128 bits on D-Code
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F2xx devices.
|
||||
|
||||
(#) FLASH Memory IO Programming functions:
|
||||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
|
||||
HAL_FLASH_Lock() functions
|
||||
(++) Program functions: byte, half word, word and double word
|
||||
(++) There Two modes of programming :
|
||||
(+++) Polling mode using HAL_FLASH_Program() function
|
||||
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
|
||||
|
||||
(#) Interrupts and flags management functions :
|
||||
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status by calling HAL_SetErrorCode()
|
||||
|
||||
[..]
|
||||
In addition to these functions, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the Instruction cache and the Data cache
|
||||
(+) Reset the Instruction cache and the Data cache
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variable used for Erase sectors under interruption */
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Program operations */
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
extern void FLASH_FlushCaches(void);
|
||||
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
FLASH->CR &= (~FLASH_CR_PG);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Enable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Enable Error source interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
|
||||
pFlash.Address = Address;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR )) != RESET)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
|
||||
{
|
||||
/*return the faulty sector*/
|
||||
addresstmp = pFlash.Sector;
|
||||
pFlash.Sector = 0xFFFFFFFFU;
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/*return the faulty bank*/
|
||||
addresstmp = pFlash.Bank;
|
||||
}
|
||||
else
|
||||
{
|
||||
/*return the faulty address*/
|
||||
addresstmp = pFlash.Address;
|
||||
}
|
||||
|
||||
/*Save the Error code*/
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/*Stop the procedure ongoing*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
|
||||
{
|
||||
/*Nb of sector to erased can be decreased*/
|
||||
pFlash.NbSectorsToErase--;
|
||||
|
||||
/* Check if there are still sectors to erase*/
|
||||
if(pFlash.NbSectorsToErase != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Sector;
|
||||
/*Indicate user which sector has been erased*/
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
pFlash.Sector++;
|
||||
addresstmp = pFlash.Sector;
|
||||
FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*No more sectors to Erase, user callback can be called.*/
|
||||
/*Reset Sector and stop Erase sectors procedure*/
|
||||
pFlash.Sector = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
|
||||
/* Flush the caches to be sure of the data consistency */
|
||||
FLASH_FlushCaches() ;
|
||||
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/* MassErase ended. Return the selected bank */
|
||||
/* Flush the caches to be sure of the data consistency */
|
||||
FLASH_FlushCaches() ;
|
||||
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Program ended. Return the selected address*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PG, SER, SNB and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
|
||||
|
||||
/* Disable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Disable Error source interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: Bank number which has been requested to erase
|
||||
* Sectors Erase: Sector which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: Bank number which has been requested to erase
|
||||
* Sectors Erase: Sector number which returned an error
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
if((FLASH->CR & FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
FLASH->KEYR = FLASH_KEY1;
|
||||
FLASH->KEYR = FLASH_KEY2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
FLASH->CR |= FLASH_CR_LOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY1;
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OPTSTRT bit in OPTCR register */
|
||||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time Errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode: The returned value can be a combination of:
|
||||
* @arg HAL_FLASH_ERROR_NONE: FLASH Programming Sequence error flag
|
||||
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
|
||||
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
|
||||
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
|
||||
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
|
||||
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout: maximum flash operationtimeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Clear Error Code */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* If there is no error flag set */
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a double word (64-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V and an External Vpp in the range 7V to 9V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint64_t*)Address = Data;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Program word (32-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= FLASH_PSIZE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint32_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.1V to 2.7V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte (8-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 1.8V to 2.1V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address: specifies the address to be programmed.
|
||||
* @param Data: specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= FLASH_PSIZE_BYTE;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint8_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
|
||||
/* Clear FLASH write protection error pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
|
||||
/* Clear FLASH Programming alignment error pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
|
||||
|
||||
/* Clear FLASH Programming parallelism error pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
|
||||
|
||||
/* Clear FLASH Programming sequence error pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
|
||||
|
||||
/* Clear FLASH Operation error pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_FLASH_H
|
||||
#define __STM32F2xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_SECTERASE,
|
||||
FLASH_PROC_MASSERASE,
|
||||
FLASH_PROC_PROGRAM
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
|
||||
|
||||
__IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
|
||||
|
||||
__IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
|
||||
|
||||
__IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
|
||||
|
||||
__IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
|
||||
|
||||
__IO uint32_t Address; /*Internal variable to save address selected for program*/
|
||||
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /* FLASH error code */
|
||||
|
||||
}FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FLASH_Error_Code FLASH Error Code
|
||||
* @brief FLASH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000001U) /*!< Programming Sequence error */
|
||||
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000002U) /*!< Programming Parallelism error */
|
||||
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000004U) /*!< Programming Alignment error */
|
||||
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000008U) /*!< Write protection error */
|
||||
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000010U) /*!< Operation Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
|
||||
#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)
|
||||
#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U)
|
||||
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)
|
||||
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define RDP_KEY ((uint16_t)0x00A5U)
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123U)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
|
||||
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
|
||||
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
|
||||
|
||||
/**
|
||||
* @brief Resets the FLASH instruction Cache.
|
||||
* @note This function must be used only when the Instruction Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
|
||||
FLASH->ACR &= ~FLASH_ACR_ICRST; \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Resets the FLASH data Cache.
|
||||
* @note This function must be used only when the data Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
|
||||
FLASH->ACR &= ~FLASH_ACR_DCRST; \
|
||||
}while(0)
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32f2xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Program operation functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ACR register byte 0 (Bits[7:0]) base address
|
||||
*/
|
||||
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)
|
||||
/**
|
||||
* @brief OPTCR register byte 0 (Bits[7:0]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)
|
||||
/**
|
||||
* @brief OPTCR register byte 1 (Bits[15:8]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)
|
||||
/**
|
||||
* @brief OPTCR register byte 2 (Bits[23:16]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)
|
||||
/**
|
||||
* @brief OPTCR register byte 3 (Bits[31:24]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,706 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH extension peripheral:
|
||||
* + Extended programming operations functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash Extension features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F2xx devices. It includes
|
||||
(#) FLASH Memory Erase functions:
|
||||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
|
||||
HAL_FLASH_Lock() functions
|
||||
(++) Erase function: Erase sector, erase all sectors
|
||||
(++) There are two modes of erase :
|
||||
(+++) Polling Mode using HAL_FLASHEx_Erase()
|
||||
(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
|
||||
|
||||
(#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Set the BOR level
|
||||
(++) Program the user Option Bytes
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx FLASHEx
|
||||
* @brief FLASH HAL Extension module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Option bytes control */
|
||||
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
|
||||
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
static uint16_t FLASH_OB_GetWRP(void);
|
||||
static uint8_t FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetBOR(void);
|
||||
|
||||
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
|
||||
* @brief Extended IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the Extension FLASH
|
||||
programming operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory sectors
|
||||
* @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] SectorError: pointer to variable that
|
||||
* contains the configuration information on faulty sector in case of error
|
||||
* (0xFFFFFFFF means that all the sectors have been correctly erased)
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t index = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/*Initialization of SectorError variable*/
|
||||
*SectorError = 0xFFFFFFFFU;
|
||||
|
||||
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the erase operation is completed, disable the MER Bit */
|
||||
FLASH->CR &= (~FLASH_MER_BIT);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
|
||||
|
||||
/* Erase by sector by sector to be done*/
|
||||
for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
|
||||
{
|
||||
FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the SER and SNB Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
|
||||
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty sector*/
|
||||
*SectorError = index;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Flush the caches to be sure of the data consistency */
|
||||
FLASH_FlushCaches();
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
|
||||
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Enable Error source interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
|
||||
|
||||
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
pFlash.Bank = pEraseInit->Banks;
|
||||
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by sector to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
|
||||
pFlash.NbSectorsToErase = pEraseInit->NbSectors;
|
||||
pFlash.Sector = pEraseInit->Sector;
|
||||
pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
|
||||
|
||||
/*Erase 1st sector and wait for IT*/
|
||||
FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/*Write protection configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
|
||||
{
|
||||
/*Enable of Write protection on the selected Sector*/
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Disable of Write protection on the selected Sector*/
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
|
||||
}
|
||||
}
|
||||
|
||||
/*Read protection configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
}
|
||||
|
||||
/*USER configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW,
|
||||
pOBInit->USERConfig&OB_STOP_NO_RST,
|
||||
pOBInit->USERConfig&OB_STDBY_NO_RST);
|
||||
}
|
||||
|
||||
/*BOR Level configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
|
||||
{
|
||||
status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
|
||||
|
||||
/*Get BOR Level*/
|
||||
pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory sector
|
||||
* @param Sector: FLASH sector to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @param VoltageRange: The device voltage range which defines the erase parallelism.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
|
||||
* the operation will be done by byte (8-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
|
||||
* the operation will be done by half word (16-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
|
||||
* the operation will be done by word (32-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
|
||||
* the operation will be done by double word (64-bit)
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
|
||||
{
|
||||
uint32_t tmp_psize = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_SECTOR(Sector));
|
||||
assert_param(IS_VOLTAGERANGE(VoltageRange));
|
||||
|
||||
if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
|
||||
{
|
||||
tmp_psize = FLASH_PSIZE_BYTE;
|
||||
}
|
||||
else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
|
||||
{
|
||||
tmp_psize = FLASH_PSIZE_HALF_WORD;
|
||||
}
|
||||
else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
|
||||
{
|
||||
tmp_psize = FLASH_PSIZE_WORD;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
|
||||
}
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the sector */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= tmp_psize;
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
|
||||
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Flush the instruction and data caches
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_FlushCaches(void)
|
||||
{
|
||||
/* Flush instruction cache */
|
||||
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
|
||||
{
|
||||
/* Disable instruction cache */
|
||||
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
|
||||
/* Reset instruction cache */
|
||||
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
|
||||
/* Enable instruction cache */
|
||||
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
||||
}
|
||||
|
||||
/* Flush data cache */
|
||||
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
|
||||
{
|
||||
/* Disable data cache */
|
||||
__HAL_FLASH_DATA_CACHE_DISABLE();
|
||||
/* Reset data cache */
|
||||
__HAL_FLASH_DATA_CACHE_RESET();
|
||||
/* Enable data cache */
|
||||
__HAL_FLASH_DATA_CACHE_ENABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Mass erase of FLASH memory
|
||||
* @param VoltageRange: The device voltage range which defines the erase parallelism.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
|
||||
* the operation will be done by byte (8-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
|
||||
* the operation will be done by half word (16-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
|
||||
* the operation will be done by word (32-bit)
|
||||
* @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
|
||||
* the operation will be done by double word (64-bit)
|
||||
*
|
||||
* @param Banks: Banks to be erased
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_BANK_1: Bank1 to be erased
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_VOLTAGERANGE(VoltageRange));
|
||||
assert_param(IS_FLASH_BANK(Banks));
|
||||
|
||||
/* If the previous operation is completed, proceed to erase all sectors */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
|
||||
FLASH->CR |= FLASH_CR_MER;
|
||||
FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired bank 1 sectors
|
||||
*
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash sector i if CortexM3
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WRPSector: specifies the sector(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @param Banks: Enable write protection on all the sectors for the specific bank
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_BANK_1: WRP on all sectors of bank1
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP_SECTOR(WRPSector));
|
||||
assert_param(IS_FLASH_BANK(Banks));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired bank 1 sectors
|
||||
*
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash sector if CortexM3
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WRPSector: specifies the sector(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @param Banks: Enable write protection on all the sectors for the specific bank
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_BANK_1: WRP on all sectors of bank1
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP_SECTOR(WRPSector));
|
||||
assert_param(IS_FLASH_BANK(Banks));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param Level: specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_RDP_LEVEL_0: No protection
|
||||
* @arg OB_RDP_LEVEL_1: Read protection of the memory
|
||||
* @arg OB_RDP_LEVEL_2: Full chip protection
|
||||
*
|
||||
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(Level));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
*(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
|
||||
* @param Iwdg: Selects the IWDG mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_IWDG_SW: Software IWDG selected
|
||||
* @arg OB_IWDG_HW: Hardware IWDG selected
|
||||
* @param Stop: Reset event when entering STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_STOP_NO_RST: No reset generated when entering in STOP
|
||||
* @arg OB_STOP_RST: Reset generated when entering in STOP
|
||||
* @param Stdby: Reset event when entering Standby mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
|
||||
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
|
||||
{
|
||||
uint8_t optiontmp = 0xFFU;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE(Iwdg));
|
||||
assert_param(IS_OB_STOP_SOURCE(Stop));
|
||||
assert_param(IS_OB_STDBY_SOURCE(Stdby));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
|
||||
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
|
||||
|
||||
/* Update User Option Byte */
|
||||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the BOR Level.
|
||||
* @param Level: specifies the Option Bytes BOR Reset Level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
|
||||
* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
|
||||
* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
|
||||
* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_BOR_LEVEL(Level));
|
||||
|
||||
/* Set the BOR Level */
|
||||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
|
||||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
|
||||
* and RST_STDBY(Bit2).
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return ((uint8_t)(FLASH->OPTCR & 0xE0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @retval uint16_t FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint16_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @retval FLASH ReadOut Protection Status:
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OB_RDP_LEVEL_0: No protection
|
||||
* @arg OB_RDP_LEVEL_1: Read protection of the memory
|
||||
* @arg OB_RDP_LEVEL_2: Full chip protection
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetRDP(void)
|
||||
{
|
||||
uint8_t readstatus = OB_RDP_LEVEL_0;
|
||||
|
||||
if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
|
||||
{
|
||||
readstatus = OB_RDP_LEVEL_2;
|
||||
}
|
||||
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
|
||||
{
|
||||
readstatus = OB_RDP_LEVEL_1;
|
||||
}
|
||||
else
|
||||
{
|
||||
readstatus = OB_RDP_LEVEL_0;
|
||||
}
|
||||
|
||||
return readstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH BOR level.
|
||||
* @retval uint8_t The FLASH BOR level:
|
||||
* - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
|
||||
* - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
|
||||
* - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
|
||||
* - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetBOR(void)
|
||||
{
|
||||
/* Return the FLASH BOR level */
|
||||
return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of FLASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_FLASH_EX_H
|
||||
#define __STM32F2xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or sector Erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
|
||||
This parameter must be a value of @ref FLASHEx_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
|
||||
This parameter must be a value of @ref FLASHEx_Voltage_Range */
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Type */
|
||||
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_WRP_State */
|
||||
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
|
||||
The value of this parameter depend on device used within the same series */
|
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t RDPLevel; /*!< Set the read protection level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
|
||||
|
||||
uint32_t BORLevel; /*!< Set the BOR Level.
|
||||
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
|
||||
|
||||
uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
|
||||
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
|
||||
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
|
||||
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
|
||||
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
|
||||
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
|
||||
it s no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x20U) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint8_t)0x40U) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint8_t)0x80U) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL3 ((uint8_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
|
||||
#define OB_BOR_LEVEL2 ((uint8_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
|
||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
|
||||
#define OB_BOR_OFF ((uint8_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 ((uint32_t)1U) /*!< Bank 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
|
||||
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
|
||||
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
|
||||
#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
|
||||
#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
|
||||
#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
|
||||
#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U) /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020U) /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040U) /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080U) /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100U) /*!< Write protection of Sector8 */
|
||||
#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200U) /*!< Write protection of Sector9 */
|
||||
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400U) /*!< Write protection of Sector10 */
|
||||
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800U) /*!< Write protection of Sector11 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension Program operation functions *************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_SECTOR_TOTAL 12U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_4))
|
||||
|
||||
#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
|
||||
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
|
||||
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || \
|
||||
((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || \
|
||||
((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || \
|
||||
((LATENCY) == FLASH_LATENCY_7))
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
|
||||
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
|
||||
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
|
||||
|
||||
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
|
||||
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
||||
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
|
||||
void FLASH_FlushCaches(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,541 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
|
||||
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
|
||||
in several modes:
|
||||
(+) Input mode
|
||||
(+) Analog mode
|
||||
(+) Output mode
|
||||
(+) Alternate function mode
|
||||
(+) External interrupt/event lines
|
||||
|
||||
[..]
|
||||
During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
[..]
|
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
[..]
|
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
[..]
|
||||
All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
[..]
|
||||
The external interrupt/event controller consists of up to 23 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE ((uint32_t)0x00000003U)
|
||||
#define EXTI_MODE ((uint32_t)0x10000000U)
|
||||
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
|
||||
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
|
||||
#define RISING_EDGE ((uint32_t)0x00100000U)
|
||||
#define FALLING_EDGE ((uint32_t)0x00200000U)
|
||||
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
|
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize and de-initialize the GPIOs
|
||||
to be ready for use.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00U;
|
||||
uint32_t iocurrent = 0x00U;
|
||||
uint32_t temp = 0x00U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
for(position = 0U; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01U) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
||||
|
||||
if(iocurrent == ioposition)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameter */
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3U];
|
||||
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
|
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
|
||||
GPIOx->AFR[position >> 3U] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
||||
temp |= (GPIO_Init->Speed << (position * 2U));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2U];
|
||||
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03)));
|
||||
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
||||
SYSCFG->EXTICR[position >> 2U] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00U;
|
||||
uint32_t iocurrent = 0x00U;
|
||||
uint32_t tmp = 0x00U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
|
||||
/* Configure the port pins */
|
||||
for(position = 0U; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01U) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (GPIO_Pin) & ioposition;
|
||||
|
||||
if(iocurrent == ioposition)
|
||||
{
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floating Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
tmp = SYSCFG->EXTICR[position >> 2U];
|
||||
tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
|
||||
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
|
||||
{
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
|
||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for all STM32F2XX devices
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if(PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_GPIO_H
|
||||
#define __STM32F2xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< IO works at 2 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f2xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_GPIO_EX_H
|
||||
#define __STM32F2xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FSMC ((uint8_t)0xCU) /* FSMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U :\
|
||||
((__GPIOx__) == (GPIOI))? 8U : 9U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
|
||||
((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
|
||||
#else /* STM32F207xx || STM32F217xx */
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
|
||||
((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
|
||||
((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,432 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_HASH_H
|
||||
#define __STM32F2xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH
|
||||
* @brief HASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref HASH_Data_Type */
|
||||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation */
|
||||
}HASH_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
|
||||
HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
|
||||
HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
|
||||
HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
|
||||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in processing phase */
|
||||
}HAL_HASH_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
HASH_InitTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
__IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
|
||||
|
||||
__IO uint32_t HashInCount; /*!< Counter of input data */
|
||||
|
||||
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< HASH locking object */
|
||||
|
||||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
|
||||
} HASH_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */
|
||||
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */
|
||||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type HASH Data Type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */
|
||||
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
|
||||
* @brief HASH HMAC Long key used only for HMAC mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */
|
||||
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
|
||||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
|
||||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset HASH handle state
|
||||
* @param __HANDLE__: specifies the HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
|
||||
|
||||
/** @brief Check whether the specified HASH flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
|
||||
* @arg HASH_FLAG_DCIS: Digest calculation complete
|
||||
* @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
|
||||
* @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
|
||||
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)))
|
||||
/**
|
||||
* @brief Start the digest computation
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
|
||||
|
||||
/**
|
||||
* @brief Set the number of valid bits in last word written in Data register
|
||||
* @param SIZE: size in byte of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
|
||||
HASH->STR |= 8U * ((SIZE) % 4U);\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Functions HASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group8
|
||||
* @{
|
||||
*/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Types HASH Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Variables HASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Constants HASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
|
||||
((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
|
||||
|
||||
|
||||
#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
|
||||
((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
|
||||
|
||||
|
||||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_16B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_8B) || \
|
||||
((__DATATYPE__) == HASH_DATATYPE_1B))
|
||||
|
||||
|
||||
#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
|
||||
((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
|
||||
|
||||
#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4U) != 0U)? 0U: 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Functions HASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F215xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_HASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,264 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_HCD_H
|
||||
#define __STM32F2xx_HAL_HCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_usb.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_STATE_RESET = 0x00U,
|
||||
HAL_HCD_STATE_READY = 0x01U,
|
||||
HAL_HCD_STATE_ERROR = 0x02U,
|
||||
HAL_HCD_STATE_BUSY = 0x03U,
|
||||
HAL_HCD_STATE_TIMEOUT = 0x04U
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
|
||||
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
|
||||
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HCD_TypeDef *Instance; /*!< Register base address */
|
||||
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
|
||||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||
void *pData; /*!< Pointer Stack Handler */
|
||||
} HCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_HIGH 0U
|
||||
#define HCD_SPEED_LOW 2U
|
||||
#define HCD_SPEED_FULL 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define HCD_PHY_ULPI 1U
|
||||
#define HCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
|
||||
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t pipe,
|
||||
uint8_t direction,
|
||||
uint8_t ep_type,
|
||||
uint8_t token,
|
||||
uint8_t* pbuff,
|
||||
uint16_t length,
|
||||
uint8_t do_ping);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup HCD_Instance_definition HCD Instance definition
|
||||
* @{
|
||||
*/
|
||||
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
||||
((INSTANCE) == USB_OTG_HS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_HCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,648 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_I2C_H
|
||||
#define __STM32F2xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
* x : Should be set to 0
|
||||
* b3
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||
* 1 : Listen (IP in Address Listen Mode)
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
}HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6
|
||||
* 0 : None
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)
|
||||
* b5
|
||||
* 0 : None
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)
|
||||
* b4
|
||||
* 0 : None
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)
|
||||
* b3-b2-b1-b0 (not used)
|
||||
* xxxx : Should be set to 0000
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
}HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2C handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
||||
context for internal usage */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
|
||||
|
||||
__IO uint32_t EventCount; /*!< I2C Event counter */
|
||||
|
||||
}I2C_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code I2C Error Code
|
||||
* @brief I2C Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
|
||||
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
|
||||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_addressing_mode I2C addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
|
||||
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
|
||||
#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
|
||||
#define I2C_LAST_FRAME ((uint32_t)0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_BUF I2C_CR2_ITBUFEN
|
||||
#define I2C_IT_EVT I2C_CR2_ITEVTEN
|
||||
#define I2C_IT_ERR I2C_CR2_ITERREN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
|
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x00011000U)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x00010800U)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x00010400U)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x00010200U)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x00010100U)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x00010080U)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x00010040U)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x00010010U)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x00010004U)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x00010002U)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x00010001U)
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00100080U)
|
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
|
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00100004U)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00100002U)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00100001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified I2C interrupts.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @arg I2C_FLAG_TXE: Data register empty flag
|
||||
* @arg I2C_FLAG_RXNE: Data register not empty flag
|
||||
* @arg I2C_FLAG_STOPF: Stop detection flag
|
||||
* @arg I2C_FLAG_ADD10: 10-bit header sent flag
|
||||
* @arg I2C_FLAG_BTF: Byte transfer finished flag
|
||||
* @arg I2C_FLAG_ADDR: Address sent flag
|
||||
* Address matched flag
|
||||
* @arg I2C_FLAG_SB: Start bit flag
|
||||
* @arg I2C_FLAG_DUALF: Dual flag
|
||||
* @arg I2C_FLAG_SMBHOST: SMBus host header
|
||||
* @arg I2C_FLAG_SMBDEFAULT: SMBus default header
|
||||
* @arg I2C_FLAG_GENCALL: General call header flag
|
||||
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
|
||||
* @arg I2C_FLAG_BUSY: Bus busy flag
|
||||
* @arg I2C_FLAG_MSL: Master/Slave flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
|
||||
|
||||
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||||
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||||
* @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
|
||||
|
||||
/** @brief Clears the I2C ADDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_addr = 0x00U; \
|
||||
tmpreg_addr = (__HANDLE__)->Instance->SR1; \
|
||||
tmpreg_addr = (__HANDLE__)->Instance->SR2; \
|
||||
UNUSED(tmpreg_addr); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clears the I2C STOPF pending flag.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_stop = 0x00U; \
|
||||
tmpreg_stop = (__HANDLE__)->Instance->SR1; \
|
||||
(__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
|
||||
UNUSED(tmpreg_stop); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the I2C peripheral.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
|
||||
|
||||
/** @brief Disable the I2C peripheral.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions *****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Errors functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
|
||||
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
|
||||
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
|
||||
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
|
||||
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
|
||||
|
||||
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
|
||||
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
|
||||
|
||||
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF0U))))
|
||||
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF1U))))
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
|
||||
((CYCLE) == I2C_DUTYCYCLE_16_9))
|
||||
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,480 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_I2S_H
|
||||
#define __STM32F2xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
|
||||
This parameter can be a value of @ref I2S_Clock_Source */
|
||||
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
|
||||
|
||||
}HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SPI_TypeDef *Instance; /* I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /* I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /* I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /* I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* I2S Rx transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /* I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* I2S Error code */
|
||||
|
||||
}I2S_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Error_Code I2S Error Code
|
||||
* @brief I2S Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U) /*!< I2S Underrun error */
|
||||
#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< I2S Overrun error */
|
||||
#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U) /*!< I2S extended Underrun error */
|
||||
#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U) /*!< I2S extended Overrun error */
|
||||
#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U) /*!< I2S Frame format error */
|
||||
#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Source I2S Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CLOCK_PLL ((uint32_t)0x00000000U)
|
||||
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
|
||||
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
|
||||
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
|
||||
#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
|
||||
#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
|
||||
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
|
||||
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
|
||||
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
|
||||
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S Mclk Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
|
||||
#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
|
||||
#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
|
||||
#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
|
||||
#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
|
||||
#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
|
||||
#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
|
||||
#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
|
||||
#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
|
||||
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2S interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr ); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_udr = 0x00U; \
|
||||
tmpreg_udr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_udr); \
|
||||
} while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions *****************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Peripheral Control and State functions **************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
|
||||
((CLOCK) == I2S_CLOCK_PLL))
|
||||
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||
((MODE) == I2S_MODE_MASTER_TX) || \
|
||||
((MODE) == I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
|
||||
((STANDARD) == I2S_STANDARD_MSB) || \
|
||||
((STANDARD) == I2S_STANDARD_LSB) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_24B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||
((CPOL) == I2S_CPOL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Functions I2S Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_I2S_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,594 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_IRDA_H
|
||||
#define __STM32F2xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDA_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler */
|
||||
|
||||
uint32_t IrDAMode; /*!< Specifies the IrDA mode
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
}IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State structures definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
}HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /* IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /* IRDA Error code */
|
||||
|
||||
}IRDA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IRDA_Error_Code IRDA Error Code
|
||||
* @brief IRDA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE ((uint32_t)0x00000000U)
|
||||
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
|
||||
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
|
||||
#define IRDA_FLAG_TC ((uint32_t)0x00000040U)
|
||||
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
|
||||
#define IRDA_FLAG_IDLE ((uint32_t)0x00000010U)
|
||||
#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
|
||||
#define IRDA_FLAG_NE ((uint32_t)0x00000004U)
|
||||
#define IRDA_FLAG_FE ((uint32_t)0x00000002U)
|
||||
#define IRDA_FLAG_PE ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask in the XX register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
|
||||
#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
|
||||
|
||||
#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
|
||||
#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle gstate & RxState
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0)
|
||||
|
||||
/** @brief Flushs the IRDA DR register
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||
|
||||
/** @brief Checks whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the specified IRDA pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag.
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_SR register followed by a read
|
||||
* operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_pe = 0x00U; \
|
||||
tmpreg_pe = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_pe); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enables or disables the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* UART peripheral.
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_ERR: Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
|
||||
|
||||
/** @brief Macro to enable the IRDA's one bit sample method
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Macro to disable the IRDA's one bit sample method
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Constants IRDA Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief IRDA interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
|
||||
|
||||
#define IRDA_CR1_REG_INDEX 1U
|
||||
#define IRDA_CR2_REG_INDEX 2U
|
||||
#define IRDA_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Macros IRDA Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
|
||||
((PARITY) == IRDA_PARITY_EVEN) || \
|
||||
((PARITY) == IRDA_PARITY_ODD))
|
||||
#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))
|
||||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
|
||||
|
||||
#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
|
||||
#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
|
||||
#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Functions IRDA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and Start functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM5 CH4 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts downcounting.
|
||||
(+) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
|
||||
(+) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(+) wait for status flags to be reset"
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver:
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||
the reload register
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to HSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Start functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters in the
|
||||
IWDG_InitTypeDef of associated handle.
|
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||
is reloaded in order to exit function with correct time base.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified parameters in the
|
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||
* watchdog is refreshed in order to have correct time base.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if(hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
|
||||
/* Enable IWDG. LSI is turned on automaticaly */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||
|
||||
/* Check pending flag, if previous update not done, return timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while(hiwdg->Instance->SR != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_IWDG_H
|
||||
#define __STM32F2xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
}IWDG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR & IWDG_RLR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,305 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_NAND_H
|
||||
#define __STM32F2xx_HAL_NAND_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_fsmc.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Types NAND Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL NAND State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
|
||||
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
|
||||
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
|
||||
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
|
||||
}HAL_NAND_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory electronic signature Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*<! NAND memory electronic signature maker and device IDs */
|
||||
|
||||
uint8_t Maker_Id;
|
||||
|
||||
uint8_t Device_Id;
|
||||
|
||||
uint8_t Third_Id;
|
||||
|
||||
uint8_t Fourth_Id;
|
||||
}NAND_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory address Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Page; /*!< NAND memory Page address */
|
||||
|
||||
uint16_t Zone; /*!< NAND memory Zone address */
|
||||
|
||||
uint16_t Block; /*!< NAND memory Block address */
|
||||
|
||||
}NAND_AddressTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size number of pages */
|
||||
|
||||
uint32_t BlockNbr; /*!< NAND memory number of blocks */
|
||||
|
||||
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
}NAND_InfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NAND locking object */
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
|
||||
}NAND_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset NAND handle state
|
||||
* @param __HANDLE__: specifies the NAND handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NAND Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define NAND_DEVICE1 ((uint32_t)0x70000000U)
|
||||
#define NAND_DEVICE2 ((uint32_t)0x80000000U)
|
||||
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
|
||||
|
||||
#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
|
||||
#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
|
||||
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
|
||||
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90U)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70U)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFFU)
|
||||
|
||||
/* NAND memory status */
|
||||
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
|
||||
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
|
||||
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
|
||||
#define NAND_BUSY ((uint32_t)0x00000000U)
|
||||
#define NAND_ERROR ((uint32_t)0x00000001U)
|
||||
#define NAND_READY ((uint32_t)0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Macros NAND Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NAND memory address computation.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @param __HANDLE__ : NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
|
||||
|
||||
/**
|
||||
* @brief NAND memory address cycling.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @retval NAND address cycling value.
|
||||
*/
|
||||
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
|
||||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
|
||||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
|
||||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_NAND_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,296 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_NOR_H
|
||||
#define __STM32F2xx_HAL_NOR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_fsmc.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Types NOR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
|
||||
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
|
||||
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
|
||||
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
|
||||
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
|
||||
}HAL_NOR_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR Status typedef
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATUS_SUCCESS = 0U,
|
||||
HAL_NOR_STATUS_ONGOING,
|
||||
HAL_NOR_STATUS_ERROR,
|
||||
HAL_NOR_STATUS_TIMEOUT
|
||||
}HAL_NOR_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR ID typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
|
||||
|
||||
uint16_t Device_Code1;
|
||||
|
||||
uint16_t Device_Code2;
|
||||
|
||||
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
||||
These codes can be accessed by performing read operations with specific
|
||||
control signals and addresses set.They can also be accessed by issuing
|
||||
an Auto Select command */
|
||||
}NOR_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR CFI typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!< Defines the information stored in the memory's Common flash interface
|
||||
which contains a description of various electrical and timing parameters,
|
||||
density information and functions supported by the memory */
|
||||
|
||||
uint16_t CFI_1;
|
||||
|
||||
uint16_t CFI_2;
|
||||
|
||||
uint16_t CFI_3;
|
||||
|
||||
uint16_t CFI_4;
|
||||
}NOR_CFITypeDef;
|
||||
|
||||
/**
|
||||
* @brief NOR handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NOR locking object */
|
||||
|
||||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||
|
||||
}NOR_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Macros NOR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset NOR handle state
|
||||
* @param __HANDLE__: specifies the NOR handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
|
||||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR Control functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Constants NOR Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* NOR device IDs addresses */
|
||||
#define MC_ADDRESS ((uint16_t)0x0000U)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
|
||||
|
||||
/* NOR CFI IDs addresses */
|
||||
#define CFI1_ADDRESS ((uint16_t)0x61U)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x62U)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x63U)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x64U)
|
||||
|
||||
/* NOR operation wait timeout */
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
|
||||
|
||||
/* NOR memory data width */
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x0U)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x1U)
|
||||
|
||||
/* NOR memory device read/write start address */
|
||||
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Macros NOR Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief NOR memory address shifting.
|
||||
* @param __NOR_ADDRESS__: NOR base address
|
||||
* @param __NOR_MEMORY_WIDTH__: NOR memory width
|
||||
* @param __ADDRESS__: NOR memory address
|
||||
* @retval NOR shifted address value
|
||||
*/
|
||||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, __NOR_MEMORY_WIDTH__, __ADDRESS__) \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH__) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)((__NOR_ADDRESS__) + (2U * (__ADDRESS__)))): \
|
||||
((uint32_t)((__NOR_ADDRESS__) + (__ADDRESS__)))))
|
||||
|
||||
/**
|
||||
* @brief NOR memory write data to specified address.
|
||||
* @param __ADDRESS__: NOR memory address
|
||||
* @param __DATA__: Data to write
|
||||
* @retval None
|
||||
*/
|
||||
#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_NOR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,747 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pccard.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief PCCARD HAL module driver.
|
||||
* This file provides a generic firmware to drive PCCARD memories mounted
|
||||
* as external device.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control PCCARD/compact flash memories. It uses the FSMC layer functions
|
||||
to interface with PCCARD devices. This driver is used for:
|
||||
|
||||
(+) PCCARD/Compact Flash memory configuration sequence using the function
|
||||
HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
|
||||
both common and attribute spaces.
|
||||
|
||||
(+) Read PCCARD/Compact Flash memory maker and device IDs using the function
|
||||
HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
|
||||
the CompactFlash_ID structure declared by the function caller.
|
||||
|
||||
(+) Access PCCARD/Compact Flash memory by read/write operations using the functions
|
||||
HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
|
||||
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
|
||||
|
||||
(+) Perform PCCARD/Compact Flash Reset chip operation using the function
|
||||
HAL_PCCARD_Reset()/HAL_CF_Reset.
|
||||
|
||||
(+) Perform PCCARD/Compact Flash erase sector operation using the function
|
||||
HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
|
||||
|
||||
(+) Read the PCCARD/Compact Flash status operation using the function
|
||||
HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
|
||||
|
||||
(+) You can monitor the PCCARD/Compact Flash device HAL state by calling
|
||||
the function HAL_PCCARD_GetState()/HAL_CF_GetState()
|
||||
|
||||
[..]
|
||||
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
|
||||
operations. If a PCCARD/Compact Flash device contains different operations
|
||||
and/or implementations, it should be implemented separately.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
/** @defgroup PCCARD PCCARD
|
||||
* @brief PCCARD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
|
||||
* @{
|
||||
*/
|
||||
#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFFU
|
||||
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFFU
|
||||
#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400U
|
||||
#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000U
|
||||
|
||||
#define PCCARD_STATUS_OK (uint8_t)0x58U
|
||||
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function ----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize/de-initialize
|
||||
the PCCARD memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Perform the PCCARD memory Initialization sequence
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param ComSpaceTiming: Common space timing structure
|
||||
* @param AttSpaceTiming: Attribute space timing structure
|
||||
* @param IOSpaceTiming: IO space timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
|
||||
{
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hpccard->Lock = HAL_UNLOCKED;
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_PCCARD_MspInit(hpccard);
|
||||
}
|
||||
|
||||
/* Initialize the PCCARD state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize PCCARD control Interface */
|
||||
FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
|
||||
|
||||
/* Init PCCARD common space timing Interface */
|
||||
FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
|
||||
|
||||
/* Init PCCARD attribute space timing Interface */
|
||||
FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
|
||||
|
||||
/* Init PCCARD IO space timing Interface */
|
||||
FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
|
||||
|
||||
/* Enable the PCCARD device */
|
||||
__FSMC_PCCARD_ENABLE(hpccard->Instance);
|
||||
|
||||
/* Update the PCCARD state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform the PCCARD memory De-initialization sequence
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* De-Initialize the low level hardware (MSP) */
|
||||
HAL_PCCARD_MspDeInit(hpccard);
|
||||
|
||||
/* Configure the PCCARD registers with their reset values */
|
||||
FSMC_PCCARD_DeInit(hpccard->Instance);
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD MSP Init
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpccard);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD MSP DeInit
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpccard);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the PCCARD memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Compact Flash's ID.
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param CompactFlash_ID: Compact flash ID structure.
|
||||
* @param pStatus: pointer to compact flash status
|
||||
* @retval HAL status
|
||||
*
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
|
||||
uint8_t status = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
|
||||
|
||||
/* Initialize the PCCARD status */
|
||||
*pStatus = PCCARD_READY;
|
||||
|
||||
/* Send the Identify Command */
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU;
|
||||
|
||||
/* Read PCCARD IDs and timeout treatment */
|
||||
do
|
||||
{
|
||||
/* Read the PCCARD status */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
|
||||
timeout--;
|
||||
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if(timeout == 0U)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read PCCARD ID bytes */
|
||||
for(index = 0U; index < 16U; index++)
|
||||
{
|
||||
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
|
||||
}
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read sector from PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param pBuffer: pointer to destination read buffer
|
||||
* @param SectorAddress: Sector address to read
|
||||
* @param pStatus: pointer to PCCARD status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
|
||||
uint8_t status = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize PCCARD status */
|
||||
*pStatus = PCCARD_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0U;
|
||||
|
||||
do
|
||||
{
|
||||
/* wait till the Status = 0x80 */
|
||||
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status == 0x80U) && timeout);
|
||||
|
||||
if(timeout == 0U)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
|
||||
|
||||
do
|
||||
{
|
||||
/* wait till the Status = PCCARD_STATUS_OK */
|
||||
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if(timeout == 0U)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Read bytes */
|
||||
for(; index < PCCARD_SECTOR_SIZE; index++)
|
||||
{
|
||||
*(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write sector to PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param pBuffer: pointer to source write buffer
|
||||
* @param SectorAddress: Sector address to write
|
||||
* @param pStatus: pointer to PCCARD status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
|
||||
uint8_t status = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize PCCARD status */
|
||||
*pStatus = PCCARD_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
|
||||
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0U;
|
||||
|
||||
do
|
||||
{
|
||||
/* Wait till the Status = PCCARD_STATUS_OK */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||
|
||||
if(timeout == 0U)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Write bytes */
|
||||
for(; index < PCCARD_SECTOR_SIZE; index++)
|
||||
{
|
||||
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
|
||||
|
||||
if(timeout == 0U)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Erase sector from PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @param SectorAddress: Sector address to erase
|
||||
* @param pStatus: pointer to PCCARD status
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
|
||||
uint8_t status = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Update the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
/* Initialize PCCARD status */
|
||||
*pStatus = PCCARD_READY;
|
||||
|
||||
/* Set the parameters to write a sector */
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00U;
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00U;
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01U;
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0U;
|
||||
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
|
||||
|
||||
/* wait till the PCCARD is ready */
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
|
||||
while((status != PCCARD_STATUS_WRITE_OK) && timeout)
|
||||
{
|
||||
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the PCCARD memory
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hpccard);
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Provide a SW reset and Read and verify the:
|
||||
- PCCard Configuration Option Register at address 0x98000200 --> 0x80
|
||||
- Card Configuration and Status Register at address 0x98000202 --> 0x00
|
||||
- Pin Replacement Register at address 0x98000204 --> 0x0C
|
||||
- Socket and Copy Register at address 0x98000206 --> 0x00
|
||||
*/
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||
|
||||
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01U;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hpccard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PCCARD device interrupt request.
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Check PCCARD interrupt Rising edge flag */
|
||||
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Rising edge pending bit */
|
||||
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt Level flag */
|
||||
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Level pending bit */
|
||||
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt Falling edge flag */
|
||||
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt Falling edge pending bit */
|
||||
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
|
||||
}
|
||||
|
||||
/* Check PCCARD interrupt FIFO empty flag */
|
||||
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
|
||||
{
|
||||
/* PCCARD interrupt callback*/
|
||||
HAL_PCCARD_ITCallback(hpccard);
|
||||
|
||||
/* Clear PCCARD interrupt FIFO empty pending bit */
|
||||
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PCCARD interrupt feature callback
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpccard);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PCCARD_ITCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PCCARD State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the PCCARD controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief return the PCCARD controller state
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
return hpccard->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the compact flash memory status
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval New status of the PCCARD operation. This parameter can be:
|
||||
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
|
||||
* a Timeout error
|
||||
* - CompactFlash_READY: when memory is ready for the next operation
|
||||
*/
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_PCCARD_STATUS_ONGOING;
|
||||
}
|
||||
|
||||
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
|
||||
while((status_pccard == PCCARD_BUSY) && timeout)
|
||||
{
|
||||
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if(timeout == 0)
|
||||
{
|
||||
status_pccard = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
|
||||
/* Return the operation status */
|
||||
return (HAL_PCCARD_StatusTypeDef) status_pccard;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the Compact Flash memory status using the Read status command
|
||||
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for PCCARD module.
|
||||
* @retval The status of the Compact Flash memory. This parameter can be:
|
||||
* - CompactFlash_BUSY: when memory is busy
|
||||
* - CompactFlash_READY: when memory is ready for the next operation
|
||||
* - CompactFlash_ERROR: when the previous operation generates error
|
||||
*/
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
|
||||
{
|
||||
uint8_t data = 0, status_pccard = PCCARD_BUSY;
|
||||
|
||||
/* Check the PCCARD controller state */
|
||||
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||
{
|
||||
return HAL_PCCARD_STATUS_ONGOING;
|
||||
}
|
||||
|
||||
/* Read status operation */
|
||||
data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||
|
||||
if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
|
||||
{
|
||||
status_pccard = PCCARD_TIMEOUT_ERROR;
|
||||
}
|
||||
else if((data & PCCARD_READY) == PCCARD_READY)
|
||||
{
|
||||
status_pccard = PCCARD_READY;
|
||||
}
|
||||
|
||||
return (HAL_PCCARD_StatusTypeDef) status_pccard;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pccard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of PCCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_PCCARD_H
|
||||
#define __STM32F2xx_HAL_PCCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PCCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL PCCARD State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
|
||||
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
|
||||
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
|
||||
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
|
||||
}HAL_PCCARD_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCCARD_STATUS_SUCCESS = 0U,
|
||||
HAL_PCCARD_STATUS_ONGOING,
|
||||
HAL_PCCARD_STATUS_ERROR,
|
||||
HAL_PCCARD_STATUS_TIMEOUT
|
||||
}HAL_PCCARD_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC_PCCARD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
|
||||
|
||||
FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
|
||||
|
||||
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
|
||||
|
||||
}PCCARD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset PCCARD handle state
|
||||
* @param __HANDLE__: specifies the PCCARD handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCCARD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
|
||||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* PCCARD State functions *******************************************************/
|
||||
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define PCCARD_DEVICE_ADDRESS ((uint32_t)0x90000000U)
|
||||
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000U) /* Attribute space size to @0x9BFF FFFF */
|
||||
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
|
||||
#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)0x9C000000U) /* IO space size to @0x9FFF FFFF */
|
||||
#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0U) /* IO space size to @0x9FFF FFFF */
|
||||
|
||||
/* Flash-ATA registers description */
|
||||
#define ATA_DATA ((uint8_t)0x00U) /* Data register */
|
||||
#define ATA_SECTOR_COUNT ((uint8_t)0x02U) /* Sector Count register */
|
||||
#define ATA_SECTOR_NUMBER ((uint8_t)0x03U) /* Sector Number register */
|
||||
#define ATA_CYLINDER_LOW ((uint8_t)0x04U) /* Cylinder low register */
|
||||
#define ATA_CYLINDER_HIGH ((uint8_t)0x05U) /* Cylinder high register */
|
||||
#define ATA_CARD_HEAD ((uint8_t)0x06U) /* Card/Head register */
|
||||
#define ATA_STATUS_CMD ((uint8_t)0x07U) /* Status(read)/Command(write) register */
|
||||
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0EU) /* Alternate Status(read)/Command(write) register */
|
||||
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
|
||||
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202U) /* Card Configuration and Status Register */
|
||||
|
||||
/* Flash-ATA commands */
|
||||
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20U)
|
||||
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30U)
|
||||
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0U)
|
||||
#define ATA_IDENTIFY_CMD ((uint8_t)0xECU)
|
||||
|
||||
/* PC Card/Compact Flash status */
|
||||
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60U)
|
||||
#define PCCARD_BUSY ((uint8_t)0x80U)
|
||||
#define PCCARD_PROGR ((uint8_t)0x01U)
|
||||
#define PCCARD_READY ((uint8_t)0x40U)
|
||||
|
||||
#define PCCARD_SECTOR_SIZE ((uint32_t)255U) /* In half words */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Compact Flash redefinition */
|
||||
#define HAL_CF_Init HAL_PCCARD_Init
|
||||
#define HAL_CF_DeInit HAL_PCCARD_DeInit
|
||||
#define HAL_CF_MspInit HAL_PCCARD_MspInit
|
||||
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
|
||||
|
||||
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
|
||||
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
|
||||
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
|
||||
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
|
||||
#define HAL_CF_Reset HAL_PCCARD_Reset
|
||||
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
|
||||
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
|
||||
|
||||
#define HAL_CF_GetState HAL_PCCARD_GetState
|
||||
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
|
||||
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
|
||||
|
||||
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
|
||||
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
|
||||
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
|
||||
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
|
||||
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
|
||||
|
||||
|
||||
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
|
||||
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
|
||||
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
|
||||
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
|
||||
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
|
||||
|
||||
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
|
||||
#define CF_BUSY PCCARD_BUSY
|
||||
#define CF_PROGR PCCARD_PROGR
|
||||
#define CF_READY PCCARD_READY
|
||||
|
||||
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_PCCARD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,323 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_PCD_H
|
||||
#define __STM32F2xx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_usb.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00U,
|
||||
HAL_PCD_STATE_READY = 0x01U,
|
||||
HAL_PCD_STATE_ERROR = 0x02U,
|
||||
HAL_PCD_STATE_BUSY = 0x03U,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04U
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PCD HAL Extension module */
|
||||
#include "stm32f2xx_hal_pcd_ex.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_HIGH 0U
|
||||
#define PCD_SPEED_HIGH_IN_FULL 1U
|
||||
#define PCD_SPEED_FULL 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
|
||||
* @{
|
||||
*/
|
||||
#ifndef USBD_HS_TRDT_VALUE
|
||||
#define USBD_HS_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
#ifndef USBD_FS_TRDT_VALUE
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#endif /* USBD_FS_TRDT_VALUE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
|
||||
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
|
||||
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
|
||||
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
||||
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
||||
}while(0);
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
||||
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup PCD_Instance_definition PCD Instance definition
|
||||
* @{
|
||||
*/
|
||||
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
||||
((INSTANCE) == USB_OTG_HS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_PCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx PCDEx
|
||||
* @brief PCD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Update FIFO configuration
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set Tx FIFO
|
||||
* @param hpcd: PCD handle
|
||||
* @param fifo: The number of Tx fifo
|
||||
* @param size: Fifo size
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
||||
{
|
||||
uint8_t i = 0U;
|
||||
uint32_t Tx_Offset = 0U;
|
||||
|
||||
/* TXn min size = 16 words. (n : Transmit FIFO index)
|
||||
When a TxFIFO is not used, the Configuration should be as follows:
|
||||
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
--> Txm can use the space allocated for Txn.
|
||||
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
--> Txn should be configured with the minimum space of 16 words
|
||||
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
||||
|
||||
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
||||
|
||||
if(fifo == 0U)
|
||||
{
|
||||
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
|
||||
}
|
||||
else
|
||||
{
|
||||
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
|
||||
for (i = 0U; i < (fifo - 1U); i++)
|
||||
{
|
||||
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
|
||||
}
|
||||
|
||||
/* Multiply Tx_Size by 2 to get higher performance */
|
||||
hpcd->Instance->DIEPTXF[fifo - 1U] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Rx FIFO
|
||||
* @param hpcd: PCD handle
|
||||
* @param size: Size of Rx fifo
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
||||
{
|
||||
hpcd->Instance->GRXFSIZ = size;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_PCD_EX_H
|
||||
#define __STM32F2xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_PCD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,571 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT ((uint32_t)0x00010000U)
|
||||
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
|
||||
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
|
||||
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers and backup SRAM) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
*** Wake-up pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
|
||||
forced in input pull-down configuration and is active on rising edges.
|
||||
(+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off.
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
-@@- The Regulator parameter is not used for the STM32F2 family
|
||||
and is kept as parameter just to maintain compatibility with the
|
||||
lower power families (STM32L).
|
||||
(+) Exit:
|
||||
Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption In Stop mode, FLASH can be powered off before
|
||||
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
|
||||
It can be switched on again by software after exiting the Stop mode using
|
||||
the HAL_PWREx_DisableFlashPowerDown() function.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(+) Exit:
|
||||
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
(+)
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M3 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||||
circuitry.
|
||||
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(++) Entry:
|
||||
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(++) Exit:
|
||||
(+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wake-up (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
|
||||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wake-up event, a tamper event or a time-stamp event, without depending on
|
||||
an external interrupt (Auto-wake-up mode).
|
||||
|
||||
(+) RTC auto-wake-up (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
|
||||
configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Wake-up PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
|
||||
/* Enable the wake up pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Wake-up PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
|
||||
/* Disable the wake up pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
*
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
*
|
||||
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
|
||||
* systick interrupt when used as time base for Timeout
|
||||
*
|
||||
* @param Regulator: Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @note This parameter is not used for the STM32F2 family and is kept as parameter
|
||||
* just to maintain compatibility with the lower power families.
|
||||
* @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wake-up event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator: Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Standby mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
|
||||
* - WKUP pin 1 (PA0) if enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select Standby mode */
|
||||
SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR Exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M3 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M3 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,443 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_PWR_H
|
||||
#define __STM32F2xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
|
||||
(Compare internally to VREFINT) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_BRR PWR_CSR_BRR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A
|
||||
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* An additional wakeup event is detected if the WKUP pin is enabled
|
||||
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
||||
* when the device wakes up from Standby mode or by a system reset
|
||||
* or power reset.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD Exti flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on PVD EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f2xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* PVD configuration */
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration */
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes entry */
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Power PVD IRQ Handler */
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
/* Cortex System Control functions *******************************************/
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_register_alias_address PWR Register alias address
|
||||
* @{
|
||||
*/
|
||||
/* ------------- PWR registers bit address in the alias region ---------------*/
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
#define PWR_CR_OFFSET 0x00U
|
||||
#define PWR_CSR_OFFSET 0x04U
|
||||
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
|
||||
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
|
||||
* @{
|
||||
*/
|
||||
/* --- CR Register ---*/
|
||||
/* Alias word address of DBP bit */
|
||||
#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
|
||||
#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
|
||||
#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
|
||||
* @{
|
||||
*/
|
||||
/* --- CSR Register ---*/
|
||||
/* Alias word address of EWUP bit */
|
||||
#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
|
||||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of PWR extension peripheral:
|
||||
* + Peripheral Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BKPREG_TIMEOUT_VALUE 1000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
|
||||
* @brief Peripheral Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended features functions #####
|
||||
===============================================================================
|
||||
|
||||
*** Main and Backup Regulators configuration ***
|
||||
================================================
|
||||
[..]
|
||||
(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
|
||||
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
|
||||
retained even in Standby or VBAT mode when the low power backup regulator
|
||||
is enabled. It can be considered as an internal EEPROM when VBAT is
|
||||
always present. You can use the HAL_PWREx_EnableBkUpReg() function to
|
||||
enable the low power backup regulator.
|
||||
|
||||
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
|
||||
the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
||||
save battery life.
|
||||
|
||||
(+) The backup SRAM is not mass erased by a tamper event. It is read
|
||||
protected to prevent confidential data, such as cryptographic private
|
||||
key, from being accessed. The backup SRAM can be erased only through
|
||||
the Flash interface when a protection level change from level 1 to
|
||||
level 0 is requested.
|
||||
-@- Refer to the description of Read protection (RDP) in the Flash
|
||||
programming manual.
|
||||
|
||||
Refer to the product datasheets for more details.
|
||||
|
||||
*** FLASH Power Down configuration ****
|
||||
=======================================
|
||||
[..]
|
||||
(+) By setting the FPDS bit in the PWR_CR register by using the
|
||||
HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
|
||||
down mode when the device enters Stop mode. When the Flash memory
|
||||
is in power down mode, an additional startup delay is incurred when
|
||||
waking up from Stop mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the Backup Regulator.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till Backup regulator ready flag is set */
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Backup Regulator.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till Backup regulator ready flag is set */
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Flash Power Down in Stop mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableFlashPowerDown(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Flash Power Down in Stop mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableFlashPowerDown(void)
|
||||
{
|
||||
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_PWR_EX_H
|
||||
#define __STM32F2xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
void HAL_PWREx_EnableFlashPowerDown(void);
|
||||
void HAL_PWREx_DisableFlashPowerDown(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_register_alias_address PWR Register alias address
|
||||
* @{
|
||||
*/
|
||||
/* ------------- PWR registers bit address in the alias region ---------------*/
|
||||
/* --- CR Register ---*/
|
||||
/* Alias word address of FPDS bit */
|
||||
#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
|
||||
#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_CSR_register_alias PWR CSR Register alias address
|
||||
* @{
|
||||
*/
|
||||
/* --- CSR Register ---*/
|
||||
/* Alias word address of BRE bit */
|
||||
#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
|
||||
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_IS_PWR_Definitions PWR Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F2xx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,251 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Extension RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx RCCEx
|
||||
* @brief RCCEx HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
|
||||
* RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
|
||||
*
|
||||
* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
|
||||
* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
|
||||
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t tmpreg1 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||||
|
||||
/*---------------------------- I2S configuration ---------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))|| \
|
||||
(PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
||||
{
|
||||
/* check for Parameters */
|
||||
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
||||
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
||||
|
||||
/* Disable the PLLI2S */
|
||||
__HAL_RCC_PLLI2S_DISABLE();
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Wait till PLLI2S is disabled */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
||||
{
|
||||
/* return in case of Timeout detected */
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Configure the PLLI2S division factors */
|
||||
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
|
||||
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
||||
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
|
||||
|
||||
/* Enable the PLLI2S */
|
||||
__HAL_RCC_PLLI2S_ENABLE();
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Wait till PLLI2S is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
||||
{
|
||||
/* return in case of Timeout detected */
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------- RTC configuration ---------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
/* Check for RTC Parameters used to output RTCCLK */
|
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
||||
|
||||
/* Enable Power Clock*/
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
||||
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
||||
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = tmpreg1;
|
||||
|
||||
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
||||
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
||||
{
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
}
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the RCC_OscInitStruct according to the internal
|
||||
* RCC configuration registers.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* will be configured.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tempreg;
|
||||
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
|
||||
|
||||
/* Get the PLLI2S Clock configuration --------------------------------------*/
|
||||
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
||||
PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
||||
|
||||
/* Get the RTC Clock configuration -----------------------------------------------*/
|
||||
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
||||
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
||||
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,438 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of RCC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_RCC_EX_H
|
||||
#define __STM32F2xx_HAL_RCC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief PLLI2S Clock structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
|
||||
This parameter must be a number between Min_Data = 192 and Max_Data = 432.
|
||||
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
|
||||
|
||||
uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
|
||||
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
|
||||
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
|
||||
|
||||
}RCC_PLLI2SInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC extended clocks structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
|
||||
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
|
||||
|
||||
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
|
||||
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
|
||||
|
||||
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
|
||||
This parameter can be a value of @ref RCC_RTC_Clock_Source */
|
||||
|
||||
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
|
||||
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
|
||||
|
||||
}RCC_PeriphCLKInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
|
||||
#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
|
||||
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
|
||||
#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
|
||||
#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Macros RCC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
|
||||
* @brief Enables or disables the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
|
||||
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
|
||||
#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
|
||||
#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
|
||||
#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
|
||||
#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
|
||||
#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
|
||||
#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
|
||||
__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
|
||||
__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
|
||||
#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
|
||||
#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
|
||||
#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
|
||||
#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
|
||||
#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
|
||||
__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
|
||||
__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ETHERNET clock.
|
||||
*/
|
||||
#define __HAL_RCC_ETH_CLK_ENABLE() do { \
|
||||
__HAL_RCC_ETHMAC_CLK_ENABLE(); \
|
||||
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
|
||||
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
|
||||
} while(0)
|
||||
/**
|
||||
* @brief Disable ETHERNET clock.
|
||||
*/
|
||||
#define __HAL_RCC_ETH_CLK_DISABLE() do { \
|
||||
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
|
||||
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
|
||||
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
|
||||
} while(0)
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#define __HAL_RCC_HASH_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
|
||||
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
|
||||
#endif /* STM32F215xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the AHB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
|
||||
#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
|
||||
#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
|
||||
#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
|
||||
|
||||
#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
|
||||
#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
|
||||
#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
|
||||
* @brief Force or release AHB1 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
|
||||
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
|
||||
* @brief Force or release AHB2 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
|
||||
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
|
||||
#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
|
||||
|
||||
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
|
||||
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
|
||||
#endif /* STM32F215xx || STM32F217xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
|
||||
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
|
||||
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
|
||||
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
|
||||
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
|
||||
|
||||
#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
|
||||
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
|
||||
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
|
||||
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
|
||||
* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F207xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
|
||||
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
|
||||
#endif /* STM32F207xx || STM32F217xx */
|
||||
|
||||
#if defined(STM32F215xx) || defined(STM32F217xx)
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
|
||||
#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
|
||||
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
|
||||
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
|
||||
#endif /* STM32F215xx || STM32F217xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Constants RCC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
|
||||
* @brief RCC registers bit address in the alias region
|
||||
* @{
|
||||
*/
|
||||
#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Macros RCC Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_RCC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,518 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rng.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief RNG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Random Number Generator (RNG) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The RNG HAL driver can be used as follows:
|
||||
|
||||
(#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
|
||||
in HAL_RNG_MspInit().
|
||||
(#) Activate the RNG peripheral using HAL_RNG_Init() function.
|
||||
(#) Wait until the 32 bit Random Number Generator contains a valid
|
||||
random data using (polling/interrupt) mode.
|
||||
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup RNG_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define RNG_TIMEOUT_VALUE 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the RNG according to the specified parameters
|
||||
in the RNG_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the RNG peripheral
|
||||
(+) Initialize the RNG MSP
|
||||
(+) DeInitialize RNG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG peripheral and creates the associated handle.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG handle allocation */
|
||||
if(hrng == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
if(hrng->State == HAL_RNG_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hrng->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_RNG_MspInit(hrng);
|
||||
}
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Enable the RNG Peripheral */
|
||||
__HAL_RNG_ENABLE(hrng);
|
||||
|
||||
/* Initialize the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG peripheral.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG handle allocation */
|
||||
if(hrng == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Disable the RNG Peripheral */
|
||||
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
|
||||
|
||||
/* Clear RNG interrupt status flags */
|
||||
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_RNG_MspDeInit(hrng);
|
||||
|
||||
/* Update the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return the function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG MSP.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_MspInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG MSP.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_MspDeInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group2
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Get the 32 bit Random number
|
||||
(+) Get the 32 bit Random number with interrupt enabled
|
||||
(+) Handle RNG interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generates a 32-bit random number.
|
||||
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
|
||||
* is automatically cleared.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @param random32bit: pointer to generated random number variable if successful.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Check RNG peripheral state */
|
||||
if(hrng->State == HAL_RNG_STATE_READY)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if data register contains valid random data */
|
||||
while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
|
||||
{
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get a 32bit Random number */
|
||||
hrng->RandomNumber = hrng->Instance->DR;
|
||||
*random32bit = hrng->RandomNumber;
|
||||
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a 32-bit random number in interrupt mode.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Check RNG peripheral state */
|
||||
if(hrng->State == HAL_RNG_STATE_READY)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
|
||||
__HAL_RNG_ENABLE_IT(hrng);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles RNG interrupt request.
|
||||
* @note In the case of a clock error, the RNG is no more able to generate
|
||||
* random numbers because the PLL48CLK clock is not correct. User has
|
||||
* to check that the clock controller is correctly configured to provide
|
||||
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
|
||||
* The clock error has no impact on the previously generated
|
||||
* random numbers, and the RNG_DR register contents can be used.
|
||||
* @note In the case of a seed error, the generation of random numbers is
|
||||
* interrupted as long as the SECS bit is '1'. If a number is
|
||||
* available in the RNG_DR register, it must not be used because it may
|
||||
* not have enough entropy. In this case, it is recommended to clear the
|
||||
* SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
|
||||
* the RNG peripheral to reinitialize and restart the RNG.
|
||||
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
|
||||
* or CEIS are set.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
|
||||
*/
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* RNG clock error interrupt occurred */
|
||||
if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
|
||||
HAL_RNG_ErrorCallback(hrng);
|
||||
|
||||
/* Clear the clock error flag */
|
||||
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
|
||||
|
||||
}
|
||||
|
||||
/* Check RNG data ready interrupt occurred */
|
||||
if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
|
||||
{
|
||||
/* Generate random number once, so disable the IT */
|
||||
__HAL_RNG_DISABLE_IT(hrng);
|
||||
|
||||
/* Get the 32bit Random number (DRDY flag automatically cleared) */
|
||||
hrng->RandomNumber = hrng->Instance->DR;
|
||||
|
||||
if(hrng->State != HAL_RNG_STATE_ERROR)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
|
||||
/* Data Ready callback */
|
||||
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns generated random number in polling mode (Obsolete)
|
||||
* Use HAL_RNG_GenerateRandomNumber() API instead.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval Random value
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
|
||||
{
|
||||
return hrng->RandomNumber;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
|
||||
* Use HAL_RNG_GenerateRandomNumber_IT() API instead.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval 32-bit random number
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
uint32_t random32bit = 0U;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Get a 32bit Random number */
|
||||
random32bit = hrng->Instance->DR;
|
||||
|
||||
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
|
||||
__HAL_RNG_ENABLE_IT(hrng);
|
||||
|
||||
/* Return the 32 bit random number */
|
||||
return random32bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read latest generated random number.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval random value
|
||||
*/
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
return(hrng->RandomNumber);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Data Ready callback in non-blocking mode.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @param random32bit: generated random number.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
UNUSED(random32bit);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RNG error callbacks.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_ErrorCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group3
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the RNG state.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
return hrng->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,356 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_RNG_H
|
||||
#define __STM32F2xx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
||||
|
||||
}HAL_RNG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
||||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
||||
|
||||
}RNG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RNG handle state
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG peripheral.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Check the selected RNG flag status.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __FLAG__: RNG flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_FLAG_DRDY: Data ready
|
||||
* @arg RNG_FLAG_CECS: Clock error current status
|
||||
* @arg RNG_FLAG_SECS: Seed error current status
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the selected RNG flag status.
|
||||
* @param __HANDLE__: RNG handle
|
||||
* @param __FLAG__: RNG flag to clear
|
||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG interrupts.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG interrupts.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RNG interrupt status flags.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
|
||||
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Types RNG Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Defines RNG Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Variables RNG Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Constants RNG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
||||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Functions RNG Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,758 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_RTC_H
|
||||
#define __STM32F2xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
}HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTC_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
}RTC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
|
||||
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U)
|
||||
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U)
|
||||
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
|
||||
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
|
||||
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN ((uint32_t)0x000000000U)
|
||||
#define RTC_FORMAT_BCD ((uint32_t)0x000000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
* @{
|
||||
*/
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000U)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000U)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000U)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000U)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000U)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000U)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800U)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400U)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200U)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100U)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040U)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020U)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010U)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004U)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002U)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @arg RTC_FLAG_ALRAWF
|
||||
* @arg RTC_FLAG_ALRBWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();\
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extension module */
|
||||
#include "stm32f2xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
|
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
|
||||
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
|
||||
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
|
||||
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
|
||||
((OUTPUT) == RTC_OUTPUT_WAKEUP))
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFFU)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_RTC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,808 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of RTC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_RTC_EX_H
|
||||
#define __STM32F2xx_HAL_RTC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief RTC Tamper structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Tamper; /*!< Specifies the Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
|
||||
|
||||
uint32_t PinSelection; /*!< Specifies the Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
|
||||
|
||||
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
|
||||
}RTC_TamperTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000U)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001U)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002U)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003U)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004U)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005U)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006U)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007U)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008U)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009U)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000AU)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000BU)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000CU)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000DU)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000EU)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000FU)
|
||||
#define RTC_BKP_DR16 ((uint32_t)0x00000010U)
|
||||
#define RTC_BKP_DR17 ((uint32_t)0x00000011U)
|
||||
#define RTC_BKP_DR18 ((uint32_t)0x00000012U)
|
||||
#define RTC_BKP_DR19 ((uint32_t)0x00000013U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
|
||||
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000U)
|
||||
#define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
|
||||
#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
|
||||
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U)
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U)
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U)
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000U)
|
||||
#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ---------------------------------WAKEUPTIMER---------------------------------*/
|
||||
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC WakeUp Timer peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Wake-up Timer peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_WUT: WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC WakeUpTimer's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC WakeUpTimer Flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_WUTF
|
||||
* @arg RTC_FLAG_WUTWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake Up timer's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_WUTF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake-up Timer associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* ---------------------------------TIMESTAMP---------------------------------*/
|
||||
/** @defgroup RTCEx_Timestamp RTC Timestamp
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TS: TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC TimeStamp's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC TimeStamp flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TSF
|
||||
* @arg RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Time Stamp's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* ---------------------------------TAMPER------------------------------------*/
|
||||
/** @defgroup RTCEx_Tamper RTC Tamper
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Tamper1 input detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Tamper1 input detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP: Tamper interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Tamper's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Tamper's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
|
||||
/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* ------------------------------Calibration----------------------------------*/
|
||||
/** @defgroup RTCEx_Calibration RTC Calibration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the Coarse calibration process.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
|
||||
|
||||
/**
|
||||
* @brief Disable the Coarse calibration process.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC calibration output.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
|
||||
|
||||
/**
|
||||
* @brief Disable the calibration output.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
|
||||
|
||||
/**
|
||||
* @brief Enable the clock reference detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
|
||||
|
||||
/**
|
||||
* @brief Disable the clock reference detection.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Functions RTC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* RTC TimeStamp and Tamper functions *****************************************/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* RTC Wake-up functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Extension Control functions ************************************************/
|
||||
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
|
||||
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Extension RTC features functions *******************************************/
|
||||
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4) || \
|
||||
((BKP) == RTC_BKP_DR5) || \
|
||||
((BKP) == RTC_BKP_DR6) || \
|
||||
((BKP) == RTC_BKP_DR7) || \
|
||||
((BKP) == RTC_BKP_DR8) || \
|
||||
((BKP) == RTC_BKP_DR9) || \
|
||||
((BKP) == RTC_BKP_DR10) || \
|
||||
((BKP) == RTC_BKP_DR11) || \
|
||||
((BKP) == RTC_BKP_DR12) || \
|
||||
((BKP) == RTC_BKP_DR13) || \
|
||||
((BKP) == RTC_BKP_DR14) || \
|
||||
((BKP) == RTC_BKP_DR15) || \
|
||||
((BKP) == RTC_BKP_DR16) || \
|
||||
((BKP) == RTC_BKP_DR17) || \
|
||||
((BKP) == RTC_BKP_DR18) || \
|
||||
((BKP) == RTC_BKP_DR19))
|
||||
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
|
||||
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
|
||||
|
||||
#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
|
||||
((PIN) == RTC_TAMPERPIN_POS1))
|
||||
|
||||
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
|
||||
((PIN) == RTC_TIMESTAMPPIN_POS1))
|
||||
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
|
||||
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))
|
||||
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
|
||||
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
|
||||
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
|
||||
((SIGN) == RTC_CALIBSIGN_NEGATIVE))
|
||||
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
|
||||
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_RTC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,789 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_sd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_SD_H
|
||||
#define __STM32F2xx_HAL_SD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD SD
|
||||
* @brief SD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Types SD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define SD_InitTypeDef SDIO_InitTypeDef
|
||||
#define SD_TypeDef SDIO_TypeDef
|
||||
|
||||
typedef struct
|
||||
{
|
||||
SD_TypeDef *Instance; /*!< SDIO register base address */
|
||||
|
||||
SD_InitTypeDef Init; /*!< SD required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SD locking object */
|
||||
|
||||
uint32_t CardType; /*!< SD card type */
|
||||
|
||||
uint32_t RCA; /*!< SD relative card address */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< SD card identification number table */
|
||||
|
||||
__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
|
||||
|
||||
__IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
|
||||
|
||||
__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
|
||||
|
||||
__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
|
||||
|
||||
}SD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CSDTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CIDTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
|
||||
__IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
|
||||
__IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
|
||||
__IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
|
||||
__IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
|
||||
__IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
|
||||
__IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
|
||||
__IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
|
||||
__IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
|
||||
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
|
||||
|
||||
}HAL_SD_CardStatusTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group5 SD Card information structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
|
||||
HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
|
||||
uint64_t CardCapacity; /*!< Card capacity */
|
||||
uint32_t CardBlockSize; /*!< Card block size */
|
||||
uint16_t RCA; /*!< SD relative card address */
|
||||
uint8_t CardType; /*!< SD card type */
|
||||
|
||||
}HAL_SD_CardInfoTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/**
|
||||
* @brief SD specific error defines
|
||||
*/
|
||||
SD_CMD_CRC_FAIL = (1U), /*!< Command response received (but CRC check failed) */
|
||||
SD_DATA_CRC_FAIL = (2U), /*!< Data block sent/received (CRC check failed) */
|
||||
SD_CMD_RSP_TIMEOUT = (3U), /*!< Command response timeout */
|
||||
SD_DATA_TIMEOUT = (4U), /*!< Data timeout */
|
||||
SD_TX_UNDERRUN = (5U), /*!< Transmit FIFO underrun */
|
||||
SD_RX_OVERRUN = (6U), /*!< Receive FIFO overrun */
|
||||
SD_START_BIT_ERR = (7U), /*!< Start bit not detected on all data signals in wide bus mode */
|
||||
SD_CMD_OUT_OF_RANGE = (8U), /*!< Command's argument was out of range. */
|
||||
SD_ADDR_MISALIGNED = (9U), /*!< Misaligned address */
|
||||
SD_BLOCK_LEN_ERR = (10U), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
|
||||
SD_ERASE_SEQ_ERR = (11U), /*!< An error in the sequence of erase command occurs. */
|
||||
SD_BAD_ERASE_PARAM = (12U), /*!< An invalid selection for erase groups */
|
||||
SD_WRITE_PROT_VIOLATION = (13U), /*!< Attempt to program a write protect block */
|
||||
SD_LOCK_UNLOCK_FAILED = (14U), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
|
||||
SD_COM_CRC_FAILED = (15U), /*!< CRC check of the previous command failed */
|
||||
SD_ILLEGAL_CMD = (16U), /*!< Command is not legal for the card state */
|
||||
SD_CARD_ECC_FAILED = (17U), /*!< Card internal ECC was applied but failed to correct the data */
|
||||
SD_CC_ERROR = (18U), /*!< Internal card controller error */
|
||||
SD_GENERAL_UNKNOWN_ERROR = (19U), /*!< General or unknown error */
|
||||
SD_STREAM_READ_UNDERRUN = (20U), /*!< The card could not sustain data transfer in stream read operation. */
|
||||
SD_STREAM_WRITE_OVERRUN = (21U), /*!< The card could not sustain data programming in stream mode */
|
||||
SD_CID_CSD_OVERWRITE = (22U), /*!< CID/CSD overwrite error */
|
||||
SD_WP_ERASE_SKIP = (23U), /*!< Only partial address space was erased */
|
||||
SD_CARD_ECC_DISABLED = (24U), /*!< Command has been executed without using internal ECC */
|
||||
SD_ERASE_RESET = (25U), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
|
||||
SD_AKE_SEQ_ERROR = (26U), /*!< Error in sequence of authentication. */
|
||||
SD_INVALID_VOLTRANGE = (27U),
|
||||
SD_ADDR_OUT_OF_RANGE = (28U),
|
||||
SD_SWITCH_ERROR = (29U),
|
||||
SD_SDIO_DISABLED = (30U),
|
||||
SD_SDIO_FUNCTION_BUSY = (31U),
|
||||
SD_SDIO_FUNCTION_FAILED = (32U),
|
||||
SD_SDIO_UNKNOWN_FUNCTION = (33U),
|
||||
|
||||
/**
|
||||
* @brief Standard error defines
|
||||
*/
|
||||
SD_INTERNAL_ERROR = (34U),
|
||||
SD_NOT_CONFIGURED = (35U),
|
||||
SD_REQUEST_PENDING = (36U),
|
||||
SD_REQUEST_NOT_APPLICABLE = (37U),
|
||||
SD_INVALID_PARAMETER = (38U),
|
||||
SD_UNSUPPORTED_FEATURE = (39U),
|
||||
SD_UNSUPPORTED_HW = (40U),
|
||||
SD_ERROR = (41U),
|
||||
SD_OK = (0U)
|
||||
|
||||
}HAL_SD_ErrorTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_TRANSFER_OK = 0U, /*!< Transfer success */
|
||||
SD_TRANSFER_BUSY = 1U, /*!< Transfer is occurring */
|
||||
SD_TRANSFER_ERROR = 2U /*!< Transfer failed */
|
||||
|
||||
}HAL_SD_TransferStateTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */
|
||||
|
||||
}HAL_SD_CardStateTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */
|
||||
SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */
|
||||
SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */
|
||||
SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */
|
||||
|
||||
}HAL_SD_OperationTypedef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Constants SD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SD Commands Index
|
||||
*/
|
||||
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
|
||||
#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
|
||||
#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
|
||||
#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
|
||||
#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
|
||||
#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
|
||||
operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
|
||||
#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
|
||||
#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
|
||||
and asks the card whether card supports voltage. */
|
||||
#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
|
||||
#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
|
||||
#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
|
||||
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
|
||||
#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
|
||||
#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U)
|
||||
#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
|
||||
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
|
||||
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
|
||||
for SDHS and SDXC. */
|
||||
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
|
||||
STOP_TRANSMISSION command. */
|
||||
#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
|
||||
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
|
||||
#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
|
||||
#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
|
||||
fixed 512 bytes in case of SDHC and SDXC. */
|
||||
#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
|
||||
#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
|
||||
#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
|
||||
#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
|
||||
#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
|
||||
#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
|
||||
#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
|
||||
#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
|
||||
#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
|
||||
system set by switch function command (CMD6). */
|
||||
#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
|
||||
Reserved for each command system set by switch function command (CMD6). */
|
||||
#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
|
||||
#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
|
||||
the SET_BLOCK_LEN command. */
|
||||
#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
|
||||
than a standard command. */
|
||||
#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
|
||||
for general purpose/application specific commands. */
|
||||
#define SD_CMD_NO_CMD ((uint8_t)64U)
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific commands.
|
||||
* SDIO_APP_CMD should be sent before sending these commands.
|
||||
*/
|
||||
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
|
||||
widths are given in SCR register. */
|
||||
#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
|
||||
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
|
||||
32bit+CRC data block. */
|
||||
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
|
||||
send its operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
|
||||
#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
|
||||
#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
|
||||
|
||||
/**
|
||||
* @brief Following commands are SD Card Specific security commands.
|
||||
* SD_CMD_APP_CMD should be sent before sending these commands.
|
||||
*/
|
||||
#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */
|
||||
|
||||
/**
|
||||
* @brief Supported SD Memory Cards
|
||||
*/
|
||||
#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U)
|
||||
#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U)
|
||||
#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U)
|
||||
#define MULTIMEDIA_CARD ((uint32_t)0x00000003U)
|
||||
#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U)
|
||||
#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U)
|
||||
#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U)
|
||||
#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_macros SD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
|
||||
|
||||
/**
|
||||
* @brief Enable the SDIO DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
|
||||
|
||||
/**
|
||||
* @brief Disable the SDIO DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE()
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD flag is set or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval The new state of SD FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's pending flags.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD interrupt has occurred or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's interrupt pending bits.
|
||||
* @param __HANDLE__ : SD Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Functions SD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
|
||||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
|
||||
HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
|
||||
HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||
HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
|
||||
HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||
HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
|
||||
HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Types SD Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Defines SD Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Variables SD Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Constants SD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Macros SD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions SD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_SD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,677 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_SMARTCARD_H
|
||||
#define __STM32F2xx_HAL_SMARTCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref SMARTCARD_Word_Length */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref SMARTCARD_Stop_Bits */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits).*/
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Mode */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
|
||||
to provide the smartcard clock. The value given in the register (5 significant bits)
|
||||
is multiplied by 2 to give the division factor of the source clock frequency.
|
||||
This parameter can be a value of @ref SMARTCARD_Prescaler */
|
||||
|
||||
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
|
||||
|
||||
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
|
||||
This parameter can be a value of @ref SMARTCARD_NACK_State */
|
||||
}SMARTCARD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD State structures definition
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains SMARTCARD state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
}HAL_SMARTCARD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* USART registers base address */
|
||||
|
||||
SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* SmartCard Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* SmartCard Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /* SmartCard state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef RxState; /* SmartCard state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /* SmartCard Error code */
|
||||
|
||||
}SMARTCARD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
|
||||
* @brief SMARTCARD Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
|
||||
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||
#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
|
||||
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001U) /*!< SYSCLK divided by 2 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002U) /*!< SYSCLK divided by 4 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003U) /*!< SYSCLK divided by 6 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004U) /*!< SYSCLK divided by 8 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005U) /*!< SYSCLK divided by 10 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006U) /*!< SYSCLK divided by 12 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007U) /*!< SYSCLK divided by 14 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008U) /*!< SYSCLK divided by 16 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009U) /*!< SYSCLK divided by 18 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000AU) /*!< SYSCLK divided by 20 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000BU) /*!< SYSCLK divided by 22 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000CU) /*!< SYSCLK divided by 24 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000DU) /*!< SYSCLK divided by 26 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000EU) /*!< SYSCLK divided by 28 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000FU) /*!< SYSCLK divided by 30 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010U) /*!< SYSCLK divided by 32 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011U) /*!< SYSCLK divided by 34 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012U) /*!< SYSCLK divided by 36 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013U) /*!< SYSCLK divided by 38 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014U) /*!< SYSCLK divided by 40 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015U) /*!< SYSCLK divided by 42 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016U) /*!< SYSCLK divided by 44 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017U) /*!< SYSCLK divided by 46 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018U) /*!< SYSCLK divided by 48 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019U) /*!< SYSCLK divided by 50 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001AU) /*!< SYSCLK divided by 52 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001BU) /*!< SYSCLK divided by 54 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001CU) /*!< SYSCLK divided by 56 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001DU) /*!< SYSCLK divided by 58 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001EU) /*!< SYSCLK divided by 60 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001FU) /*!< SYSCLK divided by 62 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
|
||||
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
|
||||
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
|
||||
#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
|
||||
#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
|
||||
#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
|
||||
#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
|
||||
#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask in the XX register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMARTCARD handle gstate & RxState
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
|
||||
} while(0)
|
||||
|
||||
/** @brief Flushs the Smartcard DR register
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
*/
|
||||
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||
|
||||
/** @brief Checks whether the specified Smartcard flag is set or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg SMARTCARD_FLAG_ORE: Overrun Error flag
|
||||
* @arg SMARTCARD_FLAG_NE: Noise Error flag
|
||||
* @arg SMARTCARD_FLAG_FE: Framing Error flag
|
||||
* @arg SMARTCARD_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the specified Smartcard pending flags.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
|
||||
* error) flags are cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a read operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clear the SMARTCARD PE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* SMARTCARD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_pe = 0x00U; \
|
||||
tmpreg_pe = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg_pe = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg_pe); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the SMARTCARD FE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* SMARTCARD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD NE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* SMARTCARD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD ORE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* SMARTCARD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD IDLE pending flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
|
||||
* SMARTCARD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enables or disables the specified SmartCard interrupts.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @param __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the SmartCard Handle.
|
||||
* @param __IT__: specifies the SMARTCARD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
|
||||
|
||||
/** @brief Macro to enable the SMARTCARD's one bit sample method
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Macro to disable the SMARTCARD's one bit sample method
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Macros to enable or disable the SmartCard DMA request.
|
||||
* @param __HANDLE__: specifies the SmartCard Handle.
|
||||
* @param __REQUEST__: specifies the SmartCard DMA request.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMARTCARD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
|
||||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SMARTCARD interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_IDLEIE | USART_CR3_EIE )
|
||||
|
||||
#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
|
||||
#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||
/* SMARTCARD BRR = mantissa + overflow + fraction
|
||||
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
|
||||
#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||
(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||
|
||||
#define SMARTCARD_CR1_REG_INDEX 1U
|
||||
#define SMARTCARD_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
|
||||
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
|
||||
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
|
||||
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
|
||||
((PARITY) == SMARTCARD_PARITY_ODD))
|
||||
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))
|
||||
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
|
||||
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
|
||||
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
|
||||
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
|
||||
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
|
||||
((NACK) == SMARTCARD_NACK_DISABLE))
|
||||
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_SMARTCARD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,584 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_SPI_H
|
||||
#define __STM32F2xx_HAL_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_Mode */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_Data_Size */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
|
||||
}HAL_SPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /* SPI registers base address */
|
||||
|
||||
SPI_InitTypeDef Init; /* SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* SPI Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* SPI Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
|
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* SPI locking object */
|
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* SPI Error code */
|
||||
|
||||
}SPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Error_Code SPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
|
||||
#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
|
||||
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
|
||||
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
|
||||
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Flag: RXNE,TXE, BSY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Mode SPI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
|
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction SPI Direction Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
|
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Data_Size SPI Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
|
||||
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
|
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
|
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
|
||||
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
|
||||
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
|
||||
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
|
||||
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
|
||||
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
|
||||
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
|
||||
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
|
||||
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
|
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{
|
||||
*/
|
||||
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SPI handle state.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI interrupts.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the SPI FRE pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
}while(0)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions **************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
|
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
|
||||
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
|
||||
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
|
||||
((MODE) == SPI_MODE_MASTER))
|
||||
|
||||
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_8BIT))
|
||||
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
|
||||
((CPOL) == SPI_POLARITY_HIGH))
|
||||
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
|
||||
((CPHA) == SPI_PHASE_2EDGE))
|
||||
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
|
||||
((NSS) == SPI_NSS_HARD_INPUT) || \
|
||||
((NSS) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
|
||||
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
|
||||
((MODE) == SPI_TIMODE_ENABLE))
|
||||
|
||||
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
|
||||
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Functions SPI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_SPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,686 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_sram.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief SRAM HAL module driver.
|
||||
* This file provides a generic firmware to drive SRAM memories
|
||||
* mounted as external device.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver is a generic layered driver which contains a set of APIs used to
|
||||
control SRAM memories. It uses the FSMC layer functions to interface
|
||||
with SRAM devices.
|
||||
The following sequence should be followed to configure the FSMC to interface
|
||||
with SRAM/PSRAM memories:
|
||||
|
||||
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
|
||||
SRAM_HandleTypeDef hsram; and:
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
|
||||
values of the structure member.
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
|
||||
base register instance for NOR or SRAM device
|
||||
|
||||
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
|
||||
base register instance for NOR or SRAM extended mode
|
||||
|
||||
(#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
|
||||
mode timings; for example:
|
||||
FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
|
||||
and fill its fields with the allowed values of the structure member.
|
||||
|
||||
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
|
||||
performs the following sequence:
|
||||
|
||||
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
|
||||
(##) Control register configuration using the FSMC NORSRAM interface function
|
||||
FSMC_NORSRAM_Init()
|
||||
(##) Timing register configuration using the FSMC NORSRAM interface function
|
||||
FSMC_NORSRAM_Timing_Init()
|
||||
(##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
|
||||
FSMC_NORSRAM_Extended_Timing_Init()
|
||||
(##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
|
||||
|
||||
(#) At this stage you can perform read/write accesses from/to the memory connected
|
||||
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
|
||||
following APIs:
|
||||
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
|
||||
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
|
||||
|
||||
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
|
||||
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
|
||||
|
||||
(#) You can continuously monitor the SRAM device HAL state by calling the function
|
||||
HAL_SRAM_GetState()
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM SRAM
|
||||
* @brief SRAM driver modules
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Initialization and de_initialization functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to initialize/de-initialize
|
||||
the SRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Performs the SRAM device initialization sequence
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param Timing: Pointer to SRAM control timing structure
|
||||
* @param ExtTiming: Pointer to SRAM extended mode timing structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||
{
|
||||
/* Check the SRAM handle parameter */
|
||||
if(hsram == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(hsram->State == HAL_SRAM_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hsram->Lock = HAL_UNLOCKED;
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_SRAM_MspInit(hsram);
|
||||
}
|
||||
|
||||
/* Initialize SRAM control Interface */
|
||||
FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
|
||||
|
||||
/* Initialize SRAM timing Interface */
|
||||
FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
|
||||
|
||||
/* Initialize SRAM extended mode timing Interface */
|
||||
FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
|
||||
|
||||
/* Enable the NORSRAM device */
|
||||
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Performs the SRAM device De-initialization sequence.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* De-Initialize the low level hardware (MSP) */
|
||||
HAL_SRAM_MspDeInit(hsram);
|
||||
|
||||
/* Configure the SRAM registers with their reset values */
|
||||
FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
|
||||
|
||||
hsram->State = HAL_SRAM_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SRAM MSP Init.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hsram);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SRAM MSP DeInit.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hsram);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete callback.
|
||||
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdma);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA transfer complete error callback.
|
||||
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hdma);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
|
||||
* @brief Input Output and memory control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Input and Output functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to use and control the SRAM memory
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads 8-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint8_t *)pSramAddress;
|
||||
pDstBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 8-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*(__IO uint8_t *)pSramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads 16-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint16_t *)pSramAddress;
|
||||
pDstBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 16-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*(__IO uint16_t *)pSramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSramAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads 32-bit buffer from SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Read data from memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*pDstBuffer = *(__IO uint32_t *)pAddress;
|
||||
pDstBuffer++;
|
||||
pAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes 32-bit buffer to SRAM memory.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Write data to memory */
|
||||
for(; BufferSize != 0U; BufferSize--)
|
||||
{
|
||||
*(__IO uint32_t *)pAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pAddress++;
|
||||
}
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to read start address
|
||||
* @param pDstBuffer: Pointer to destination buffer
|
||||
* @param BufferSize: Size of the buffer to read from memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @param pAddress: Pointer to write start address
|
||||
* @param pSrcBuffer: Pointer to source buffer to write
|
||||
* @param BufferSize: Size of the buffer to write to memory
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||
{
|
||||
/* Check the SRAM controller state */
|
||||
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Configure DMA user callbacks */
|
||||
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control dynamically
|
||||
the SRAM interface.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables dynamically SRAM write operation.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Enable write operation */
|
||||
FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables dynamically SRAM write operation.
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsram);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||
|
||||
/* Disable write operation */
|
||||
FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
||||
|
||||
/* Update the SRAM controller state */
|
||||
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hsram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Functions_Group4 State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SRAM State functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the SRAM controller
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the SRAM controller state
|
||||
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||
* the configuration information for SRAM module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
||||
{
|
||||
return hsram->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f2xx_hal_sram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.3
|
||||
* @date 29-June-2016
|
||||
* @brief Header file of SRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F2xx_HAL_SRAM_H
|
||||
#define __STM32F2xx_HAL_SRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F2xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||
|
||||
}HAL_SRAM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SRAM handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||
|
||||
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||
|
||||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
}SRAM_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset SRAM handle state
|
||||
* @param __HANDLE__: SRAM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* SRAM Control functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* SRAM State functions *********************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F2xx_HAL_SRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue