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[M2351] Refine UART code 

1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
pull/7302/head
ccli8 2018-03-08 13:56:42 +08:00
parent ebf53b9f64
commit dcfe1d4283
1 changed files with 281 additions and 331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

420
targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c
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@ -26,14 +26,10 @@
#include "nu_bitutil.h"
#include <string.h>
#define NVT_SERIAL_SYNC_ONLY
#if DEVICE_SERIAL_ASYNCH
#ifndef NVT_SERIAL_SYNC_ONLY
#include "dma_api.h"
#include "dma.h"
#endif
#endif
struct nu_uart_var {
uint32_t ref_cnt; // Reference count of the H/W module
@ -182,8 +178,6 @@ static const struct nu_modinit_s uart_modinit_tab[] = {
extern void mbed_sdk_init(void);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
// NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
@ -204,13 +198,23 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
if (! var->ref_cnt) {
do {
// Reset this module
SYS_ResetModule(modinit->rsetidx);
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
@ -250,7 +254,6 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
}
}
__attribute__((cmse_nonsecure_entry))
void serial_free(serial_t *obj)
{
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
@ -262,7 +265,6 @@ void serial_free(serial_t *obj)
var->ref_cnt --;
if (! var->ref_cnt) {
#if DEVICE_SERIAL_ASYNCH
#ifndef NVT_SERIAL_SYNC_ONLY
if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
dma_channel_free(obj->serial.dma_chn_id_tx);
obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
@ -271,7 +273,6 @@ void serial_free(serial_t *obj)
dma_channel_free(obj->serial.dma_chn_id_rx);
obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
}
#endif
#endif
do {
@ -280,8 +281,11 @@ void serial_free(serial_t *obj)
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
NVIC_DisableIRQ(modinit->irq_n);
// Disable IP clock
CLK_DisableModuleClock(modinit->clkidx);
/* Disable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(modinit->clkidx);
} while (0);
}
@ -299,9 +303,9 @@ void serial_free(serial_t *obj)
uart_modinit_mask &= ~(1 << i);
}
}
#endif
void serial_baud(serial_t *obj, int baudrate) {
void serial_baud(serial_t *obj, int baudrate)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -309,28 +313,33 @@ void serial_baud(serial_t *obj, int baudrate) {
UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
// TODO: Assert for not supported parity and data bits
// Sanity check arguments
MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
obj->serial.databits = data_bits;
obj->serial.parity = parity;
obj->serial.stopbits = stop_bits;
uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
(data_bits == 6) ? UART_WORD_LEN_6 :
(data_bits == 7) ? UART_WORD_LEN_7 :
UART_WORD_LEN_8;
(data_bits == 6) ? UART_WORD_LEN_6 :
(data_bits == 7) ? UART_WORD_LEN_7 :
UART_WORD_LEN_8;
uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
(parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
UART_PARITY_NONE;
(parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
UART_PARITY_NONE;
uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
UART_SetLineConfig((UART_T *) NU_MODBASE(obj->serial.uart),
0, // Don't change baudrate
databits_intern,
parity_intern,
stopbits_intern);
0, // Don't change baudrate
databits_intern,
parity_intern,
stopbits_intern);
}
#if DEVICE_SERIAL_FC
@ -437,7 +446,6 @@ void serial_putc(serial_t *obj, int c)
int serial_readable(serial_t *obj)
{
//return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
}
@ -520,7 +528,6 @@ static void uart_irq(serial_t *obj)
#if DEVICE_SERIAL_ASYNCH
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
#ifndef NVT_SERIAL_SYNC_ONLY
MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
obj->serial.dma_usage_tx = hint;
@ -529,9 +536,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
// UART IRQ is necessary for both interrupt way and DMA way
serial_tx_enable_event(obj, event, 1);
serial_tx_buffer_set(obj, tx, tx_length, tx_width);
//UART_HAL_DisableTransmitter(obj->serial.address);
//UART_HAL_FlushTxFifo(obj->serial.address);
//UART_HAL_EnableTransmitter(obj->serial.address);
int n_word = 0;
if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
@ -548,54 +552,55 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
PDMA_SetTransferMode(pdma_base,
obj->serial.dma_chn_id_tx,
((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
0); // Scatter-gather descriptor address
obj->serial.dma_chn_id_tx,
((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
0); // Scatter-gather descriptor address
PDMA_SetTransferCnt(pdma_base,
obj->serial.dma_chn_id_tx,
(tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
tx_length);
obj->serial.dma_chn_id_tx,
(tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
tx_length);
PDMA_SetTransferAddr(pdma_base,
obj->serial.dma_chn_id_tx,
(uint32_t) tx, // NOTE:
// NUC472: End of source address
// M451: Start of source address
// M480: Start of source address
// M2351: Start of source address
PDMA_SAR_INC, // Source address incremental
(uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
PDMA_DAR_FIX); // Destination address fixed
obj->serial.dma_chn_id_tx,
(uint32_t) tx, // NOTE:
// NUC472: End of source address
// M451: Start of source address
// M480: Start of source address
// M2351: Start of source address
PDMA_SAR_INC, // Source address incremental
(uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
PDMA_DAR_FIX); // Destination address fixed
PDMA_SetBurstType(pdma_base,
obj->serial.dma_chn_id_tx,
PDMA_REQ_SINGLE, // Single mode
0); // Burst size
obj->serial.dma_chn_id_tx,
PDMA_REQ_SINGLE, // Single mode
0); // Burst size
PDMA_EnableInt(pdma_base,
obj->serial.dma_chn_id_tx,
PDMA_INT_TRANS_DONE); // Interrupt type
obj->serial.dma_chn_id_tx,
PDMA_INT_TRANS_DONE); // Interrupt type
// Register DMA event handler
dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
serial_tx_enable_interrupt(obj, handler, 1);
/* We needn't actually enable UART INT to go UART ISR -> handler.
* Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
* with serial_tx/rx_enable_interrupt having set up this call path. */
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
}
return n_word;
#else
return 0;
#endif
}
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
{
#ifndef NVT_SERIAL_SYNC_ONLY
MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
obj->serial.dma_usage_rx = hint;
serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
// DMA doesn't support char match, so fall back to IRQ if it is requested.
if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
(event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
char_match != SERIAL_RESERVED_CHAR_MATCH) {
(event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
char_match != SERIAL_RESERVED_CHAR_MATCH) {
obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
dma_channel_free(obj->serial.dma_chn_id_rx);
obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
@ -605,9 +610,6 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
serial_rx_enable_event(obj, event, 1);
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
serial_rx_set_char_match(obj, char_match);
//UART_HAL_DisableReceiver(obj->serial.address);
//UART_HAL_FlushRxFifo(obj->serial.address);
//UART_HAL_EnableReceiver(obj->serial.address);
if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
// Interrupt way
@ -622,42 +624,44 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
PDMA_SetTransferMode(pdma_base,
obj->serial.dma_chn_id_rx,
((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
0); // Scatter-gather descriptor address
obj->serial.dma_chn_id_rx,
((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
0, // Scatter-gather disabled
0); // Scatter-gather descriptor address
PDMA_SetTransferCnt(pdma_base,
obj->serial.dma_chn_id_rx,
(rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
rx_length);
obj->serial.dma_chn_id_rx,
(rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
rx_length);
PDMA_SetTransferAddr(pdma_base,
obj->serial.dma_chn_id_rx,
(uint32_t) NU_MODBASE(obj->serial.uart), // Source address
PDMA_SAR_FIX, // Source address fixed
(uint32_t) rx, // NOTE:
// NUC472: End of destination address
// M451: Start of destination address
// M480: Start of destination address
// M2351: Start of destination address
PDMA_DAR_INC); // Destination address incremental
obj->serial.dma_chn_id_rx,
(uint32_t) NU_MODBASE(obj->serial.uart), // Source address
PDMA_SAR_FIX, // Source address fixed
(uint32_t) rx, // NOTE:
// NUC472: End of destination address
// M451: Start of destination address
// M480: Start of destination address
// M2351: Start of destination address
PDMA_DAR_INC); // Destination address incremental
PDMA_SetBurstType(pdma_base,
obj->serial.dma_chn_id_rx,
PDMA_REQ_SINGLE, // Single mode
0); // Burst size
obj->serial.dma_chn_id_rx,
PDMA_REQ_SINGLE, // Single mode
0); // Burst size
PDMA_EnableInt(pdma_base,
obj->serial.dma_chn_id_rx,
PDMA_INT_TRANS_DONE); // Interrupt type
obj->serial.dma_chn_id_rx,
PDMA_INT_TRANS_DONE); // Interrupt type
// Register DMA event handler
dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
serial_rx_enable_interrupt(obj, handler, 1);
((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
/* We needn't actually enable UART INT to go UART ISR -> handler.
* Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
* with serial_tx/rx_enable_interrupt having set up this call path. */
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
}
#endif
}
void serial_tx_abort_asynch(serial_t *obj)
{
#ifndef NVT_SERIAL_SYNC_ONLY
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -666,8 +670,7 @@ void serial_tx_abort_asynch(serial_t *obj)
if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_tx);
// NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
@ -676,19 +679,16 @@ void serial_tx_abort_asynch(serial_t *obj)
// Necessary for both interrupt way and DMA way
serial_enable_interrupt(obj, TxIrq, 0);
serial_rollback_interrupt(obj, TxIrq);
#endif
}
void serial_rx_abort_asynch(serial_t *obj)
{
#ifndef NVT_SERIAL_SYNC_ONLY
if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
PDMA_T *pdma_base = dma_modbase();
if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
// FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
//PDMA_STOP(obj->serial.dma_chn_id_rx);
// NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
}
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
@ -697,12 +697,10 @@ void serial_rx_abort_asynch(serial_t *obj)
// Necessary for both interrupt way and DMA way
serial_enable_interrupt(obj, RxIrq, 0);
serial_rollback_interrupt(obj, RxIrq);
#endif
}
uint8_t serial_tx_active(serial_t *obj)
{
#ifndef NVT_SERIAL_SYNC_ONLY
// NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
@ -710,14 +708,10 @@ uint8_t serial_tx_active(serial_t *obj)
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
return (obj->serial.vec == var->vec_async);
#else
return 1;
#endif
}
uint8_t serial_rx_active(serial_t *obj)
{
#ifndef NVT_SERIAL_SYNC_ONLY
// NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
@ -725,14 +719,10 @@ uint8_t serial_rx_active(serial_t *obj)
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
return (obj->serial.vec == var->vec_async);
#else
return 1;
#endif
}
int serial_irq_handler_asynch(serial_t *obj)
{
#ifndef NVT_SERIAL_SYNC_ONLY
int event_rx = 0;
int event_tx = 0;
@ -752,40 +742,8 @@ int serial_irq_handler_asynch(serial_t *obj)
}
return (obj->serial.event & (event_rx | event_tx));
#else
return 0;
#endif
}
int serial_allow_powerdown(void)
{
#ifndef NVT_SERIAL_SYNC_ONLY
uint32_t modinit_mask = uart_modinit_mask;
while (modinit_mask) {
int uart_idx = nu_ctz(modinit_mask);
const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
if (modinit->modname != NC) {
UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
// Disallow entering power-down mode if Tx FIFO has data to flush
if (! UART_IS_TX_EMPTY((uart_base))) {
return 0;
}
// Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
return 0;
}
// Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
return 0;
}
}
modinit_mask &= ~(1 << uart_idx);
}
#endif
return 1;
}
static void uart0_vec_async(void)
{
uart_irq_async(uart0_var.obj);
@ -826,62 +784,6 @@ static void uart_irq_async(serial_t *obj)
}
}
static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
{
if (enable) {
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
NVIC_EnableIRQ(modinit->irq_n);
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
// Multiple serial S/W objects for single UART H/W module possibly.
// Bind serial S/W object to UART H/W module as interrupt is enabled.
var->obj = obj;
switch (irq) {
// NOTE: Setting inten_msk first to avoid race condition
case RxIrq:
obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
break;
case TxIrq:
obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
break;
}
}
else { // disable
switch (irq) {
case RxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
break;
case TxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
break;
}
}
}
static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
{
int inten_msk = 0;
switch (irq) {
case RxIrq:
inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
break;
case TxIrq:
inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
break;
}
return !! inten_msk;
}
#ifndef NVT_SERIAL_SYNC_ONLY
static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
{
obj->char_match = char_match;
@ -893,8 +795,9 @@ static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
//if (event & SERIAL_EVENT_TX_COMPLETE) {
//}
if (event & SERIAL_EVENT_TX_COMPLETE) {
// N/A
}
}
static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
@ -902,10 +805,12 @@ static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
//if (event & SERIAL_EVENT_RX_COMPLETE) {
//}
//if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
//}
if (event & SERIAL_EVENT_RX_COMPLETE) {
// N/A
}
if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
// N/A
}
if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
}
@ -915,21 +820,19 @@ static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
if (event & SERIAL_EVENT_RX_OVERFLOW) {
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
}
//if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
//}
if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
// N/A
}
}
static int serial_is_tx_complete(serial_t *obj)
{
// NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
//return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
// FIXME: Premature abort???
return (obj->tx_buff.pos == obj->tx_buff.length);
}
static int serial_is_rx_complete(serial_t *obj)
{
//return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
return (obj->rx_buff.pos == obj->rx_buff.length);
}
@ -992,8 +895,6 @@ static uint32_t serial_rx_event_check(serial_t *obj)
}
if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
// FIXME: Timing to reset char_found?
//obj->char_found = 0;
}
return event;
@ -1063,13 +964,13 @@ static int serial_write_async(serial_t *obj)
int n_words = 0;
while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
switch (bytes_per_word) {
case 4:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
case 2:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
case 1:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
case 4:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
case 2:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
case 1:
UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
}
n_words ++;
@ -1094,10 +995,6 @@ static int serial_read_async(serial_t *obj)
MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
//uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
//if (rx_fifo_free == 0) {
// return 0;
//}
uint32_t bytes_per_word = obj->rx_buff.width / 8;
@ -1105,13 +1002,13 @@ static int serial_read_async(serial_t *obj)
int n_words = 0;
while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
switch (bytes_per_word) {
case 4:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
case 2:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
case 1:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
case 4:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
case 2:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
case 1:
*rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
}
n_words ++;
@ -1119,15 +1016,15 @@ static int serial_read_async(serial_t *obj)
obj->rx_buff.pos ++;
if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
uint8_t *rx_cmp = rx;
switch (bytes_per_word) {
case 4:
rx_cmp -= 2;
case 2:
rx_cmp --;
case 1:
rx_cmp --;
case 4:
rx_cmp -= 2;
case 2:
rx_cmp --;
case 1:
rx_cmp --;
}
if (*rx_cmp == obj->char_match) {
obj->char_found = 1;
@ -1190,6 +1087,45 @@ static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t
serial_enable_interrupt(obj, RxIrq, enable);
}
static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
{
if (enable) {
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
NVIC_EnableIRQ(modinit->irq_n);
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
// Multiple serial S/W objects for single UART H/W module possibly.
// Bind serial S/W object to UART H/W module as interrupt is enabled.
var->obj = obj;
switch (irq) {
// NOTE: Setting inten_msk first to avoid race condition
case RxIrq:
obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
break;
case TxIrq:
obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
break;
}
} else { // disable
switch (irq) {
case RxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
break;
case TxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
break;
}
}
}
static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
{
@ -1212,13 +1148,27 @@ static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
*dma_usage = DMA_USAGE_NEVER;
}
}
else {
} else {
dma_channel_free(*dma_ch);
*dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
}
}
#endif //#ifndef NVT_SERIAL_SYNC_ONLY
static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
{
int inten_msk = 0;
switch (irq) {
case RxIrq:
inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
break;
case TxIrq:
inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
break;
}
return !! inten_msk;
}
#endif // #if DEVICE_SERIAL_ASYNCH
#endif // #if DEVICE_SERIAL
#endif // #if DEVICE_SERIAL