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STM32F1 STM32Cube FW V1.8.0: update for MBED

pull/13086/head
jeromecoutant 2020-06-08 18:04:53 +02:00
parent c99c8b5036
commit dcf2490b5a
11 changed files with 36 additions and 25 deletions
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4
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/Legacy/stm32_hal_legacy.h
View File

@ -1409,7 +1409,7 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
// #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@ -1418,7 +1418,7 @@
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
// #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT

2
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/Legacy/stm32f1xx_hal_can_legacy.c
View File

@ -131,7 +131,7 @@
#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f1xx_hal_conf.h file'
#endif /* HAL_CAN_MODULE_ENABLED */
#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
// #warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/

2
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_adc.c
View File

@ -2057,7 +2057,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */

2
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_adc_ex.c
View File

@ -1209,7 +1209,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */

4
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_def.h
View File

@ -28,9 +28,9 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
#if defined(USE_HAL_LEGACY)
// #if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
#endif
// #endif
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/

30
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_eth.c
View File

@ -882,7 +882,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
uint32_t bufcount = 0U, size = 0U, i = 0U;
/* Process Locked */
__HAL_LOCK(heth);
// MBED patch
//__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
@ -893,7 +894,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
return HAL_ERROR;
}
@ -905,7 +907,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->State = HAL_ETH_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
return HAL_ERROR;
}
@ -978,7 +981,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
@ -995,7 +999,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
uint32_t framelength = 0U;
/* Process Locked */
__HAL_LOCK(heth);
// MBED patch
//__HAL_LOCK(heth);
/* Check the ETH state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
@ -1031,7 +1036,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
@ -1058,7 +1064,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;
@ -1075,7 +1082,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
uint32_t descriptorscancounter = 0U;
/* Process Locked */
__HAL_LOCK(heth);
// MBED patch
//__HAL_LOCK(heth);
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
@ -1132,7 +1140,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
@ -1143,7 +1152,8 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
// MBED patch
//__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;

2
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_iwdg.c
View File

@ -104,7 +104,7 @@
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
#define HAL_IWDG_DEFAULT_TIMEOUT 96U // MBED
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_rtc.c
View File

@ -221,8 +221,6 @@
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc);
static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter);
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc);
static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter);
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
@ -1584,7 +1582,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
* the configuration information for RTC.
* @retval Time counter
*/
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc)
uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc)
{
uint16_t high1 = 0U, high2 = 0U, low = 0U;
uint32_t timecounter = 0U;
@ -1616,7 +1614,7 @@ static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc)
* @param TimeCounter: Counter to write in RTC_CNT registers
* @retval HAL status
*/
static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
{
HAL_StatusTypeDef status = HAL_OK;

3
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_rtc.h
View File

@ -549,6 +549,9 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_usart.c
View File

@ -2767,7 +2767,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
if((husart->Instance == USART1))
if (husart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);

4
targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/stm32f1xx_hal_conf.h
View File

@ -36,8 +36,8 @@ extern "C" {
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
#define HAL_CAN_LEGACY_MODULE_ENABLED // MBED
#define HAL_CEC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED