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Removed Toshiba target AdBun-M066, M3H6 and M3HQ. 

---
AdBun-M066

Removed from targets.json
5d64e55880/targets/targets.json (L12900-L12941)

Deleted directory
https://github.com/ARMmbed/mbed-os/tree/master/targets/TARGET_TOSHIBA/TARGET_TMPM066

Removed from mbed_rtx.h
5d64e55880/targets/TARGET_TOSHIBA/mbed_rtx.h (L23-L33)
---

AdBun-M3H6

Removed from targets.json
5d64e55880/targets/targets.json (L13465-L13507)

Deleted directory
https://github.com/ARMmbed/mbed-os/tree/master/targets/TARGET_TOSHIBA/TARGET_TMPM3H6

Removed from mbed_rtx.h
5d64e55880/targets/TARGET_TOSHIBA/mbed_rtx.h (L47-L53)
---

AdBun-M3HQ

Removed from targets.json
5d64e55880/targets/targets.json (L14159-L14208)

Deleted directory
https://github.com/ARMmbed/mbed-os/tree/master/targets/TARGET_TOSHIBA/TARGET_TMPM3HQ

Removed from mbed_rtx.h
5d64e55880/targets/TARGET_TOSHIBA/mbed_rtx.h (L63-L69)
---
pull/12746/head
Deepak Shreshti 2020-04-02 16:05:41 +05:30
parent 7b0c38aabb
commit dc4f086129
124 changed files with 0 additions and 44115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

207
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h
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/**
*******************************************************************************
* @file tmpm066_adc.h
* @brief This file provides all the functions prototypes for ADC driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_ADC_H
#define __TMPM066_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_ADC_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Exported_Types
* @{
*/
#define ADC_CONVERSION_35_CLOCK ((uint32_t)0x00000000) /* 35.5 conversion clock */
#define ADC_CONVERSION_42_CLOCK ((uint32_t)0x00000040) /* 42 conversion clock */
#define ADC_CONVERSION_68_CLOCK ((uint32_t)0x00000080) /* 68 conversion clock */
#define ADC_CONVERSION_81_CLOCK ((uint32_t)0x000000C0) /* 81 conversion clock */
#define IS_ADC_CONVERSION_TIME(param) (((param) == ADC_CONVERSION_35_CLOCK) || \
((param) == ADC_CONVERSION_42_CLOCK) || \
((param) == ADC_CONVERSION_68_CLOCK) || \
((param) == ADC_CONVERSION_81_CLOCK))
#define ADC_FC_DIVIDE_LEVEL_1 ((uint32_t)0x00000000)
#define ADC_FC_DIVIDE_LEVEL_2 ((uint32_t)0x00000001)
#define ADC_FC_DIVIDE_LEVEL_4 ((uint32_t)0x00000002)
#define ADC_FC_DIVIDE_LEVEL_6 ((uint32_t)0x00000008)
#define ADC_FC_DIVIDE_LEVEL_8 ((uint32_t)0x00000003)
#define ADC_FC_DIVIDE_LEVEL_12 ((uint32_t)0x00000009)
#define ADC_FC_DIVIDE_LEVEL_16 ((uint32_t)0x00000004)
#define ADC_FC_DIVIDE_LEVEL_24 ((uint32_t)0x0000000A)
#define ADC_FC_DIVIDE_LEVEL_48 ((uint32_t)0x0000000B)
#define ADC_FC_DIVIDE_LEVEL_96 ((uint32_t)0x0000000C)
#define IS_ADC_PRESCALER(param) (((param) == ADC_FC_DIVIDE_LEVEL_1) || \
((param) == ADC_FC_DIVIDE_LEVEL_2) || \
((param) == ADC_FC_DIVIDE_LEVEL_4) || \
((param) == ADC_FC_DIVIDE_LEVEL_6) || \
((param) == ADC_FC_DIVIDE_LEVEL_8) || \
((param) == ADC_FC_DIVIDE_LEVEL_12) || \
((param) == ADC_FC_DIVIDE_LEVEL_16) || \
((param) == ADC_FC_DIVIDE_LEVEL_24) || \
((param) == ADC_FC_DIVIDE_LEVEL_48) || \
((param) == ADC_FC_DIVIDE_LEVEL_96))
#define ADC_INT_SINGLE ((uint32_t)0x00000000)
#define ADC_INT_CONVERSION_4 ((uint32_t)0x00000008)
#define ADC_INT_CONVERSION_8 ((uint32_t)0x00000010)
#define IS_ADC_INT_MODE(param) (((param) == ADC_INT_SINGLE) || \
((param) == ADC_INT_CONVERSION_4) || \
((param) == ADC_INT_CONVERSION_8))
#define ADC_AN_0 ((uint32_t)0x00000000)
#define ADC_AN_1 ((uint32_t)0x00000001)
#define ADC_AN_2 ((uint32_t)0x00000002)
#define ADC_AN_3 ((uint32_t)0x00000003)
#define ADC_AN_4 ((uint32_t)0x00000004)
#define ADC_AN_5 ((uint32_t)0x00000005)
#define ADC_AN_6 ((uint32_t)0x00000006)
#define ADC_AN_7 ((uint32_t)0x00000007)
#define IS_ADC_INPUT_CH(param) (((param) == ADC_AN_0) || \
((param) == ADC_AN_1) || \
((param) == ADC_AN_2) || \
((param) == ADC_AN_3) || \
((param) == ADC_AN_4) || \
((param) == ADC_AN_5) || \
((param) == ADC_AN_6) || \
((param) == ADC_AN_7))
#define ADC_CMP_0 ((uint8_t)0x00)
#define ADC_CMP_1 ((uint8_t)0x01)
#define IS_ADC_CMP(param) (((param) == ADC_CMP_0) || \
((param) == ADC_CMP_1))
#define ADC_REG_0 ((uint32_t)0x00000000)
#define ADC_REG_1 ((uint32_t)0x00000001)
#define ADC_REG_2 ((uint32_t)0x00000002)
#define ADC_REG_3 ((uint32_t)0x00000003)
#define ADC_REG_4 ((uint32_t)0x00000004)
#define ADC_REG_5 ((uint32_t)0x00000005)
#define ADC_REG_6 ((uint32_t)0x00000006)
#define ADC_REG_7 ((uint32_t)0x00000007)
#define ADC_REG_SP ((uint32_t)0x00000008)
#define IS_ADC_REG(param) ((param) <= ADC_REG_SP)
#define IS_ADC_RESULT_CMP_REG(param) ((param) <= ADC_REG_SP)
#define ADC_EXT_TRG ((uint32_t)0x00000000)
#define ADC_MATCH_TB_0 ((uint32_t)0x00000020)
#define IS_ADC_HW_TRG_NORMAL(param) (((param) == ADC_EXT_TRG) || \
((param) == ADC_MATCH_TB_0))
#define ADC_MATCH_TB_1 ((uint32_t)0x00000080)
#define IS_ADC_HW_TRG_TOP(param) (((param) == ADC_EXT_TRG) || \
((param) == ADC_MATCH_TB_1))
#define IS_ADC_CMP_VALUE(param) ((param) <= (uint16_t)0x03ff)
typedef enum {
ADC_NO_OVERRUN = 0U,
ADC_OVERRUN = 1U
} ADC_OverrunState;
typedef enum {
ADC_SCAN_4CH = 0U,
ADC_SCAN_8CH = 1U
} ADC_ChannelScanMode;
#define IS_ADC_CH_SCAN_MODE(param) (((param) == ADC_SCAN_4CH) || \
((param) == ADC_SCAN_8CH))
typedef enum {
ADC_COMPARISON_SMALLER = 0U,
ADC_COMPARISON_LARGER = 1U
} ADC_ComparisonState;
#define IS_ADC_CMP_INT(param) (((param) == ADC_COMPARISON_SMALLER) || \
((param) == ADC_COMPARISON_LARGER))
typedef struct {
WorkState ADCResultStored; /*!< ADC result storage flag */
ADC_OverrunState ADCOverrunState; /*!< ADC overrun flag */
uint16_t ADCResultValue; /*!< ADC result value */
} ADC_ResultTypeDef;
#define ADC_DMA_REQ_NORMAL ((uint8_t)0x00)
#define ADC_DMA_REQ_TOP ((uint8_t)0x01)
#define ADC_DMA_REQ_MONITOR1 ((uint8_t)0x02)
#define ADC_DMA_REQ_MONITOR2 ((uint8_t)0x03)
#define IS_ADC_DMA_REQ(param) ((param) <= ADC_DMA_REQ_MONITOR2)
typedef union {
uint32_t All;
struct {
uint32_t NormalBusy:1; /*!< bit0, Normal A/D conversion busy flag (MOD0<ADBFN>) */
uint32_t NormalComplete:1; /*!< bit1, Normal AD conversion complete flag (MOD0<EOCFN>) */
uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (MOD2<ADBFHP>) */
uint32_t TopComplete:1; /*!< bit3, Top-priority AD conversion complete flag (MOD2<EOCFHP>) */
uint32_t Reserved:28; /*!< bit4 to bit 31, reserved */
} Bit;
} ADC_State;
/** @} */
/* End of group ADC_Exported_Types */
/** @defgroup ADC_Exported_FunctionPrototypes
* @{
*/
void ADC_SWReset(void);
void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output);
void ADC_Start(void);
void ADC_SetScanMode(FunctionalState NewState);
void ADC_SetRepeatMode(FunctionalState NewState);
void ADC_SetINTMode(uint32_t INTMode);
ADC_State ADC_GetConvertState(void);
void ADC_SetInputChannel(uint32_t InputChannel);
void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode);
void ADC_SetIdleMode(FunctionalState NewState);
void ADC_SetVref(FunctionalState NewState);
void ADC_SetInputChannelTop(uint32_t TopInputChannel);
void ADC_StartTopConvert(void);
void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState);
void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison);
void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState);
void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState);
void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState);
ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx);
void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value);
void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState);
/** @} */
/* End of group ADC_Exported_FunctionPrototypes */
/** @} */
/* End of group ADC */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* (__TMPM066_ADC_H) */
#ifdef __cplusplus
}
#endif
#endif /* __TMPM066_ADC_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h
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@ -1,180 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_cg.h
* @brief This file provides all the functions prototypes for CG driver.
* @version V2.0.2.1
* @date 2015/09/29
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_CG_H
#define __TMPM066_CG_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup CG
* @{
*/
/** @addtogroup CG_Exported_types
* @{
*/
typedef enum {
CG_DIVIDE_1 = 0U,
CG_DIVIDE_2 = 1U,
CG_DIVIDE_4 = 2U,
CG_DIVIDE_8 = 3U,
CG_DIVIDE_16 = 4U,
CG_DIVIDE_32 = 5U,
CG_DIVIDE_64 = 6U,
CG_DIVIDE_128 = 7U,
CG_DIVIDE_256 = 8U,
CG_DIVIDE_512 = 9U,
CG_DIVIDE_UNKNOWN = 10U,
CG_DIVIDE_MAX = 16U
} CG_DivideLevel;
#define IS_CG_GEAR_DIVIDE_LEVEL(param) (((param) == CG_DIVIDE_1) || \
((param) == CG_DIVIDE_2) || \
((param) == CG_DIVIDE_4) || \
((param) == CG_DIVIDE_8) || \
((param) == CG_DIVIDE_16))
#define IS_CG_DIVIDE_FC_LEVEL(param) (((param) == CG_DIVIDE_1) || \
((param) == CG_DIVIDE_2) || \
((param) == CG_DIVIDE_4) || \
((param) == CG_DIVIDE_8) || \
((param) == CG_DIVIDE_16) || \
((param) == CG_DIVIDE_32) || \
((param) == CG_DIVIDE_64)|| \
((param) == CG_DIVIDE_128) || \
((param) == CG_DIVIDE_256) || \
((param) == CG_DIVIDE_512))
typedef enum {
CG_FOSC_OSC_INT = 0U,
CG_FOSC_OSC_EXT = 1U,
CG_FOSC_CLKIN_EXT = 2U
} CG_FoscSrc;
#define IS_CG_FOSC_SRC(param) (((param) == CG_FOSC_OSC_EXT) || \
((param) == CG_FOSC_OSC_INT) || \
((param) == CG_FOSC_CLKIN_EXT))
#define IS_CG_FOSC_STATE(param) (((param) == CG_FOSC_OSC_EXT) || \
((param) == CG_FOSC_OSC_INT) )
typedef enum {
CG_WARM_UP_SRC_OSC_INT_HIGH = 0U,
CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U,
} CG_WarmUpSrc;
#define IS_CG_WARM_UP_SRC(param) (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \
((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH))
typedef enum {
CG_FC_SRC_FOSC = 0U,
CG_FC_SRC_FPLL = 1U
} CG_FcSrc;
#define IS_CG_FC_SRC(param) (((param) == CG_FC_SRC_FOSC) || \
((param) == CG_FC_SRC_FPLL))
#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U) /* 12 fold, input 8MHz, output 96MHz */
#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U) /* 10 fold, input 10MHz, output 80MHz */
#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U) /* 12 fold, input 12MHz, output 96MHz */
#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U) /* 16 fold, input 16MHz, output 96MHz */
#define IS_CG_FPLL_VALUE(param) (((param) == CG_8M_MUL_12_FPLL) || \
((param) == CG_10M_MUL_8_FPLL) || \
((param) == CG_12M_MUL_8_FPLL) || \
((param) == CG_16M_MUL_6_FPLL))
typedef enum {
CG_STBY_MODE_IDLE = 0U,
CG_STBY_MODE_STOP1 = 1U,
CG_STBY_MODE_UNKNOWN = 2U,
CG_STBY_MODE_MAX = 4U
} CG_STBYMode;
#define IS_CG_STBY_MODE(param) (((param) == CG_STBY_MODE_STOP1) || \
((param) == CG_STBY_MODE_IDLE))
#define CG_FC_PERIPH_PORTH (0x00000001U << 7U)
#define CG_FC_PERIPH_PORTJ (0x00000001U << 8U)
#define CG_FC_PERIPH_TMRB0_3 (0x00000001U << 9U)
#define CG_FC_PERIPH_TMRB4_6 (0x00000001U << 10U)
#define CG_FC_PERIPH_TMR16A (0x00000001U << 11U)
#define CG_FC_PERIPH_I2C0 (0x00000001U << 12U)
#define CG_FC_PERIPH_SIO0 (0x00000001U << 13U)
#define CG_FC_PERIPH_TSPI (0x00000001U << 14U)
#define CG_FC_PERIPH_DMAC (0x00000001U << 15U)
#define CG_FC_PERIPH_ADC (0x00000001U << 16U)
#define CG_FC_PERIPH_USBD (0x00000001U << 17U)
#define CG_FC_PERIPH_TMRD (0x00000001U << 18U)
#define CG_FC_PERIPHA_ALL (0xFFFFFFFFU)
#define IS_CG_FC_PERIPHA(param) ( ((param) >= CG_FC_PERIPH_PORTH) && ((param) <= CG_FC_PERIPH_TMRD ))
#define CG_FC_PERIPH_TMRB7 (0x00000001U << 28U)
#define CG_FC_PERIPH_SIO1 (0x00000001U << 29U)
#define CG_FC_PERIPH_WDT (0x00000001U << 30U)
#define CG_FC_PERIPH_I2C1 (0x00000001U << 31U)
#define CG_FC_PERIPHB_ALL (0xFFFFFFFFU)
#define IS_CG_FC_PERIPHB(param) (((param) >= CG_FC_PERIPH_TMRB7))
#define CG_FPLL_PERIPH_TMRD (0x00000001U << 5U)
#define CG_EHCLKSEL_8_24_48MHZ (0x00000001U << 4U)
#define CG_USBSEL_PLL_CLOCKIN (0x00000001U << 1U)
#define CG_USBENA_USB (0x00000001U)
#define CG_FPLL_OPTIONAL_ALL (0x0FFFFFFFU)
#define IS_CG_FPLL_OPTIONAL(param) (((param) > 0U) && ((param) <= CG_FPLL_OPTIONAL_ALL))
/** @} */
/* End of group CG_Exported_types */
/** @defgroup CG_Exported_FunctionPrototypes
* @{
*/
void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc);
CG_DivideLevel CG_GetFgearLevel(void);
Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc);
CG_DivideLevel CG_GetPhiT0Level(void);
void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time);
void CG_StartWarmUp(void);
WorkState CG_GetWarmUpState(void);
Result CG_SetFPLLValue(uint32_t NewValue);
uint32_t CG_GetFPLLValue(void);
Result CG_SetPLL(FunctionalState NewState);
FunctionalState CG_GetPLLState(void);
void CG_SetFoscSrc(CG_FoscSrc Source);
CG_FoscSrc CG_GetFoscSrc(void);
void CG_SetSTBYMode(CG_STBYMode Mode);
CG_STBYMode CG_GetSTBYMode(void);
void CG_SetFcSrc(CG_FcSrc Source);
CG_FcSrc CG_GetFcSrc(void);
void CG_SetProtectCtrl(FunctionalState NewState);
void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState);
void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState);
void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState);
void CG_SetADCClkSupply(FunctionalState NewState);
/** @} */
/* End of group CG_Exported_FunctionPrototype */
/** @} */
/* End of group CG */
/** @} */
/* End of group TX00_Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_CG_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h
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@ -1,229 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_gpio.h
* @brief This file provides all the functions prototypes for GPIO driver.
* @version V2.0.2.1
* @date 2015/09/29
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_GPIO_H
#define __TMPM066_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_GPIO_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @addtogroup GPIO_Parameter_Definition
* @{
*/
/** @brief :The maximum number of the Function Register
* Note for porting:
* If functiong register 2 is the maximum number in
* all the GPIO port,then define FRMAX (2U)
*/
#define FRMAX (2U) /* the max number of Port I/O function register is 2 */
/** @brief: define for function register
* Note for porting:
* If the maximum number of the function Register is 2,
* then you need to define 2 GPIO_FUNC_REG_x ,
* the value should be increased from 0 to 1
*/
#define GPIO_FUNC_REG_1 ((uint8_t)0x00)
#define GPIO_FUNC_REG_2 ((uint8_t)0x01)
/** @brief :The GPIO_Port enum
* Note for porting:
* the port value order from low to high with '1' step
* and begin with "0".
*/
typedef enum {
GPIO_PA = 0U,
GPIO_PB = 1U,
GPIO_PC = 2U,
GPIO_PD = 3U,
GPIO_PE = 4U,
GPIO_PF = 5U,
GPIO_PG = 6U,
GPIO_PH = 7U,
GPIO_PJ = 8U
} GPIO_Port;
#define IS_GPIO_PORT(param) ((param) <= GPIO_PJ) /*parameter checking for port number */
#define IS_GPIO_PORT_INPUT_VOLTAGE(param) (((param) == GPIO_PC) || \
((param) == GPIO_PD) || \
((param) == GPIO_PG))
#define RESER (8U-(FRMAX))
typedef struct {
__IO uint32_t DATA;
__IO uint32_t CR;
__IO uint32_t FR[FRMAX];
uint32_t RESERVED0[RESER];
__IO uint32_t OD;
__IO uint32_t PUP;
__IO uint32_t PDN;
__IO uint32_t SEL;
__IO uint32_t IE;
} TSB_Port_TypeDef;
typedef struct {
uint8_t PinDATA;
uint8_t PinCR;
uint8_t PinFR[FRMAX];
uint8_t PinOD;
uint8_t PinPUP;
uint8_t PinPDN;
uint8_t PinSEL;
uint8_t PinIE;
} GPIO_RegTypeDef;
typedef struct {
uint8_t IOMode; /* Set the port input or output mode */
uint8_t PullUp; /* Enable or disable Pullup function */
uint8_t OpenDrain; /* Enable or disable open drain function */
uint8_t PullDown; /* Enable or disable Pulldown function */
uint8_t InputVoltage; /* Enable or disable Input Voltage function */
} GPIO_InitTypeDef;
#define GPIO_INPUT_MODE ((uint8_t)0x00)
#define GPIO_OUTPUT_MODE ((uint8_t)0x01)
#define GPIO_IO_MODE_NONE ((uint8_t)0x02)
#define IS_GPIO_IO_MODE_STATE(param) (((param) == GPIO_INPUT_MODE) || \
((param) == GPIO_OUTPUT_MODE) || \
((param) == GPIO_IO_MODE_NONE))
#define GPIO_PULLUP_DISABLE ((uint8_t)0x00)
#define GPIO_PULLUP_ENABLE ((uint8_t)0x01)
#define GPIO_PULLUP_NONE ((uint8_t)0x02)
#define IS_GPIO_PULLUP_STATE(param) (((param) == GPIO_PULLUP_ENABLE) || \
((param) == GPIO_PULLUP_DISABLE) || \
((param) == GPIO_PULLUP_NONE))
#define GPIO_PULLDOWN_DISABLE ((uint8_t)0x00)
#define GPIO_PULLDOWN_ENABLE ((uint8_t)0x01)
#define GPIO_PULLDOWN_NONE ((uint8_t)0x02)
#define IS_GPIO_PULLDOWN_STATE(param) (((param) == GPIO_PULLDOWN_ENABLE) || \
((param) == GPIO_PULLDOWN_DISABLE) || \
((param) == GPIO_PULLDOWN_NONE))
#define GPIO_OPEN_DRAIN_DISABLE ((uint8_t)0x00)
#define GPIO_OPEN_DRAIN_ENABLE ((uint8_t)0x01)
#define GPIO_OPEN_DRAIN_NONE ((uint8_t)0x02)
#define IS_GPIO_OPEN_DRAIN_STATE(param) (((param) == GPIO_OPEN_DRAIN_ENABLE) || \
((param) == GPIO_OPEN_DRAIN_DISABLE) || \
((param) == GPIO_OPEN_DRAIN_NONE))
#define GPIO_INPUT_VOLTAGE_3V ((uint8_t)0x00)
#define GPIO_INPUT_VOLTAGE_1V8 ((uint8_t)0x01)
#define GPIO_INPUT_VOLTAGE_NONE ((uint8_t)0x02)
#define IS_GPIO_INPUT_VOLTAGE_STATE(param) (((param) == GPIO_INPUT_VOLTAGE_3V) || \
((param) == GPIO_INPUT_VOLTAGE_1V8) || \
((param) == GPIO_INPUT_VOLTAGE_NONE))
#define GPIO_BIT_VALUE_1 ((uint8_t)0x01)
#define GPIO_BIT_VALUE_0 ((uint8_t)0x00)
#define IS_GPIO_BIT_VALUE(BitValue) (((BitValue) == GPIO_BIT_VALUE_1)|| \
((BitValue) == GPIO_BIT_VALUE_0))
#define GPIO_BIT_0 ((uint8_t)0x01)
#define GPIO_BIT_1 ((uint8_t)0x02)
#define GPIO_BIT_2 ((uint8_t)0x04)
#define GPIO_BIT_3 ((uint8_t)0x08)
#define GPIO_BIT_4 ((uint8_t)0x10)
#define GPIO_BIT_5 ((uint8_t)0x20)
#define GPIO_BIT_6 ((uint8_t)0x40)
#define GPIO_BIT_7 ((uint8_t)0x80)
#define GPIO_BIT_ALL ((uint8_t)0xFF)
#define IS_GPIO_WRITE(GPIO_x) (GPIO_SFRs[(GPIO_x)].PinCR)
#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x) ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\
(!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x)))))
#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x)))))
#define IS_GPIO_BIT_IN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x)))))
#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x)))))
#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x)))))
#define IS_GPIO_BIT_OD(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x)))))
#define IS_GPIO_BIT_SEL(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinSEL &(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinSEL)&(Bit_x)))))
#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x)))))
#define IS_GPIO_FUNCTION_REG(param) ((param) < (FRMAX))
#define IS_GPIO_BIT(param) (((param) == GPIO_BIT_0)|| \
((param) == GPIO_BIT_1)|| \
((param) == GPIO_BIT_2)|| \
((param) == GPIO_BIT_3)|| \
((param) == GPIO_BIT_4)|| \
((param) == GPIO_BIT_5)|| \
((param) == GPIO_BIT_6)|| \
((param) == GPIO_BIT_7))
/** @} */
/* End of group GPIO_Bit_Define */
/** @defgroup GPIO_Exported_FunctionPrototypes
* @{
*/
uint8_t GPIO_ReadData(GPIO_Port GPIO_x);
uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x);
void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data);
void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct);
void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x);
void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x);
void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
/** @} */
/* End of group GPIO_Exported_FunctionPrototypes */
/** @} */
/* End of group GPIO */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_GPIO_H) */
#ifdef __cplusplus
}
#endif
#endif /* __TMPM066_GPIO_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h
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@ -1,203 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_i2c.h
* @brief This file provides all the functions prototypes for I2C driver.
* @version V2.0.2.1
* @date 2015/09/10
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_I2C_H
#define __TMPM066_I2C_H
#ifdef __cplusplus
extern "C" {
#endif /*__cplusplus*/
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_I2C_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Exported_Types
* @{
*/
typedef struct {
uint32_t I2CSelfAddr; /*!< Specify self-address of the I2C channel in I2C mode */
uint32_t I2CDataLen; /*!< Specify data length of the I2C channel in I2C mode */
FunctionalState I2CACKState; /*!< Enable or disable the generation of ACK clock */
uint32_t I2CClkDiv; /*!< Select the division of the prescaler clock for generating the serial clock */
uint32_t PrescalerClkDiv; /* Select the division of fsys for generating the fprsck */
} I2C_InitTypeDef;
typedef union {
uint32_t All;
struct {
uint32_t LastRxBit:1;
uint32_t GeneralCall:1;
uint32_t SlaveAddrMatch:1;
uint32_t ArbitrationLost:1;
uint32_t INTReq:1;
uint32_t BusState:1;
uint32_t TRx:1;
uint32_t MasterSlave:1;
} Bit;
} I2C_State;
#define I2C_CHANNEL_NUMBER 2U
#define IS_I2C_PERIPH(param) (((param) == TSB_I2C0) || \
((param) == TSB_I2C1))
#define I2C_DATA_LEN_8 ((uint32_t)0x00000000)
#define I2C_DATA_LEN_1 ((uint32_t)0x00000001)
#define I2C_DATA_LEN_2 ((uint32_t)0x00000002)
#define I2C_DATA_LEN_3 ((uint32_t)0x00000003)
#define I2C_DATA_LEN_4 ((uint32_t)0x00000004)
#define I2C_DATA_LEN_5 ((uint32_t)0x00000005)
#define I2C_DATA_LEN_6 ((uint32_t)0x00000006)
#define I2C_DATA_LEN_7 ((uint32_t)0x00000007)
#define I2C_SCK_CLK_DIV_20 ((uint32_t)0x00000000)
#define I2C_SCK_CLK_DIV_24 ((uint32_t)0x00000001)
#define I2C_SCK_CLK_DIV_32 ((uint32_t)0x00000002)
#define I2C_SCK_CLK_DIV_48 ((uint32_t)0x00000003)
#define I2C_SCK_CLK_DIV_80 ((uint32_t)0x00000004)
#define I2C_SCK_CLK_DIV_144 ((uint32_t)0x00000005)
#define I2C_SCK_CLK_DIV_272 ((uint32_t)0x00000006)
#define I2C_SCK_CLK_DIV_528 ((uint32_t)0x00000007)
#define IS_I2C_SCK_CLK_DIV(param) (((param) == I2C_SCK_CLK_DIV_20) || \
((param) == I2C_SCK_CLK_DIV_24) || \
((param) == I2C_SCK_CLK_DIV_32) || \
((param) == I2C_SCK_CLK_DIV_48) || \
((param) == I2C_SCK_CLK_DIV_80) || \
((param) == I2C_SCK_CLK_DIV_144) || \
((param) == I2C_SCK_CLK_DIV_272) || \
((param) == I2C_SCK_CLK_DIV_528))
#define I2C_PRESCALER_DIV_1 ((uint32_t)0x00000001)
#define I2C_PRESCALER_DIV_2 ((uint32_t)0x00000002)
#define I2C_PRESCALER_DIV_3 ((uint32_t)0x00000003)
#define I2C_PRESCALER_DIV_4 ((uint32_t)0x00000004)
#define I2C_PRESCALER_DIV_5 ((uint32_t)0x00000005)
#define I2C_PRESCALER_DIV_6 ((uint32_t)0x00000006)
#define I2C_PRESCALER_DIV_7 ((uint32_t)0x00000007)
#define I2C_PRESCALER_DIV_8 ((uint32_t)0x00000008)
#define I2C_PRESCALER_DIV_9 ((uint32_t)0x00000009)
#define I2C_PRESCALER_DIV_10 ((uint32_t)0x0000000A)
#define I2C_PRESCALER_DIV_11 ((uint32_t)0x0000000B)
#define I2C_PRESCALER_DIV_12 ((uint32_t)0x0000000C)
#define I2C_PRESCALER_DIV_13 ((uint32_t)0x0000000D)
#define I2C_PRESCALER_DIV_14 ((uint32_t)0x0000000E)
#define I2C_PRESCALER_DIV_15 ((uint32_t)0x0000000F)
#define I2C_PRESCALER_DIV_16 ((uint32_t)0x00000010)
#define I2C_PRESCALER_DIV_17 ((uint32_t)0x00000011)
#define I2C_PRESCALER_DIV_18 ((uint32_t)0x00000012)
#define I2C_PRESCALER_DIV_19 ((uint32_t)0x00000013)
#define I2C_PRESCALER_DIV_20 ((uint32_t)0x00000014)
#define I2C_PRESCALER_DIV_21 ((uint32_t)0x00000015)
#define I2C_PRESCALER_DIV_22 ((uint32_t)0x00000016)
#define I2C_PRESCALER_DIV_23 ((uint32_t)0x00000017)
#define I2C_PRESCALER_DIV_24 ((uint32_t)0x00000018)
#define I2C_PRESCALER_DIV_25 ((uint32_t)0x00000019)
#define I2C_PRESCALER_DIV_26 ((uint32_t)0x0000001A)
#define I2C_PRESCALER_DIV_27 ((uint32_t)0x0000001B)
#define I2C_PRESCALER_DIV_28 ((uint32_t)0x0000001C)
#define I2C_PRESCALER_DIV_29 ((uint32_t)0x0000001D)
#define I2C_PRESCALER_DIV_30 ((uint32_t)0x0000001E)
#define I2C_PRESCALER_DIV_31 ((uint32_t)0x0000001F)
#define I2C_PRESCALER_DIV_32 ((uint32_t)0x00000020)
/** @} */
/* End of group I2C_Exported_Types */
/** @defgroup I2C_Exported_Macros
* @{
*/
#define IS_PRESCALER_CLK_VALID(param1, param2) (((param1) >= I2C_PRESCALER_DIV_1) && \
((param1) <= I2C_PRESCALER_DIV_32) && \
(((param2) / (param1)) > 666666U) && \
(((param2) / (param1)) < 20000000U))
#define IS_I2C_DATA(param) ((param) <= (uint32_t)0x000000FF)
#define IS_I2C_BIT_NUM(param) ((param) <= (uint32_t)0x00000007)
#define IS_I2C_ADDR(param) (((param) < (uint32_t)0x000000FF) && \
(!((param) & (uint32_t)0x00000001)))
/** @} */
/* End of group I2C_Exported_Macros */
/** @defgroup I2C_Exported_FunctionPrototypes
* @{
*/
void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct);
void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum);
void I2C_SWReset(TSB_I2C_TypeDef * I2Cx);
void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx);
void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx);
void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx);
I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx);
void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data);
uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx);
void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx);
void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock);
void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx);
FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx);
FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx);
FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx);
void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx);
void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx);
void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx);
void I2C_ClearINTI2COutput(TSB_I2C_TypeDef * I2Cx);
void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx);
void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx);
/** @} */
/* End of group I2C_Exported_FunctionPrototypes */
/** @} */
/* End of group I2C */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_I2C_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_I2C_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h
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@ -1,100 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_intifao.h
* @brief This file provides all the functions prototypes for INTIFAO driver.
* @version V2.0.2.1
* @date 2015/10/19
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_INTIFAO_H
#define __TMPM066_INTIFAO_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup INTIFAO
* @{
*/
/** @addtogroup INTIFAO_Exported_types
* @{
*/
typedef struct {
uint32_t All;
} INTIFAO_IntFlag1Factor;
typedef enum {
INTIFAO_INT_SRC_0 = 0U,
INTIFAO_INT_SRC_1 = 1U,
INTIFAO_INT_SRC_2 = 2U,
INTIFAO_INT_SRC_3 = 3U,
INTIFAO_INT_SRC_4 = 4U,
INTIFAO_INT_SRC_5 = 5U,
INTIFAO_INT_SRC_I2CS = 6U,
INTIFAO_INT_SRC_USBWKUP = 7U
} INTIFAO_INTSrc;
#define IS_INTIFAO_INT_SRC(param) (((param) == INTIFAO_INT_SRC_0) || \
((param) == INTIFAO_INT_SRC_1) || \
((param) == INTIFAO_INT_SRC_2) || \
((param) == INTIFAO_INT_SRC_3) || \
((param) == INTIFAO_INT_SRC_4) || \
((param) == INTIFAO_INT_SRC_5) || \
((param) == INTIFAO_INT_SRC_I2CS) || \
((param) == INTIFAO_INT_SRC_USBWKUP))
typedef enum {
INTIFAO_INT_ACTIVE_STATE_L = 0x0U,
INTIFAO_INT_ACTIVE_STATE_H = 0x1U,
INTIFAO_INT_ACTIVE_STATE_FALLING = 0x2U,
INTIFAO_INT_ACTIVE_STATE_RISING = 0x3U,
INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES = 0x4U,
INTIFAO_INT_ACTIVE_STATE_INVALID = 0x5U
} INTIFAO_INTActiveState;
#define IS_INTIFAO_INT_ACTIVE_STATE(param) (((param) == INTIFAO_INT_ACTIVE_STATE_L) || \
((param) == INTIFAO_INT_ACTIVE_STATE_H) || \
((param) == INTIFAO_INT_ACTIVE_STATE_FALLING) || \
((param) == INTIFAO_INT_ACTIVE_STATE_RISING) || \
((param) == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES))
#define IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(param) ((param) == INTIFAO_INT_ACTIVE_STATE_RISING)
/** @} */
/* End of group INTIFAO_Exported_types */
/** @defgroup INTIFAO_Exported_FunctionPrototypes
* @{
*/
void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource,
INTIFAO_INTActiveState ActiveState, FunctionalState NewState);
INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource);
void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource);
INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void);
/** @} */
/* End of group INTIFAO_Exported_FunctionPrototype */
/** @} */
/* End of group INTIFAO */
/** @} */
/* End of group TX00_Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_INTIFAO_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h
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@ -1,228 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_intifsd.h
* @brief This file provides all the functions prototypes for INTIFSD driver.
* @version V2.0.2.2
* @date 2016/02/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_INTIFSD_H
#define __TMPM066_INTIFSD_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup INTIFSD
* @{
*/
/** @addtogroup INTIFSD_Exported_types
* @{
*/
typedef union {
uint32_t All;
struct {
uint32_t Reserved1:16;
uint32_t DetectLowVoltage:1;
uint32_t DetectOverVoltage:1;
uint32_t WDT:1;
uint32_t Reserved2:13;
} Bit;
} INTIFSD_NMIFactor;
typedef struct {
uint32_t All;
} INTIFSD_IntFlag3Factor;
typedef struct {
uint32_t All;
} INTIFSD_IntFlag4Factor;
typedef struct {
uint32_t All;
} INTIFSD_IntFlag5Factor;
typedef enum {
INTIFSD_INT_SRC_LVD_PSFD = 0U,
INTIFSD_INT_SRC_LVD_PRD = 1U,
INTIFSD_INT_SRC_WDT = 2U,
INTIFSD_INT_SRC_DMAC_0 = 3U,
INTIFSD_INT_SRC_DMAC_1 = 4U,
INTIFSD_INT_SRC_DMAC_2 = 5U,
INTIFSD_INT_SRC_DMAC_3 = 6U,
INTIFSD_INT_SRC_DMAC_4 = 7U,
INTIFSD_INT_SRC_DMAC_5 = 8U,
INTIFSD_INT_SRC_DMAC_6 = 9U,
INTIFSD_INT_SRC_DMAC_7 = 10U,
INTIFSD_INT_SRC_DMAC_8 = 11U,
INTIFSD_INT_SRC_DMAC_9 = 12U,
INTIFSD_INT_SRC_DMAC_10 = 13U,
INTIFSD_INT_SRC_DMAC_11 = 14U,
INTIFSD_INT_SRC_DMAC_12 = 15U,
INTIFSD_INT_SRC_DMAC_13 = 16U,
INTIFSD_INT_SRC_DMAC_14 = 17U,
INTIFSD_INT_SRC_DMAC_15 = 18U,
INTIFSD_INT_SRC_DMAC_16 = 19U,
INTIFSD_INT_SRC_DMAC_17 = 20U,
INTIFSD_INT_SRC_DMAC_18 = 21U,
INTIFSD_INT_SRC_DMAC_19 = 22U,
INTIFSD_INT_SRC_DMAC_20 = 23U,
INTIFSD_INT_SRC_DMAC_21 = 24U,
INTIFSD_INT_SRC_DMAC_22 = 25U,
INTIFSD_INT_SRC_DMAC_23 = 26U,
INTIFSD_INT_SRC_DMAC_24 = 27U,
INTIFSD_INT_SRC_DMAC_25 = 28U,
INTIFSD_INT_SRC_DMAC_26 = 29U,
INTIFSD_INT_SRC_DMAC_27 = 30U,
INTIFSD_INT_SRC_DMAC_28 = 31U,
INTIFSD_INT_SRC_DMAC_29 = 32U,
INTIFSD_INT_SRC_DMAC_30 = 33U,
INTIFSD_INT_SRC_DMAC_31 = 34U,
INTIFSD_INT_SRC_DMAC_ERR = 35U,
INTIFSD_INT_SRC_TMRB_0_MDOVF = 36U,
INTIFSD_INT_SRC_TMRB_0_CAP0 = 37U,
INTIFSD_INT_SRC_TMRB_0_CAP1 = 38U,
INTIFSD_INT_SRC_TMRB_1_MDOVF = 39U,
INTIFSD_INT_SRC_TMRB_1_CAP0 = 40U,
INTIFSD_INT_SRC_TMRB_1_CAP1 = 41U,
INTIFSD_INT_SRC_TMRB_2_MDOVF = 42U,
INTIFSD_INT_SRC_TMRB_2_CAP0 = 43U,
INTIFSD_INT_SRC_TMRB_2_CAP1 = 44U,
INTIFSD_INT_SRC_TMRB_3_MDOVF = 45U,
INTIFSD_INT_SRC_TMRB_3_CAP0 = 46U,
INTIFSD_INT_SRC_TMRB_3_CAP1 = 47U,
INTIFSD_INT_SRC_TMRB_4_MDOVF = 48U,
INTIFSD_INT_SRC_TMRB_4_CAP0 = 49U,
INTIFSD_INT_SRC_TMRB_4_CAP1 = 50U,
INTIFSD_INT_SRC_TMRB_5_MDOVF = 51U,
INTIFSD_INT_SRC_TMRB_5_CAP0 = 52U,
INTIFSD_INT_SRC_TMRB_5_CAP1 = 53U,
INTIFSD_INT_SRC_TMRB_6_MDOVF = 54U,
INTIFSD_INT_SRC_TMRB_6_CAP0 = 55U,
INTIFSD_INT_SRC_TMRB_6_CAP1 = 56U,
INTIFSD_INT_SRC_TMRB_7_MDOVF = 57U,
INTIFSD_INT_SRC_TMRB_7_CAP0 = 58U,
INTIFSD_INT_SRC_TMRB_7_CAP1 = 59U,
INTIFSD_INT_SRC_TMRD_00 = 60U,
INTIFSD_INT_SRC_TMRD_01 = 61U,
INTIFSD_INT_SRC_TMRD_02 = 62U,
INTIFSD_INT_SRC_TMRD_03 = 63U,
INTIFSD_INT_SRC_TMRD_04 = 64U,
INTIFSD_INT_SRC_TMRD_10 = 65U,
INTIFSD_INT_SRC_TMRD_11 = 66U,
INTIFSD_INT_SRC_TMRD_12 = 67U,
INTIFSD_INT_SRC_TMRD_13 = 68U,
INTIFSD_INT_SRC_TMRD_14 = 69U
} INTIFSD_INTSrc;
#define IS_INTIFSD_INT_SRC(param) (((param) == INTIFSD_INT_SRC_LVD_PSFD) || \
((param) == INTIFSD_INT_SRC_LVD_PRD) || \
((param) == INTIFSD_INT_SRC_WDT) || \
((param) == INTIFSD_INT_SRC_DMAC_0) || \
((param) == INTIFSD_INT_SRC_DMAC_1) || \
((param) == INTIFSD_INT_SRC_DMAC_2) || \
((param) == INTIFSD_INT_SRC_DMAC_3) || \
((param) == INTIFSD_INT_SRC_DMAC_4) || \
((param) == INTIFSD_INT_SRC_DMAC_5) || \
((param) == INTIFSD_INT_SRC_DMAC_6) || \
((param) == INTIFSD_INT_SRC_DMAC_7) || \
((param) == INTIFSD_INT_SRC_DMAC_8) || \
((param) == INTIFSD_INT_SRC_DMAC_9) || \
((param) == INTIFSD_INT_SRC_DMAC_10) || \
((param) == INTIFSD_INT_SRC_DMAC_11) || \
((param) == INTIFSD_INT_SRC_DMAC_12) || \
((param) == INTIFSD_INT_SRC_DMAC_13) || \
((param) == INTIFSD_INT_SRC_DMAC_14) || \
((param) == INTIFSD_INT_SRC_DMAC_15) || \
((param) == INTIFSD_INT_SRC_DMAC_16) || \
((param) == INTIFSD_INT_SRC_DMAC_17) || \
((param) == INTIFSD_INT_SRC_DMAC_18) || \
((param) == INTIFSD_INT_SRC_DMAC_19) || \
((param) == INTIFSD_INT_SRC_DMAC_20) || \
((param) == INTIFSD_INT_SRC_DMAC_21) || \
((param) == INTIFSD_INT_SRC_DMAC_22) || \
((param) == INTIFSD_INT_SRC_DMAC_23) || \
((param) == INTIFSD_INT_SRC_DMAC_24) || \
((param) == INTIFSD_INT_SRC_DMAC_25) || \
((param) == INTIFSD_INT_SRC_DMAC_26) || \
((param) == INTIFSD_INT_SRC_DMAC_27) || \
((param) == INTIFSD_INT_SRC_DMAC_28) || \
((param) == INTIFSD_INT_SRC_DMAC_29) || \
((param) == INTIFSD_INT_SRC_DMAC_30) || \
((param) == INTIFSD_INT_SRC_DMAC_31) || \
((param) == INTIFSD_INT_SRC_DMAC_ERR) || \
((param) == INTIFSD_INT_SRC_TMRB_0_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_0_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_0_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_1_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_1_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_1_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_2_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_2_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_2_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_3_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_3_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_3_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_4_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_4_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_4_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_5_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_5_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_5_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_6_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_6_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_6_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRB_7_MDOVF) || \
((param) == INTIFSD_INT_SRC_TMRB_7_CAP0) || \
((param) == INTIFSD_INT_SRC_TMRB_7_CAP1) || \
((param) == INTIFSD_INT_SRC_TMRD_00) || \
((param) == INTIFSD_INT_SRC_TMRD_01) || \
((param) == INTIFSD_INT_SRC_TMRD_02) || \
((param) == INTIFSD_INT_SRC_TMRD_03) || \
((param) == INTIFSD_INT_SRC_TMRD_04) || \
((param) == INTIFSD_INT_SRC_TMRD_10) || \
((param) == INTIFSD_INT_SRC_TMRD_11) || \
((param) == INTIFSD_INT_SRC_TMRD_12) || \
((param) == INTIFSD_INT_SRC_TMRD_13) || \
((param) == INTIFSD_INT_SRC_TMRD_14))
/** @} */
/* End of group INTIFSD_Exported_types */
/** @defgroup INTIFSD_Exported_FunctionPrototypes
* @{
*/
INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void);
void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource);
INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void);
INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void);
INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void);
/** @} */
/* End of group INTIFSD_Exported_FunctionPrototype */
/** @} */
/* End of group INTIFSD */
/** @} */
/* End of group TX00_Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_INTIFSD_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h
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@ -1,108 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_tmr16a.h
* @brief This file provides all the functions prototypes for TMR16A driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_TMR16A_H
#define __TMPM066_TMR16A_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_TMR16A_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup TMR16A
* @{
*/
/** @defgroup TMR16A_Exported_Types
* @{
*/
/**
* @brief TMR16A Flip-flop Structure definition
*/
typedef struct {
uint32_t TMR16AFlipflopCtrl; /*!< Select TMR16A flip-flop output level */
uint32_t TMR16AFlipflopReverseTrg; /*!< Specify TMR16A flip-flop reverse trigger */
} TMR16A_FFOutputTypeDef;
/** @} */
/* End of group TMR16A_Exported_Types */
/** @defgroup TMR16A_Exported_Constants
* @{
*/
#define IS_TMR16A_ALL_PERIPH(param) (((param) == TSB_T16A0) || \
((param) == TSB_T16A1))
#define TMR16A_SYSCK ((uint32_t)0x00000000)
#define TMR16A_PRCK ((uint32_t)0x00000001)
#define IS_TMR16A_SRCCLK(param) (((param) == TMR16A_SYSCK) || ((param) == TMR16A_PRCK))
#define TMR16A_RUN ((uint32_t)0x00000001)
#define TMR16A_STOP ((uint32_t)0x00000000)
#define IS_TMR16A_CMD(param) (((param) == TMR16A_RUN) || ((param) == TMR16A_STOP))
#define TMR16A_RUNNING_IN_CORE_HALT ((uint8_t)0x00)
#define TMR16A_STOP_IN_CORE_HALT ((uint8_t)0x02)
#define IS_TMR16A_CLK_IN_CORE_HALT(param) (((param) == TMR16A_RUNNING_IN_CORE_HALT) || \
((param) == TMR16A_STOP_IN_CORE_HALT))
#define TMR16A_FLIPFLOP_INVERT ((uint32_t)0x00000000)
#define TMR16A_FLIPFLOP_SET ((uint32_t)0x00000001)
#define TMR16A_FLIPFLOP_CLEAR ((uint32_t)0x00000002)
#define IS_TMR16A_FLIPFLOP_CTRL(param) (((param) == TMR16A_FLIPFLOP_INVERT) || \
((param) == TMR16A_FLIPFLOP_SET) || \
((param) == TMR16A_FLIPFLOP_CLEAR))
#define TMR16A_DISABLE_FLIPFLOP ((uint32_t)0x00000000)
#define TMR16A_FLIPFLOP_MATCH_CYCLE ((uint32_t)0x00000080)
#define IS_TMR16A_FLIPFLOP_TRG(param) (((param) == TMR16A_DISABLE_FLIPFLOP) || \
((param) == TMR16A_FLIPFLOP_MATCH_CYCLE))
#define IS_TMR16A_VALUE(param) ((param) <= 0x0000FFFFU)
#define IS_TMR16A_VALID_DUTY(param1, param2) ((param1) <= (param2))
/* End of group TMR16A_Exported_Constants */
/** @defgroup TMR16A_Exported_FunctionPrototypes
* @{
*/
void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState);
void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd);
void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk);
void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct);
void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle);
uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax);
/** @} */
/* End of group TMR16A_Exported_FunctionPrototypes */
/** @} */
/* End of group TMR16A */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_TMR16A_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_TMR16A_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h
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@ -1,259 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_tmrb.h
* @brief This file provides all the functions prototypes for TMRB driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_TMRB_H
#define __TMPM066_TMRB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_TMRB_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup TMRB
* @{
*/
/** @defgroup TMRB_Exported_Types
* @{
*/
/**
* @brief TMRB Init Structure definition
*/
typedef struct {
uint32_t Mode; /*!< Select TMRB mode between internal interval
timer mode and external event counter */
uint32_t ClkDiv; /*!< Select the division for TMRB source clock */
uint32_t TrailingTiming; /*!< Specify the trailingtiming value to be written
into TBnRG1 */
uint32_t UpCntCtrl; /*!< Select up-counter work mode between
freerun and auto-reload */
uint32_t LeadingTiming; /*!< Specify the leadingtiming value to be written
into TBnRG0 */
} TMRB_InitTypeDef;
/**
* @brief TMRB Flip-flop Structure definition
*/
typedef struct {
uint32_t FlipflopCtrl; /*!< Select TMRB flip-flop output level */
uint32_t FlipflopReverseTrg; /*!< Specify TMRB flip-flop reverse trigger */
} TMRB_FFOutputTypeDef;
/**
* @brief TMRB Interrupt factor Union definition
*/
typedef union {
uint32_t All;
struct {
uint32_t MatchLeadingTiming:1;
uint32_t MatchTrailingTiming:1;
uint32_t OverFlow:1;
uint32_t Reserverd:29;
} Bit;
} TMRB_INTFactor;
/**
* @brief TMRB Interrupt masked Union definition
*/
typedef union {
uint32_t All;
struct {
uint32_t MatchLeadingTimingMask:1;
uint32_t MatchTrailingTimingMask:1;
uint32_t OverFlowMask:1;
uint32_t Reserverd:29;
} Bit;
} TMRB_INTMask;
/** @} */
/* End of group TMRB_Exported_Types */
/** @defgroup TMRB_Exported_Constants
* @{
*/
#define IS_TMRB_ALL_PERIPH(param) (((param) == TSB_TB0) || \
((param) == TSB_TB1) || \
((param) == TSB_TB2) || \
((param) == TSB_TB3) || \
((param) == TSB_TB4) || \
((param) == TSB_TB5) || \
((param) == TSB_TB6) || \
((param) == TSB_TB7))
#define IS_TMRB_SYNC_PERIPH(param) (((param) == TSB_TB1) || \
((param) == TSB_TB2) || \
((param) == TSB_TB3) || \
((param) == TSB_TB5) || \
((param) == TSB_TB6) || \
((param) == TSB_TB7))
#define IS_TMRB_CAP_PERIPH(param) (((param) == TSB_TB0) || \
((param) == TSB_TB1) || \
((param) == TSB_TB2) || \
((param) == TSB_TB3) || \
((param) == TSB_TB4) || \
((param) == TSB_TB5))
#define TMRB_INTERVAL_TIMER ((uint32_t)0x00000001)
#define TMRB_EVENT_CNT ((uint32_t)0x00000000)
#define IS_TMRB_MODE(param) (((param) == TMRB_INTERVAL_TIMER) || \
((param) == TMRB_EVENT_CNT))
#define TMRB_CLK_DIV_2 ((uint32_t)0x00000001)
#define TMRB_CLK_DIV_8 ((uint32_t)0x00000002)
#define TMRB_CLK_DIV_32 ((uint32_t)0x00000003)
#define TMRB_CLK_DIV_64 ((uint32_t)0x00000004)
#define TMRB_CLK_DIV_128 ((uint32_t)0x00000005)
#define TMRB_CLK_DIV_256 ((uint32_t)0x00000006)
#define TMRB_CLK_DIV_512 ((uint32_t)0x00000007)
#define IS_TMRB_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \
((param) == TMRB_CLK_DIV_8) || \
((param) == TMRB_CLK_DIV_32) || \
((param) == TMRB_CLK_DIV_64) || \
((param) == TMRB_CLK_DIV_128) || \
((param) == TMRB_CLK_DIV_256) || \
((param) == TMRB_CLK_DIV_512))
#define TMRB_FREE_RUN ((uint32_t)0x00000000)
#define TMRB_AUTO_CLEAR ((uint32_t)0x00000008)
#define IS_TMRB_UC_CTRL(param) (((param) == TMRB_FREE_RUN) || \
((param) == TMRB_AUTO_CLEAR))
#define TMRB_FLIPFLOP_INVERT ((uint32_t)0x00000000)
#define TMRB_FLIPFLOP_SET ((uint32_t)0x00000001)
#define TMRB_FLIPFLOP_CLEAR ((uint32_t)0x00000002)
#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \
((param) == TMRB_FLIPFLOP_SET) || \
((param) == TMRB_FLIPFLOP_CLEAR))
#define TMRB_DISABLE_FLIPFLOP ((uint32_t)0x00000000)
#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010)
#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020)
#define TMRB_FLIPFLOP_MATCH_TRAILINGTIMING ((uint32_t)0x00000008)
#define TMRB_FLIPFLOP_MATCH_LEADINGTIMING ((uint32_t)0x00000004)
#define IS_TMRB_FLIPFLOP_TRG(param) (((param) == TMRB_DISABLE_FLIPFLOP) || \
((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \
((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \
((param) == TMRB_FLIPFLOP_MATCH_TRAILINGTIMING) || \
((param) == TMRB_FLIPFLOP_MATCH_LEADINGTIMING) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)))
#define TMRB_DISABLE_CAPTURE ((uint32_t)0x00000000)
#define TMRB_CAPTURE_IN_RISING_FALLING ((uint32_t)0x00000020)
#define TMRB_CAPTURE_FF_RISING_FALLING ((uint32_t)0x00000030)
#define IS_TMRB_CAPTURE_TIMING(param) (((param) == TMRB_DISABLE_CAPTURE) || \
((param) == TMRB_CAPTURE_IN_RISING_FALLING) || \
((param) == TMRB_CAPTURE_FF_RISING_FALLING))
#define TMRB_RUN ((uint32_t)0x00000005)
#define TMRB_STOP ((uint32_t)0x00000000)
#define IS_TMRB_CMD(param) (((param) == TMRB_RUN) || ((param) == TMRB_STOP))
#define TMRB_REG_0 ((uint8_t)0x00)
#define TMRB_REG_1 ((uint8_t)0x01)
#define IS_TMRB_REG(param) (((param) == TMRB_REG_0) || ((param) == TMRB_REG_1))
#define TMRB_CAPTURE_0 ((uint8_t)0x00)
#define TMRB_CAPTURE_1 ((uint8_t)0x01)
#define IS_TMRB_CAPTURE_REG(param) (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1))
#define TMRB_NO_INT_MASK ((uint32_t)0x00000000)
#define TMRB_MASK_MATCH_LEADINGTIMING_INT ((uint32_t)0x00000001)
#define TMRB_MASK_MATCH_TRAILINGTIMING_INT ((uint32_t)0x00000002)
#define TMRB_MASK_OVERFLOW_INT ((uint32_t)0x00000004)
#define IS_TMRB_INT_MASK(param) (((param) == TMRB_NO_INT_MASK) || \
((param) == TMRB_MASK_MATCH_LEADINGTIMING_INT) || \
((param) == TMRB_MASK_MATCH_TRAILINGTIMING_INT) || \
((param) == TMRB_MASK_OVERFLOW_INT) || \
((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT)) || \
((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
((param) == (TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)))
#define TMRB_TRG_EDGE_RISING ((uint8_t)0x00)
#define TMRB_TRG_EDGE_FALLING ((uint8_t)0x02)
#define IS_TMRB_TRG_EDGE(param) (((param) == TMRB_TRG_EDGE_RISING) || \
((param) == TMRB_TRG_EDGE_FALLING))
#define TMRB_RUNNING_IN_CORE_HALT ((uint8_t)0x00)
#define TMRB_STOP_IN_CORE_HALT ((uint8_t)0x40)
#define IS_TMRB_CLK_IN_CORE_HALT(param) (((param) == TMRB_RUNNING_IN_CORE_HALT) || \
((param) == TMRB_STOP_IN_CORE_HALT))
#define TMRB_NO_INT ((uint32_t)0x00000000)
#define IS_TMRB_VALUE(param) ((param) <= 0x0000FFFFU)
#define IS_VALID_LEADINGTIMING(param1, param2) ((param1) <= (param2))
#define TMRB_DMA_REQ_CMP_MATCH ((uint32_t)0x000000004)
#define TMRB_DMA_REQ_CAPTURE_1 ((uint32_t)0x000000002)
#define TMRB_DMA_REQ_CAPTURE_0 ((uint32_t)0x000000001)
#define IS_TMRB_DMA_REQ(param) (((param) == TMRB_DMA_REQ_CMP_MATCH) || \
((param) == TMRB_DMA_REQ_CAPTURE_1) || \
((param) == TMRB_DMA_REQ_CAPTURE_0))
/** @} */
/* End of group TMRB_Exported_Constants */
/** @defgroup TMRB_Exported_FunctionPrototypes
* @{
*/
void TMRB_Enable(TSB_TB_TypeDef * TBx);
void TMRB_Disable(TSB_TB_TypeDef * TBx);
void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd);
void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct);
void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming);
void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct);
TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx);
TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx);
void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask);
void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming);
void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming);
uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg);
uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx);
uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg);
void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx);
void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState);
void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode);
void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState);
void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq);
/** @} */
/* End of group TMRB_Exported_FunctionPrototypes */
/** @} */
/* End of group TMRB */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_TMRB_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TMPM066_TMRB_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h
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/**
*******************************************************************************
* @file tmpm066_uart.h
* @brief This file provides all the functions prototypes for UART driver.
* @version V2.0.2.1
* @date 2015/09/10
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TMPM066_UART_H
#define __TMPM066_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "TMPM066.h"
#include "tx00_common.h"
#if defined(__TMPM066_UART_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/** @defgroup UART_Exported_Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
typedef struct {
uint32_t BaudRate; /*!< This member configures the UART communication
baud rate. */
uint32_t DataBits; /*!< Specifies UART transfer mode, which could be
7-bit mode, 8-bit mode or 9-bit mode. */
uint32_t StopBits; /*!< Specifies the length of stop bit transmission
in UART mode. */
uint32_t Parity; /*!< Specifies the parity mode which could be odd
parity, even parity or no parity. */
uint32_t Mode; /*!< Enables or disables Receive, Transmit or
both. */
uint32_t FlowCtrl; /*!< Specifies wether the hardware flow control
mode is enabled or disabled. */
} UART_InitTypeDef;
typedef struct {
uint32_t InputClkEdge; /*!< Select the input clock edge.on the SCLK output mode
this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */
uint32_t TIDLE; /*!< The status of TXDx pin after output of the
last bit */
uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error
is occured in SCLK input mode */
uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK
input mode */
uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which
could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK.
this bit is valid only for SCLK output mode and double
buffer is enabled. */
uint32_t TransferMode; /*!< Setting transfer mode which could be transfer prohibited,
half duplex(Receive),half duplex(Transmit) or full duplex. */
uint32_t TransferDir; /*!< Setting transfer direction which could be
LSB_FRIST or MSB_FRIST. */
uint32_t Mode; /*!< Enables or disables Receive, Transmit or both. */
uint32_t DoubleBuffer; /*!< Double Buffer mode is enabled or disabled. */
uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */
uint32_t Divider; /*!< Division ratio "N" */
} SIO_InitTypeDef;
/** @} */
/* End of group UART_Exported_Types */
/** @defgroup UART_Exported_Constants
* @{
*/
#define UART0 TSB_SC0
#define UART1 TSB_SC1
#define IS_UART_PERIPH(param) (((param) == UART0) || \
((param) == UART1))
#define SIO0 TSB_SC0
#define SIO1 TSB_SC1
#define IS_SIO_PERIPH(param) (((param) == SIO0) || \
((param) == SIO1))
#define UART_DATA_BITS_7 ((uint32_t)0x00000004)
#define UART_DATA_BITS_8 ((uint32_t)0x00000008)
#define UART_DATA_BITS_9 ((uint32_t)0x0000000C)
#define IS_UART_DATA_BITS(param) (((param) == UART_DATA_BITS_7) || \
((param) == UART_DATA_BITS_8) || \
((param) == UART_DATA_BITS_9))
#define UART_STOP_BITS_1 ((uint32_t)0x00000000)
#define UART_STOP_BITS_2 ((uint32_t)0x00000010)
#define IS_UART_STOPBITS(param) (((param) == UART_STOP_BITS_1) || \
((param) == UART_STOP_BITS_2))
#define UART_NO_PARITY ((uint32_t)0x00000000)
#define UART_EVEN_PARITY ((uint32_t)0x00000060)
#define UART_ODD_PARITY ((uint32_t)0x00000020)
#define IS_UART_PARITY(param) (((param) == UART_NO_PARITY) || \
((param) == UART_EVEN_PARITY) || \
((param) == UART_ODD_PARITY))
#define SIO_CLK_SCLKOUTPUT ((uint32_t)0x00000000)
#define SIO_CLK_SCLKINPUT ((uint32_t)0x00000001)
#define IS_SIO_CLK_SEL(param) (((param) == SIO_CLK_SCLKOUTPUT) || \
((param) == SIO_CLK_SCLKINPUT))
#define SIO_SCLKS_TXDF_RXDR ((uint32_t)0x00000000)
#define SIO_SCLKS_TXDR_RXDF ((uint32_t)0x00000002)
#define IS_SIO_SCLKS_TRXD(param) (((param) == SIO_SCLKS_TXDF_RXDR) || \
((param) == SIO_SCLKS_TXDR_RXDF))
#define SIO_TIDLE_LOW ((uint32_t)0x00000000)
#define SIO_TIDLE_HIGH ((uint32_t)0x00000100)
#define SIO_TIDLE_LAST ((uint32_t)0x00000200)
#define IS_SIO_TIDLE_LEVEL(param) (((param) == SIO_TIDLE_LOW) || \
((param) == SIO_TIDLE_HIGH) || \
((param) == SIO_TIDLE_LAST))
#define SIO_TXDEMP_LOW ((uint32_t)0x00000000)
#define SIO_TXDEMP_HIGH ((uint32_t)0x00000400)
#define IS_SIO_TXDEMP_LEVEL(param) (((param) == SIO_TXDEMP_LOW) || \
((param) == SIO_TXDEMP_HIGH))
#define SIO_EHOLD_FC_2 ((uint32_t)0x00000000)
#define SIO_EHOLD_FC_4 ((uint32_t)0x00001000)
#define SIO_EHOLD_FC_8 ((uint32_t)0x00002000)
#define SIO_EHOLD_FC_16 ((uint32_t)0x00003000)
#define SIO_EHOLD_FC_32 ((uint32_t)0x00004000)
#define SIO_EHOLD_FC_64 ((uint32_t)0x00005000)
#define SIO_EHOLD_FC_128 ((uint32_t)0x00006000)
#define IS_SIO_EHOLD_TIME(param) (((param) == SIO_EHOLD_FC_2) || \
((param) == SIO_EHOLD_FC_4) || \
((param) == SIO_EHOLD_FC_8) || \
((param) == SIO_EHOLD_FC_16) || \
((param) == SIO_EHOLD_FC_32) || \
((param) == SIO_EHOLD_FC_64) || \
((param) == SIO_EHOLD_FC_128))
#define SIO_SINT_TIME_NONE ((uint32_t)0x00000000)
#define SIO_SINT_TIME_SCLK_1 ((uint32_t)0x00000002)
#define SIO_SINT_TIME_SCLK_2 ((uint32_t)0x00000004)
#define SIO_SINT_TIME_SCLK_4 ((uint32_t)0x00000006)
#define SIO_SINT_TIME_SCLK_8 ((uint32_t)0x00000008)
#define SIO_SINT_TIME_SCLK_16 ((uint32_t)0x0000000A)
#define SIO_SINT_TIME_SCLK_32 ((uint32_t)0x0000000C)
#define SIO_SINT_TIME_SCLK_64 ((uint32_t)0x0000000E)
#define IS_SIO_SINT_TIME(param) (((param) == SIO_SINT_TIME_NONE) || \
((param) == SIO_SINT_TIME_SCLK_1) || \
((param) == SIO_SINT_TIME_SCLK_2) || \
((param) == SIO_SINT_TIME_SCLK_4) || \
((param) == SIO_SINT_TIME_SCLK_8) || \
((param) == SIO_SINT_TIME_SCLK_16) || \
((param) == SIO_SINT_TIME_SCLK_32) || \
((param) == SIO_SINT_TIME_SCLK_64))
#define SIO_TRANSFER_PROHIBIT ((uint32_t)0x00000000)
#define SIO_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020)
#define SIO_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040)
#define SIO_TRANSFER_FULLDPX ((uint32_t)0x00000060)
#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \
((param) == SIO_TRANSFER_HALFDPX_RX) || \
((param) == SIO_TRANSFER_HALFDPX_TX) || \
((param) == SIO_TRANSFER_FULLDPX))
#define SIO_ENABLE_RX ((uint32_t)0x00000020)
#define SIO_ENABLE_TX ((uint32_t)0x00000010)
#define IS_SIO_MODE(param) (((param) == SIO_ENABLE_RX) || \
((param) == SIO_ENABLE_TX) || \
((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX)))
#define SIO_LSB_FRIST ((uint32_t)0x00000000)
#define SIO_MSB_FRIST ((uint32_t)0x00000008)
#define IS_SIO_TRANS_DIR(param) (((param) == SIO_LSB_FRIST) || \
((param) == SIO_MSB_FRIST))
#define SIO_WBUF_DISABLE ((uint32_t)0x00000000)
#define SIO_WBUF_ENABLE ((uint32_t)0x00000004)
#define IS_SIO_WBUF_SET(param) (((param) == SIO_WBUF_DISABLE) || \
((param) == SIO_WBUF_ENABLE))
#define SIO_BR_CLOCK_TS0 ((uint32_t)0x00000000)
#define SIO_BR_CLOCK_TS2 ((uint32_t)0x00000010)
#define SIO_BR_CLOCK_TS8 ((uint32_t)0x00000020)
#define SIO_BR_CLOCK_TS32 ((uint32_t)0x00000030)
#define IS_SIO_BR_CLOCK(param) (((param) == SIO_BR_CLOCK_TS0) || \
((param) == SIO_BR_CLOCK_TS2) || \
((param) == SIO_BR_CLOCK_TS8) || \
((param) == SIO_BR_CLOCK_TS32))
#define SIO_BR_DIVIDER_16 ((uint32_t)0x00000000)
#define SIO_BR_DIVIDER_1 ((uint32_t)0x00000001)
#define SIO_BR_DIVIDER_2 ((uint32_t)0x00000002)
#define SIO_BR_DIVIDER_3 ((uint32_t)0x00000003)
#define SIO_BR_DIVIDER_4 ((uint32_t)0x00000004)
#define SIO_BR_DIVIDER_5 ((uint32_t)0x00000005)
#define SIO_BR_DIVIDER_6 ((uint32_t)0x00000006)
#define SIO_BR_DIVIDER_7 ((uint32_t)0x00000007)
#define SIO_BR_DIVIDER_8 ((uint32_t)0x00000008)
#define SIO_BR_DIVIDER_9 ((uint32_t)0x00000009)
#define SIO_BR_DIVIDER_10 ((uint32_t)0x0000000A)
#define SIO_BR_DIVIDER_11 ((uint32_t)0x0000000B)
#define SIO_BR_DIVIDER_12 ((uint32_t)0x0000000C)
#define SIO_BR_DIVIDER_13 ((uint32_t)0x0000000D)
#define SIO_BR_DIVIDER_14 ((uint32_t)0x0000000E)
#define SIO_BR_DIVIDER_15 ((uint32_t)0x0000000F)
#define IS_SIO_BR_DIVIDER(param) ((param) <= SIO_BR_DIVIDER_15)
#define IS_SIO_DATA(param) ((param) <= 0xFFU)
#define SIO_CLOCK_T0_HALF ((uint32_t)0x00000000)
#define SIO_CLOCK_T0 ((uint32_t)0x00000002)
#define IS_SIO_CLOCK(param) (((param) == SIO_CLOCK_T0_HALF) || \
((param) == SIO_CLOCK_T0))
#define UART_ENABLE_RX ((uint32_t)0x00000020)
#define UART_ENABLE_TX ((uint32_t)0x00000010)
#define IS_UART_MODE(param) (((param) == UART_ENABLE_RX) || \
((param) == UART_ENABLE_TX) || \
((param) == (UART_ENABLE_TX | UART_ENABLE_RX)))
#define UART_NONE_FLOW_CTRL ((uint32_t)0x00000000)
#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL)
#define IS_UART_BAUDRATE(param) (((param) >= 2400U) && \
((param) <= 115200U))
#define IS_UART_DATA(param) ((param) <= 0x01FFU)
#define IS_UART_CLOCK(param) ((param) <= ((uint32_t)0x00000001))
#define IS_UART_TIME(param) ((param) <= ((uint32_t)0x00000006))
#define UART_RX ((uint32_t)0x00000020)
#define UART_TX ((uint32_t)0x00000040)
#define IS_UART_TRX(param) (((param) == UART_RX) || \
((param) == UART_TX))
#define UART_TRANSFER_PROHIBIT ((uint32_t)0x00000000)
#define UART_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020)
#define UART_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040)
#define UART_TRANSFER_FULLDPX ((uint32_t)0x00000060)
#define IS_UART_TRANSFER_MODE(param) (((param) == UART_TRANSFER_PROHIBIT) || \
((param) == UART_TRANSFER_HALFDPX_RX) || \
((param) == UART_TRANSFER_HALFDPX_TX) || \
((param) == UART_TRANSFER_FULLDPX))
#define UART_RXFIFO_MAX ((uint32_t)0x00000000)
#define UART_RXFIFO_RXFLEVEL ((uint32_t)0x00000010)
#define IS_UATR_RXFIFO_BYTESUSED(param) (((param) == UART_RXFIFO_MAX) || \
((param) == UART_RXFIFO_RXFLEVEL))
#define UART_RXFIFO4B_FLEVLE_4_2B ((uint32_t)0x00000000)
#define UART_RXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001)
#define UART_RXFIFO4B_FLEVLE_2_2B ((uint32_t)0x00000002)
#define UART_RXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003)
#define IS_UART_RXFIFO4B_FLEVLE(param) (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \
((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \
((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \
((param) == UART_RXFIFO4B_FLEVLE_3_1B))
#define UART_RFIS_REACH_FLEVEL ((uint32_t)0x00000000)
#define UART_RFIS_REACH_EXCEED_FLEVEL ((uint32_t)0x00000040)
#define IS_UATR_RFIS_CONDITION(param) (((param) == UART_RFIS_REACH_FLEVEL) || \
((param) == UART_RFIS_REACH_EXCEED_FLEVEL))
#define UART_TXFIFO4B_FLEVLE_0_0B ((uint32_t)0x00000000)
#define UART_TXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001)
#define UART_TXFIFO4B_FLEVLE_2_0B ((uint32_t)0x00000002)
#define UART_TXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003)
#define IS_UART_TXFIFO4B_FLEVLE(param) (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \
((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \
((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \
((param) == UART_TXFIFO4B_FLEVLE_3_1B))
#define UART_TRXFIFO_EMPTY ((uint32_t)0x00000000)
#define UART_TRXFIFO_1B ((uint32_t)0x00000001)
#define UART_TRXFIFO_2B ((uint32_t)0x00000002)
#define UART_TRXFIFO_3B ((uint32_t)0x00000003)
#define UART_TRXFIFO_4B ((uint32_t)0x00000004)
#define UART_TFIS_REACH_FLEVEL ((uint32_t)0x00000000)
#define UART_TFIS_REACH_NOREACH_FLEVEL ((uint32_t)0x00000040)
#define IS_UATR_TFIS_CONDITION(param) (((param) == UART_TFIS_REACH_FLEVEL) || \
((param) == UART_TFIS_REACH_NOREACH_FLEVEL))
#define UART_RXFIFO_OVERRUN ((uint32_t)0x00000001)
#define UART_TXFIFO_UNDERRUN ((uint32_t)0x00000001)
/** @} */
/* End of group UART_Exported_Constants */
/** @addtogroup UART_Exported_Types
* @{
*/
typedef enum {
UART_NO_ERR = 0U,
UART_OVERRUN = 1U,
UART_PARITY_ERR = 2U,
UART_FRAMING_ERR = 3U,
UART_ERRS = 4U
} UART_Err;
typedef enum {
UART_RXTXCNT_NONE = 0U,
UART_RXTXCNT_AUTODISABLE = 1U
} UART_TRxDisable;
#define IS_UATR_TRX_AUTODISABLE(param) (((param) == UART_RXTXCNT_NONE) || \
((param) == UART_RXTXCNT_AUTODISABLE))
/** @} */
/* End of group UART_Exported_Types */
/** @defgroup UART_Exported_FunctionPrototypes
* @{
*/
void UART_Enable(TSB_SC_TypeDef * UARTx);
void UART_Disable(TSB_SC_TypeDef * UARTx);
WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction);
void UART_SWReset(TSB_SC_TypeDef * UARTx);
void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct);
uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx);
void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data);
void UART_DefaultConfig(TSB_SC_TypeDef * UARTx);
UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx);
void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock);
void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode);
void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable);
void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed);
void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel);
void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition);
void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx);
void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel);
void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition);
void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx);
void UART_TxBufferClear(TSB_SC_TypeDef * UARTx);
uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx);
uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx);
void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock);
void SIO_Enable(TSB_SC_TypeDef * SIOx);
void SIO_Disable(TSB_SC_TypeDef * SIOx);
uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx);
void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data);
void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct);
/** @} */
/* End of group UART_Exported_FunctionPrototypes */
/** @} */
/* End of group UART */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_UART_H) */
#ifdef __cplusplus
}
#endif
#endif /* __TMPM066_UART_H */

47
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h
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@ -1,47 +0,0 @@
/**
*******************************************************************************
* @file tx00_common.h
* @brief All common macro and definition for TX00 peripheral drivers
* @version V2.1.1
* @date 2014/11/22
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TX00_COMMON_H
#define __TX00_COMMON_H
typedef enum {
SUCCESS = 0U,
ERROR = 1U
} Result;
typedef enum {
BUSY = 0U,
DONE = 1U
} WorkState;
typedef enum {
DISABLE = 0U,
ENABLE = 1U
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0)
/*
* To report the name of the source file and source line number where the
* assert_param error has occurred, "DEBUG" must be defined. And detailed
* definition of assert_failed() is needed to be implemented, which can be
* done, for example, in the main.c file.
*/
#ifdef DEBUG
void assert_failed(char *file, int32_t line);
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
#else
#define assert_param(expr)
#endif /* DEBUG */
#endif /* __TX00_COMMON_H */

571
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c
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@ -1,571 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_adc.c
* @brief This file provides API functions for ADC driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_adc.h"
#if defined(__TMPM066_ADC_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
/** @defgroup ADC_Private_Defines
* @{
*/
#define MOD0_ADS_SET ((uint32_t)0x00000001)
#define MOD0_SCAN_MASK ((uint32_t)0xFFFFFFFD)
#define MOD0_REPEAT_MASK ((uint32_t)0xFFFFFFFB)
#define MOD0_ITM_CLEAR ((uint32_t)0xFFFFFFE7)
#define MOD0_ADBFN_EOCFN_MASK ((uint32_t)0x000000C0)
#define MOD1_ADCH_CLEAR ((uint32_t)0xFFFFFFF0)
#define MOD1_ADSCN_CLEAR ((uint32_t)0xFFFFFFCF)
#define MOD2_HPADCH_CLEAR ((uint32_t)0xFFFFFFF0)
#define MOD2_HPADCE_SET ((uint32_t)0x00000020)
#define MOD2_ADBFHP_EOCFHP_MASK ((uint32_t)0x000000C0)
#define MOD4_ADHTG_CLEAR ((uint32_t)0xFFFFFFEF)
#define MOD4_ADHTG_SET ((uint32_t)0x00000010)
#define MOD4_ADHS_CLEAR ((uint32_t)0xFFFFFFDF)
#define MOD4_HADHTG_CLEAR ((uint32_t)0xFFFFFFBF)
#define MOD4_HADHTG_SET ((uint32_t)0x00000040)
#define MOD4_HADHS_CLEAR ((uint32_t)0xFFFFFF7F)
#define MOD4_ADRST_MASK ((uint32_t)0xFFFFFFFC)
#define MOD4_ADRST_10 ((uint32_t)0x00000002)
#define MOD4_ADRST_01 ((uint32_t)0x00000001)
#define ADC_CMPREG_CLEAR ((uint32_t)0xFFFFFF21)
#define ADC_REGx_ADRxRF_MASK ((uint32_t)0x00000001)
#define ADC_REGx_OVRx_MASK ((uint32_t)0x00000002)
#define ADC_REGx_RESULT_MASK ((uint32_t)0x0000FFC0)
/** @} */
/* End of group ADC_Private_Defines */
/** @defgroup ADC_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group ADC_Private_FunctionPrototypes */
/** @defgroup ADC_Private_Functions
* @{
*/
/** @} */
/* End of group ADC_Private_Functions */
/** @defgroup ADC_Exported_Functions
* @{
*/
/**
* @brief Software reset ADC function.
* @param None.
* @retval None.
*/
void ADC_SWReset(void)
{
/* Set MOD4<ADRST[1:0]> = 0b10, 0b01 to reset ADC */
TSB_AD->MOD4 = MOD4_ADRST_10;
TSB_AD->MOD4 = MOD4_ADRST_01;
}
/**
* @brief Set A/D conversion time and prescaler output.
* @param Conversion_Time: Select the A/D conversion time.
* This parameter can be one of the following values:
* ADC_CONVERSION_35_CLOCK, ADC_CONVERSION_42_CLOCK,
* ADC_CONVERSION_68_CLOCK, ADC_CONVERSION_81_CLOCK
* @param Prescaler_Output: Select the A/D prescaler output.
* This parameter can be one of the following values:
* ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2, ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_6,
* ADC_FC_DIVIDE_LEVEL_8, ADC_FC_DIVIDE_LEVEL_12, ADC_FC_DIVIDE_LEVEL_16,
* ADC_FC_DIVIDE_LEVEL_24, ADC_FC_DIVIDE_LEVEL_48, ADC_FC_DIVIDE_LEVEL_96.
* @retval None.
*/
void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output)
{
/* Check the parameters */
assert_param(IS_ADC_CONVERSION_TIME(Conversion_Time));
assert_param(IS_ADC_PRESCALER(Prescaler_Output));
/* Set ADCLK */
TSB_AD->CLK = Conversion_Time + Prescaler_Output;
}
/**
* @brief Start ADC function.
* @param None.
* @retval None.
*/
void ADC_Start(void)
{
/* Set ADMOD0<ADS> = 1 to start ADC */
TSB_AD->MOD0 |= MOD0_ADS_SET;
}
/**
* @brief Set ADC scan mode.
* @param NewState: Specify ADC scan mode.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetScanMode(FunctionalState NewState)
{
/* read MOD0, and clear bit1 which is "ADMOD0<SCAN>" */
uint32_t tmp = TSB_AD->MOD0 & MOD0_SCAN_MASK;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD0<SCAN> */
tmp |= (uint32_t) NewState << 1U;
TSB_AD->MOD0 = tmp;
}
/**
* @brief Set ADC repeat mode.
* @param NewState: Specify ADC repeat mode.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetRepeatMode(FunctionalState NewState)
{
/* read MOD0, and clear bit2 which is "ADMOD0<REPEAT>" */
uint32_t tmp = TSB_AD->MOD0 & MOD0_REPEAT_MASK;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD0<REPEAT> */
tmp |= (uint32_t) NewState << 2U;
TSB_AD->MOD0 = tmp;
}
/**
* @brief Set ADC interrupt mode in fixed channel repeat conversion mode.
* @param INTMode: Specify AD conversion interrupt mode.
* This parameter can be one of the following values:
* ADC_INT_SINGLE, ADC_INT_CONVERSION_4 or ADC_INT_CONVERSION_8.
* @retval None.
*/
void ADC_SetINTMode(uint32_t INTMode)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_INT_MODE(INTMode));
/* Set ADMOD0<ITM[1:0]> */
tmp = TSB_AD->MOD0;
tmp &= MOD0_ITM_CLEAR;
tmp |= INTMode;
TSB_AD->MOD0 = tmp;
}
/**
* @brief Read AD conversion completion/busy flag (normal and top-priority).
* @param None
* @retval A union with the state of AD conversion.
*/
ADC_State ADC_GetConvertState(void)
{
uint32_t tmpmod0 = TSB_AD->MOD0;
uint32_t tmpmod2 = TSB_AD->MOD2;
ADC_State retval = { 0U };
tmpmod0 &= MOD0_ADBFN_EOCFN_MASK;
tmpmod2 &= MOD2_ADBFHP_EOCFHP_MASK;
retval.All = (tmpmod0 >> 6U) | (tmpmod2 >> 4U);
return retval;
}
/**
* @brief Set ADC input channel.
* @param InputChannel: Analog input channel, it also related with other settings.
* This parameter can be one of the following values:
* ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3,
* ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7.
* @retval None.
*/
void ADC_SetInputChannel(uint32_t InputChannel)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_INPUT_CH(InputChannel));
/* Set ADMOD1<ADCH[3:0]> */
tmp = TSB_AD->MOD1;
tmp &= MOD1_ADCH_CLEAR;
tmp |= InputChannel;
TSB_AD->MOD1 = tmp;
}
/**
* @brief Set ADC operation for scanning.
* @param ScanMode: Spcifiy operation mode for channel scanning.
* This parameter can be one of the following values:
* ADC_SCAN_4CH, ADC_SCAN_8CH.
* @retval None.
*/
void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_CH_SCAN_MODE(ScanMode));
tmp = TSB_AD->MOD1;
tmp &= MOD1_ADSCN_CLEAR;
tmp |= ((uint32_t) ScanMode << 4U);
TSB_AD->MOD1 = tmp;
}
/**
* @brief Set ADC in IDLE mode.
* @param NewState: Specify AD conversion in IDLE mode.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetIdleMode(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD1<I2AD> */
TSB_AD_MOD1_I2AD = NewState;
}
/**
* @brief Set ADC VREF application.
* @param NewState: Specify ADC Vref application.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetVref(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD1<VREFON> */
TSB_AD_MOD1_VREFON = NewState;
}
/**
* @brief Set ADC top-priority conversion analog input channel select.
* @param TopInputChannel: Analog input channel for top-priority conversion.
* This parameter can be one of the following values:
* ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3,
* ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7.
* @retval None.
*/
void ADC_SetInputChannelTop(uint32_t TopInputChannel)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_INPUT_CH(TopInputChannel));
/* Set ADMOD2<HPADCH[3:0]> */
tmp = TSB_AD->MOD2;
tmp &= MOD2_HPADCH_CLEAR;
tmp |= TopInputChannel;
TSB_AD->MOD2 = tmp;
}
/**
* @brief Start top-priority ADC.
* @param None.
* @retval None.
*/
void ADC_StartTopConvert(void)
{
/* Set ADMOD2<HPADCE> = 1 to start top-priority ADC */
TSB_AD->MOD2 |= MOD2_HPADCE_SET;
}
/**
* @brief Set ADC monitor function.
* @param ADCMPx: Select ADC compare register.
* This parameter can be one of the following values:
* ADC_CMP_0 or ADC_CMP_1.
* @param NewState: Specify ADC monitor function.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_ADC_CMP(ADCMPx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (ADCMPx == ADC_CMP_0) {
/* Set ADMOD3<ADOBSV0> */
TSB_AD_MOD3_ADOBSV0 = NewState;
} else {
/* Set ADMOD5<ADOBSV1> */
TSB_AD_MOD5_ADOBSV1 = NewState;
}
}
/**
* @brief Set ADC result output register or comparison register.
* @param ADCMPx: Select AD compare register.
* This parameter can be one of the following values:
* ADC_CMP_0 or ADC_CMP_1.
* @param ResultComparison: Set AD conversion result storage register or
* comparison register if ADC monitor function is enabled.
* This parameter can be one of the following values:
* ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3,
* ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP.
* @retval None.
*/
void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_CMP(ADCMPx));
assert_param(IS_ADC_RESULT_CMP_REG(ResultComparison));
if (ADC_CMP_0 == ADCMPx) {
/* Set ADMOD3<REGS0[3:0]> */
tmp = TSB_AD->MOD3;
tmp &= ADC_CMPREG_CLEAR;
tmp |= ResultComparison;
TSB_AD->MOD3 = tmp;
} else {
/* Set ADMOD5<REGS1[3:0]> */
tmp = TSB_AD->MOD5;
tmp &= ADC_CMPREG_CLEAR;
tmp |= ResultComparison;
TSB_AD->MOD5 = tmp;
}
}
/**
* @brief Set ADC monitor interrupt.
* @param ADCMPx: Select ADC compare register.
* This parameter can be one of the following values:
* ADC_CMP_0 or ADC_CMP_1.
* @param NewState: Specify ADC monitor function.
* This parameter can be one of the following values:
* ADC_COMPARISON_SMALLER or ADC_COMPARISON_LARGER.
* @retval None.
*/
void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState)
{
/* Check the parameters */
assert_param(IS_ADC_CMP(ADCMPx));
assert_param(IS_ADC_CMP_INT(NewState));
if (ADCMPx == ADC_CMP_0) {
/* Set ADMOD3<ADOBIC0> */
TSB_AD_MOD3_ADOBIC0 = NewState;
} else {
/* Set ADMOD5<ADOBIC1> */
TSB_AD_MOD5_ADOBIC1 = NewState;
}
}
/**
* @brief Set hardware trigger for normal ADC function.
* @param HwSource: HW source for activating normal ADC.
* This parameter can be one of the following values:
* ADC_EXT_TRG or ADC_MATCH_TB_0.
* @param NewState: Specify HW for activating normal ADC.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_HW_TRG_NORMAL(HwSource));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD4<ADHS> */
tmp = TSB_AD->MOD4;
tmp &= MOD4_ADHS_CLEAR;
tmp |= HwSource;
/* Set ADMOD4<ADHTG> */
if (NewState == ENABLE) {
tmp |= MOD4_ADHTG_SET;
} else {
tmp &= MOD4_ADHTG_CLEAR;
}
TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK;
}
/**
* @brief Set hardware trigger for top-priority ADC function.
* @param HwSource: HW source for activating top-priority ADC.
* This parameter can be one of the following values:
* ADC_EXT_TRG or ADC_MATCH_TB_1.
* @param NewState: Specify HW for activating top-priority ADC.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_HW_TRG_TOP(HwSource));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set ADMOD4<HADHS> */
tmp = TSB_AD->MOD4;
tmp &= MOD4_HADHS_CLEAR;
tmp |= HwSource;
/* Set ADMOD4<HADHTG> */
if (NewState == ENABLE) {
tmp |= MOD4_HADHTG_SET;
} else {
tmp &= MOD4_HADHTG_CLEAR;
}
TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK;
}
/**
* @brief Read ADC result.
* @param ADREGx: ADC result register.
* This parameter can be one of the following values:
* ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3,
* ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP.
* @retval ADC result.
*/
ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx)
{
uint32_t tmp = 0U;
ADC_ResultTypeDef retval = { BUSY, ADC_NO_OVERRUN, 0U };
/* Check the parameters */
assert_param(IS_ADC_REG(ADREGx));
/* Read ADREGx<ADRx[9:0]> to get ADC result */
switch (ADREGx) {
case ADC_REG_0:
tmp = TSB_AD->REG0;
break;
case ADC_REG_1:
tmp = TSB_AD->REG1;
break;
case ADC_REG_2:
tmp = TSB_AD->REG2;
break;
case ADC_REG_3:
tmp = TSB_AD->REG3;
break;
case ADC_REG_4:
tmp = TSB_AD->REG4;
break;
case ADC_REG_5:
tmp = TSB_AD->REG5;
break;
case ADC_REG_6:
tmp = TSB_AD->REG6;
break;
case ADC_REG_7:
tmp = TSB_AD->REG7;
break;
case ADC_REG_SP:
tmp = TSB_AD->REGSP;
break;
default: /* Do nothing */
break;
}
if ((tmp & ADC_REGx_ADRxRF_MASK) == 0U) {
retval.ADCResultStored = BUSY;
} else {
retval.ADCResultStored = DONE;
}
if ((tmp & ADC_REGx_OVRx_MASK) == 0U) {
retval.ADCOverrunState = ADC_NO_OVERRUN;
} else {
retval.ADCOverrunState = ADC_OVERRUN;
}
retval.ADCResultValue = (uint16_t) tmp & ADC_REGx_RESULT_MASK;
retval.ADCResultValue >>= 6U;
return retval;
}
/**
* @brief Set ADC comparison register value.
* @param ADCMPx: Select AD compare register.
* This parameter can be one of the following values:
* ADC_CMP_0 or ADC_CMP_1.
* @param value: The value setting to ADC comparison register.
* @retval None.
*/
void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value)
{
/* Check the parameters */
assert_param(IS_ADC_CMP(ADCMPx));
assert_param(IS_ADC_CMP_VALUE(value));
value <<= 6U;
if (ADCMPx == ADC_CMP_0) {
/* Set ADCMP0<ADCOM0[9:0]> */
TSB_AD->CMP0 = value;
} else {
/* Set ADCMP1<ADCOM1[9:0]> */
TSB_AD->CMP1 = value;
}
}
/**
* @breif Enable or disable DMA activation factor for normal or top-priority AD conversion.
* @param DMAReq: Specify AD conversion DMA request type.
* This parameter can be one of the following values:
* ADC_DMA_REQ_NORMAL, ADC_DMA_REQ_TOP,
* ADC_DMA_REQ_MONITOR1, ADC_DMA_REQ_MONITOR2.
* @param NewState: Specify AD conversion DMA activation factor.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_ADC_DMA_REQ(DMAReq));
assert_param(IS_FUNCTIONAL_STATE(NewState));
switch (DMAReq) {
case ADC_DMA_REQ_NORMAL:
TSB_AD_MOD6_ADDMA = NewState;
break;
case ADC_DMA_REQ_TOP:
TSB_AD_MOD6_ADHPDMA = NewState;
break;
case ADC_DMA_REQ_MONITOR1:
TSB_AD_MOD6_ADM0DMA = NewState;
break;
case ADC_DMA_REQ_MONITOR2:
TSB_AD_MOD6_ADM1DMA = NewState;
break;
default:
/* Do nothing */
break;
}
}
/** @} */
/* End of group ADC_Exported_Functions */
/** @} */
/* End of group ADC */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_ADC_H) */

698
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c
View File

@ -1,698 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_cg.c
* @brief This file provides API functions for CG driver
* @version V2.0.2.1
* @date 2015/09/22
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_cg.h"
#if defined(__TMPM066_CG_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup CG
* @brief CG driver modules
* @{
*/
/** @defgroup CG_Private_Defines
* @{
*/
#define CG_FC_GEAR_MASK ((uint32_t)0xFFFFFFF8)
#define CG_PRCK_MASK ((uint32_t)0xFFFFF0FF)
#define CG_WUP_TIME_MASK ((uint32_t)0x000FFFFF)
#define CG_WUP_COUNTER_MASK ((uint32_t)0xFFFFFEFF)
#define CG_WUP_START_SET ((uint32_t)0x00000001)
#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002)
#define CG_OSCCR_IOSCEN_SET ((uint32_t)0x00000001)
#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_OSCCR_EOSCEN_EHOSC ((uint32_t)0x00000002)
#define CG_OSCCR_EOSCEN_NOUSE ((uint32_t)0xFFFFFFF9)
#define CG_OSCCR_EOSCEN_MASK ((uint32_t)0x00000006)
#define CG_OSCCR_EOSCEN_CLKIN ((uint32_t)0x00000004)
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
#define CG_OSCCR_OSCSEL_CLEAR ((uint32_t)0xFFFFFEFF)
#define CG_OSCCR_OSCF_SET ((uint32_t)0x00000200)
#define CG_OSCCR_WUPT_MASK ((uint32_t)0x00FFFFFF)
#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
#define CG_PLL0SEL_PLLST_SET ((uint32_t)0x00000004)
#define CG_PLL0SET_VALUE_MASK ((uint32_t)0xFFFFFF00)
#define CG_PLL0SEL_PLL0SET_MASK ((uint32_t)0xFFFFFF00)
#define CG_STBY_MODE_MASK ((uint32_t)0xFFFFFFFC)
//#define CG_NMIFLG_MASK ((uint32_t)0xFFF8FFFF)
#define FC_GEAR_1_1 ((uint32_t)0x00000000)
#define FC_GEAR_1_2 ((uint32_t)0x00000001)
#define FC_GEAR_1_4 ((uint32_t)0x00000002)
#define FC_GEAR_1_8 ((uint32_t)0x00000003)
#define FC_GEAR_1_16 ((uint32_t)0x00000004)
#define WARM_UP_SEL_OSC_INT_HIGH ((uint32_t)0xFFFFFEFF)
#define WARM_UP_SEL_OSC_EXT_HIGH ((uint32_t)0x00000100)
#define CG_PROTECT_SET ((uint32_t)0x000000C1)
#define CG_PROTECT_CLEAR ((uint32_t)0x0000003E)
//#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01)
#define ADC_MOD0_BUSY_MASK ((uint32_t)0x00000040)
#define CG_SPCLKEN_ADCKEN_CLEAR ((uint32_t)0xFFFEFFFF)
#define CG_SPCLKEN_ADCKEN_SET ((uint32_t)0x00010000)
static CG_DivideLevel numToDivideLevel_table[CG_DIVIDE_MAX] = {
CG_DIVIDE_1,
CG_DIVIDE_2,
CG_DIVIDE_4,
CG_DIVIDE_8,
CG_DIVIDE_16,
CG_DIVIDE_32,
CG_DIVIDE_64,
CG_DIVIDE_128,
CG_DIVIDE_256,
CG_DIVIDE_512,
CG_DIVIDE_UNKNOWN,
};
static CG_STBYMode numToSTBYMode_table[CG_STBY_MODE_MAX] = {
CG_STBY_MODE_IDLE,
CG_STBY_MODE_STOP1,
CG_STBY_MODE_UNKNOWN,
CG_STBY_MODE_UNKNOWN,
};
/** @} */
/* End of group CG_Private_Defines */
/** @defgroup CG_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group CG_Private_FunctionPrototypes */
/** @defgroup CG_Private_Functions
* @{
*/
/** @} */
/* End of group CG_Private_Functions */
/** @defgroup CG_Exported_Functions
* @{
*/
/**
* @brief Set dividing level between clock fgear and fc.
* @param DivideFgearFromFc: Dividing level between fgear and fc.
* This parameter can be one of the following values:
* CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, CG_DIVIDE_16
* @retval None
*/
void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc)
{
uint32_t gear = FC_GEAR_1_1;
uint32_t regval = TSB_CG->SYSCR;
/* Check the parameters */
assert_param(IS_CG_GEAR_DIVIDE_LEVEL(DivideFgearFromFc));
/* Set the value of fgear */
switch (DivideFgearFromFc) {
case CG_DIVIDE_1:
gear = FC_GEAR_1_1;
break;
case CG_DIVIDE_2:
gear = FC_GEAR_1_2;
break;
case CG_DIVIDE_4:
gear = FC_GEAR_1_4;
break;
case CG_DIVIDE_8:
gear = FC_GEAR_1_8;
break;
case CG_DIVIDE_16:
gear = FC_GEAR_1_16;
break;
default:
/* Do nothing */
break;
}
regval &= CG_FC_GEAR_MASK;
regval |= gear;
TSB_CG->SYSCR = regval;
}
/**
* @brief Get dividing level between clock fgear and fc.
* @param None
* @retval The dividing level between clock fgear and fc
* The value returned can be one of the following values:
* CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4,
* CG_DIVIDE_8, CG_DIVIDE_16 or CG_DIVIDE_UNKNOWN
*/
CG_DivideLevel CG_GetFgearLevel(void)
{
CG_DivideLevel DivideFgearFromFc = CG_DIVIDE_UNKNOWN;
uint32_t syscr = TSB_CG->SYSCR;
syscr &= (~CG_FC_GEAR_MASK);
switch (syscr) {
case FC_GEAR_1_1:
DivideFgearFromFc = CG_DIVIDE_1;
break;
case FC_GEAR_1_2:
DivideFgearFromFc = CG_DIVIDE_2;
break;
case FC_GEAR_1_4:
DivideFgearFromFc = CG_DIVIDE_4;
break;
case FC_GEAR_1_8:
DivideFgearFromFc = CG_DIVIDE_8;
break;
case FC_GEAR_1_16:
DivideFgearFromFc = CG_DIVIDE_16;
break;
default:
/* Do nothing */
break;
}
return DivideFgearFromFc;
}
/**
* @brief Set dividing level between clock PhiT0 and fc.
* @param DividePhiT0FromFc: Dividing level between PhiT0 and fc.
* This parameter can be one of the following values:
* CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
* CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
* CG_DIVIDE_256 or CG_DIVIDE_512
* @retval Success or not
* The value returned can be one of the following values:
* SUCCESS or ERROR
*/
Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc)
{
uint32_t fprclk = 0U;
Result retval = ERROR;
uint32_t regval = TSB_CG->SYSCR;
/* Check the parameters */
assert_param(IS_CG_DIVIDE_FC_LEVEL(DividePhiT0FromFc));
fprclk = (uint32_t) DividePhiT0FromFc;
regval &= CG_PRCK_MASK;
fprclk <<= 8U;
regval |= fprclk;
TSB_CG->SYSCR = regval;
retval = SUCCESS;
return retval;
}
/**
* @brief Get dividing level between clock phiT0 and fc.
* @param None
* @retval The divide level between clock phiT0 and fc
* The value returned can be one of the following values:
* CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
* CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
* CG_DIVIDE_256, CG_DIVIDE_512 or CG_DIVIDE_UNKNOWN
*/
CG_DivideLevel CG_GetPhiT0Level(void)
{
uint32_t fprclk = 0U;
CG_DivideLevel phiT0Level = CG_DIVIDE_UNKNOWN;
fprclk = TSB_CG->SYSCR & (~CG_PRCK_MASK);
fprclk = (uint32_t) (fprclk >> 8U);
phiT0Level = numToDivideLevel_table[fprclk];
return phiT0Level;
}
/**
* @brief Set the warm up time
* @param Source: Select source of warm-up counter
* This parameter can be one of the following values:
* CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WARM_UP_SRC_OSC_EXT_HIGH.
* Warm-up function is not necessary when using stable external clock.
* @param Time: Set number of warm-up cycle. It is between 0x0000 and 0xFFFF.
* @retval None
*/
void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time)
{
uint32_t wupt = 0U;
uint32_t regval = TSB_CG->WUPHCR;
/* Check the parameters */
assert_param(IS_CG_WARM_UP_SRC(Source));
/* Get high 12 bits of warm-up time */
wupt = (((uint32_t) Time) & CG_OSCCR_WUPT_MASK) << 20U;
regval &= CG_WUP_TIME_MASK;
regval &= CG_WUP_COUNTER_MASK;
switch (Source) {
case CG_WARM_UP_SRC_OSC_INT_HIGH:
regval |= wupt;
regval &= WARM_UP_SEL_OSC_INT_HIGH;
break;
case CG_WARM_UP_SRC_OSC_EXT_HIGH:
regval |= wupt;
regval |= WARM_UP_SEL_OSC_EXT_HIGH;
break;
default:
/* Do nothing */
break;
}
TSB_CG->WUPHCR = regval;
}
/**
* @brief Start operation of warm up timer for oscillator.
* @param None
* @retval None
*/
void CG_StartWarmUp(void)
{
uint32_t regval = TSB_CG->WUPHCR;
regval |= CG_WUP_START_SET;
TSB_CG->WUPHCR = regval;
}
/**
* @brief Check whether warm up is completed or not.
* @param None
* @retval The state of warm-up
* The value returned can be one of the following values:
* DONE or BUSY
*/
WorkState CG_GetWarmUpState(void)
{
WorkState state = BUSY;
uint32_t wuef = 0U;
uint32_t regval = TSB_CG->WUPHCR;
wuef = regval & CG_WUEF_VALUE_MASK;
if (wuef == 0U) {
state = DONE;
} else {
/* Do nothing */
}
return state;
}
/**
* @brief Set PLL multiplying value
* @param NewValue: PLL multiplying value
* This parameter can be one of the following values:
* CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL,
* CG_16M_MUL_6_FPLL.
* @retval Success or not
* The value returned can be one of the following values:
* SUCCESS or ERROR
*/
Result CG_SetFPLLValue(uint32_t NewValue)
{
Result retval = SUCCESS;
/* read PLL0SEL and clear PLL0SET(bit14:0) */
uint32_t tmp = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0SET_MASK;
/* Check the parameters */
assert_param(IS_CG_FPLL_VALUE(NewValue));
/* Don't use the PLL when internal high-speed oscillator (IHOSC) is used as system clock */
/* When PLL is on, don't change the PLL setting value */
if (CG_FOSC_OSC_INT == CG_GetFoscSrc()) {
retval = ERROR;
} else if (ENABLE == CG_GetPLLState()) {
retval = ERROR;
} else {
tmp |= NewValue;
TSB_CG->PLL0SEL = tmp;
}
return retval;
}
/**
* @brief Get the value of PLL setting
* @param None
* @retval Get the value of PLL setting.
* CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL,
* CG_16M_MUL_6_FPLL.
*/
uint32_t CG_GetFPLLValue(void)
{
uint32_t PLL0SEL = TSB_CG->PLL0SEL & CG_PLL0SET_VALUE_MASK;
return PLL0SEL;
}
/**
* @brief Enable PLL or disable it.
* @param NewState: New state of PLL
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval Success or not
* The value returned can be one of the following values:
* SUCCESS or ERROR
*/
Result CG_SetPLL(FunctionalState NewState)
{
Result retval = ERROR;
uint32_t regval = TSB_CG->PLL0SEL;
CG_FcSrc fcsrc = CG_FC_SRC_FPLL;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
regval |= CG_PLL0SEL_PLL0ON_SET;
retval = SUCCESS;
} else {
fcsrc = CG_GetFcSrc();
if (fcsrc == CG_FC_SRC_FOSC) { /* PLL is not used. So it can be shut off */
/* Set register to disable PLL */
regval &= CG_PLL0SEL_PLL0ON_CLEAR;
retval = SUCCESS;
} else { /*fcsrc == CG_FC_SRC_FPLL. PLL is in use, so disabling it should be invalid */
/* Do nothing */
}
}
TSB_CG->PLL0SEL = regval;
return retval;
}
/**
* @brief Get the status of PLL operation
* @param None
* @retval Run or stop
* The value returned can be one of the following values:
* ENABLE or DISABLE
*/
FunctionalState CG_GetPLLState(void)
{
FunctionalState pllstate = DISABLE;
uint32_t regval = TSB_CG->PLL0SEL;
regval &= CG_PLL0SEL_PLL0ON_SET;
if (regval == CG_PLL0SEL_PLL0ON_SET) {
pllstate = ENABLE;
} else {
/* Do nothing */
}
return pllstate;
}
/**
* @brief Set the source of high-speed oscillator (fosc)
* @param Source: Select clock source for fosc
* This parameter can be one of the following values:
* CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
* @retval None
*/
void CG_SetFoscSrc(CG_FoscSrc Source)
{
/* Check the parameters */
assert_param(IS_CG_FOSC_SRC(Source));
if (Source == CG_FOSC_OSC_INT) {
/*Selects internal high-speed oscillator */
TSB_CG->OSCCR |= CG_OSCCR_IOSCEN_SET;
TSB_CG->OSCCR &= CG_OSCCR_OSCSEL_CLEAR;
} else {
/*Selects external high-speed oscillator */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
TSB_CG->OSCCR &= CG_OSCCR_IOSCEN_CLEAR | CG_OSCCR_EOSCEN_NOUSE;
if (Source == CG_FOSC_OSC_EXT) {
/*Selects external high-speed oscillator */
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_EHOSC;
} else {
/*Selects an external clock input */
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_CLKIN;
}
}
}
/**
* @brief Get the source of high-speed oscillator (fosc)
* @param None
* @retval Source of fosc
* The value returned can be one of the following values:
* CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
*/
CG_FoscSrc CG_GetFoscSrc(void)
{
uint32_t regval = TSB_CG->OSCCR;
uint32_t oscf = 0U;
uint32_t hoscon = 0U;
CG_FoscSrc fosc_src = CG_FOSC_CLKIN_EXT;
oscf = regval & CG_OSCCR_OSCF_SET;
hoscon = regval & CG_OSCCR_EOSCEN_MASK;
if (oscf == 0U) {
fosc_src = CG_FOSC_OSC_INT;
} else {
if (hoscon == CG_OSCCR_EOSCEN_EHOSC) {
fosc_src = CG_FOSC_OSC_EXT;
} else {
/* Do nothing */
}
}
return fosc_src;
}
/**
* @brief Set to the specified low-power mode
* @param Low power mode
* The value can be one of the following values:
* CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE.
* @retval None
*/
void CG_SetSTBYMode(CG_STBYMode Mode)
{
uint32_t regval = TSB_CG->STBYCR;
/* Check the parameter */
assert_param(IS_CG_STBY_MODE(Mode));
regval &= CG_STBY_MODE_MASK;
regval |= (uint32_t) Mode;
TSB_CG->STBYCR = regval;
}
/**
* @brief Get the low-power consumption mode
* @param None
* @retval Low power mode
* The value returned can be one of the following values:
* CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE, CG_STBY_MODE_UNKNOWN.
*/
CG_STBYMode CG_GetSTBYMode(void)
{
CG_STBYMode stby_mode = CG_STBY_MODE_UNKNOWN;
uint8_t regval = (uint8_t) (TSB_CG->STBYCR & (~CG_STBY_MODE_MASK));
stby_mode = numToSTBYMode_table[regval];
return stby_mode;
}
/**
* @brief Set the source of fc
* @param Source: The source of fc
* This parameter can be one of the following values:
* CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
* @retval None
*/
void CG_SetFcSrc(CG_FcSrc Source)
{
uint32_t regval = TSB_CG->PLL0SEL;
/* Check the parameters */
assert_param(IS_CG_FC_SRC(Source));
if (Source == CG_FC_SRC_FOSC) {
regval &= CG_PLL0SEL_PLL0SEL_CLEAR;
} else {
regval |= CG_PLL0SEL_PLL0SEL_SET;
}
TSB_CG->PLL0SEL = regval;
}
/**
* @brief Get the source of fc
* @param None
* @retval The source of fc
* The value returned can be one of the following values:
* CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
*/
CG_FcSrc CG_GetFcSrc(void)
{
uint32_t regval = TSB_CG->PLL0SEL;
CG_FcSrc fcsrc = CG_FC_SRC_FOSC;
regval &= CG_PLL0SEL_PLLST_SET;
if (regval == CG_PLL0SEL_PLLST_SET) {
fcsrc = CG_FC_SRC_FPLL;
} else {
/* Do nothing */
}
return fcsrc;
}
/**
* @brief Enable or disable to protect CG registers
* @param NewState: New state of the CG protect register
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval None
*/
void CG_SetProtectCtrl(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
TSB_CG->PROTECT = CG_PROTECT_SET;
} else {
TSB_CG->PROTECT = CG_PROTECT_CLEAR;
}
}
/**
* @brief Enable or disable supplying clock fsys to peripheries
* @param Periph: The target peripheral of CG supplies clock
* This parameter can be one of the following values or their combination:
* CG_FC_PERIPH_PORTH, CG_FC_PERIPH_PORTJ, CG_FC_PERIPH_TMRB0_3,
* CG_FC_PERIPH_TMRB4_6, CG_FC_PERIPH_TMR16A, CG_FC_PERIPH_I2C0,
* CG_FC_PERIPH_SIO0, CG_FC_PERIPH_TSPI, CG_FC_PERIPH_DMAC,
* CG_FC_PERIPH_ADC, CG_FC_PERIPH_USBD, CG_FC_PERIPH_TMRD,
* CG_FC_PERIPHA_ALL.
* @param NewState: New state of clock supply setting.
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval None
*/
void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_CG_FC_PERIPHA(Periph));
if (NewState == ENABLE) { /* write '1' to enable */
TSB_CG->FSYSENA |= Periph;
} else { /* clear to '0' to disable */
TSB_CG->FSYSENA &= ~Periph;
}
}
/**
* @brief Enable or disable supplying clock fsys to peripheries
* @param Periph: The target peripheral of CG supplies clock
* This parameter can be one of the following values or their combination:
* CG_FC_PERIPH_TMRB7, CG_FC_PERIPH_SIO1, CG_FC_PERIPH_WDT,
* CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL.
* @param NewState: New state of clock supply setting.
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval None
*/
void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_CG_FC_PERIPHB(Periph));
if (NewState == ENABLE) { /* write '1' to enable */
TSB_CG->FSYSENB |= Periph;
} else { /* clear to '0' to disable */
TSB_CG->FSYSENB &= ~Periph;
}
}
/**
* @brief Enable or disable supplying clock fsys to peripheries
* @param Periph: The target peripheral of CG supplies clock
* This parameter can be one of the following values or their combination:
* CG_FPLL_PERIPH_TMRD, CG_EHCLKSEL_8_24_48MHZ, CG_USBSEL_PLL_CLOCKIN,
* CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL.
* @param NewState: New state of clock supply setting.
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval None
*/
void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_CG_FPLL_OPTIONAL(Periph));
if (NewState == ENABLE) { /* write '1' to enable */
TSB_CG->EXTENDO0 |= Periph;
} else { /* clear to '0' to disable */
TSB_CG->EXTENDO0 &= ~Periph;
}
}
/**
* @brief Enable or disable supplying clock fsys for ADC.
* @param NewState: New state of clock fsys supply setting for ADC.
* This parameter can be one of the following values:
* ENABLE or DISABLE.
* @retval None.
*/
void CG_SetADCClkSupply(FunctionalState NewState)
{
volatile uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Check ADC is not during conversion */
do {
tmp = TSB_AD->MOD0 & ADC_MOD0_BUSY_MASK;
}
while (tmp);
/* Set CGSPCLKEN<ADCKEN> */
tmp = TSB_CG->SPCLKEN;
if (NewState == ENABLE) {
tmp |= CG_SPCLKEN_ADCKEN_SET;
} else {
tmp &= CG_SPCLKEN_ADCKEN_CLEAR;
}
TSB_CG->SPCLKEN = tmp;
}
/** @} */
/* End of group CG_Exported_Functions */
/** @} */
/* End of group CG */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_CG_H) */

696
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c
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@ -1,696 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_gpio.c
* @brief This file provides API functions for GPIO driver.
* @version V2.0.2.1
* @date 2015/09/08
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_gpio.h"
#if defined(__TMPM066_GPIO_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
#define GPIO_NUM (9U) /*total number of gpio */
/**
* @brief the base address of GPIO port.
*/
const uint32_t GPIO_Base[GPIO_NUM] = {
TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE,
TSB_PD_BASE, TSB_PE_BASE, TSB_PF_BASE,
TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE
};
/**
* @brief:Information of gpio port.
* Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means:
* '0': that bit is not available
* '1': that bit is availabe
* For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are avaiable;
*/
const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = {
/* DATA CR FR1 FR2 OD PUP PDN SEL IE */
/* PA */ {0xFFU, 0xFFU, {0x80U, 0x00U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU},
/* PB */ {0x0FU, 0x0FU, {0x00U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU},
/* PC */ {0x3FU, 0x3FU, {0x3FU, 0x00U}, 0x3FU, 0x3FU, 0x3FU, 0x03U, 0x3FU},
/* PD */ {0x3FU, 0x3FU, {0x1FU, 0x0FU}, 0x3FU, 0x3FU, 0x3FU, 0x30U, 0x3FU},
/* PE */ {0x3FU, 0x3FU, {0x3FU, 0x02U}, 0x3FU, 0x3FU, 0x3FU, 0x00U, 0x3FU},
/* PF */ {0xFFU, 0xFFU, {0x3FU, 0x01U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU},
/* PG */ {0x03U, 0x03U, {0x03U, 0x00U}, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U},
/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU},
/* PJ */ {0x0FU, 0x0FU, {0x03U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x0FU, 0x0FU}
};
/** @defgroup GPIO_Exported_Functions
* @{
*/
/**
* @brief Read GPIO Data register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @retval Data:The value of DATA register.
*/
uint8_t GPIO_ReadData(GPIO_Port GPIO_x)
{
uint8_t Data = 0U;
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
Data = (uint8_t) PORT->DATA;
return Data;
}
/**
* @brief Read Bit of GPIO Data register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7.
* @retval BitValue:The value of specified Bit.
* This parameter can be one of the following values:
* GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
*/
uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x)
{
uint8_t Data = 0U;
uint8_t tmp = 0U;
uint8_t BitValue = 0U;
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_GPIO_BIT(Bit_x));
assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
Data = (uint8_t) PORT->DATA;
tmp = (uint8_t) (Data & Bit_x);
if (tmp) {
BitValue = GPIO_BIT_VALUE_1;
} else {
BitValue = GPIO_BIT_VALUE_0;
}
return (BitValue);
}
/**
* @brief Write specified value to GPIO DATA register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Data: specified value will be written to GPIO DATA register.
* @retval None
*/
void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_GPIO_WRITE(GPIO_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
PORT->DATA = Data;
}
/**
* @brief Write to specified Bit of GPIO DATA register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin,which can set as output.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param BitValue:The value of specified Bit.
* This parameter can be one of the following values:
* GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
* @retval None
*/
void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
{
uint8_t tmp = 0U;
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_GPIO_BIT_VALUE(BitValue));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
tmp = GPIO_ReadData(GPIO_x);
if (BitValue) {
tmp |= Bit_x;
} else {
Bit_x = (~Bit_x);
tmp &= Bit_x;
}
PORT->DATA = tmp;
}
/**
* @brief Initialize the specified GPIO pin.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param GPIO_InitStruct: The structure containing basic GPIO configuration.
* @retval None
*/
void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct)
{
uint8_t tmp = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct));
assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode));
assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp));
assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown));
assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain));
if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) {
assert_param(IS_GPIO_INPUT_VOLTAGE_STATE(GPIO_InitStruct->InputVoltage));
}
tmp = GPIO_InitStruct->IOMode;
switch (tmp) {
case GPIO_INPUT_MODE:
GPIO_SetInput(GPIO_x, Bit_x);
break;
case GPIO_OUTPUT_MODE:
GPIO_SetOutput(GPIO_x, Bit_x);
break;
default:
/* Do nothing */
break;
}
tmp = GPIO_InitStruct->PullUp;
switch (tmp) {
case GPIO_PULLUP_ENABLE:
GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE);
break;
case GPIO_PULLUP_DISABLE:
GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE);
break;
default:
/* Do nothing */
break;
}
tmp = GPIO_InitStruct->PullDown;
switch (tmp) {
case GPIO_PULLDOWN_ENABLE:
GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE);
break;
case GPIO_PULLDOWN_DISABLE:
GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE);
break;
default:
/* Do nothing */
break;
}
tmp = GPIO_InitStruct->OpenDrain;
switch (tmp) {
case GPIO_OPEN_DRAIN_ENABLE:
GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE);
break;
case GPIO_OPEN_DRAIN_DISABLE:
GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE);
break;
default:
/* Do nothing */
break;
}
if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) {
tmp = GPIO_InitStruct->InputVoltage;
switch (tmp) {
case GPIO_INPUT_VOLTAGE_3V:
GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_0);
break;
case GPIO_INPUT_VOLTAGE_1V8:
GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_1);
break;
default:
/* Do nothing */
break;
}
}
}
/**
* @brief Set specified GPIO Pin as output port.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @retval None
*/
void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x)
{
uint8_t tmp = 0U;
uint32_t i;
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
tmp = (~Bit_x);
for (i = 0U; i < FRMAX; i++) {
if (GPIO_SFRs[GPIO_x].PinFR[i]) {
PORT->FR[i] &= tmp;
} else {
/* Do nothing */
}
}
if (GPIO_SFRs[GPIO_x].PinIE) {
PORT->IE &= tmp;
} else {
/* Do nothing */
}
PORT->CR |= Bit_x;
}
/**
* @brief Set specified GPIO Pin as input port.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @retval None
*/
void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x)
{
uint8_t tmp = 0U;
uint32_t i;
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinIE;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
tmp = (~Bit_x);
for (i = 0U; i < FRMAX; i++) {
if (GPIO_SFRs[GPIO_x].PinFR[i]) {
PORT->FR[i] &= tmp;
} else {
/* Do nothing */
}
}
if (GPIO_SFRs[GPIO_x].PinCR) {
PORT->CR &= tmp;
} else {
/* Do nothing */
}
PORT->IE |= Bit_x;
}
/**
* @brief Set or clear the bit setting in output control register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param NewState: The output state of the pin.
* This parameter can be one of the following values:
* ENABLE , DISABLE.
* @retval None
*/
void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (NewState == ENABLE) {
PORT->CR |= Bit_x;
} else {
PORT->CR &= (~(uint32_t) Bit_x);
}
}
/**
* @brief Set or clear the bit setting in input control register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param NewState: The input state of the pin.
* This parameter can be one of the following values:
* ENABLE , DISABLE.
* @retval None
*/
void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinIE;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (NewState == ENABLE) {
PORT->IE |= Bit_x;
} else {
PORT->IE &= (~(uint32_t) Bit_x);
}
}
/**
* @brief Enable or Disable pull-up function of specified GPIO Pin.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param NewState: New state of the Pull-Up function.
* This parameter can be one of the following values:
* ENABLE , DISABLE.
* @retval None
*/
void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinPUP;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (NewState == ENABLE) {
PORT->PUP |= Bit_x;
} else {
PORT->PUP &= (~(uint32_t) Bit_x);
}
}
/**
* @brief Enable or Disable pull-down function of specified GPIO Pin.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param NewState: New state of the Pull-Down function.
* This parameter can be one of the following values:
* ENABLE , DISABLE.
* @retval None
*/
void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinPDN;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (NewState == ENABLE) {
PORT->PDN |= Bit_x;
} else {
PORT->PDN &= (~(uint32_t) Bit_x);
}
}
/**
* @brief Set specified GPIO Pin as open drain port or CMOS port.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param NewState: New state of the Open Drian function.
* This parameter can be one of the following values:
* ENABLE , DISABLE.
* @retval None
*/
void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinOD;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (NewState == ENABLE) {
PORT->OD |= Bit_x;
} else {
PORT->OD &= (~(uint32_t) Bit_x);
}
}
/**
* @brief Input voltage selection function of specified GPIO Pin.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PC, GPIO_PD, GPIO_PG.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @param BitValue:The value of specified Bit.
* This parameter can be one of the following values:
* GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
* @retval None
*/
void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT_INPUT_VOLTAGE(GPIO_x));
assert_param(IS_GPIO_BIT_VALUE(BitValue));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinSEL;
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_SEL(GPIO_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
if (BitValue) {
PORT->SEL |= Bit_x;
} else {
PORT->SEL &= (~(uint8_t) Bit_x);
}
}
/**
* @brief Enable specified GPIO Function register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param FuncReg_x: Select Function register of GPIO.
* This parameter can be one of the following values:
* GPIO_FUNC_REG_1, GPIO_FUNC_REG_2.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @retval None
*/
void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
PORT->FR[FuncReg_x] |= Bit_x;
}
/**
* @brief Disable specified GPIO Function register.
* @param GPIO_x: Select GPIO port.
* This parameter can be one of the following values:
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
* GPIO_PH, GPIO_PJ.
* @param FuncReg_x: Select Function register of GPIO.
* This parameter can be one of the following values:
* GPIO_FUNC_REG_1, GPIO_FUNC_REG_2.
* @param Bit_x: Select GPIO pin.
* This parameter can be one of the following values:
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
* or combination of the effective bits.
* @retval None
*/
void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
{
TSB_Port_TypeDef *PORT = 0U;
/* Check the parameters */
assert_param(IS_GPIO_PORT(GPIO_x));
assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
if (Bit_x == GPIO_BIT_ALL) {
Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
} else {
/* Do nothing */
}
/* Check the parameters */
assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x);
}
/** @} */
/* End of group GPIO_Exported_Functions */
/** @} */
/* End of group GPIO */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* (__TMPM066_GPIO_H) */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c
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@ -1,931 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_i2c.c
* @brief This file provides API functions for I2C driver.
* @version V2.0.2.1
* @date 2015/09/10
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_i2c.h"
#if defined(__TMPM066_I2C_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup I2C
* @brief I2C driver modules
* @{
*/
/** @defgroup I2C_Private_Defines
* @{
*/
#define I2CCR1_BC_MASK ((uint32_t)0x0000001F)
#define I2CCR1_ACK_SET ((uint32_t)0x00000010)
#define I2CCR1_ACK_CLEAR ((uint32_t)0x000000EF)
#define I2CCR1_SCK_MASK ((uint32_t)0x000000F8)
#define I2CCR1_NOACK_MASK ((uint32_t)0x00000008)
#define I2CCR1_NOACK_ENABLE ((uint32_t)0x00000000)
#define I2CCR2_PIN_SET ((uint32_t)0x00000010)
#define I2CCR2_I2CM_I2C ((uint32_t)0x00000008)
#define I2CCR2_SWRST_MASK ((uint32_t)0xFFFFFFFC)
#define I2CCR2_SWRST_CMD1 ((uint32_t)0x00000002)
#define I2CCR2_SWRST_CMD2 ((uint32_t)0x00000001)
#define I2CCR2_START_CONDITION ((uint32_t)0x000000F0)
#define I2CCR2_STOP_CONDITION ((uint32_t)0x000000D0)
#define I2CAR_SA_MASK ((uint32_t)0x000000FE)
#define I2CAR_ALS_SET ((uint32_t)0x00000001)
#define I2CAR_ALS_CLEAR ((uint32_t)0xFFFFFFFE)
#define I2C_DATA_MASK ((uint32_t)0x000000FF)
#define I2CIE_IE_SELPINCD_SET ((uint32_t)0x00000040)
#define I2CIE_IE_DMARI2CTX_SET ((uint32_t)0x00000020)
#define I2CIE_IE_DMARI2CRX_SET ((uint32_t)0x00000010)
#define I2CIE_IE_INTNACK_SET ((uint32_t)0x00000008)
#define I2CIE_IE_INTI2CBF_SET ((uint32_t)0x00000004)
#define I2CIE_IE_INTI2CAL_SET ((uint32_t)0x00000002)
#define I2CIE_IE_INTI2C_SET ((uint32_t)0x00000001)
#define I2CIE_IE_SELPINCD_CLEAR ((uint32_t)0xFFFFFFBF)
#define I2CIE_IE_DMARI2CTX_CLEAR ((uint32_t)0xFFFFFFDF)
#define I2CIE_IE_DMARI2CRX_CLEAR ((uint32_t)0xFFFFFFEF)
#define I2CIE_IE_INTNACK_CLEAR ((uint32_t)0xFFFFFFF7)
#define I2CIE_IE_INTI2CBF_CLEAR ((uint32_t)0xFFFFFFFB)
#define I2CIE_IE_INTI2CAL_CLEAR ((uint32_t)0xFFFFFFFD)
#define I2CIE_IE_NTI2C_CLEAR ((uint32_t)0xFFFFFFFE)
#define I2CST_NACK_MASK ((uint32_t)0x00000008)
#define I2CST_I2CBF_MASK ((uint32_t)0x00000004)
#define I2CST_I2CAL_MASK ((uint32_t)0x00000002)
#define I2CST_I2C_MASK ((uint32_t)0x00000001)
#define I2CST_NACK_SET ((uint32_t)0x00000008)
#define I2CST_I2CBF_SET ((uint32_t)0x00000004)
#define I2CST_I2CAL_SET ((uint32_t)0x00000002)
#define I2CST_I2C_SET ((uint32_t)0x00000001)
#define I2COP_GCDI_ON ((uint32_t)0x000000FB)
#define I2COP_GCDI_OFF ((uint32_t)0x00000004)
#define I2COP_RSTA_SET ((uint32_t)0x00000008)
#define I2COP_RSTA_CLEAR ((uint32_t)0xFFFFFFF7)
#define I2COP_MFACK_NACK ((uint32_t)0x00000001)
#define I2COP_MFACK_ACK ((uint32_t)0xFFFFFFFE)
#define I2COP_SREN_SET ((uint32_t)0x00000002)
#define I2COP_SREN_CLEAR ((uint32_t)0xFFFFFFFD)
#define I2CAR2_SA2EN_USE ((uint32_t)0x00000001)
#define I2CAR2_SA2EN_NOUSE ((uint32_t)0x000000FE)
/** @} */
/* End of group I2C_Private_Defines */
/** @defgroup I2C_Exported_Functions
* @{
*/
/**
* @brief Enable or disable the generation of ACK clock.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of ACK clock.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmp = I2Cx->CR1;
if (NewState == ENABLE) {
/* Set I2CxCR1<ACK> to enable generation of ACK clock */
tmp |= I2CCR1_ACK_SET;
} else {
/* Clear I2CxCR1<ACK> to disable generation of ACK clock */
tmp &= I2CCR1_ACK_CLEAR;
}
I2Cx->CR1 = tmp;
}
/**
* @brief Initialize the specified I2C channel in I2C mode.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param InitI2CStruct: The structure containing I2C in I2C mode configuration.
* @retval None
*/
void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_POINTER_NOT_NULL(InitI2CStruct));
assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr));
assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen));
assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv));
assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState));
/* Get the system clock frequency */
SystemCoreClockUpdate();
/* Check the prescaler clock in the range between 50ns and 150ns */
assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock));
/* Set prescaler clock */
I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32;
/* Set selfaddress for I2Cx */
I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK;
/* Set I2C bit length of transfer data */
tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
tmp |= (InitI2CStruct->I2CDataLen << 5U);
/* Set I2C clock division */
tmp &= I2CCR1_SCK_MASK;
tmp |= InitI2CStruct->I2CClkDiv;
if (InitI2CStruct->I2CACKState) {
/* Set I2CxCR1<ACK> to enable generation of ACK clock */
tmp |= I2CCR1_ACK_SET;
} else {
/* Clear I2CxCR1<ACK> to disable generation of ACK clock */
tmp &= I2CCR1_ACK_CLEAR;
}
I2Cx->CR1 = tmp;
/* Intilize I2C to I2C Slave-Rx mode */
I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C;
}
/**
* @brief Specify the number of bits per transfer.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param I2CBitNum: Specify the number of bits.
* This parameter can be one of the following values:
* I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3,
* I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7.
* @retval None
*/
void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_I2C_BIT_NUM(I2CBitNum));
/* Write number of bits per transfer into I2CxCR1<BC> */
tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
tmp |= ((uint32_t) I2CBitNum << 5U);
I2Cx->CR1 = tmp;
}
/**
* @brief Reset the state of the specified I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_SWReset(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK;
I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1;
I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2;
}
/**
* @brief Clear I2C interrupt request in I2C mode.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxCR2<PIN> to clear request, and Set I2CxCR2<I2CM> to enable I2C operation */
tmp = I2Cx->SR;
tmp &= (uint32_t) 0x000000E0;
tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C);
I2Cx->CR2 = tmp;
}
/**
* @brief Set I2c bus to Master mode and Generate start condition in I2C mode.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxCR2<MST>, <TRX>, <BB> and <PIN> to generate start condition */
I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C;
}
/**
* @brief Set I2c bus to Master mode and Generate stop condition in I2C mode.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxCR2<MST>, <TRX>, <PIN> and clear <BB> to generate stop condition */
I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C;
}
/**
* @brief Get the I2C channel state in I2C mode
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval The state of the I2C channel in I2C bus.
*/
I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx)
{
I2C_State state;
state.All = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
state.All = I2Cx->SR;
state.All &= I2C_DATA_MASK;
return state;
}
/**
* @brief Set data to be sent and MCU starts transmission.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param Data: The data to be sent, max 0xFF.
* @retval None
*/
void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_I2C_DATA(Data));
/* Write data into I2CxDBR */
I2Cx->DBR = Data;
}
/**
* @brief Get data having been received.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval The data having been received
*/
uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx)
{
uint32_t retval = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Save the received data */
retval = I2Cx->DBR;
retval &= I2C_DATA_MASK;
return retval;
}
/**
* @brief Enable or disable I2C free data mode of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of free data mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxI2CAR<ALS> to use free data mode transfer in I2C mode */
I2Cx->AR |= I2CAR_ALS_SET;
} else {
/* Clear I2CxI2CAR<ALS> to not use free data mode transfer in I2C mode */
I2Cx->AR &= I2CAR_ALS_CLEAR;
}
}
/**
* @brief Get slave address match detection state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK;
if (tmp == I2CCR1_NOACK_ENABLE) {
/* the slave address match or general call detection are enabled. */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Set prescaler clock of the specified I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param PrescalerClock: the prescaler clock value.
* This parameter can be one of the following values:
* I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32
* @retval None
*/
void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Get the system clock frequency */
SystemCoreClockUpdate();
/* Check the prescaler clock in the range between 50ns and 150ns */
assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock));
/* Write prescaler clock into I2CxPRS<PRSCK> */
I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32;
}
/**
* @brief Enable or disable open condition of the pin.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<SELPINCD> to enable pin open by reading DBR */
I2Cx->IE |= I2CIE_IE_SELPINCD_SET;
} else {
/* Clear I2CxIE<SELPINCD> to disable pin open by reading DBR */
I2Cx->IE &= I2CIE_IE_SELPINCD_CLEAR;
}
}
/**
* @brief Enable or disable a DMAC transmisstion request output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<DMARI2CTX> to enable a DMAC transmisstion request */
I2Cx->IE |= I2CIE_IE_DMARI2CTX_SET;
} else {
/* Clear I2CxIE<DMARI2CTX> to disable a DMAC transmisstion request */
I2Cx->IE &= I2CIE_IE_DMARI2CTX_CLEAR;
}
}
/**
* @brief Enable or disable a DMAC reception request output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<DMARI2CRX> to enable a DMAC reception request */
I2Cx->IE |= I2CIE_IE_DMARI2CRX_SET;
} else {
/* Clear I2CxIE<DMARI2CRX> to disable a DMAC reception request */
I2Cx->IE &= I2CIE_IE_DMARI2CRX_CLEAR;
}
}
/**
* @brief Enable or disable NACK detection interrupt of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<INTNACK> to enable NACK detection interrupt */
I2Cx->IE |= I2CIE_IE_INTNACK_SET;
} else {
/* Clear I2CxIE<INTNACK> to disable NACK detection interrupt */
I2Cx->IE &= I2CIE_IE_INTNACK_CLEAR;
}
}
/**
* @brief Enable or disable bus-free interrupt of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<INTNACK> to enable bus-free interrupt */
I2Cx->IE |= I2CIE_IE_INTI2CBF_SET;
} else {
/* Clear I2CxIE<INTNACK> to disable bus-free interrupt */
I2Cx->IE &= I2CIE_IE_INTI2CBF_CLEAR;
}
}
/**
* @brief Enable or disable AL interrupt of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<INTNACK> to enable AL interrupt */
I2Cx->IE |= I2CIE_IE_INTI2CAL_SET;
} else {
/* Clear I2CxIE<INTNACK> to disable AL interrupt */
I2Cx->IE &= I2CIE_IE_INTI2CAL_CLEAR;
}
}
/**
* @brief Enable or disable I2C interrupt request of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: Specify I2C interrupt setting.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxIE<IE> to enable I2C interrupt request */
I2Cx->IE |= I2CIE_IE_INTI2C_SET;
} else {
/* Clear I2CxIE<IE> to disable I2C interrupt request */
I2Cx->IE &= I2CIE_IE_NTI2C_CLEAR;
}
}
/**
* @brief Get NACK interrupt generation state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->ST & I2CST_NACK_MASK;
if (tmp == I2CST_NACK_SET) {
/* the NACK interrupt has been generated */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Get I2CBF interrupt generation state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->ST & I2CST_I2CBF_MASK;
if (tmp == I2CST_I2CBF_SET) {
/* the I2CBF interrupt has been generated */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Get I2CAL interrupt generation state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->ST & I2CST_I2CAL_MASK;
if (tmp == I2CST_I2CAL_SET) {
/* the I2CAL interrupt has been generated */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Get I2C interrupt generation state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->ST & I2CST_I2C_MASK;
if (tmp == I2CST_I2C_SET) {
/* the I2C interrupt has been generated */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Clear the NACK interrupt output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxST<NACK> to clear the NACK interrupt output(INTI2Cx) */
I2Cx->ST = I2CST_NACK_SET;
}
/**
* @brief Clear the I2CBF interrupt output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxST<I2CBF> to clear the I2CBF interrupt output(INTI2Cx) */
I2Cx->ST = I2CST_I2CBF_SET;
}
/**
* @brief Clear the I2CAL interrupt output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxST<I2CAL> to clear the I2CAL interrupt output(INTI2Cx) */
I2Cx->ST = I2CST_I2CAL_SET;
}
/**
* @brief Clear the I2C interrupt output.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval None
*/
void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
/* Set I2CxST<I2C> to clear the I2C interrupt output(INTI2Cx) */
I2Cx->ST = I2CST_I2C_SET;
}
/**
* @brief Enable or disable general-call detection.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of general call detection.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmp = I2Cx->OP;
if (NewState == ENABLE) {
/* Clear I2CxOP<GCDI>, general-call detection is ON */
tmp &= I2COP_GCDI_ON;
} else {
/* Set I2CxOP<GCDI>, general-call detection is OFF */
tmp |= I2COP_GCDI_OFF;
}
I2Cx->OP = tmp;
}
/**
* @brief Detect or not a repeated start of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of free data mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxI2COP<RSTA> to detect a repeated start */
I2Cx->OP |= I2COP_RSTA_SET;
} else {
/* Clear I2CxI2COP<RSTA> to not detect a repeated start */
I2Cx->OP &= I2COP_RSTA_CLEAR;
}
}
/**
* @brief Get repeated start detection state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval DISABLE or ENABLE.
*/
FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
FunctionalState retval = DISABLE;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->OP & I2COP_RSTA_SET;
if (tmp == I2COP_RSTA_SET) {
/* the repeated start detection are enabled. */
retval = ENABLE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Select an ACK output of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of free data mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxI2COP<MFACK> to select NACK output */
I2Cx->OP |= I2COP_MFACK_NACK;
} else {
/* Clear I2CxI2COP<MFACK> to select ACK output */
I2Cx->OP &= I2COP_MFACK_ACK;
}
}
/**
* @brief Enable or disable repeat start of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of free data mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxI2COP<SREN> to enable repeat start output */
I2Cx->OP |= I2COP_SREN_SET;
} else {
/* Clear I2CxI2COP<SREN> to disable repeat start output */
I2Cx->OP &= I2COP_SREN_CLEAR;
}
}
/**
* @brief Get repeated start state.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @retval BUSY or DONE.
*/
WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx)
{
uint32_t tmp = 0U;
WorkState retval = BUSY;
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
tmp = I2Cx->OP & I2COP_SREN_SET;
if (tmp == I2COP_SREN_SET) {
/* the repeated start detection has completed. */
retval = DONE;
} else {
/* Do nothing */
}
return retval;
}
/**
* @brief Enable or disable using 2nd slave address of the I2C channel.
* @param I2Cx: Select the I2C channel.
* This parameter can be one of the following values:
* TSB_I2C0,TSB_I2C1
* @param NewState: New state of free data mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void I2C_Set2ndSlaveAddress(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) {
/* Set I2CxI2CAR2<SA2EN> to using 2nd slave address */
I2Cx->AR2 |= I2CAR2_SA2EN_USE;
} else {
/* Clear I2CxI2CAR2<SA2EN> to not using 2nd slave address */
I2Cx->AR2 &= I2CAR2_SA2EN_NOUSE;
}
}
/** @} */
/* End of group I2C_Exported_Functions */
/** @} */
/* End of group I2C */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_I2C_H) */

284
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c
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@ -1,284 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_intifao.c
* @brief This file provides API functions for INTIFAO driver
* @version V2.0.2.2
* @date 2016/02/15
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_intifao.h"
#if defined(__TMPM066_INTIFAO_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup INTIFAO
* @brief INTIFAO driver modules
* @{
*/
/** @defgroup INTIFAO_Private_Defines
* @{
*/
#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01)
#define INT_EN_MODE_MASK ((uint8_t)0xF0)
#define INT_MODE_MASK ((uint8_t)0x0E)
#define INTIFAO_INTFLAG1_MASK ((uint32_t)0xFFFFFF00)
/** @} */
/* End of group INTIFAO_Private_Defines */
/** @defgroup INTIFAO_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group INTIFAO_Private_FunctionPrototypes */
/** @defgroup INTIFAO_Private_Functions
* @{
*/
/** @} */
/* End of group INTIFAO_Private_Functions */
/** @defgroup INTIFAO_Exported_Functions
* @{
*/
/**
* @brief Setup the INT source for releasing low power mode.
* @param INTSource: Select the release INT source
* This parameter can be one of the following values:
* INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
* INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
* @param ActiveState: select the active state for release trigger
* This parameter can be one of the following values:
* INTIFAO_INT_ACTIVE_STATE_L,
* INTIFAO_INT_ACTIVE_STATE_H,
* INTIFAO_INT_ACTIVE_STATE_FALLING,
* INTIFAO_INT_ACTIVE_STATE_RISING or
* INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES.
* @param NewState: Enable or disable this release trigger
* This parameter can be one of the following values:
* DISABLE or ENABLE
* @retval None
*/
void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource,
INTIFAO_INTActiveState ActiveState, FunctionalState NewState)
{
uint8_t num = 0U;
uint32_t regval;
/* Check the parameters */
assert_param(IS_INTIFAO_INT_SRC(INTSource));
assert_param(IS_INTIFAO_INT_ACTIVE_STATE(ActiveState));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if ((INTSource == INTIFAO_INT_SRC_I2CS) || (INTSource == INTIFAO_INT_SRC_USBWKUP)) {
assert_param(IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(ActiveState));
} else {
/* Do nothing */
}
num = (uint32_t) INTSource;
switch (num) {
case 0U: /* STOP2INT_032 */
regval = TSB_INTIFAO ->STOP2INT_032;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_032 = regval;
break;
case 1U: /* STOP2INT_033 */
regval = TSB_INTIFAO ->STOP2INT_033;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_033 = regval;
break;
case 2U: /* STOP2INT_034 */
regval = TSB_INTIFAO ->STOP2INT_034;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_034 = regval;
break;
case 3U: /* STOP2INT_035 */
regval = TSB_INTIFAO ->STOP2INT_035;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_035 = regval;
break;
case 4U: /* STOP2INT_036 */
regval = TSB_INTIFAO ->STOP2INT_036;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_036 = regval;
break;
case 5U: /* STOP2INT_037 */
regval = TSB_INTIFAO ->STOP2INT_037;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_037 = regval;
break;
case 6U: /* STOP2INT_038 */
regval = TSB_INTIFAO ->STOP2INT_038;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_038 = regval;
break;
case 7U: /* STOP2INT_039 */
regval = TSB_INTIFAO ->STOP2INT_039;
regval &= INT_EN_MODE_MASK;
regval |= NewState;
regval |= ActiveState << 1;
TSB_INTIFAO ->STOP2INT_039 = regval;
break;
default:
/* Do nothing */
break;
}
}
/**
* @brief Get the active state of INT source standby clear request
* @param INTSource: Select the release INT source
* This parameter can be one of the following values:
* INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
* INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
* @retval Active state of the input INT
* The value returned can be one of the following values:
* INTIFAO_INT_ACTIVE_STATE_FALLING, INTIFAO_INT_ACTIVE_STATE_RISING,
* INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES or INTIFAO_INT_ACTIVE_STATE_INVALID
*/
INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource)
{
INTIFAO_INTActiveState int_active_state = INTIFAO_INT_ACTIVE_STATE_INVALID;
uint8_t tmp = 0U;
uint8_t num = 0U;
uint8_t regval[8] = {0};
/* Check the parameters */
assert_param(IS_INTIFAO_INT_SRC(INTSource));
regval[0] = TSB_INTIFAO ->STOP2INT_032 & INT_MODE_MASK;
regval[1] = TSB_INTIFAO ->STOP2INT_033 & INT_MODE_MASK;
regval[2] = TSB_INTIFAO ->STOP2INT_034 & INT_MODE_MASK;
regval[3] = TSB_INTIFAO ->STOP2INT_035 & INT_MODE_MASK;
regval[4] = TSB_INTIFAO ->STOP2INT_036 & INT_MODE_MASK;
regval[5] = TSB_INTIFAO ->STOP2INT_037 & INT_MODE_MASK;
regval[6] = TSB_INTIFAO ->STOP2INT_038 & INT_MODE_MASK;
regval[7] = TSB_INTIFAO ->STOP2INT_039 & INT_MODE_MASK;
num = (uint32_t) INTSource;
tmp = regval[num];
tmp = tmp >>1;
switch (tmp) {
case 3U:
int_active_state = INTIFAO_INT_ACTIVE_STATE_RISING;
break;
case 2U:
int_active_state = INTIFAO_INT_ACTIVE_STATE_FALLING;
break;
case 4U:
int_active_state = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
break;
default:
/* Do nothing */
break;
}
return (int_active_state);
}
/**
* @brief Clears the input INT request.
* @param INTSource: Select the release INT source
* This parameter can be one of the following values:
* INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
* INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
* @retval None
*/
void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource)
{
uint8_t num = 0U;
/* Check the parameters */
assert_param(IS_INTIFAO_INT_SRC(INTSource));
num = (uint32_t) INTSource;
switch (num) {
case 0U: /* STOP2INT_032 */
TSB_INTIFAO_STOP2INT_032_INT032PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_032_INT032NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 1U: /* STOP2INT_033 */
TSB_INTIFAO_STOP2INT_033_INT033PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_033_INT033NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 2U: /* STOP2INT_034 */
TSB_INTIFAO_STOP2INT_034_INT034PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_034_INT034NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 3U: /* STOP2INT_035 */
TSB_INTIFAO_STOP2INT_035_INT035PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_035_INT035NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 4U: /* STOP2INT_036 */
TSB_INTIFAO_STOP2INT_036_INT036PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_036_INT036NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 5U: /* STOP2INT_037 */
TSB_INTIFAO_STOP2INT_037_INT037PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_037_INT037NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 6U: /* STOP2INT_038 */
TSB_INTIFAO_STOP2INT_038_INT038PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_038_INT038NCLR = INT_NCLR_PCLR_CLEAR;
break;
case 7U: /* STOP2INT_039 */
TSB_INTIFAO_STOP2INT_039_INT039PCLR = INT_NCLR_PCLR_CLEAR;
TSB_INTIFAO_STOP2INT_039_INT039NCLR = INT_NCLR_PCLR_CLEAR;
break;
default:
/* Do nothing */
break;
}
}
/**
* @brief Get the INTFLAG1.
* @param None
* @retval INTFLAG1 flag
*/
INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void)
{
INTIFAO_IntFlag1Factor intifao_intflag1_factor = { 0U };
intifao_intflag1_factor.All = TSB_INTIFSD->FLAG1 & (~INTIFAO_INTFLAG1_MASK);
return intifao_intflag1_factor;
}
/** @} */
/* End of group INTIFAO_Exported_Functions */
/** @} */
/* End of group INTIFAO */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_INTIFAO_H) */

368
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c
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@ -1,368 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_intifsd.c
* @brief This file provides API functions for INTIFSD driver
* @version V2.0.2.1
* @date 2015/10/19
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_intifsd.h"
#if defined(__TMPM066_INTIFSD_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup INTIFSD
* @brief INTIFSD driver modules
* @{
*/
/** @defgroup INTIFSD_Private_Defines
* @{
*/
#define INTIFSD_NMIFLG_MASK ((uint32_t)0xFFF8FFFF)
#define INTIFSD_INTFLAG4_MASK ((uint32_t)0xE0000000)
#define INTIFSD_INTFLAG5_MASK ((uint32_t)0xFFFFFC00)
/** @} */
/* End of group INTIFSD_Private_Defines */
/** @defgroup INTIFSD_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group INTIFSD_Private_FunctionPrototypes */
/** @defgroup INTIFSD_Private_Functions
* @{
*/
/** @} */
/* End of group INTIFSD_Private_Functions */
/** @defgroup INTIFSD_Exported_Functions
* @{
*/
/**
* @brief Get the NMI flag that shows who triggered NMI.
* @param None
* @retval NMI flag
*/
INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void)
{
INTIFSD_NMIFactor intifsd_nmi_factor = { 0U };
intifsd_nmi_factor.All = TSB_INTIFSD->FLAG0 & (~INTIFSD_NMIFLG_MASK);
return intifsd_nmi_factor;
}
/**
* @brief Get the INTFLAG3.
* @param None
* @retval INTFLAG3 flag
*/
INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void)
{
INTIFSD_IntFlag3Factor intifsd_intflag3_factor = { 0U };
intifsd_intflag3_factor.All = TSB_INTIFSD->FLAG3;
return intifsd_intflag3_factor;
}
/**
* @brief Get the INTFLAG4.
* @param None
* @retval INTFLAG4 flag
*/
INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void)
{
INTIFSD_IntFlag4Factor intifsd_intflag4_factor = { 0U };
intifsd_intflag4_factor.All = TSB_INTIFSD->FLAG4 & (~INTIFSD_INTFLAG4_MASK);
return intifsd_intflag4_factor;
}
/**
* @brief Get the INTFLAG5.
* @param None
* @retval INTFLAG5 flag
*/
INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void)
{
INTIFSD_IntFlag5Factor intifsd_intflag5_factor = { 0U };
intifsd_intflag5_factor.All = TSB_INTIFSD->FLAG5 & (~INTIFSD_INTFLAG5_MASK);
return intifsd_intflag5_factor;
}
/**
* @brief Clears the input INT request.
* @param INTSource: Select the release INT source
* This parameter can be one of the following values:
* INTIFSD_INT_SRC_LVD_PSFD, INTIFSD_INT_SRC_LVD_PRD, INTIFSD_INT_SRC_WDT, INTIFSD_INT_SRC_DMAC_0,
* INTIFSD_INT_SRC_DMAC_1, INTIFSD_INT_SRC_DMAC_2, INTIFSD_INT_SRC_DMAC_3, INTIFSD_INT_SRC_DMAC_4,
* INTIFSD_INT_SRC_DMAC_5, INTIFSD_INT_SRC_DMAC_6, INTIFSD_INT_SRC_DMAC_7, INTIFSD_INT_SRC_DMAC_8,
* INTIFSD_INT_SRC_DMAC_9, INTIFSD_INT_SRC_DMAC_10, INTIFSD_INT_SRC_DMAC_11, INTIFSD_INT_SRC_DMAC_12,
* INTIFSD_INT_SRC_DMAC_13, INTIFSD_INT_SRC_DMAC_14, INTIFSD_INT_SRC_DMAC_15, INTIFSD_INT_SRC_DMAC_16,
* INTIFSD_INT_SRC_DMAC_17, INTIFSD_INT_SRC_DMAC_18, INTIFSD_INT_SRC_DMAC_19, INTIFSD_INT_SRC_DMAC_20,
* INTIFSD_INT_SRC_DMAC_21, INTIFSD_INT_SRC_DMAC_22, INTIFSD_INT_SRC_DMAC_23, INTIFSD_INT_SRC_DMAC_24,
* INTIFSD_INT_SRC_DMAC_25, INTIFSD_INT_SRC_DMAC_26, INTIFSD_INT_SRC_DMAC_27, INTIFSD_INT_SRC_DMAC_28,
* INTIFSD_INT_SRC_DMAC_29, INTIFSD_INT_SRC_DMAC_30, INTIFSD_INT_SRC_DMAC_31, INTIFSD_INT_SRC_DMAC_ERR,
* INTIFSD_INT_SRC_TMRB_0_MDOVF, INTIFSD_INT_SRC_TMRB_0_CAP0, INTIFSD_INT_SRC_TMRB_0_CAP1, INTIFSD_INT_SRC_TMRB_1_MDOVF,
* INTIFSD_INT_SRC_TMRB_1_CAP0, INTIFSD_INT_SRC_TMRB_1_CAP1, INTIFSD_INT_SRC_TMRB_2_MDOVF, INTIFSD_INT_SRC_TMRB_2_CAP0,
* INTIFSD_INT_SRC_TMRB_2_CAP1, INTIFSD_INT_SRC_TMRB_3_MDOVF, INTIFSD_INT_SRC_TMRB_3_CAP0, INTIFSD_INT_SRC_TMRB_3_CAP1,
* INTIFSD_INT_SRC_TMRB_4_MDOVF,INTIFSD_INT_SRC_TMRB_4_CAP0, INTIFSD_INT_SRC_TMRB_4_CAP1, INTIFSD_INT_SRC_TMRB_5_MDOVF,
* INTIFSD_INT_SRC_TMRB_5_CAP0, INTIFSD_INT_SRC_TMRB_5_CAP1, INTIFSD_INT_SRC_TMRB_6_MDOVF, INTIFSD_INT_SRC_TMRB_6_CAP0,
* INTIFSD_INT_SRC_TMRB_6_CAP1, INTIFSD_INT_SRC_TMRB_7_MDOVF, INTIFSD_INT_SRC_TMRB_7_CAP0, INTIFSD_INT_SRC_TMRB_7_CAP1,
* INTIFSD_INT_SRC_TMRD_00, INTIFSD_INT_SRC_TMRD_01, INTIFSD_INT_SRC_TMRD_02, INTIFSD_INT_SRC_TMRD_03,
* INTIFSD_INT_SRC_TMRD_04, INTIFSD_INT_SRC_TMRD_10, INTIFSD_INT_SRC_TMRD_11, INTIFSD_INT_SRC_TMRD_12,
* INTIFSD_INT_SRC_TMRD_13, INTIFSD_INT_SRC_TMRD_14.
* @retval None
*/
void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource)
{
uint8_t num = 0U;
/* Check the parameters */
assert_param(IS_INTIFSD_INT_SRC(INTSource));
num = (uint32_t) INTSource;
switch (num) {
case 0U: /* STOP1INT_016 */
TSB_INTIFSD->STOP1INT_016 |= 0xC0;
break;
case 1U: /* STOP1INT_017 */
TSB_INTIFSD->STOP1INT_017 |= 0xC0;
break;
case 2U: /* IDLEINT_018 */
TSB_INTIFSD->IDLEINT_018 |= 0xC0;
break;
case 3U: /* IDLEINT_096 */
TSB_INTIFSD->IDLEINT_096 |= 0xC0;
break;
case 4U: /* IDLEINT_097 */
TSB_INTIFSD->IDLEINT_097 |= 0xC0;
break;
case 5U: /* IDLEINT_098 */
TSB_INTIFSD->IDLEINT_098 |= 0xC0;
break;
case 6U: /* IDLEINT_099 */
TSB_INTIFSD->IDLEINT_099 |= 0xC0;
break;
case 7U: /* IDLEINT_100 */
TSB_INTIFSD->IDLEINT_100 |= 0xC0;
break;
case 8U: /* IDLEINT_101 */
TSB_INTIFSD->IDLEINT_101 |= 0xC0;
break;
case 9U: /* IDLEINT_102 */
TSB_INTIFSD->IDLEINT_102 |= 0xC0;
break;
case 10U: /* IDLEINT_103 */
TSB_INTIFSD->IDLEINT_103 |= 0xC0;
break;
case 11U: /* IDLEINT_104 */
TSB_INTIFSD->IDLEINT_104 |= 0xC0;
break;
case 12U: /* IDLEINT_105 */
TSB_INTIFSD->IDLEINT_105 |= 0xC0;
break;
case 13U: /* IDLEINT_106 */
TSB_INTIFSD->IDLEINT_106 |= 0xC0;
break;
case 14U: /* IDLEINT_107 */
TSB_INTIFSD->IDLEINT_107 |= 0xC0;
break;
case 15U: /* IDLEINT_108 */
TSB_INTIFSD->IDLEINT_108 |= 0xC0;
break;
case 16U: /* IDLEINT_109 */
TSB_INTIFSD->IDLEINT_109 |= 0xC0;
break;
case 17U: /* IDLEINT_110 */
TSB_INTIFSD->IDLEINT_110 |= 0xC0;
break;
case 18U: /* IDLEINT_111 */
TSB_INTIFSD->IDLEINT_111 |= 0xC0;
break;
case 19U: /* IDLEINT_112 */
TSB_INTIFSD->IDLEINT_112 |= 0xC0;
break;
case 20U: /* IDLEINT_113 */
TSB_INTIFSD->IDLEINT_113 |= 0xC0;
break;
case 21U: /* IDLEINT_114 */
TSB_INTIFSD->IDLEINT_114 |= 0xC0;
break;
case 22U: /* IDLEINT_115 */
TSB_INTIFSD->IDLEINT_115 |= 0xC0;
break;
case 23U: /* IDLEINT_116 */
TSB_INTIFSD->IDLEINT_116 |= 0xC0;
break;
case 24U: /* IDLEINT_117 */
TSB_INTIFSD->IDLEINT_117 |= 0xC0;
break;
case 25U: /* IDLEINT_118 */
TSB_INTIFSD->IDLEINT_118 |= 0xC0;
break;
case 26U: /* IDLEINT_119 */
TSB_INTIFSD->IDLEINT_119 |= 0xC0;
break;
case 27U: /* IDLEINT_120 */
TSB_INTIFSD->IDLEINT_120 |= 0xC0;
break;
case 28U: /* IDLEINT_121 */
TSB_INTIFSD->IDLEINT_121 |= 0xC0;
break;
case 29U: /* IDLEINT_122 */
TSB_INTIFSD->IDLEINT_122 |= 0xC0;
break;
case 30U: /* IDLEINT_123 */
TSB_INTIFSD->IDLEINT_123 |= 0xC0;
break;
case 31U: /* IDLEINT_124 */
TSB_INTIFSD->IDLEINT_124 |= 0xC0;
break;
case 32U: /* IDLEINT_125 */
TSB_INTIFSD->IDLEINT_125 |= 0xC0;
break;
case 33U: /* IDLEINT_126 */
TSB_INTIFSD->IDLEINT_126 |= 0xC0;
break;
case 34U: /* IDLEINT_127 */
TSB_INTIFSD->IDLEINT_127 |= 0xC0;
break;
case 35U: /* IDLEINT_128 */
TSB_INTIFSD->IDLEINT_128 |= 0xC0;
break;
case 36U: /* IDLEINT_129 */
TSB_INTIFSD->IDLEINT_129 |= 0xC0;
break;
case 37U: /* IDLEINT_130 */
TSB_INTIFSD->IDLEINT_130 |= 0xC0;
break;
case 38U: /* IDLEINT_131 */
TSB_INTIFSD->IDLEINT_131 |= 0xC0;
break;
case 39U: /* IDLEINT_132 */
TSB_INTIFSD->IDLEINT_132 |= 0xC0;
break;
case 40U: /* IDLEINT_133 */
TSB_INTIFSD->IDLEINT_133 |= 0xC0;
break;
case 41U: /* IDLEINT_134 */
TSB_INTIFSD->IDLEINT_134 |= 0xC0;
break;
case 42U: /* IDLEINT_135 */
TSB_INTIFSD->IDLEINT_135 |= 0xC0;
break;
case 43U: /* IDLEINT_136 */
TSB_INTIFSD->IDLEINT_136 |= 0xC0;
break;
case 44U: /* IDLEINT_137 */
TSB_INTIFSD->IDLEINT_137 |= 0xC0;
break;
case 45U: /* IDLEINT_138 */
TSB_INTIFSD->IDLEINT_138 |= 0xC0;
break;
case 46U: /* IDLEINT_139 */
TSB_INTIFSD->IDLEINT_139 |= 0xC0;
break;
case 47U: /* IDLEINT_140 */
TSB_INTIFSD->IDLEINT_140 |= 0xC0;
break;
case 48U: /* IDLEINT_141 */
TSB_INTIFSD->IDLEINT_141 |= 0xC0;
break;
case 49U: /* IDLEINT_142 */
TSB_INTIFSD->IDLEINT_142 |= 0xC0;
break;
case 50U: /* IDLEINT_143 */
TSB_INTIFSD->IDLEINT_143 |= 0xC0;
break;
case 51U: /* IDLEINT_144 */
TSB_INTIFSD->IDLEINT_144 |= 0xC0;
break;
case 52U: /* IDLEINT_145 */
TSB_INTIFSD->IDLEINT_145 |= 0xC0;
break;
case 53U: /* IDLEINT_146 */
TSB_INTIFSD->IDLEINT_146 |= 0xC0;
break;
case 54U: /* IDLEINT_147 */
TSB_INTIFSD->IDLEINT_147 |= 0xC0;
break;
case 55U: /* IDLEINT_148 */
TSB_INTIFSD->IDLEINT_148 |= 0xC0;
break;
case 56U: /* IDLEINT_149 */
TSB_INTIFSD->IDLEINT_149 |= 0xC0;
break;
case 57U: /* IDLEINT_150 */
TSB_INTIFSD->IDLEINT_150 |= 0xC0;
break;
case 58U: /* IDLEINT_151 */
TSB_INTIFSD->IDLEINT_151 |= 0xC0;
break;
case 59U: /* IDLEINT_152 */
TSB_INTIFSD->IDLEINT_152 |= 0xC0;
break;
case 60U: /* IDLEINT_160 */
TSB_INTIFSD->IDLEINT_160 |= 0xC0;
break;
case 61U: /* IDLEINT_161 */
TSB_INTIFSD->IDLEINT_161 |= 0xC0;
break;
case 62U: /* IDLEINT_162 */
TSB_INTIFSD->IDLEINT_162 |= 0xC0;
break;
case 63U: /* IDLEINT_163 */
TSB_INTIFSD->IDLEINT_163 |= 0xC0;
break;
case 64U: /* IDLEINT_164 */
TSB_INTIFSD->IDLEINT_164 |= 0xC0;
break;
case 65U: /* IDLEINT_165 */
TSB_INTIFSD->IDLEINT_165 |= 0xC0;
break;
case 66U: /* IDLEINT_166 */
TSB_INTIFSD->IDLEINT_166 |= 0xC0;
break;
case 67U: /* IDLEINT_167 */
TSB_INTIFSD->IDLEINT_167 |= 0xC0;
break;
case 68U: /* IDLEINT_168 */
TSB_INTIFSD->IDLEINT_168 |= 0xC0;
break;
case 69U: /* IDLEINT_169 */
TSB_INTIFSD->IDLEINT_169 |= 0xC0;
break;
default:
/* Do nothing */
break;
}
}
/** @} */
/* End of group INTIFSD_Exported_Functions */
/** @} */
/* End of group INTIFSD */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_INTIFSD_H) */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c
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@ -1,195 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_tmr16a.c
* @brief This file provides API functions for TMR16A driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_tmr16a.h"
#if defined(__TMPM066_TMR16A_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup TMR16A
* @brief TMR16A driver modules
* @{
*/
/** @defgroup TMR16A_Private_Defines
* @{
*/
#define CR_CLK_SYSCK ((uint32_t)0xFFFFFFFE)
#define CR_CLK_PRCK ((uint32_t)0x00000001)
#define CR_FF_MASK ((uint32_t)0xFFFFFF4F)
#define CP_CP_CLEAR ((uint32_t)0xFFFF0000)
/** @} */
/* End of group TMR16A_Private_Defines */
/** @defgroup TMR16A_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group TMR16A_Private_FunctionPrototypes */
/** @defgroup TMR16A_Private_Functions
* @{
*/
/** @} */
/* End of group TMR16A_Private_Functions */
/** @defgroup TMR16A_Exported_Functions
* @{
*/
/**
* @brief Start or stop counter of the specified TMR16A channel.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @param Cmd: The command for the counter.
* This parameter can be TMR16A_RUN or TMR16A_STOP.
* @retval None
*/
void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd)
{
/* Check the parameters */
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_CMD(Cmd));
/* Write command into RUN register */
T16Ax->RUN = Cmd;
}
/**
* @brief Specifies a source clock.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @param SrcClk: The command for the counter.
* This parameter can be TMR16A_SYSCK or TMR16A_PRCK.
* @retval None
*/
void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_SRCCLK(SrcClk));
tmp = T16Ax->CR;
/* Write Sorce clock into register */
if (SrcClk == TMR16A_PRCK) {
/* Set T16AxCR<CLK> Source clock to PRCK */
tmp |= CR_CLK_PRCK;
} else {
/* Clear T16AxCR<CLK> Source clock to SYSCK */
tmp &= CR_CLK_SYSCK;
}
T16Ax->CR = tmp;
}
/**
* @brief Configure the flip-flop function.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @param FFStruct: The structure containing TMR16A flip-flop configuration
* @retval None
*/
void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(FFStruct));
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_FLIPFLOP_CTRL(FFStruct->TMR16AFlipflopCtrl));
assert_param(IS_TMR16A_FLIPFLOP_TRG(FFStruct->TMR16AFlipflopReverseTrg));
/* Configure the flip-flop function of T16Ax */
tmp = T16Ax->CR;
tmp &= CR_FF_MASK;
tmp |= (FFStruct->TMR16AFlipflopCtrl | FFStruct->TMR16AFlipflopReverseTrg);
T16Ax->CR = tmp;
}
/**
* @brief Change cycle value of T16Ax.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @param Cycle: New cycle value, max 0xFFFF.
* @retval None
*/
void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle)
{
/* Check the parameters */
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_VALUE(Cycle));
/* Write cycle into RG1 */
T16Ax->RG = Cycle;
}
/**
* @brief Get TMR16A capture value of T16Ax.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @retval Capture value of T16Ax
*/
uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax)
{
uint16_t CapVal;
/* Check the parameters */
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
CapVal = (uint16_t) T16Ax->CP;
return CapVal;
}
/**
* @brief Enable or disable clock operation during debug HALT.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1.
* @param ClkState: Timer state in HALT mode.
* This parameter can be TMR16A_RUNNING_IN_CORE_HALT or TMR16A_STOP_IN_CORE_HALT.
* @retval None
*/
void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState)
{
/* Check the parameters */
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_CLK_IN_CORE_HALT(ClkState));
if (ClkState == TMR16A_STOP_IN_CORE_HALT) {
/* Set T16AEN<T16AHALT> */
T16Ax->EN |= (uint32_t) TMR16A_STOP_IN_CORE_HALT;
} else {
/* Clear T16AEN<T16AHALT> */
T16Ax->EN &= ~(uint32_t) TMR16A_STOP_IN_CORE_HALT;
}
}
/** @} */
/* End of group TMR16A_Exported_Functions */
/** @} */
/* End of group TMR16A */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_TMR16A_H) */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c
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@ -1,555 +0,0 @@
/**
*******************************************************************************
* @file tmpm066_tmrb.c
* @brief This file provides API functions for TMRB driver.
* @version V2.0.2.1
* @date 2015/10/09
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tmpm066_tmrb.h"
#if defined (__TMPM066_TMRB_H)
/** @addtogroup TX00_Periph_Driver
* @{
*/
/** @defgroup TMRB
* @brief TMRB driver modules
* @{
*/
/** @defgroup TMRB_Private_Defines
* @{
*/
#define EN_TBEN_SET ((uint32_t)0x00000080)
#define EN_TBEN_CLEAR ((uint32_t)0xFFFFFF7F)
#define CR_TBSYNC_SET ((uint32_t)0x00000020)
#define CR_TBSYNC_CLEAR ((uint32_t)0xFFFFFFDF)
#define CR_TBWBF_SET ((uint32_t)0x00000080)
#define CR_TBWBF_CLEAR ((uint32_t)0xFFFFFF7F)
#define CR_CSSEL_SET ((uint32_t)0x00000001)
#define CR_CSSEL_CLEAR ((uint32_t)0xFFFFFFFE)
#define CR_TRGSEL_CLEAR ((uint32_t)0xFFFFFFFD)
#define CR_BIT6_CLEAR ((uint32_t)0xFFFFFFBF)
#define MOD_BIT7_CLEAR ((uint32_t)0xFFFFFF7F)
#define MOD_CLK_CLE_CLEAR ((uint32_t)0xFFFFFFF0)
#define MOD_TBCPM_CLEAR ((uint32_t)0xFFFFFF8F)
#define MOD_TBCP_SET ((uint32_t)0x00000040)
#define MOD_TBCP_CLEAR ((uint32_t)0xFFFFFFBF)
#define TB_ST_MASK ((uint32_t)0x00000007)
#define TB_IM_MASK ((uint32_t)0x00000007)
/** @} */
/* End of group TMRB_Private_Defines */
/** @defgroup TMRB_Private_FunctionPrototypes
* @{
*/
/** @} */
/* End of group TMRB_Private_FunctionPrototypes */
/** @defgroup TMRB_Private_Functions
* @{
*/
/** @} */
/* End of group TMRB_Private_Functions */
/** @defgroup TMRB_Exported_Functions
* @{
*/
/**
* @brief Enable the specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @retval None
*/
void TMRB_Enable(TSB_TB_TypeDef * TBx)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
/* Set TBxEN<TBEN> to enable TBx */
TBx->EN |= EN_TBEN_SET;
}
/**
* @brief Disable the specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @retval None
*/
void TMRB_Disable(TSB_TB_TypeDef * TBx)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
/* Clear TBxEN<TBEN> to disable TBx */
TBx->EN &= EN_TBEN_CLEAR;
}
/**
* @brief Start or stop counter of the specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param Cmd: The command for the counter.
* This parameter can be TMRB_RUN or TMRB_STOP.
* @retval None
*/
void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_CMD(Cmd));
/* Write command into RUN register */
TBx->RUN = Cmd;
}
/**
* @brief Initialize the specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param InitStruct: The structure containing basic TMRB configuration.
* @retval None
*/
void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_MODE(InitStruct->Mode));
if (InitStruct->Mode != 0U) {
assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv));
} else {
/* Do nothing */
}
assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming));
assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl));
assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming));
assert_param(IS_VALID_LEADINGTIMING(InitStruct->LeadingTiming, InitStruct->TrailingTiming));
/* Configure source clock for TBx */
tmp = TBx->MOD;
tmp &= MOD_BIT7_CLEAR;
tmp &= MOD_CLK_CLE_CLEAR;
if (InitStruct->Mode != 0U) {
/* Use internal clock, set the prescaler */
tmp |= InitStruct->ClkDiv;
} else {
/* Use external clock */
tmp |= InitStruct->Mode;
}
/* Set up-counter running mode */
tmp |= InitStruct->UpCntCtrl;
tmp |= MOD_TBCP_SET;
TBx->MOD = tmp;
/* Write leadingtiming into RG0 */
TBx->RG0 = InitStruct->LeadingTiming;
/* Write trailingtiminginto RG1 */
TBx->RG1 = InitStruct->TrailingTiming;
}
/**
* @brief Configure the capture timing.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5.
* @param CaptureTiming: Specify TMRB capture timing.
* This parameter can be one of the following values:
* TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_IN_RISING_FALLING, TMRB_CAPTURE_FF_RISING_FALLING.
* @retval None
*/
void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMRB_CAP_PERIPH(TBx));
assert_param(IS_TMRB_CAPTURE_TIMING(CaptureTiming));
/* Configure capture timing */
tmp = TBx->MOD;
tmp &= MOD_BIT7_CLEAR;
tmp &= MOD_TBCPM_CLEAR;
tmp |= CaptureTiming;
tmp |= MOD_TBCP_SET;
TBx->MOD = tmp;
}
/**
* @brief Configure the flip-flop function.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param FFStruct: The structure containing TMRB flip-flop configuration
* @retval None
*/
void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct)
{
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(FFStruct));
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl));
assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg));
/* Configure the flip-flop function of TBx */
TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg);
}
/**
* @brief Indicate what causes the interrupt.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @retval The interrupt factor of TBx.
*/
TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx)
{
TMRB_INTFactor retval = { 0U };
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
retval.All = TBx->ST & TB_ST_MASK;
return retval;
}
/**
* @brief Indicate what interrupt cause source be masked.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @retval The masked interrupt cause source of TBx.
*/
TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx)
{
TMRB_INTMask retval = { 0U };
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
retval.All = TBx->IM & TB_IM_MASK;
return retval;
}
/**
* @brief Mask some TMRB interrupts.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param INTMask: Select the mask of TMRB interrupt.
* This parameter can be one of the following values:
* TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADINGTIMING_INT, TMRB_MASK_MATCH_TRAILINGTIMING_INT,
* or TMRB_MASK_OVERFLOW_INT.
* @retval None
*/
void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_INT_MASK(INTMask));
/* Mask the specified interrupt */
TBx->IM = INTMask;
}
/**
* @brief Change leadingtiming value of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param LeadingTiming: New leadingtiming value, max 0xFFFF.
* @retval None
*/
void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_VALUE(LeadingTiming));
assert_param(IS_VALID_LEADINGTIMING(LeadingTiming, TBx->RG1));
/* Write leadingtiming into RG0 */
TBx->RG0 = LeadingTiming;
}
/**
* @brief Change trailingtiming value of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param TrailingTiming: New trailingtiming value, max 0xFFFF.
* @retval None
*/
void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_VALUE(TrailingTiming));
assert_param(IS_VALID_LEADINGTIMING(TBx->RG0, TrailingTiming));
/* Write trailingtiming into RG1 */
TBx->RG1 = TrailingTiming;
}
/**
* @brief Get TMRB register value of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param Reg: Select the timer register to read.
* This parameter can be: TMRB_REG_0 or TMRB_REG_1.
* @retval Register value of TBx
*/
uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_REG(Reg));
return Reg ? (uint16_t) TBx->RG1 : (uint16_t) TBx->RG0;
}
/**
* @brief Get up-counter value of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @retval Up-counter value of TBx
*/
uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
/* Return up-counter value */
return (uint16_t) TBx->UC;
}
/**
* @brief Get TMRB capture value of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5.
* @param CapReg: Select the capture register to read.
* This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1.
* @retval Capture value of TBx
*/
uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg)
{
/* Check the parameters */
assert_param(IS_TMRB_CAP_PERIPH(TBx));
assert_param(IS_TMRB_CAPTURE_REG(CapReg));
return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0;
}
/**
* @brief Capture counter by software and take them into capture register 0.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5.
* @retval None
*/
void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMRB_CAP_PERIPH(TBx));
/* Set software capture */
tmp = TBx->MOD;
tmp &= MOD_BIT7_CLEAR;
TBx->MOD = tmp & MOD_TBCP_CLEAR;
}
/**
* @brief Enable or disable the synchronous mode of specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7.
* @param NewState: New state of TBx synchronous mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMRB_SYNC_PERIPH(TBx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmp = TBx->CR;
tmp &= CR_BIT6_CLEAR;
if (NewState == ENABLE) {
/* Set TBxCR<TBSYNC> to make TBx running in synchronous mode */
TBx->CR = tmp | CR_TBSYNC_SET;
} else {
/* Clear TBxCR<TBSYNC> to make TBx running in individual mode */
TBx->CR = tmp & CR_TBSYNC_CLEAR;
}
}
/**
* @brief Enable or disable double buffer of TBx.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param NewState: New state of TBx double buffer.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmp = TBx->CR;
tmp &= CR_BIT6_CLEAR;
if (NewState == ENABLE) {
/* Set TBxCR<TBWBF> to enable TBx double buffer */
TBx->CR = tmp | CR_TBWBF_SET;
} else {
/* Clear TBxCR<TBWBF> to disable TBx double buffer */
TBx->CR = tmp & CR_TBWBF_CLEAR;
}
}
/**
* @brief Enable or disable external trigger to start count and set the active edge.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param NewState: New state of external trigger.
* This parameter can be ENABLE or DISABLE.
* @param TrgMode: Active edge of the external trigger signal.
* This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING.
* @retval None
*/
void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_TMRB_TRG_EDGE(TrgMode));
tmp = TBx->CR;
tmp &= CR_BIT6_CLEAR;
if (NewState == ENABLE) {
/* Set TBxCR<CSSEL> to choose external trigger */
tmp |= CR_CSSEL_SET;
} else {
/* Clear TBxCR<CSSEL> to choose software start */
tmp &= CR_CSSEL_CLEAR;
}
/* external trigger selection */
tmp &= CR_TRGSEL_CLEAR;
tmp |= (uint32_t) TrgMode;
TBx->CR = tmp;
}
/**
* @brief Enable or disable clock operation during debug HALT.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param ClkState: Timer state in HALT mode.
* This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT.
* @retval None
*/
void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState));
if (ClkState == TMRB_STOP_IN_CORE_HALT) {
/* Set TBxEN<TBHALT> */
TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT;
} else {
/* Clear TBxEN<TBHALT> */
TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT;
}
}
/**
* @brief Enable or disable DMA request.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3,
* TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* @param NewState: New state of DMA request.
* This parameter can be ENABLE or DISABLE.
* @param DMAReq: DMA request.
* This parameter can be TMRB_DMA_REQ_CMP_MATCH, TMRB_DMA_REQ_CAPTURE_1 or TMRB_DMA_REQ_CAPTURE_0.
* @retval None
*/
void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq)
{
/* Check the parameters */
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_TMRB_DMA_REQ(DMAReq));
if (NewState == ENABLE) {
/* set TBxDMA<TBDMAENn>(n can be 0,1,2) */
TBx->DMA |= (uint32_t) DMAReq;
} else {
/* clear TBxDMA<TBDMAENn>(n can be 0,1,2) */
TBx->DMA &= ~((uint32_t) DMAReq);
}
}
/** @} */
/* End of group TMRB_Exported_Functions */
/** @} */
/* End of group TMRB */
/** @} */
/* End of group TX00_Periph_Driver */
#endif /* defined(__TMPM066_TMRB_H) */

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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c
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targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
ADC_A0 = 0,
ADC_A1,
ADC_A2,
ADC_A3,
ADC_A4,
ADC_A5,
ADC_A6,
ADC_A7,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
I2C_0 = 0,
I2C_1,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
GPIO_IRQ_0 = 0,
GPIO_IRQ_1,
GPIO_IRQ_2,
GPIO_IRQ_3,
GPIO_IRQ_4,
GPIO_IRQ_5,
INVALID_GPIO_IRQ = (int)NC
} GPIO_IRQName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART SERIAL_0
#define MBED_UART0 PC2, PC3
#define MBED_UART1 PE2, PE1
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PC1, PC0
#define MBED_I2C1 PG1, PG0
#define MBED_ANALOGIN0 A0
#define MBED_ANALOGIN1 A1
#define MBED_ANALOGIN2 A2
#define MBED_ANALOGIN3 A3
#define MBED_ANALOGIN4 A4
#define MBED_ANALOGIN5 A5
#define MBED_PWMOUT0 PD1
#define MBED_PWMOUT1 PD2
#define MBED_PWMOUT2 PD3
#define MBED_PWMOUT3 PF4
#define MBED_PWMOUT4 PF5
#define MBED_PWMOUT5 PJ0
#define MBED_PWMOUT6 PJ1
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF)
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16)
#define PIN_DIR(X) ((X) & 0xffff)
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM066 Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
PB0 = 1 << 3, PB1, PB2, PB3,
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5,
PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5,
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
PG0 = 6 << 3, PG1,
PH0 = 7 << 3, PH1, PH2, PH3,
PJ0 = 8 << 3, PJ1, PJ2, PJ3,
// Other mbed Pin Names
LED1 = PB0,
LED2 = PB1,
LED3 = LED1,
LED4 = LED2,
// External data bus Pin Names
D0 = PE1,
D1 = PE2,
D2 = PE0,
D3 = PD1,
D4 = PJ1,
D5 = PD2,
D6 = PD3,
D7 = PJ2,
D8 = PJ3,
D9 = PF4,
D10 = PF0,
D11 = PF1,
D12 = PF2,
D13 = PF3,
D14 = PC1,
D15 = PC0,
// Analogue out pins
A0 = PA2,
A1 = PA3,
A2 = PA4,
A3 = PA5,
A4 = PA6,
A5 = PA7,
// DAP_UART
USBTX = PC2,
USBRX = PC3,
MBEDIF_TXD = USBTX,
MBEDIF_RXD = USBRX,
// Switches
SW1 = PB2,
SW2 = PB3,
// I2C pins
SDA = PC1,
SCL = PC0,
I2C_SDA = SDA,
I2C_SCL = SCL,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
static uint8_t adc_reset_init = 0; // Is ADC Reset happened yet?
#define ADC_10BIT_RANGE 0x3FF
static const PinMap PinMap_ADC[] = {
{PA0, ADC_A0, PIN_DATA(0, 0)},
{PA1, ADC_A1, PIN_DATA(0, 0)},
{PA2, ADC_A2, PIN_DATA(0, 0)},
{PA3, ADC_A3, PIN_DATA(0, 0)},
{PA4, ADC_A4, PIN_DATA(0, 0)},
{PA5, ADC_A5, PIN_DATA(0, 0)},
{PA6, ADC_A6, PIN_DATA(0, 0)},
{PA7, ADC_A7, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
// enable clock supply to ADC
CG_SetFcPeriphA(CG_FC_PERIPH_ADC, ENABLE);
CG_SetADCClkSupply(ENABLE);
// Set pin function as ADC
pinmap_pinout(pin, PinMap_ADC);
if (!adc_reset_init) {
// Software reset ADC
ADC_SWReset();
adc_reset_init = 1;
}
// Set sample hold time and pre-scale clock
ADC_SetClk(ADC_CONVERSION_81_CLOCK, ADC_FC_DIVIDE_LEVEL_8);
// Set input channel
ADC_SetInputChannel(obj->adc);
// Turn VREF on
ADC_SetVref(ENABLE);
// Use fixed-channel single conversion mode
ADC_SetRepeatMode(DISABLE);
ADC_SetScanMode(DISABLE);
}
uint16_t analogin_read_u16(analogin_t *obj)
{
ADC_ResultTypeDef ret;
// Assert that ADC channel is valid
MBED_ASSERT(obj->adc != (ADCName) NC);
// Set input channel
ADC_SetInputChannel(obj->adc);
// Enable Vref
ADC_SetVref(ENABLE);
// Wait at least 3us to ensure the voltage is stable
wait_us(10U);
// Start ADC conversion
ADC_Start();
// Wait until AD conversion complete
while (ADC_GetConvertState().Bit.NormalComplete != 1) {
// Do nothing
}
// Convert result
ret = ADC_GetConvertResult(obj->adc);
// Disable Vref to go into standby mode
ADC_SetVref(DISABLE);
return (uint16_t)ret.ADCResultValue;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = analogin_read_u16(obj);
return (float)(value * (1.0f / (float)ADC_10BIT_RANGE));
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#include "objects.h"
#include <stddef.h>
#endif

2287
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h
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189
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S
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;/**
; *******************************************************************************
; * @file startup_TMPM066.S
; * @brief CMSIS Cortex-M0 Core Device Startup File for the
; * TOSHIBA 'TMPM066' Device Series
; * @version V2.0.2.1 (Tentative)
; * @date 2015/08/05
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT0_IRQHandler ; 0: Interrupt Pin0
DCD INT1_IRQHandler ; 1: Interrupt Pin1
DCD INT2_IRQHandler ; 2: Interrupt Pin2
DCD INT3_IRQHandler ; 3: Interrupt Pin3
DCD INT4_IRQHandler ; 4: Interrupt Pin4
DCD INT5_IRQHandler ; 5: Interrupt Pin5
DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0)
DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0)
DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1)
DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1)
DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt
DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt
DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt
DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0)
DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1)
DCD INTDMA_IRQHandler ; 15: DMAC interrupt
DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0)
DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1)
DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0)
DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1)
DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2)
DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3)
DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4)
DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5)
DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6)
DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7)
DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1)
DCD INTTMRD_IRQHandler ; 27: TMRD interrupt
DCD INTUSB_IRQHandler ; 28: USB interrupt
DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt
DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt
DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT0_IRQHandler [WEAK]
EXPORT INT1_IRQHandler [WEAK]
EXPORT INT2_IRQHandler [WEAK]
EXPORT INT3_IRQHandler [WEAK]
EXPORT INT4_IRQHandler [WEAK]
EXPORT INT5_IRQHandler [WEAK]
EXPORT INTRX0_IRQHandler [WEAK]
EXPORT INTTX0_IRQHandler [WEAK]
EXPORT INTRX1_IRQHandler [WEAK]
EXPORT INTTX1_IRQHandler [WEAK]
EXPORT INTSPIRX_IRQHandler [WEAK]
EXPORT INTSPITX_IRQHandler [WEAK]
EXPORT INTSPIERR_IRQHandler [WEAK]
EXPORT INTI2C0_IRQHandler [WEAK]
EXPORT INTI2C1_IRQHandler [WEAK]
EXPORT INTDMA_IRQHandler [WEAK]
EXPORT INT16A0_IRQHandler [WEAK]
EXPORT INT16A1_IRQHandler [WEAK]
EXPORT INTTB0_IRQHandler [WEAK]
EXPORT INTTB1_IRQHandler [WEAK]
EXPORT INTTB2_IRQHandler [WEAK]
EXPORT INTTB3_IRQHandler [WEAK]
EXPORT INTTB4_IRQHandler [WEAK]
EXPORT INTTB5_IRQHandler [WEAK]
EXPORT INTTB6_IRQHandler [WEAK]
EXPORT INTTB7_IRQHandler [WEAK]
EXPORT INTI2CS_IRQHandler [WEAK]
EXPORT INTTMRD_IRQHandler [WEAK]
EXPORT INTUSB_IRQHandler [WEAK]
EXPORT INTUSBWKUP_IRQHandler [WEAK]
EXPORT INTADHP_IRQHandler [WEAK]
EXPORT INTAD_IRQHandler [WEAK]
INT0_IRQHandler
INT1_IRQHandler
INT2_IRQHandler
INT3_IRQHandler
INT4_IRQHandler
INT5_IRQHandler
INTRX0_IRQHandler
INTTX0_IRQHandler
INTRX1_IRQHandler
INTTX1_IRQHandler
INTSPIRX_IRQHandler
INTSPITX_IRQHandler
INTSPIERR_IRQHandler
INTI2C0_IRQHandler
INTI2C1_IRQHandler
INTDMA_IRQHandler
INT16A0_IRQHandler
INT16A1_IRQHandler
INTTB0_IRQHandler
INTTB1_IRQHandler
INTTB2_IRQHandler
INTTB3_IRQHandler
INTTB4_IRQHandler
INTTB5_IRQHandler
INTTB6_IRQHandler
INTTB7_IRQHandler
INTI2CS_IRQHandler
INTTMRD_IRQHandler
INTUSB_IRQHandler
INTUSBWKUP_IRQHandler
INTADHP_IRQHandler
INTAD_IRQHandler
B .
ENDP
END

43
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct
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#! armcc -E
;; TMPM066FWUG scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 0x00000000 0x20000
{
ER_IROM1 0x00000000 0x20000
{
*.o (RESET, +First)
*(InRoot$$Sections)
*.o (+RO-CODE)
.ANY2 (+RO-DATA)
.ANY (+RO)
}
/* 8_byte_aligned(32 + 16 vect * 4 bytes) = 8_byte_aligned(0xC0) */
RW_IRAM1 0x200000C0 (0x4000 - 0xC0 - Stack_Size)
{
.ANY (+RW, +ZI)
}
ARM_LIB_STACK (0x200000C0+0x4000) EMPTY -Stack_Size { ; stack
}
}

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targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S
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/**
*******************************************************************************
* @file startup_TMPM066.S
* @brief CMSIS Cortex-M0 Core Device Startup File for the
* TOSHIBA 'TMPM066' Device Series
* @version V2.0.2.1 (Tentative)
* @date 2015/08/05
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*******************************************************************************
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
/* Vector Table */
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long INT0_IRQHandler // 0: Interrupt Pin0
.long INT1_IRQHandler // 1: Interrupt Pin1
.long INT2_IRQHandler // 2: Interrupt Pin2
.long INT3_IRQHandler // 3: Interrupt Pin3
.long INT4_IRQHandler // 4: Interrupt Pin4
.long INT5_IRQHandler // 5: Interrupt Pin5
.long INTRX0_IRQHandler // 6: Serial reception interrupt(channel0)
.long INTTX0_IRQHandler // 7: Serial transmission interrupt(channel0)
.long INTRX1_IRQHandler // 8: Serial reception interrupt(channel1)
.long INTTX1_IRQHandler // 9: Serial transmission interrupt(channel1)
.long INTSPIRX_IRQHandler // 10: SPI serial reception interrupt
.long INTSPITX_IRQHandler // 11: SPI serial transmission interrupt
.long INTSPIERR_IRQHandler // 12: SPI serial error interrupt
.long INTI2C0_IRQHandler // 13: Serial bus interface (channel.0)
.long INTI2C1_IRQHandler // 14: Serial bus interface (channel.1)
.long INTDMA_IRQHandler // 15: DMAC interrupt
.long INT16A0_IRQHandler // 16: 16-bit TMR16A match detection (channel.0)
.long INT16A1_IRQHandler // 17: 16-bit TMR16A match detection (channel.1)
.long INTTB0_IRQHandler // 18: 16-bit TMRB interrupt(channel.0)
.long INTTB1_IRQHandler // 19: 16-bit TMRB interrupt(channel.1)
.long INTTB2_IRQHandler // 20: 16-bit TMRB interrupt(channel.2)
.long INTTB3_IRQHandler // 21: 16-bit TMRB interrupt(channel.3)
.long INTTB4_IRQHandler // 22: 16-bit TMRB interrupt(channel.4)
.long INTTB5_IRQHandler // 23: 16-bit TMRB interrupt(channel.5)
.long INTTB6_IRQHandler // 24: 16-bit TMRB interrupt(channel.6)
.long INTTB7_IRQHandler // 25: 16-bit TMRB interrupt(channel.7)
.long INTI2CS_IRQHandler // 26: Serial bus interface for Wakeup(channel.1)
.long INTTMRD_IRQHandler // 27: TMRD interrupt
.long INTUSB_IRQHandler // 28: USB interrupt
.long INTUSBWKUP_IRQHandler // 29: USB wakeup interrupt
.long INTADHP_IRQHandler // 30: High Priority A/D conversion interrupt
.long INTAD_IRQHandler // 31: Normal A/D conversion completion interrupt
.size __isr_vector, . - __isr_vector
/* Reset Handler */
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler INT0_IRQHandler
def_irq_default_handler INT1_IRQHandler
def_irq_default_handler INT2_IRQHandler
def_irq_default_handler INT3_IRQHandler
def_irq_default_handler INT4_IRQHandler
def_irq_default_handler INT5_IRQHandler
def_irq_default_handler INTRX0_IRQHandler
def_irq_default_handler INTTX0_IRQHandler
def_irq_default_handler INTRX1_IRQHandler
def_irq_default_handler INTTX1_IRQHandler
def_irq_default_handler INTSPIRX_IRQHandler
def_irq_default_handler INTSPITX_IRQHandler
def_irq_default_handler INTSPIERR_IRQHandler
def_irq_default_handler INTI2C0_IRQHandler
def_irq_default_handler INTI2C1_IRQHandler
def_irq_default_handler INTDMA_IRQHandler
def_irq_default_handler INT16A0_IRQHandler
def_irq_default_handler INT16A1_IRQHandler
def_irq_default_handler INTTB0_IRQHandler
def_irq_default_handler INTTB1_IRQHandler
def_irq_default_handler INTTB2_IRQHandler
def_irq_default_handler INTTB3_IRQHandler
def_irq_default_handler INTTB4_IRQHandler
def_irq_default_handler INTTB5_IRQHandler
def_irq_default_handler INTTB6_IRQHandler
def_irq_default_handler INTTB7_IRQHandler
def_irq_default_handler INTI2CS_IRQHandler
def_irq_default_handler INTTMRD_IRQHandler
def_irq_default_handler INTUSB_IRQHandler
def_irq_default_handler INTUSBWKUP_IRQHandler
def_irq_default_handler INTADHP_IRQHandler
def_irq_default_handler INTAD_IRQHandler
.end

157
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld
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@ -1,157 +0,0 @@
/* Linker script for Toshiba TMPM066 */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
Image$$RW_IRAM1$$Base = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_IRAM1$$ZI$$Limit = . ;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

281
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S
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@ -1,281 +0,0 @@
;/**
; *******************************************************************************
; * @file startup_TMPM066.S
; * @brief CMSIS Cortex-M0 Core Device Startup File for the
; * TOSHIBA 'TMPM066' Device Series
; * @version V2.0.2.1 (Tentative)
; * @date 2015/08/05
; *
; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT0_IRQHandler ; 0: Interrupt Pin0
DCD INT1_IRQHandler ; 1: Interrupt Pin1
DCD INT2_IRQHandler ; 2: Interrupt Pin2
DCD INT3_IRQHandler ; 3: Interrupt Pin3
DCD INT4_IRQHandler ; 4: Interrupt Pin4
DCD INT5_IRQHandler ; 5: Interrupt Pin5
DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0)
DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0)
DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1)
DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1)
DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt
DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt
DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt
DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0)
DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1)
DCD INTDMA_IRQHandler ; 15: DMAC interrupt
DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0)
DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1)
DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0)
DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1)
DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2)
DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3)
DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4)
DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5)
DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6)
DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7)
DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1)
DCD INTTMRD_IRQHandler ; 27: TMRD interrupt
DCD INTUSB_IRQHandler ; 28: USB interrupt
DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt
DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt
DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK INT0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT0_IRQHandler
B INT0_IRQHandler
PUBWEAK INT1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT1_IRQHandler
B INT1_IRQHandler
PUBWEAK INT2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT2_IRQHandler
B INT2_IRQHandler
PUBWEAK INT3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT3_IRQHandler
B INT3_IRQHandler
PUBWEAK INT4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT4_IRQHandler
B INT4_IRQHandler
PUBWEAK INT5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT5_IRQHandler
B INT5_IRQHandler
PUBWEAK INTRX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTRX0_IRQHandler
B INTRX0_IRQHandler
PUBWEAK INTTX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTX0_IRQHandler
B INTTX0_IRQHandler
PUBWEAK INTRX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTRX1_IRQHandler
B INTRX1_IRQHandler
PUBWEAK INTTX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTX1_IRQHandler
B INTTX1_IRQHandler
PUBWEAK INTSPIRX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTSPIRX_IRQHandler
B INTSPIRX_IRQHandler
PUBWEAK INTSPITX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTSPITX_IRQHandler
B INTSPITX_IRQHandler
PUBWEAK INTSPIERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTSPIERR_IRQHandler
B INTSPIERR_IRQHandler
PUBWEAK INTI2C0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C0_IRQHandler
B INTI2C0_IRQHandler
PUBWEAK INTI2C1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C1_IRQHandler
B INTI2C1_IRQHandler
PUBWEAK INTDMA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTDMA_IRQHandler
B INTDMA_IRQHandler
PUBWEAK INT16A0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT16A0_IRQHandler
B INT16A0_IRQHandler
PUBWEAK INT16A1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT16A1_IRQHandler
B INT16A1_IRQHandler
PUBWEAK INTTB0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB0_IRQHandler
B INTTB0_IRQHandler
PUBWEAK INTTB1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB1_IRQHandler
B INTTB1_IRQHandler
PUBWEAK INTTB2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB2_IRQHandler
B INTTB2_IRQHandler
PUBWEAK INTTB3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB3_IRQHandler
B INTTB3_IRQHandler
PUBWEAK INTTB4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB4_IRQHandler
B INTTB4_IRQHandler
PUBWEAK INTTB5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB5_IRQHandler
B INTTB5_IRQHandler
PUBWEAK INTTB6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB6_IRQHandler
B INTTB6_IRQHandler
PUBWEAK INTTB7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTB7_IRQHandler
B INTTB7_IRQHandler
PUBWEAK INTI2CS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2CS_IRQHandler
B INTI2CS_IRQHandler
PUBWEAK INTTMRD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTTMRD_IRQHandler
B INTTMRD_IRQHandler
PUBWEAK INTUSB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUSB_IRQHandler
B INTUSB_IRQHandler
PUBWEAK INTUSBWKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUSBWKUP_IRQHandler
B INTUSBWKUP_IRQHandler
PUBWEAK INTADHP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADHP_IRQHandler
B INTADHP_IRQHandler
PUBWEAK INTAD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTAD_IRQHandler
B INTAD_IRQHandler
END

34
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf
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@ -1,34 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0xC00;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

12
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h
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@ -1,12 +0,0 @@
/* mbed Microcontroller Library - CMSIS for TMPM066
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in TMPM066 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM066.h"
#include "cmsis_nvic.h"
#endif

33
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c
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@ -1,33 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic for TMPM066
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
static int vector_copied = 0;
uint32_t *vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (vector_copied == 0) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
vector_copied = 1;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

43
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h
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@ -1,43 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic for TMPM066
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
/** Set the ISR for IRQn
*
* Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
* the first time this function is called
* @param[in] IRQn The Interrupt Request number for which a vector will be registered
* @param[in] vector The ISR vector to register for IRQn
*/
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
/** Get the ISR registered for IRQn
*
* Reads the Interrupt Service Routine currently registered for IRQn
* @param[in] IRQn The Interrupt Request number the vector of which will be read
* @return Returns the ISR registered for IRQn
*/
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

301
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c
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/**
*******************************************************************************
* @file system_TMPM066.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM066' Device Series
* @version V2.0.2.1
* @date 2015/10/22
*
* (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved
*******************************************************************************
*/
#include "TMPM066.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Watchdog Timer (WD) Configuration */
#define WD_SETUP (1U)
#define WDMOD_Val (0x00000000UL)
#define WDCR_Val (0x000000B1UL)
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U)
#define SYSCR_Val (0x00000000UL)
#define OSCCR_Val (0x00000102UL) /* OSCCR<OSCSEL> = 1, OSCCR<EOSCEN> = 01 */
#define STBYCR_Val (0x00000000UL)
#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U)
#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U)
#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U)
#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U)
#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
#define CG_PLL0SEL_PLL0ST_MASK ((uint32_t)0x00000004)
#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
#define CG_OSCCR_OSCF_MASK ((uint32_t)0x00000200)
#define CG_WUON_START_SET ((uint32_t)0x00000001)
#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002)
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
#define WD_MOD_WDTE_SET ((uint32_t)0x00000080)
#define PLLSEL_Ready CG_12M_MUL_8_FPLL
#define PLLSEL_Val (PLLSEL_Ready|0x00000003UL)
#define PLLSEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define OSC_8M ( 8000000UL)
#define OSC_10M (10000000UL)
#define OSC_12M (12000000UL)
#define OSC_16M (16000000UL)
#define EXTALH OSC_12M /* External high-speed oscillator freq */
#define XTALH OSC_10M /* Internal high-speed oscillator freq */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define WU_TIME_PLL (100UL) /* warm-up time for PLL is 100us */
#define WUPHCR_WUPT_MASK (0x000FFFFFUL)
#define WUPHCR_WUPT_EXT ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* WUPHCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
#define WUPHCR_WUPT_PLL ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U)
#if (CLOCK_SETUP) /* Clock(external) Setup */
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (OSCCR_Val & (1U<<8U))
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (XTALH)
#endif
#if ((PLLSEL_Val & (1U<<1U)) && (PLLSEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == OSC_8M) /* If input is 8MHz */
#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL))
#define __CORE_CLK ((CORE_TALH * 12U) / 4U) /* output clock is 24MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == OSC_10M) /* If input is 10MHz */
#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL))
#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 20MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#elif (CORE_TALH == OSC_12M) /* If input is 12MHz */
#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL)
#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 24MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == OSC_16M) /* If input is 16MHz */
#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_6_FPLL)
#define __CORE_CLK ((CORE_TALH * 6U) / 4U) /* output clock is 24MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 16MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U)
#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
#else
#define __CORE_SYS (XTALH)
#endif /* clock Setup */
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{ /* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t CoreClockInput = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pllsel = 0U;
uint32_t pllon = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = XTALH;
}
regval = TSB_CG->PLL0SEL;
pllsel = regval & CG_PLL0SEL_PLL0SEL_SET;
pllon = regval & CG_PLL0SEL_PLL0ON_SET;
if (pllsel && pllon) { /* If PLL enabled */
if (CoreClock == OSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) {
CoreClockInput = (CoreClock * 12U) / 4U; /* output clock is 24MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == OSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) {
CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 20MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == OSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) {
CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 24MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == OSC_16M) { /* If input is 16MHz */
if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) {
CoreClockInput = (CoreClock * 6U) / 4U; /* output clock is 24MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else {
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U:
SystemCoreClock = CoreClockInput; /* Gear -> fc */
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
SystemCoreClock = CoreClockInput / 8U;
break;
case 4U: /* Gear -> fc/16 */
if (CoreClockInput >= OSC_16M) {
SystemCoreClock = CoreClockInput / 16U;
} else {
SystemCoreClock = 0U;
}
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
uint32_t regval = 0U;
volatile uint32_t pllst = 0U;
volatile uint32_t wuef = 0U;
volatile uint32_t oscf = 0U;
uint32_t wdte = 0U;
#if (WD_SETUP) /* Watchdog Setup */
while (TSB_WD->FLG != 0U) {
} /* When writing to WDMOD or WDCR, confirm "0" of WDFLG<FLG>. */
TSB_WD->MOD = WDMOD_Val;
regval = TSB_WD->MOD;
wdte = regval & WD_MOD_WDTE_SET;
if (!wdte) { /* If watchdog is to be disabled */
TSB_WD->CR = WDCR_Val;
} else {
/*Do nothing*/
}
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = SYSCR_Val;
TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
TSB_CG->WUPHCR |= WUPHCR_WUPT_EXT;
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR |= CG_WUPHCR_WUCLK_SET;
TSB_CG->WUPHCR |= CG_WUON_START_SET;
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
while (wuef) {
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
while (oscf != CG_OSCCR_OSCF_MASK) {
oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL;
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLLSEL_Ready;
TSB_CG->WUPHCR |= CG_WUON_START_SET;
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
while (wuef) {
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
} /* Warm-up */
TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL;
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR |= CG_WUON_START_SET;
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
while (wuef) {
wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
} /* Warm-up */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK;
while (pllst != CG_PLL0SEL_PLL0ST_MASK) {
pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK;
} /*Confirm CGPLLSEL<PLLST> = "1" */
#endif
}

49
targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h
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@ -1,49 +0,0 @@
/**
*****************************************************************************
* @file system_TMPM066.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM066' Device Series
* @version V2.0.2.1 (Tentative)
* @date 2015/8/13
*
* (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved
*****************************************************************************
*/
#include <stdint.h>
#ifndef __SYSTEM_TMPM066_H
#define __SYSTEM_TMPM066_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

99
targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_error.h"
#define GPIO_DATA PIN_DATA(0, 3)
extern const PinMap PinMap_GPIO_IRQ[];
uint32_t gpio_set(PinName pin)
{
// Check that pin is valid
MBED_ASSERT(pin != (PinName)NC);
// Checking pin name is not interrupt pins
if (pinmap_find_peripheral(pin, PinMap_GPIO_IRQ) == (uint32_t) NC) {
// Set pin function as GPIO pin
pin_function(pin, GPIO_DATA);
}
// Return pin mask
return (1 << (pin & 0x07));
}
void gpio_init(gpio_t *obj, PinName pin)
{
// Store above pin mask, pin name into GPIO object
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->mask = gpio_set(pin);
obj->port = (GPIO_Port) (pin >> 3);
if ((PortName)obj->port == PortH) {
CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
}
if ((PortName)obj->port == PortJ) {
CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
}
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
// Set pin mode
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
// Set direction
switch (direction) {
case PIN_INPUT:
// Set pin input
GPIO_SetInput(obj->port, obj->mask);
break;
case PIN_OUTPUT:
// Set pin output
GPIO_SetOutput(obj->port, obj->mask);
break;
case PIN_INOUT:
// Set pin both input and output
GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE);
break;
default:
error("Invalid direction\n");
break;
}
}
void gpio_write(gpio_t *obj, int value)
{
// Write gpio object pin data
if ((value == 0) || (value == 1)) {
GPIO_WriteDataBit(obj->port, obj->mask, value);
} else {
error("Invalid value\n");
}
}
int gpio_read(gpio_t *obj)
{
// Read gpio object pin data
return GPIO_ReadDataBit(obj->port, obj->mask);
}

234
targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_critical.h"
#define CHANNEL_NUM 6
const PinMap PinMap_GPIO_IRQ[] = {
{PD5, GPIO_IRQ_0, PIN_DATA(0, 0)},
{PA5, GPIO_IRQ_1, PIN_DATA(0, 0)},
{PA6, GPIO_IRQ_2, PIN_DATA(0, 0)},
{PF1, GPIO_IRQ_3, PIN_DATA(0, 0)},
{PC5, GPIO_IRQ_4, PIN_DATA(0, 0)},
{PF0, GPIO_IRQ_5, PIN_DATA(0, 0)},
{NC, NC, 0}
};
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index)
{
uint32_t val;
GPIO_Port port;
uint32_t mask;
INTIFAO_INTActiveState ActiveState;
port = (GPIO_Port)(pin >> 3);
mask = 0x01 << (pin & 0x07);
// Clear interrupt request
INTIFAO_ClearINTReq((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)irq_id);
ActiveState = INTIFAO_GetSTBYReleaseINTState((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
ActiveState, DISABLE);
// Get pin value
val = GPIO_ReadDataBit(port, mask);
switch (val) {
// Falling edge detection
case 0:
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
break;
// Rising edge detection
case 1:
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
break;
default:
break;
}
// Enable interrupt request
INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
ActiveState, ENABLE);
}
void INT0_IRQHandler(void)
{
INT_IRQHandler(PD5, GPIO_IRQ_0, 0);
}
void INT1_IRQHandler(void)
{
INT_IRQHandler(PA5, GPIO_IRQ_1, 1);
}
void INT2_IRQHandler(void)
{
INT_IRQHandler(PA6, GPIO_IRQ_2, 2);
}
void INT3_IRQHandler(void)
{
INT_IRQHandler(PF1, GPIO_IRQ_3, 3);
}
void INT4_IRQHandler(void)
{
INT_IRQHandler(PC5, GPIO_IRQ_4, 4);
}
void INT5_IRQHandler(void)
{
INT_IRQHandler(PF0, GPIO_IRQ_5, 5);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
// Get gpio interrupt ID
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
core_util_critical_section_enter();
// Get pin mask
obj->mask = (uint32_t)(1 << (pin & 0x07));
// Get GPIO port
obj->port = (GPIO_Port)(pin >> 3);
// Set pin level as LOW
GPIO_WriteDataBit(obj->port, obj->mask, 0);
// Enable gpio interrupt function
pinmap_pinout(pin, PinMap_GPIO_IRQ);
// Get GPIO irq source
switch (obj->irq_id) {
case GPIO_IRQ_0:
obj->irq_src = INTIFAO_INT_SRC_0;
break;
case GPIO_IRQ_1:
obj->irq_src = INTIFAO_INT_SRC_1;
break;
case GPIO_IRQ_2:
obj->irq_src = INTIFAO_INT_SRC_2;
break;
case GPIO_IRQ_3:
obj->irq_src = INTIFAO_INT_SRC_3;
break;
case GPIO_IRQ_4:
obj->irq_src = INTIFAO_INT_SRC_4;
break;
case GPIO_IRQ_5:
obj->irq_src = INTIFAO_INT_SRC_5;
break;
default:
break;
}
// Save irq handler
hal_irq_handler[obj->irq_src] = handler;
// Save irq id
channel_ids[obj->irq_src] = id;
// Initialize interrupt event as both edges detection
obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
// Set interrupt event and enable INTx clear
INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
core_util_critical_section_exit();;
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
// Clear gpio_irq
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Reset interrupt handler
hal_irq_handler[obj->irq_src] = NULL;
// Reset interrupt id
channel_ids[obj->irq_src] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
//Disable GPIO interrupt on obj
gpio_irq_disable(obj);
if (enable) {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
(obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
(obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
}
} else {
error("Not supported event\n");
}
} else {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
(obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
} else {
obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
(obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
} else {
obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
}
} else {
error("Not supported event\n");
}
}
if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID) {
// Set interrupt event and enable INTx clear
INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE);
} else {
GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
}
// Clear interrupt request
INTIFAO_ClearINTReq(obj->irq_src);
// Enable GPIO interrupt on obj
gpio_irq_enable(obj);
}
void gpio_irq_enable(gpio_irq_t *obj)
{
// Clear and Enable gpio_irq object
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
// Disable gpio_irq object
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
}

40
targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h
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@ -1,40 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
GPIO_Port port;
} gpio_t;
static inline int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin != (PinName)NC);
}
#ifdef __cplusplus
}
#endif
#endif

368
targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#if DEVICE_I2C
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#define I2C_NACK (0)
#define I2C_ACK (1)
#define I2C_NO_DATA (0)
#define I2C_READ_ADDRESSED (1)
#define I2C_WRITE_GENERAL (2)
#define I2C_WRITE_ADDRESSED (3)
#define SELF_ADDR (0xE0)
#define I2C_TIMEOUT (100000)
static const PinMap PinMap_I2C_SDA[] = {
{PC1, I2C_0, PIN_DATA(1, 2)},
{PG1, I2C_1, PIN_DATA(1, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PC0, I2C_0, PIN_DATA(1, 2)},
{PG0, I2C_1, PIN_DATA(1, 2)},
{NC, NC, 0}
};
void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx);
// Clock setting structure definition
typedef struct {
uint32_t sck;
uint32_t prsck;
} I2C_clock_setting_t;
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {20, 24, 32, 48, 80, 144, 272, 528}; // SCK Divider value table
static uint32_t start_flag = 0;
I2C_clock_setting_t clk;
I2C_State status;
static int32_t wait_status(i2c_t *obj)
{
volatile int32_t timeout = I2C_TIMEOUT;
while (I2C_GetINTI2CStatus(obj->i2c) == DISABLE) {
if ((timeout--) == 0) {
return (-1);
}
}
return (0);
}
// Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
MBED_ASSERT(obj != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)i2c_name != NC);
switch (i2c_name) {
case I2C_0:
CG_SetFcPeriphA(CG_FC_PERIPH_I2C0, ENABLE);
obj->i2c = TSB_I2C0;
obj->IRQn = INTI2C0_IRQn;
break;
case I2C_1:
CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE);
obj->i2c = TSB_I2C1;
obj->IRQn = INTI2C1_IRQn;
break;
default:
error("I2C is not available");
break;
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(scl, OpenDrain);
pin_mode(scl, PullUp);
NVIC_DisableIRQ(obj->IRQn);
i2c_reset(obj);
i2c_frequency(obj, 100000);
}
// Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz)
{
uint64_t sck, tmp_sck;
uint64_t prsck, tmp_prsck;
uint64_t fscl, tmp_fscl;
uint64_t fx;
SystemCoreClockUpdate();
if (hz <= 1000000) {
sck = tmp_sck = 0;
prsck = tmp_prsck = 1;
fscl = tmp_fscl = 0;
for (prsck = 1; prsck <= 32; prsck++) {
fx = ((uint64_t)SystemCoreClock / prsck);
if ((fx < 40000000U) && (fx > 6666666U)) {
for (sck = 0; sck <= 7; sck++) {
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
tmp_sck = sck;
tmp_prsck = (prsck < 32)? prsck: 0;
}
}
}
}
clk.sck = (uint32_t)tmp_sck;
clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck) : 0;
}
obj->myi2c.I2CSelfAddr = SELF_ADDR;
obj->myi2c.I2CDataLen = I2C_DATA_LEN_8;
obj->myi2c.I2CACKState = ENABLE;
obj->myi2c.I2CClkDiv = clk.sck;
obj->myi2c.PrescalerClkDiv = clk.prsck;
I2C_Init(obj->i2c, &obj->myi2c);
NVIC_DisableIRQ(obj->IRQn);
}
int i2c_start(i2c_t *obj)
{
start_flag = 1;
return 0;
}
int i2c_stop(i2c_t *obj)
{
I2C_GenerateStop(obj->i2c);
return 0;
}
void i2c_reset(i2c_t *obj)
{
I2C_SWReset(obj->i2c);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int32_t result = 0;
int32_t count = 0;
if (length > 0) {
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) {
while (count < length) {
int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1));
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
}
return (result);
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) // Blocking sending data
{
int32_t result = 0;
int32_t count = 0;
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, address) == I2C_ACK) {
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
return (result);
}
int i2c_byte_read(i2c_t *obj, int last)
{
int32_t result;
I2C_ClearINTOutput(obj->i2c);
if (last) {
I2C_SelectACKoutput(obj->i2c, ENABLE);
} else {
I2C_SelectACKoutput(obj->i2c, DISABLE);
}
I2C_SetSendData(obj->i2c, 0x00);
if (wait_status(obj) < 0) {
result = -1;
} else {
result = (int32_t)I2C_GetReceiveData(obj->i2c);
}
return (result);
}
void I2C_Start_Condition(i2c_t *p_obj, uint32_t data)
{
status = I2C_GetState(p_obj->i2c);
if (status.Bit.BusState) {
I2C_SetRepeatStart(p_obj->i2c, ENABLE);
}
I2C_SetSendData(p_obj->i2c, (uint32_t)data);
I2C_GenerateStart(p_obj->i2c);
}
int i2c_byte_write(i2c_t *obj, int data)
{
int32_t result;
I2C_ClearINTOutput(obj->i2c);
if (start_flag == 1) {
I2C_Start_Condition(obj, (uint32_t)data);
start_flag = 0;
} else {
I2C_SetSendData(obj->i2c, (uint32_t)data);
}
if (wait_status(obj) < 0) {
return (-1);
}
status = I2C_GetState(obj->i2c);
if (!status.Bit.LastRxBit) {
result = 1;
} else {
result = 0;
}
return (result);
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
i2c_reset(obj);
obj->myi2c.I2CDataLen = I2C_DATA_LEN_8;
obj->myi2c.I2CACKState = ENABLE;
obj->myi2c.I2CClkDiv = clk.sck;
obj->myi2c.PrescalerClkDiv = clk.prsck;
if (enable_slave) {
obj->myi2c.I2CSelfAddr = obj->address;
I2C_SetINTI2CReq(obj->i2c, ENABLE);
} else {
obj->myi2c.I2CSelfAddr = SELF_ADDR;
NVIC_DisableIRQ(obj->IRQn);
I2C_ClearINTOutput(obj->i2c);
}
I2C_Init(obj->i2c, &obj->myi2c);
}
int i2c_slave_receive(i2c_t *obj)
{
int32_t result = I2C_NO_DATA;
if ((I2C_GetINTI2CStatus(obj->i2c)) && (I2C_GetSlaveAddrMatchState(obj->i2c))) {
status = I2C_GetState(obj->i2c);
if (!status.Bit.TRx) {
result = I2C_WRITE_ADDRESSED;
} else {
result = I2C_READ_ADDRESSED;
}
}
return (result);
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
int32_t count = 0;
while (count < length) {
int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1));
status = I2C_GetState(obj->i2c);
if (status.Bit.TRx) {
return (count);
} else {
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
}
i2c_slave_mode(obj, 1);
return (count);
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
int32_t count = 0;
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
i2c_slave_mode(obj, 1);
return (count);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
obj->address = address & 0xFE;
i2c_slave_mode(obj, 1);
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}
#endif // #if DEVICE_I2C

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targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "PortNames.h"
#include "PeripheralNames.h"
#include "tmpm066_gpio.h"
#include "tmpm066_uart.h"
#include "tmpm066_cg.h"
#include "tmpm066_intifao.h"
#include "tmpm066_i2c.h"
#include "tmpm066_adc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t mask;
GPIO_Port port;
uint32_t irq_id;
INTIFAO_INTActiveState event;
INTIFAO_INTSrc irq_src;
};
struct port_s {
PortName port;
uint32_t mask;
};
struct pwmout_s {
PinName pin;
TSB_TB_TypeDef *channel;
uint16_t trailing_timing;
uint16_t leading_timing;
uint16_t divisor;
float period;
};
struct serial_s {
PinName pin;
uint32_t index;
TSB_SC_TypeDef *UARTx;
UART_InitTypeDef uart_config;
};
struct analogin_s {
PinName pin;
ADCName adc;
TSB_AD_TypeDef *obj;
};
struct i2c_s {
uint32_t address;
IRQn_Type IRQn;
TSB_I2C_TypeDef *i2c;
I2C_InitTypeDef myi2c;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c
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@ -1,106 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "tmpm066_gpio.h"
#define PIN_FUNC_MAX 6
void pin_function(PinName pin, int function)
{
uint32_t port = 0;
uint8_t bit = 0;
uint8_t i = 0;
uint8_t func = 0;
uint8_t dir = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Calculate pin function and pin direction
func = PIN_FUNC(function);
dir = PIN_DIR(function);
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Set function if function is in range
if (func <= PIN_FUNC_MAX) {
// Disable other functions
for (i = 0; i < PIN_FUNC_MAX; i++) {
if (i != (func - 1)) {
GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit));
}
}
// Set pin function
if (func) {
GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit));
}
}
// Set direction if direction is in range
switch (dir) {
case PIN_INPUT:
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
break;
case PIN_OUTPUT:
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
break;
case PIN_INOUT:
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
break;
default:
break;
}
}
void pin_mode(PinName pin, PinMode mode)
{
uint32_t port = 0;
uint8_t bit = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Check if function is in range
if (mode > OpenDrain) {
return;
}
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Set pin mode
switch (mode) {
case PullNone:
GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE);
GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE);
GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE);
break;
case PullUp:
GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE);
break;
case PullDown:
GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE);
break;
case OpenDrain:
GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE);
break;
default:
break;
}
}

124
targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#define PORT_PIN_NUM 8
PinName port_pin(PortName port, int pin_n)
{
PinName pin = NC;
pin = (PinName)((port << 3) | pin_n);
return pin;
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(port <= PortJ);
// Store port and port mask for future use
obj->port = port;
obj->mask = mask;
if ((PortName)obj->port == PortH) {
CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
}
if ((PortName)obj->port == PortJ) {
CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
}
// Set port function and port direction
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_function(port_pin(obj->port, i), dir);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortJ);
// Set mode for masked pins
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
// Assert that port is valid
MBED_ASSERT(obj->port <= PortJ);
// Set direction for masked pins
switch (dir) {
case PIN_INPUT:
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
break;
case PIN_OUTPUT:
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
break;
case PIN_INOUT:
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
break;
default:
break;
}
}
void port_write(port_t *obj, int value)
{
uint8_t port_data = 0;
uint8_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortJ);
// Get current data of port
port_data = GPIO_ReadData((GPIO_Port)obj->port);
// Calculate data to write to masked pins
data = (port_data & ~obj->mask) | (value & obj->mask);
// Write data to masked pins of the port
GPIO_WriteData((GPIO_Port)obj->port, data);
}
int port_read(port_t *obj)
{
uint8_t port_data = 0;
uint8_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortJ);
// Get current data of port
port_data = GPIO_ReadData((GPIO_Port)obj->port);
// Calculate data of masked pins
data = port_data & obj->mask;
return data;
}

248
targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "tmpm066_tmrb.h"
#define CLOCK_FREQUENCY SystemCoreClock // input source clock
#define MAX_COUNTER_16B 0xFFFF
#define DEFAULT_CLOCK_DIVISION 32
#define DEFAULT_PERIOD 0.02f // 20ms
static const PinMap PinMap_PWM[] = {
{PD1, PWM_0, PIN_DATA(1, 1)},
{PD2, PWM_1, PIN_DATA(1, 1)},
{PD3, PWM_2, PIN_DATA(1, 1)},
{PF4, PWM_3, PIN_DATA(1, 1)},
{PF5, PWM_4, PIN_DATA(1, 1)},
{PJ0, PWM_5, PIN_DATA(1, 1)},
{PJ1, PWM_6, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const uint32_t prescale_tbl[] = {
2, 8, 32, 64, 128, 256, 512
};
void pwmout_init(pwmout_t *obj, PinName pin)
{
uint16_t counter = 0;
TMRB_FFOutputTypeDef FFStruct;
TMRB_InitTypeDef m_tmrb;
// Determine the pwm channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
//Assert input is valid
MBED_ASSERT(pwm != (PWMName)NC);
// Enable clock supply to TB0
CG_SetFcPeriphA(CG_FC_PERIPH_TMRB0_3, ENABLE);
CG_SetFcPeriphA(CG_FC_PERIPH_TMRB4_6, ENABLE);
switch (pwm) {
case PWM_0:
obj->channel = TSB_TB0;
break;
case PWM_1:
obj->channel = TSB_TB1;
break;
case PWM_2:
obj->channel = TSB_TB2;
break;
case PWM_3:
obj->channel = TSB_TB3;
break;
case PWM_4:
obj->channel = TSB_TB4;
break;
case PWM_5:
obj->channel = TSB_TB5;
CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
break;
case PWM_6:
obj->channel = TSB_TB6;
CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
break;
default:
obj->channel = NULL;
return;
}
// Set pin function as PWM
pinmap_pinout(pin, PinMap_PWM);
obj->pin = pin;
obj->period = DEFAULT_PERIOD;
// Enable channel
TMRB_Enable(obj->channel);
// Stops and clear count operation
TMRB_SetRunState(obj->channel, TMRB_STOP);
// Disables double buffering
TMRB_SetDoubleBuf(obj->channel, DISABLE);
// Set default period = 20ms, duty cycle = 0
obj->divisor = DEFAULT_CLOCK_DIVISION;
counter = (uint16_t)((DEFAULT_PERIOD * CLOCK_FREQUENCY) / obj->divisor);
// Init timer variable for using PPG mode
m_tmrb.Mode = TMRB_INTERVAL_TIMER;
m_tmrb.ClkDiv = TMRB_CLK_DIV_32;
m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR; // clear UC when matching value
m_tmrb.TrailingTiming = counter; // period = 20ms
m_tmrb.LeadingTiming = counter; // duty cycle = 0%
// Init timer function
TMRB_Init(obj->channel, &m_tmrb);
obj->trailing_timing = counter;
obj->leading_timing = counter;
// Enable double buffering
TMRB_SetDoubleBuf(obj->channel, ENABLE);
// Setting to TBxFF0 reverse trigger
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING;
TMRB_SetFlipFlop(obj->channel, &FFStruct);
// Start count operation
TMRB_SetRunState(obj->channel, TMRB_RUN);
}
void pwmout_free(pwmout_t *obj)
{
// Stops and clear count operation
TMRB_SetRunState(obj->channel, TMRB_STOP);
pwmout_write(obj,0);
obj->pin = NC;
obj->channel = NULL;
obj->trailing_timing = 0;
obj->leading_timing = 0;
obj->divisor = 0;
}
void pwmout_write(pwmout_t *obj, float value)
{
TMRB_FFOutputTypeDef FFStruct;
// Stop timer for setting clock again
TMRB_SetRunState(obj->channel, TMRB_STOP);
// values outside this range will be saturated to 0.0f or 1.0f
// Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated
if (value <= 0.0f) {
value = 0;
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
TMRB_SetFlipFlop(obj->channel, &FFStruct);
} else if (value >= 1.0f) {
value = 1;
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
TMRB_SetFlipFlop(obj->channel, &FFStruct);
} else {
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING;
TMRB_SetFlipFlop(obj->channel, &FFStruct);
}
// Store the new leading_timing value
obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value);
// Setting TBxRG0 register
TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing);
TMRB_SetRunState(obj->channel, TMRB_RUN);
}
float pwmout_read(pwmout_t *obj)
{
float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
return duty_cycle;
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
float seconds = 0;
int cycles = 0;
uint32_t clkdiv = 0;
float duty_cycle = 0;
TMRB_InitTypeDef m_tmrb;
seconds = (float)((us) / 1000000.0f);
obj->period = seconds;
MBED_ASSERT(obj->channel != NULL);
// Select highest timer resolution
for (int i = 0; i < 7; ++i) {
cycles = (int)((CLOCK_FREQUENCY / prescale_tbl[i]) * seconds);
if (cycles <= MAX_COUNTER_16B) {
clkdiv = i + 1; // range 1:7
break;
}
}
// Stop timer for setting clock again
TMRB_SetRunState(obj->channel, TMRB_STOP);
// Restore the duty-cycle
duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
obj->trailing_timing = cycles;
obj->leading_timing = (cycles - (uint16_t)(cycles * duty_cycle));
// Change the source clock division and period
m_tmrb.Mode = TMRB_INTERVAL_TIMER;
m_tmrb.ClkDiv = clkdiv;
m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR;
m_tmrb.TrailingTiming = obj->trailing_timing;
m_tmrb.LeadingTiming = obj->leading_timing;
//Init timer function
TMRB_Init(obj->channel, &m_tmrb);
//Start timer function
TMRB_SetRunState(obj->channel, TMRB_RUN);
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
float seconds = 0;
float value = 0;
MBED_ASSERT(obj->channel != NULL);
seconds = (float)(us / 1000000.0f);
value = (((seconds / obj->period) * 100.0f) / 100.0f);
pwmout_write(obj, value);
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM;
}

135
targets/TARGET_TOSHIBA/TARGET_TMPM066/reset_reason_api.c
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@ -1,135 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "reset_reason_api.h"
#ifdef DEVICE_RESET_REASON
#include "TMPM066.h"
#include <stdbool.h>
#define MAXRSTREASON 6
static uint8_t set_bit_count(uint32_t reg);
static uint8_t bit_pos(uint32_t reg);
static bool bit_status(uint32_t reg, uint8_t bit_no);
static reset_reason_t reset_reason1[MAXRSTREASON] = {
RESET_REASON_POWER_ON,
RESET_REASON_UNKNOWN,
RESET_REASON_UNKNOWN,
RESET_REASON_PIN_RESET,
RESET_REASON_UNKNOWN,
RESET_REASON_BROWN_OUT
};
static reset_reason_t reset_reason2[MAXRSTREASON] = {
RESET_REASON_SOFTWARE,
RESET_REASON_UNKNOWN,
RESET_REASON_WATCHDOG
};
void hal_reset_reason_clear(void)
{
TSB_AOREG->RSTFLG = 0x00;
TSB_AOREG->RSTFLG1 = 0x00;
}
uint32_t hal_reset_reason_get_raw(void)
{
uint32_t ret = 0x00;
ret = (((TSB_AOREG->RSTFLG1 & 0xFF) << 8) | (TSB_AOREG->RSTFLG & 0xFF));
return ret;
}
reset_reason_t hal_reset_reason_get(void)
{
reset_reason_t ret;
uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_AOREG->RSTFLG);
uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_AOREG->RSTFLG1);
if (NoOfSetBitCountReg1 != 0x00) {
if (NoOfSetBitCountReg1 > 0x01) {
if (bit_status(TSB_AOREG->RSTFLG, 0) && bit_status(TSB_AOREG->RSTFLG, 3)) {
ret = RESET_REASON_POWER_ON;
} else {
ret = RESET_REASON_MULTIPLE;
}
} else {
ret = reset_reason1[bit_pos(TSB_AOREG->RSTFLG)];
}
} else if (NoOfSetBitCountReg2 != 0x00) {
if (NoOfSetBitCountReg2 > 0x01) {
ret = RESET_REASON_MULTIPLE;
} else {
ret = reset_reason2[bit_pos(TSB_AOREG->RSTFLG1)];
}
} else {
ret = RESET_REASON_UNKNOWN;
}
return ret;
}
void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
{
cap->reasons = 1 << RESET_REASON_UNKNOWN;
cap->reasons |= 1 << RESET_REASON_POWER_ON;
cap->reasons |= 1 << RESET_REASON_MULTIPLE;
}
static bool bit_status(uint32_t reg, uint8_t bit_no)
{
bool status = false;
if (reg & (1 << bit_no)) {
status = true;
}
return status;
}
static uint8_t set_bit_count(uint32_t reg)
{
uint8_t count = 0;
int8_t index = 0;
for (index = 0; index < (sizeof(uint32_t) * 8); index++) {
if (reg & (1 << index)) {
count++;
if (count > 0x01) {
break;
}
}
}
return count;
}
static uint8_t bit_pos(uint32_t reg)
{
uint8_t bit_no = 0;
for (bit_no = 0; bit_no < (sizeof(uint32_t) * 8); bit_no++) {
if (reg & (1 << bit_no)) {
return bit_no;
}
}
}
#endif // DEVICE_RESET_REASON

281
targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c
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@ -1,281 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "serial_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#define UART_NUM 2
static const PinMap PinMap_UART_TX[] = {
{PC2, SERIAL_0, PIN_DATA(1, 1)},
{PE2, SERIAL_1, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PC3, SERIAL_0, PIN_DATA(1, 0)},
{PE1, SERIAL_1, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static int serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart_name != NC);
obj->index = uart_name;
// Initialize UART instance
switch (uart_name) {
case SERIAL_0:
CG_SetFcPeriphA(CG_FC_PERIPH_SIO0, ENABLE);
obj->UARTx = UART0;
break;
case SERIAL_1:
CG_SetFcPeriphB(CG_FC_PERIPH_SIO1, ENABLE);
obj->UARTx = UART1;
break;
default:
break;
}
obj->uart_config.BaudRate = 9600;
obj->uart_config.DataBits = UART_DATA_BITS_8;
obj->uart_config.StopBits = UART_STOP_BITS_1;
obj->uart_config.Parity = UART_NO_PARITY;
obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL;
if (tx != NC && rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
} else {
if (tx != NC) {
obj->uart_config.Mode = UART_ENABLE_TX;
} else {
if (rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX;
}
}
}
// Pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Initialize UART configure
UART_Enable(obj->UARTx);
UART_SetIdleMode(obj->UARTx, ENABLE);
UART_Init(obj->UARTx, &obj->uart_config);
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
// Disable UART
UART_Disable(obj->UARTx);
UART_SWReset(obj->UARTx);
// Set information of object to invalid
obj->uart_config.BaudRate = 0;
obj->uart_config.DataBits = 0;
obj->uart_config.StopBits = 0;
obj->uart_config.Parity = 0;
obj->uart_config.Mode = 0;
obj->uart_config.FlowCtrl = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->uart_config.BaudRate = baudrate;
UART_Init(obj->UARTx, &obj->uart_config);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
// 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
// 0: 7 data bits ... 2: 9 data bits
MBED_ASSERT((data_bits > 6) && (data_bits < 10));
obj->uart_config.DataBits = data_bits;
obj->uart_config.StopBits = stop_bits;
obj->uart_config.Parity = parity;
UART_Init(obj->UARTx, &obj->uart_config);
}
// INTERRUPTS HANDLING
void INTTX0_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
}
void INTRX0_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
}
void INTTX1_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
}
void INTRX1_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
switch (obj->index) {
case SERIAL_0:
if (irq == RxIrq) {
irq_n = INTRX0_IRQn;
} else {
irq_n = INTTX0_IRQn;
}
break;
case SERIAL_1:
if (irq == RxIrq) {
irq_n = INTRX1_IRQn;
} else {
irq_n = INTTX1_IRQn;
}
break;
default:
break;
}
if (enable) {
NVIC_EnableIRQ(irq_n);
} else {
NVIC_DisableIRQ(irq_n);
}
}
int serial_getc(serial_t *obj)
{
// Wait until Rx buffer is full
while (!serial_readable(obj)) {
// Do nothing
}
return UART_GetRxData(obj->UARTx);
}
void serial_putc(serial_t *obj, int c)
{
// Wait until Tx buffer is empty
while (!serial_writable(obj)) {
// Do nothing
}
UART_SetTxData(obj->UARTx, (uint32_t)c);
}
int serial_readable(serial_t *obj)
{
int ret = 0;
if (UART_GetBufState(obj->UARTx, UART_RX) == DONE) {
ret = 1;
}
return ret;
}
int serial_writable(serial_t *obj)
{
int ret = 0;
if (UART_GetBufState(obj->UARTx, UART_TX) == DONE) {
ret = 1;
}
return ret;
}
void serial_clear(serial_t *obj)
{
UART_TxFIFOClear(obj->UARTx);
UART_RxFIFOClear(obj->UARTx);
UART_TxBufferClear(obj->UARTx);
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
}
void serial_break_clear(serial_t *obj)
{
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}

66
targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c
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@ -1,66 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
// number of warm-up cycle = warm-up time to set / input frequency cycle (s)
// number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60
#define CG_WUODR_INT ((uint16_t)0xea60)
void external_losc_enable(void);
void hal_sleep(void)
{
// Set low power consumption mode IDLE
CG_SetSTBYMode(CG_STBY_MODE_IDLE);
// Enter idle mode
__WFI();
}
void hal_deepsleep(void)
{
// Set low power consumption mode STOP1
CG_SetSTBYMode(CG_STBY_MODE_STOP1);
// Setup warm up time
CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT);
// Enter stop1 mode
__WFI();
// Switch over from IHOSC to EHOSC
external_losc_enable();
}
void external_losc_enable(void)
{
// Enable high-speed oscillator
CG_SetFoscSrc(CG_FOSC_OSC_EXT);
// Select internal(fIHOSC) as warm-up clock
CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT);
// Start warm-up
CG_StartWarmUp();
// Wait until EHOSC become stable
while (CG_GetWarmUpState() != DONE) {
// Do nothing
}
// Set fosc source
CG_SetFoscSrc(CG_FOSC_OSC_EXT);
// Wait for <OSCSEL> to become "1"
while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) {
// Do nothing
}
// Stop IHOSC
CG_SetFoscSrc(CG_FOSC_OSC_INT);
}

120
targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "us_ticker_api.h"
#include "tmpm066_tmrb.h"
#include "tmpm066_intifsd.h"
#define MAX_TICK_16_BIT 0xFFFF
static bool us_ticker_inited = false; // Is ticker initialized yet?
void INTTB7_IRQHandler(void)
{
us_ticker_irq_handler();
}
const ticker_info_t* us_ticker_get_info()
{
static const ticker_info_t info = {
3000000, // 3MHz,
16 // 16 bit counter
};
return &info;
}
// initialize us_ticker
void us_ticker_init(void)
{
TMRB_InitTypeDef m_tmrb0;
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = true;
// TSB_TB7 using free-run
m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
m_tmrb0.ClkDiv = TMRB_CLK_DIV_8;
m_tmrb0.UpCntCtrl = TMRB_FREE_RUN;
m_tmrb0.TrailingTiming = MAX_TICK_16_BIT;
m_tmrb0.LeadingTiming = MAX_TICK_16_BIT;
// Enable channel 0
TMRB_Enable(TSB_TB7);
// Stops and clear count operation
TMRB_SetRunState(TSB_TB7, TMRB_STOP);
// Mask All interrupts
TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
// Initialize timer
TMRB_Init(TSB_TB7, &m_tmrb0);
// Starts TSB_TB7
TMRB_SetRunState(TSB_TB7, TMRB_RUN);
}
uint32_t us_ticker_read(void)
{
uint32_t ret_val = 0;
if (!us_ticker_inited) {
us_ticker_init();
}
ret_val = (uint32_t)TMRB_GetUpCntValue(TSB_TB7);
return ret_val;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
NVIC_DisableIRQ(INTTB7_IRQn);
NVIC_ClearPendingIRQ(INTTB7_IRQn);
TMRB_ChangeTrailingTiming(TSB_TB7, timestamp);
//Mask all Interrupts except trailing edge interrupt
TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
NVIC_EnableIRQ(INTTB7_IRQn);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(INTTB7_IRQn);
NVIC_EnableIRQ(INTTB7_IRQn);
}
void us_ticker_disable_interrupt(void)
{
// Mask All interrupts
TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
// Also clear and disable interrupts by NVIC
NVIC_ClearPendingIRQ(INTTB7_IRQn);
NVIC_DisableIRQ(INTTB7_IRQn);
}
void us_ticker_clear_interrupt(void)
{
INTIFSD_ClearINTReq(INTIFSD_INT_SRC_TMRB_7_MDOVF);
NVIC_ClearPendingIRQ(INTTB7_IRQn);
}
void us_ticker_free(void)
{
TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
NVIC_ClearPendingIRQ(INTTB7_IRQn);
NVIC_DisableIRQ(INTTB7_IRQn);
TMRB_SetRunState(TSB_TB7, TMRB_STOP);
TMRB_Disable(TSB_TB7);
}

108
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h
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@ -1,108 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
SERIAL_2,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
ADC_AINA0 = 0,
ADC_AINA1,
ADC_AINA2,
ADC_AINA3,
ADC_AINA4,
ADC_AINA5,
ADC_AINA6,
ADC_AINA7,
ADC_AINA8,
ADC_AINA9,
ADC_AINA10,
ADC_AINA11,
ADC_AINA12,
ADC_AINA13,
ADC_AINA14,
ADC_AINA15,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
DAC_A0 = 0,
DAC_A1,
INVALID_DAC = (int)NC
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1,
INVALID_SPI = (int)NC
} SPIName;
typedef enum {
I2C_0 = 0,
I2C_1,
I2C_2,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
GPIO_IRQ_0 = 0,
GPIO_IRQ_1,
GPIO_IRQ_2,
GPIO_IRQ_3,
GPIO_IRQ_4,
GPIO_IRQ_5,
GPIO_IRQ_6,
GPIO_IRQ_7,
GPIO_IRQ_8,
GPIO_IRQ_9,
GPIO_IRQ_A,
GPIO_IRQ_B,
GPIO_IRQ_C,
GPIO_IRQ_D,
GPIO_IRQ_E,
GPIO_IRQ_F,
INVALID_GPIO_IRQ = (int)NC
} GPIO_IRQName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART SERIAL_1
#ifdef __cplusplus
}
#endif
#endif

121
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h
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@ -1,121 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM3H6 Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6,
PD0 = 3 << 3, PD1, PD2, PD3,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6,
PF0 = 5 << 3, PF1, PF2, PF3, PF4,
PG0 = 6 << 3, PG1,
PH0 = 7 << 3, PH1, PH2, PH3,
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5,
PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7,
PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6,
PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6,
PN0 = 12 << 3, PN1, PN2, PN3, PN4,PN5,
PP0 = 13 << 3, PP1, PP2, PP3,
PR0 = 14 << 3, PR1, PR2, PR3,
// Other mbed Pin Names
LED1 = PB4,
LED2 = PB5,
LED3 = PB6,
LED4 = PB7,
// external data bus Pin Names
D0 = PL0,
D1 = PL1,
D2 = PJ4,
D3 = PJ3,
D4 = PC4,
D5 = PC3,
D6 = PB3,
D7 = PB2,
D8 = PK1,
D9 = PJ0,
D10 = PL6,
D11 = PP1,
D12 = PP2,
D13 = PP0,
D14 = PA5,
D15 = PA4,
A0 = PE0,
A1 = PE1,
A2 = PE2,
A3 = PE3,
A4 = PE4,
A5 = PE5,
DAC0 = PG0,
DAC1 = PG1,
USBTX = PJ2,
USBRX = PJ1,
SW1 = PN4,
SW2 = PN3,
SW3 = PN2,
SW4 = PN1,
// I2C
EEPROM_SDA = PC1,
EEPROM_SCL = PC0,
// TSPI
MOSI = PP1,
MISO = PP2,
SCLK = PP0,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault
} PinMode;
typedef enum {
DISABLE = 0,
ENABLE
} FunctionalState;
#ifdef __cplusplus
}
#endif
#endif

47
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h
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@ -1,47 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ,
PortK,
PortL,
PortM,
PortN,
PortP,
PortR,
} PortName;
#define IS_GPIO_PORT(param) ((param) <= PortR) // parameter checking for port number
#ifdef __cplusplus
}
#endif
#endif

96
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c
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@ -1,96 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_ADC[] = {
{PD0, ADC_AINA0, PIN_DATA(0, 0)},
{PD1, ADC_AINA1, PIN_DATA(0, 0)},
{PD2, ADC_AINA2, PIN_DATA(0, 0)},
{PD3, ADC_AINA3, PIN_DATA(0, 0)},
{PE0, ADC_AINA4, PIN_DATA(0, 0)},
{PE1, ADC_AINA5, PIN_DATA(0, 0)},
{PE2, ADC_AINA6, PIN_DATA(0, 0)},
{PE3, ADC_AINA7, PIN_DATA(0, 0)},
{PE4, ADC_AINA8, PIN_DATA(0, 0)},
{PE5, ADC_AINA9, PIN_DATA(0, 0)},
{PE6, ADC_AINA10, PIN_DATA(0, 0)},
{PF0, ADC_AINA11, PIN_DATA(0, 0)},
{PF1, ADC_AINA12, PIN_DATA(0, 0)},
{PF2, ADC_AINA13, PIN_DATA(0, 0)},
{PF3, ADC_AINA14, PIN_DATA(0, 0)},
{PF4, ADC_AINA15, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->obj = TSB_ADA;
TSB_CG_FSYSENB_IPENB00 = ENABLE; // ADC CG Fsys Enable
pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC
obj->obj->CLK = ADC_SCLK_1; // Set sample hold time and prescale clock
obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON);
TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t ADCResultValue = 0;
uint32_t ADCResultStored = 0;
wait_us(3U); // Wait at least 3us to ensure the voltage is stable
obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion
obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion
obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE |
ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE);
while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) {
// Wait until AD conversion complete
}
wait_us(1U); // Wait for register to update with convert value.
ADCResultStored = obj->obj->REG0; // Convert result
if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) {
ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4);
}
return ADCResultValue;
}
float analogin_read(analogin_t *obj)
{
float result = 0.0;
uint16_t value = 0;
value = analogin_read_u16(obj);
result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE));
return result;
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

105
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c
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@ -1,105 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_DAC[] = {
{DAC0, DAC_A0, PIN_DATA(0, 3)},
{DAC1, DAC_A1, PIN_DATA(0, 3)},
{NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin)
{
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module
MBED_ASSERT(obj->dac != (DACName)NC);
pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC
TSB_CG_FSYSENA_IPENA06 = ENABLE;
if (obj->dac == DAC_A0) { // Compute handler
obj->handler = TSB_DA0;
TSB_CG_FSYSENB_IPENB01 = ENABLE;
} else {
if (obj->dac == DAC_A1) {
obj->handler = TSB_DA1;
TSB_CG_FSYSENB_IPENB02 = ENABLE;
} else {
obj->handler = NULL;
}
}
obj->handler->CTL = DAC_STOP;
}
void analogout_free(dac_t *obj)
{
obj->handler->CTL = DAC_STOP;
}
void analogout_write(dac_t *obj, float value)
{
uint8_t outputcode = 0;
// Enable DAC
obj->handler->CTL = DAC_START;
if (value < 0.0f) {
value = 0.0f;
} else {
if (value >= 1.0f) {
value = 1.0f;
}
}
outputcode = (uint8_t)(value * 255.0f);
obj->handler->REG = outputcode;
wait_ms(3);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
// Enable DAC
obj->handler->CTL = DAC_START;
obj->handler->REG = (uint8_t)(value & 0xFF);
wait_ms(3);
}
float analogout_read(dac_t *obj)
{
float result = 0.0;
uint32_t value = 0;
value = ((obj->handler->REG) & (0xFF));
result = ((float)value / 255.0f);
return result;
}
uint16_t analogout_read_u16(dac_t *obj)
{
uint16_t value = 0;
value = (uint16_t)((obj->handler->REG) & (0xFF));
return value;
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

24
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h
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@ -1,24 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define TRANSACTION_QUEUE_SIZE_SPI 4
#include "objects.h"
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h
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File diff suppressed because it is too large Load Diff

464
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S
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@ -1,464 +0,0 @@
;/**
; *******************************************************************************
; * @file startup_TMPM3H6.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for the
; * TOSHIBA 'TMPM3H6' Device Series
; * @version V1.0.0.0
; * $Date:: #$
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
; *
; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt Pin0
DCD INT01_IRQHandler ; 1: Interrupt Pin1
DCD INT02_IRQHandler ; 2: Interrupt Pin2
DCD INT03_IRQHandler ; 3: Interrupt Pin3
DCD INT04_IRQHandler ; 4: Interrupt Pin4
DCD INT05_IRQHandler ; 5: Interrupt Pin5
DCD INT06_IRQHandler ; 6: Interrupt Pin6
DCD INT07_IRQHandler ; 7: Interrupt Pin7
DCD INT08_IRQHandler ; 8: Interrupt Pin8
DCD INT09_IRQHandler ; 9: Interrupt Pin9
DCD INT10_IRQHandler ; 10: Interrupt Pin10
DCD INT11_IRQHandler ; 11: Interrupt Pin11
DCD INT12_IRQHandler ; 12: Interrupt Pin12
DCD INT13_IRQHandler ; 13: Interrupt Pin13
DCD INT14_IRQHandler ; 14: Interrupt Pin14
DCD INT15_IRQHandler ; 15: Interrupt Pin15
DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt
DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt
DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt
DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0
DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1
DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A
DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B
DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0
DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1
DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished
DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished
DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished
DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0)
DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0)
DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0)
DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1)
DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1)
DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1)
DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0)
DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt
DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt
DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt
DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt
DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt
DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt
DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt
DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt
DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt
DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt
DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt
DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt
DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0)
DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0)
DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0)
DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1)
DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1)
DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1)
DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2)
DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2)
DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2)
DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow
DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0
DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1
DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow
DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0
DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1
DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow
DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0
DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1
DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow
DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0
DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1
DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow
DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0
DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1
DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow
DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0
DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1
DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow
DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0
DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1
DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow
DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0
DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1
DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow
DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0
DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1
DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow
DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0
DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1
DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow
DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0
DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1
DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow
DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0
DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1
DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow
DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0
DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1
DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow
DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0
DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1
DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow
DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0
DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1
DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow
DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0
DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1
DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow
DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0
DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1
DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow
DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0
DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1
DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer
DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error
DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt
DCD 0 ; 113: Reserved
DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt
DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt
DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT00_IRQHandler [WEAK]
EXPORT INT01_IRQHandler [WEAK]
EXPORT INT02_IRQHandler [WEAK]
EXPORT INT03_IRQHandler [WEAK]
EXPORT INT04_IRQHandler [WEAK]
EXPORT INT05_IRQHandler [WEAK]
EXPORT INT06_IRQHandler [WEAK]
EXPORT INT07_IRQHandler [WEAK]
EXPORT INT08_IRQHandler [WEAK]
EXPORT INT09_IRQHandler [WEAK]
EXPORT INT10_IRQHandler [WEAK]
EXPORT INT11_IRQHandler [WEAK]
EXPORT INT12_IRQHandler [WEAK]
EXPORT INT13_IRQHandler [WEAK]
EXPORT INT14_IRQHandler [WEAK]
EXPORT INT15_IRQHandler [WEAK]
EXPORT INTEMG0_IRQHandler [WEAK]
EXPORT INTOVV0_IRQHandler [WEAK]
EXPORT INTPMD0_IRQHandler [WEAK]
EXPORT INTENC00_IRQHandler [WEAK]
EXPORT INTENC01_IRQHandler [WEAK]
EXPORT INTADAPDA_IRQHandler [WEAK]
EXPORT INTADAPDB_IRQHandler [WEAK]
EXPORT INTADACP0_IRQHandler [WEAK]
EXPORT INTADACP1_IRQHandler [WEAK]
EXPORT INTADATRG_IRQHandler [WEAK]
EXPORT INTADASGL_IRQHandler [WEAK]
EXPORT INTADACNT_IRQHandler [WEAK]
EXPORT INTT0RX_IRQHandler [WEAK]
EXPORT INTT0TX_IRQHandler [WEAK]
EXPORT INTT0ERR_IRQHandler [WEAK]
EXPORT INTT1RX_IRQHandler [WEAK]
EXPORT INTT1TX_IRQHandler [WEAK]
EXPORT INTT1ERR_IRQHandler [WEAK]
EXPORT INTI2CWUP_IRQHandler [WEAK]
EXPORT INTI2C0_IRQHandler [WEAK]
EXPORT INTI2C0AL_IRQHandler [WEAK]
EXPORT INTI2C0BF_IRQHandler [WEAK]
EXPORT INTI2C0NA_IRQHandler [WEAK]
EXPORT INTI2C1_IRQHandler [WEAK]
EXPORT INTI2C1AL_IRQHandler [WEAK]
EXPORT INTI2C1BF_IRQHandler [WEAK]
EXPORT INTI2C1NA_IRQHandler [WEAK]
EXPORT INTI2C2_IRQHandler [WEAK]
EXPORT INTI2C2AL_IRQHandler [WEAK]
EXPORT INTI2C2BF_IRQHandler [WEAK]
EXPORT INTI2C2NA_IRQHandler [WEAK]
EXPORT INTUART0RX_IRQHandler [WEAK]
EXPORT INTUART0TX_IRQHandler [WEAK]
EXPORT INTUART0ERR_IRQHandler [WEAK]
EXPORT INTUART1RX_IRQHandler [WEAK]
EXPORT INTUART1TX_IRQHandler [WEAK]
EXPORT INTUART1ERR_IRQHandler [WEAK]
EXPORT INTUART2RX_IRQHandler [WEAK]
EXPORT INTUART2TX_IRQHandler [WEAK]
EXPORT INTUART2ERR_IRQHandler [WEAK]
EXPORT INTT32A00A_IRQHandler [WEAK]
EXPORT INTT32A00ACAP0_IRQHandler [WEAK]
EXPORT INTT32A00ACAP1_IRQHandler [WEAK]
EXPORT INTT32A00B_IRQHandler [WEAK]
EXPORT INTT32A00BCAP0_IRQHandler [WEAK]
EXPORT INTT32A00BCAP1_IRQHandler [WEAK]
EXPORT INTT32A00C_IRQHandler [WEAK]
EXPORT INTT32A00CCAP0_IRQHandler [WEAK]
EXPORT INTT32A00CCAP1_IRQHandler [WEAK]
EXPORT INTT32A01A_IRQHandler [WEAK]
EXPORT INTT32A01ACAP0_IRQHandler [WEAK]
EXPORT INTT32A01ACAP1_IRQHandler [WEAK]
EXPORT INTT32A01B_IRQHandler [WEAK]
EXPORT INTT32A01BCAP0_IRQHandler [WEAK]
EXPORT INTT32A01BCAP1_IRQHandler [WEAK]
EXPORT INTT32A01C_IRQHandler [WEAK]
EXPORT INTT32A01CCAP0_IRQHandler [WEAK]
EXPORT INTT32A01CCAP1_IRQHandler [WEAK]
EXPORT INTT32A02A_IRQHandler [WEAK]
EXPORT INTT32A02ACAP0_IRQHandler [WEAK]
EXPORT INTT32A02ACAP1_IRQHandler [WEAK]
EXPORT INTT32A02B_IRQHandler [WEAK]
EXPORT INTT32A02BCAP0_IRQHandler [WEAK]
EXPORT INTT32A02BCAP1_IRQHandler [WEAK]
EXPORT INTT32A02C_IRQHandler [WEAK]
EXPORT INTT32A02CCAP0_IRQHandler [WEAK]
EXPORT INTT32A02CCAP1_IRQHandler [WEAK]
EXPORT INTT32A03A_IRQHandler [WEAK]
EXPORT INTT32A03ACAP0_IRQHandler [WEAK]
EXPORT INTT32A03ACAP1_IRQHandler [WEAK]
EXPORT INTT32A03B_IRQHandler [WEAK]
EXPORT INTT32A03BCAP0_IRQHandler [WEAK]
EXPORT INTT32A03BCAP1_IRQHandler [WEAK]
EXPORT INTT32A03C_IRQHandler [WEAK]
EXPORT INTT32A03CCAP0_IRQHandler [WEAK]
EXPORT INTT32A03CCAP1_IRQHandler [WEAK]
EXPORT INTT32A04A_IRQHandler [WEAK]
EXPORT INTT32A04ACAP0_IRQHandler [WEAK]
EXPORT INTT32A04ACAP1_IRQHandler [WEAK]
EXPORT INTT32A04B_IRQHandler [WEAK]
EXPORT INTT32A04BCAP0_IRQHandler [WEAK]
EXPORT INTT32A04BCAP1_IRQHandler [WEAK]
EXPORT INTT32A04C_IRQHandler [WEAK]
EXPORT INTT32A04CCAP0_IRQHandler [WEAK]
EXPORT INTT32A04CCAP1_IRQHandler [WEAK]
EXPORT INTT32A05A_IRQHandler [WEAK]
EXPORT INTT32A05ACAP0_IRQHandler [WEAK]
EXPORT INTT32A05ACAP1_IRQHandler [WEAK]
EXPORT INTT32A05B_IRQHandler [WEAK]
EXPORT INTT32A05BCAP0_IRQHandler [WEAK]
EXPORT INTT32A05BCAP1_IRQHandler [WEAK]
EXPORT INTT32A05C_IRQHandler [WEAK]
EXPORT INTT32A05CCAP0_IRQHandler [WEAK]
EXPORT INTT32A05CCAP1_IRQHandler [WEAK]
EXPORT INTDMAATC_IRQHandler [WEAK]
EXPORT INTDMAAERR_IRQHandler [WEAK]
EXPORT INTRTC_IRQHandler [WEAK]
EXPORT INTRMC0_IRQHandler [WEAK]
EXPORT INTFLCRDY_IRQHandler [WEAK]
EXPORT INTFLDRDY_IRQHandler [WEAK]
INT00_IRQHandler
INT01_IRQHandler
INT02_IRQHandler
INT03_IRQHandler
INT04_IRQHandler
INT05_IRQHandler
INT06_IRQHandler
INT07_IRQHandler
INT08_IRQHandler
INT09_IRQHandler
INT10_IRQHandler
INT11_IRQHandler
INT12_IRQHandler
INT13_IRQHandler
INT14_IRQHandler
INT15_IRQHandler
INTEMG0_IRQHandler
INTOVV0_IRQHandler
INTPMD0_IRQHandler
INTENC00_IRQHandler
INTENC01_IRQHandler
INTADAPDA_IRQHandler
INTADAPDB_IRQHandler
INTADACP0_IRQHandler
INTADACP1_IRQHandler
INTADATRG_IRQHandler
INTADASGL_IRQHandler
INTADACNT_IRQHandler
INTT0RX_IRQHandler
INTT0TX_IRQHandler
INTT0ERR_IRQHandler
INTT1RX_IRQHandler
INTT1TX_IRQHandler
INTT1ERR_IRQHandler
INTI2CWUP_IRQHandler
INTI2C0_IRQHandler
INTI2C0AL_IRQHandler
INTI2C0BF_IRQHandler
INTI2C0NA_IRQHandler
INTI2C1_IRQHandler
INTI2C1AL_IRQHandler
INTI2C1BF_IRQHandler
INTI2C1NA_IRQHandler
INTI2C2_IRQHandler
INTI2C2AL_IRQHandler
INTI2C2BF_IRQHandler
INTI2C2NA_IRQHandler
INTUART0RX_IRQHandler
INTUART0TX_IRQHandler
INTUART0ERR_IRQHandler
INTUART1RX_IRQHandler
INTUART1TX_IRQHandler
INTUART1ERR_IRQHandler
INTUART2RX_IRQHandler
INTUART2TX_IRQHandler
INTUART2ERR_IRQHandler
INTT32A00A_IRQHandler
INTT32A00ACAP0_IRQHandler
INTT32A00ACAP1_IRQHandler
INTT32A00B_IRQHandler
INTT32A00BCAP0_IRQHandler
INTT32A00BCAP1_IRQHandler
INTT32A00C_IRQHandler
INTT32A00CCAP0_IRQHandler
INTT32A00CCAP1_IRQHandler
INTT32A01A_IRQHandler
INTT32A01ACAP0_IRQHandler
INTT32A01ACAP1_IRQHandler
INTT32A01B_IRQHandler
INTT32A01BCAP0_IRQHandler
INTT32A01BCAP1_IRQHandler
INTT32A01C_IRQHandler
INTT32A01CCAP0_IRQHandler
INTT32A01CCAP1_IRQHandler
INTT32A02A_IRQHandler
INTT32A02ACAP0_IRQHandler
INTT32A02ACAP1_IRQHandler
INTT32A02B_IRQHandler
INTT32A02BCAP0_IRQHandler
INTT32A02BCAP1_IRQHandler
INTT32A02C_IRQHandler
INTT32A02CCAP0_IRQHandler
INTT32A02CCAP1_IRQHandler
INTT32A03A_IRQHandler
INTT32A03ACAP0_IRQHandler
INTT32A03ACAP1_IRQHandler
INTT32A03B_IRQHandler
INTT32A03BCAP0_IRQHandler
INTT32A03BCAP1_IRQHandler
INTT32A03C_IRQHandler
INTT32A03CCAP0_IRQHandler
INTT32A03CCAP1_IRQHandler
INTT32A04A_IRQHandler
INTT32A04ACAP0_IRQHandler
INTT32A04ACAP1_IRQHandler
INTT32A04B_IRQHandler
INTT32A04BCAP0_IRQHandler
INTT32A04BCAP1_IRQHandler
INTT32A04C_IRQHandler
INTT32A04CCAP0_IRQHandler
INTT32A04CCAP1_IRQHandler
INTT32A05A_IRQHandler
INTT32A05ACAP0_IRQHandler
INTT32A05ACAP1_IRQHandler
INTT32A05B_IRQHandler
INTT32A05BCAP0_IRQHandler
INTT32A05BCAP1_IRQHandler
INTT32A05C_IRQHandler
INTT32A05CCAP0_IRQHandler
INTT32A05CCAP1_IRQHandler
INTDMAATC_IRQHandler
INTDMAAERR_IRQHandler
INTRTC_IRQHandler
INTRMC0_IRQHandler
INTFLCRDY_IRQHandler
INTFLDRDY_IRQHandler
B .
ENDP
END

40
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct
View File

@ -1,40 +0,0 @@
#! armcc -E
;; TMPM3H6FWFG scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 0x00000000 0x20000
{
ER_IROM1 0x00000000 0x20000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218
RW_IRAM1 (0x20000000 + 0x218) (0x4000 - 0x218 - Stack_Size)
{
.ANY (+RW, +ZI)
}
ARM_LIB_STACK (0x20000000+0x4000) EMPTY -Stack_Size { ; stack
}
}

483
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S
View File

@ -1,483 +0,0 @@
/**
*******************************************************************************
* @file startup_TMPM3H6.s
* @brief CMSIS Cortex-M3 Core Device Startup File for the
* TOSHIBA 'TMPM3H6' Device Series
* @version V5.00
* @date 2016/03/02
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long INT00_IRQHandler // 0: Interrupt Pin0
.long INT01_IRQHandler // 1: Interrupt Pin1
.long INT02_IRQHandler // 2: Interrupt Pin2
.long INT03_IRQHandler // 3: Interrupt Pin3
.long INT04_IRQHandler // 4: Interrupt Pin4
.long INT05_IRQHandler // 5: Interrupt Pin5
.long INT06_IRQHandler // 6: Interrupt Pin6
.long INT07_IRQHandler // 7: Interrupt Pin7
.long INT08_IRQHandler // 8: Interrupt Pin8
.long INT09_IRQHandler // 9: Interrupt Pin9
.long INT10_IRQHandler // 10: Interrupt Pin10
.long INT11_IRQHandler // 11: Interrupt Pin11
.long INT12_IRQHandler // 12: Interrupt Pin12
.long INT13_IRQHandler // 13: Interrupt Pin13
.long INT14_IRQHandler // 14: Interrupt Pin14
.long INT15_IRQHandler // 15: Interrupt Pin15
.long INTEMG0_IRQHandler // 16: PMD0 EMG interrupt
.long INTOVV0_IRQHandler // 17: PMD0 OVV interrupt
.long INTPMD0_IRQHandler // 18: PMD0 interrupt
.long INTENC00_IRQHandler // 19: Encoder 0 interrupt 0
.long INTENC01_IRQHandler // 20: Encoder 0 interrupt 1
.long INTADAPDA_IRQHandler // 21: ADC conversion triggered by PMD is finished A
.long INTADAPDB_IRQHandler // 22: ADC conversion triggered by PMD is finished B
.long INTADACP0_IRQHandler // 23: ADC conversion monitoring function interrupt A
.long INTADACP1_IRQHandler // 24: ADC conversion monitoring function interrupt B
.long INTADATRG_IRQHandler // 25: ADC conversion triggered by General purpose is finished
.long INTADASGL_IRQHandler // 26: ADC conversion triggered by Single program is finished
.long INTADACNT_IRQHandler // 27: ADC conversion triggered by Continuity program is finished
.long INTT0RX_IRQHandler // 28: TSPI/SIO reception (channel 0)
.long INTT0TX_IRQHandler // 29: TSPI/SIO transmit (channel 0)
.long INTT0ERR_IRQHandler // 30: TSPI/SIO error (channel 0)
.long INTT1RX_IRQHandler // 31: TSPI/SIO reception (channel 1)
.long INTT1TX_IRQHandler // 32: TSPI/SIO transmit (channel 1)
.long INTT1ERR_IRQHandler // 33: TSPI/SIO error (channel 1)
.long INTI2CWUP_IRQHandler // 34: Serial bus interface (WakeUp) interrupt (channel 0)
.long INTI2C0_IRQHandler // 35: I2C0 transmission and reception interrupt
.long INTI2C0AL_IRQHandler // 36: I2C0 arbitration lost interrupt
.long INTI2C0BF_IRQHandler // 37: I2C0 bus free interrupt
.long INTI2C0NA_IRQHandler // 38: I2C0 no ack interrupt
.long INTI2C1_IRQHandler // 39: I2C1 transmission and reception interrupt
.long INTI2C1AL_IRQHandler // 40: I2C1 arbitration lost interrupt
.long INTI2C1BF_IRQHandler // 41: I2C1 bus free interrupt
.long INTI2C1NA_IRQHandler // 42: I2C1 no ack interrupt
.long INTI2C2_IRQHandler // 43: I2C2 transmission and reception interrupt
.long INTI2C2AL_IRQHandler // 44: I2C2 arbitration lost interrupt
.long INTI2C2BF_IRQHandler // 45: I2C2 bus free interrupt
.long INTI2C2NA_IRQHandler // 46: I2C2 no ack interrupt
.long INTUART0RX_IRQHandler // 47: UART reception (channel 0)
.long INTUART0TX_IRQHandler // 48: UART transmit (channel 0)
.long INTUART0ERR_IRQHandler // 49: UART error (channel 0)
.long INTUART1RX_IRQHandler // 50: UART reception (channel 1)
.long INTUART1TX_IRQHandler // 51: UART transmit (channel 1)
.long INTUART1ERR_IRQHandler // 52: UART error (channel 1)
.long INTUART2RX_IRQHandler // 53: UART reception (channel 2)
.long INTUART2TX_IRQHandler // 54: UART transmit (channel 2)
.long INTUART2ERR_IRQHandler // 55: UART error (channel 2)
.long INTT32A00A_IRQHandler // 56: 32bit T32A0A compare match detection 0 / Over flow / under flow
.long INTT32A00ACAP0_IRQHandler // 57: 32bit T32A0A input capture 0
.long INTT32A00ACAP1_IRQHandler // 58: 32bit T32A0A input capture 1
.long INTT32A00B_IRQHandler // 59: 32bit T32A0B compare match detection 0 / Over flow / under flow
.long INTT32A00BCAP0_IRQHandler // 60: 32bit T32A0B input capture 0
.long INTT32A00BCAP1_IRQHandler // 61: 32bit T32A0B input capture 1
.long INTT32A00C_IRQHandler // 62: 32bit T32A0C compare match detection 0 / Over flow / under flow
.long INTT32A00CCAP0_IRQHandler // 63: 32bit T32A0C input capture 0
.long INTT32A00CCAP1_IRQHandler // 64: 32bit T32A0C input capture 1
.long INTT32A01A_IRQHandler // 65: 32bit T32A1A compare match detection 0 / Over flow / under flow
.long INTT32A01ACAP0_IRQHandler // 66: 32bit T32A1A input capture 0
.long INTT32A01ACAP1_IRQHandler // 67: 32bit T32A1A input capture 1
.long INTT32A01B_IRQHandler // 68: 32bit T32A1B compare match detection 0 / Over flow / under flow
.long INTT32A01BCAP0_IRQHandler // 69: 32bit T32A1B input capture 0
.long INTT32A01BCAP1_IRQHandler // 70: 32bit T32A1B input capture 1
.long INTT32A01C_IRQHandler // 71: 32bit T32A1C compare match detection 0 / Over flow / under flow
.long INTT32A01CCAP0_IRQHandler // 72: 32bit T32A1C input capture 0
.long INTT32A01CCAP1_IRQHandler // 73: 32bit T32A1C input capture 1
.long INTT32A02A_IRQHandler // 74: 32bit T32A2A compare match detection 0 / Over flow / under flow
.long INTT32A02ACAP0_IRQHandler // 75: 32bit T32A2A input capture 0
.long INTT32A02ACAP1_IRQHandler // 76: 32bit T32A2A input capture 1
.long INTT32A02B_IRQHandler // 77: 32bit T32A2B compare match detection 0 / Over flow / under flow
.long INTT32A02BCAP0_IRQHandler // 78: 32bit T32A2B input capture 0
.long INTT32A02BCAP1_IRQHandler // 79: 32bit T32A2B input capture 1
.long INTT32A02C_IRQHandler // 80: 32bit T32A2C compare match detection 0 / Over flow / under flow
.long INTT32A02CCAP0_IRQHandler // 81: 32bit T32A2C input capture 0
.long INTT32A02CCAP1_IRQHandler // 82: 32bit T32A2C input capture 1
.long INTT32A03A_IRQHandler // 83: 32bit T32A3A compare match detection 0 / Over flow / under flow
.long INTT32A03ACAP0_IRQHandler // 84: 32bit T32A3A input capture 0
.long INTT32A03ACAP1_IRQHandler // 85: 32bit T32A3A input capture 1
.long INTT32A03B_IRQHandler // 86: 32bit T32A3B compare match detection 0 / Over flow / under flow
.long INTT32A03BCAP0_IRQHandler // 87: 32bit T32A3B input capture 0
.long INTT32A03BCAP1_IRQHandler // 88: 32bit T32A3B input capture 1
.long INTT32A03C_IRQHandler // 89: 32bit T32A3C compare match detection 0 / Over flow / under flow
.long INTT32A03CCAP0_IRQHandler // 90: 32bit T32A3C input capture 0
.long INTT32A03CCAP1_IRQHandler // 91: 32bit T32A3C input capture 1
.long INTT32A04A_IRQHandler // 92: 32bit T32A4A compare match detection 0 / Over flow / under flow
.long INTT32A04ACAP0_IRQHandler // 93: 32bit T32A4A input capture 0
.long INTT32A04ACAP1_IRQHandler // 94: 32bit T32A4A input capture 1
.long INTT32A04B_IRQHandler // 95: 32bit T32A4B compare match detection 0 / Over flow / under flow
.long INTT32A04BCAP0_IRQHandler // 96: 32bit T32A4B input capture 0
.long INTT32A04BCAP1_IRQHandler // 97: 32bit T32A4B input capture 1
.long INTT32A04C_IRQHandler // 98: 32bit T32A4C compare match detection 0 / Over flow / under flow
.long INTT32A04CCAP0_IRQHandler // 99: 32bit T32A4C input capture 0
.long INTT32A04CCAP1_IRQHandler // 100: 32bit T32A4C input capture 1
.long INTT32A05A_IRQHandler // 101: 32bit T32A5A compare match detection 0 / Over flow / under flow
.long INTT32A05ACAP0_IRQHandler // 102: 32bit T32A5A input capture 0
.long INTT32A05ACAP1_IRQHandler // 103: 32bit T32A5A input capture 1
.long INTT32A05B_IRQHandler // 104: 32bit T32A5B compare match detection 0 / Over flow / under flow
.long INTT32A05BCAP0_IRQHandler // 105: 32bit T32A5B input capture 0
.long INTT32A05BCAP1_IRQHandler // 106: 32bit T32A5B input capture 1
.long INTT32A05C_IRQHandler // 107: 32bit T32A5C compare match detection 0 / Over flow / under flow
.long INTT32A05CCAP0_IRQHandler // 108: 32bit T32A5C input capture 0
.long INTT32A05CCAP1_IRQHandler // 109: 32bit T32A5C input capture 1
.long INTDMAATC_IRQHandler // 110: DMA end of transfer
.long INTDMAAERR_IRQHandler // 111: DMA transfer error
.long INTRTC_IRQHandler // 112: Real time clock(XHz) interrupt
.long 0 // 113: Reserved
.long INTRMC0_IRQHandler // 114: Remote control reception interrupt
.long INTFLCRDY_IRQHandler // 115: Code FLASH Ready interrupt
.long INTFLDRDY_IRQHandler // 116: Data FLASH Ready interrupt
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT00_IRQHandler
def_irq_handler INT01_IRQHandler
def_irq_handler INT02_IRQHandler
def_irq_handler INT03_IRQHandler
def_irq_handler INT04_IRQHandler
def_irq_handler INT05_IRQHandler
def_irq_handler INT06_IRQHandler
def_irq_handler INT07_IRQHandler
def_irq_handler INT08_IRQHandler
def_irq_handler INT09_IRQHandler
def_irq_handler INT10_IRQHandler
def_irq_handler INT11_IRQHandler
def_irq_handler INT12_IRQHandler
def_irq_handler INT13_IRQHandler
def_irq_handler INT14_IRQHandler
def_irq_handler INT15_IRQHandler
def_irq_handler INTEMG0_IRQHandler
def_irq_handler INTOVV0_IRQHandler
def_irq_handler INTPMD0_IRQHandler
def_irq_handler INTENC00_IRQHandler
def_irq_handler INTENC01_IRQHandler
def_irq_handler INTADAPDA_IRQHandler
def_irq_handler INTADAPDB_IRQHandler
def_irq_handler INTADACP0_IRQHandler
def_irq_handler INTADACP1_IRQHandler
def_irq_handler INTADATRG_IRQHandler
def_irq_handler INTADASGL_IRQHandler
def_irq_handler INTADACNT_IRQHandler
def_irq_handler INTT0RX_IRQHandler
def_irq_handler INTT0TX_IRQHandler
def_irq_handler INTT0ERR_IRQHandler
def_irq_handler INTT1RX_IRQHandler
def_irq_handler INTT1TX_IRQHandler
def_irq_handler INTT1ERR_IRQHandler
def_irq_handler INTI2CWUP_IRQHandler
def_irq_handler INTI2C0_IRQHandler
def_irq_handler INTI2C0AL_IRQHandler
def_irq_handler INTI2C0BF_IRQHandler
def_irq_handler INTI2C0NA_IRQHandler
def_irq_handler INTI2C1_IRQHandler
def_irq_handler INTI2C1AL_IRQHandler
def_irq_handler INTI2C1BF_IRQHandler
def_irq_handler INTI2C1NA_IRQHandler
def_irq_handler INTI2C2_IRQHandler
def_irq_handler INTI2C2AL_IRQHandler
def_irq_handler INTI2C2BF_IRQHandler
def_irq_handler INTI2C2NA_IRQHandler
def_irq_handler INTUART0RX_IRQHandler
def_irq_handler INTUART0TX_IRQHandler
def_irq_handler INTUART0ERR_IRQHandler
def_irq_handler INTUART1RX_IRQHandler
def_irq_handler INTUART1TX_IRQHandler
def_irq_handler INTUART1ERR_IRQHandler
def_irq_handler INTUART2RX_IRQHandler
def_irq_handler INTUART2TX_IRQHandler
def_irq_handler INTUART2ERR_IRQHandler
def_irq_handler INTT32A00A_IRQHandler
def_irq_handler INTT32A00ACAP0_IRQHandler
def_irq_handler INTT32A00ACAP1_IRQHandler
def_irq_handler INTT32A00B_IRQHandler
def_irq_handler INTT32A00BCAP0_IRQHandler
def_irq_handler INTT32A00BCAP1_IRQHandler
def_irq_handler INTT32A00C_IRQHandler
def_irq_handler INTT32A00CCAP0_IRQHandler
def_irq_handler INTT32A00CCAP1_IRQHandler
def_irq_handler INTT32A01A_IRQHandler
def_irq_handler INTT32A01ACAP0_IRQHandler
def_irq_handler INTT32A01ACAP1_IRQHandler
def_irq_handler INTT32A01B_IRQHandler
def_irq_handler INTT32A01BCAP0_IRQHandler
def_irq_handler INTT32A01BCAP1_IRQHandler
def_irq_handler INTT32A01C_IRQHandler
def_irq_handler INTT32A01CCAP0_IRQHandler
def_irq_handler INTT32A01CCAP1_IRQHandler
def_irq_handler INTT32A02A_IRQHandler
def_irq_handler INTT32A02ACAP0_IRQHandler
def_irq_handler INTT32A02ACAP1_IRQHandler
def_irq_handler INTT32A02B_IRQHandler
def_irq_handler INTT32A02BCAP0_IRQHandler
def_irq_handler INTT32A02BCAP1_IRQHandler
def_irq_handler INTT32A02C_IRQHandler
def_irq_handler INTT32A02CCAP0_IRQHandler
def_irq_handler INTT32A02CCAP1_IRQHandler
def_irq_handler INTT32A03A_IRQHandler
def_irq_handler INTT32A03ACAP0_IRQHandler
def_irq_handler INTT32A03ACAP1_IRQHandler
def_irq_handler INTT32A03B_IRQHandler
def_irq_handler INTT32A03BCAP0_IRQHandler
def_irq_handler INTT32A03BCAP1_IRQHandler
def_irq_handler INTT32A03C_IRQHandler
def_irq_handler INTT32A03CCAP0_IRQHandler
def_irq_handler INTT32A03CCAP1_IRQHandler
def_irq_handler INTT32A04A_IRQHandler
def_irq_handler INTT32A04ACAP0_IRQHandler
def_irq_handler INTT32A04ACAP1_IRQHandler
def_irq_handler INTT32A04B_IRQHandler
def_irq_handler INTT32A04BCAP0_IRQHandler
def_irq_handler INTT32A04BCAP1_IRQHandler
def_irq_handler INTT32A04C_IRQHandler
def_irq_handler INTT32A04CCAP0_IRQHandler
def_irq_handler INTT32A04CCAP1_IRQHandler
def_irq_handler INTT32A05A_IRQHandler
def_irq_handler INTT32A05ACAP0_IRQHandler
def_irq_handler INTT32A05ACAP1_IRQHandler
def_irq_handler INTT32A05B_IRQHandler
def_irq_handler INTT32A05BCAP0_IRQHandler
def_irq_handler INTT32A05BCAP1_IRQHandler
def_irq_handler INTT32A05C_IRQHandler
def_irq_handler INTT32A05CCAP0_IRQHandler
def_irq_handler INTT32A05CCAP1_IRQHandler
def_irq_handler INTDMAATC_IRQHandler
def_irq_handler INTDMAAERR_IRQHandler
def_irq_handler INTRTC_IRQHandler
def_irq_handler INTRMC0_IRQHandler
def_irq_handler INTFLCRDY_IRQHandler
def_irq_handler INTFLDRDY_IRQHandler
.end

169
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld
View File

@ -1,169 +0,0 @@
/* Linker script for Toshiba TMPM3H6 */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
/* 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218 */
RAM (rwx) : ORIGIN = (0x20000000 + 0x218), LENGTH = (16K - 0x218)
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(8);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

808
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S
View File

@ -1,808 +0,0 @@
;/**
; *******************************************************************************
; * @file startup_TMPM3H6.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for the
; * TOSHIBA 'TMPM3H6' Device Series
; * @version V1.0.0.0
; * $Date:: #$
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
; *
; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt Pin0
DCD INT01_IRQHandler ; 1: Interrupt Pin1
DCD INT02_IRQHandler ; 2: Interrupt Pin2
DCD INT03_IRQHandler ; 3: Interrupt Pin3
DCD INT04_IRQHandler ; 4: Interrupt Pin4
DCD INT05_IRQHandler ; 5: Interrupt Pin5
DCD INT06_IRQHandler ; 6: Interrupt Pin6
DCD INT07_IRQHandler ; 7: Interrupt Pin7
DCD INT08_IRQHandler ; 8: Interrupt Pin8
DCD INT09_IRQHandler ; 9: Interrupt Pin9
DCD INT10_IRQHandler ; 10: Interrupt Pin10
DCD INT11_IRQHandler ; 11: Interrupt Pin11
DCD INT12_IRQHandler ; 12: Interrupt Pin12
DCD INT13_IRQHandler ; 13: Interrupt Pin13
DCD INT14_IRQHandler ; 14: Interrupt Pin14
DCD INT15_IRQHandler ; 15: Interrupt Pin15
DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt
DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt
DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt
DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0
DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1
DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A
DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B
DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0
DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1
DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished
DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished
DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished
DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0)
DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0)
DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0)
DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1)
DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1)
DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1)
DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0)
DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt
DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt
DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt
DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt
DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt
DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt
DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt
DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt
DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt
DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt
DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt
DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt
DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0)
DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0)
DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0)
DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1)
DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1)
DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1)
DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2)
DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2)
DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2)
DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow
DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0
DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1
DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow
DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0
DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1
DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow
DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0
DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1
DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow
DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0
DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1
DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow
DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0
DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1
DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow
DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0
DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1
DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow
DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0
DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1
DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow
DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0
DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1
DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow
DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0
DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1
DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow
DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0
DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1
DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow
DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0
DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1
DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow
DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0
DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1
DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow
DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0
DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1
DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow
DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0
DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1
DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow
DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0
DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1
DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow
DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0
DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1
DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow
DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0
DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1
DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow
DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0
DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1
DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer
DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error
DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt
DCD 0 ; 113: Reserved
DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt
DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt
DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK INT00_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT00_IRQHandler
B INT00_IRQHandler
PUBWEAK INT01_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT01_IRQHandler
B INT01_IRQHandler
PUBWEAK INT02_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT02_IRQHandler
B INT02_IRQHandler
PUBWEAK INT03_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT03_IRQHandler
B INT03_IRQHandler
PUBWEAK INT04_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT04_IRQHandler
B INT04_IRQHandler
PUBWEAK INT05_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT05_IRQHandler
B INT05_IRQHandler
PUBWEAK INT06_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT06_IRQHandler
B INT06_IRQHandler
PUBWEAK INT07_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT07_IRQHandler
B INT07_IRQHandler
PUBWEAK INT08_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT08_IRQHandler
B INT08_IRQHandler
PUBWEAK INT09_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT09_IRQHandler
B INT09_IRQHandler
PUBWEAK INT10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT10_IRQHandler
B INT10_IRQHandler
PUBWEAK INT11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT11_IRQHandler
B INT11_IRQHandler
PUBWEAK INT12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT12_IRQHandler
B INT12_IRQHandler
PUBWEAK INT13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT13_IRQHandler
B INT13_IRQHandler
PUBWEAK INT14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT14_IRQHandler
B INT14_IRQHandler
PUBWEAK INT15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INT15_IRQHandler
B INT15_IRQHandler
PUBWEAK INTEMG0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTEMG0_IRQHandler
B INTEMG0_IRQHandler
PUBWEAK INTOVV0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTOVV0_IRQHandler
B INTOVV0_IRQHandler
PUBWEAK INTPMD0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTPMD0_IRQHandler
B INTPMD0_IRQHandler
PUBWEAK INTENC00_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTENC00_IRQHandler
B INTENC00_IRQHandler
PUBWEAK INTENC01_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTENC01_IRQHandler
B INTENC01_IRQHandler
PUBWEAK INTADAPDA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADAPDA_IRQHandler
B INTADAPDA_IRQHandler
PUBWEAK INTADAPDB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADAPDB_IRQHandler
B INTADAPDB_IRQHandler
PUBWEAK INTADACP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADACP0_IRQHandler
B INTADACP0_IRQHandler
PUBWEAK INTADACP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADACP1_IRQHandler
B INTADACP1_IRQHandler
PUBWEAK INTADATRG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADATRG_IRQHandler
B INTADATRG_IRQHandler
PUBWEAK INTADASGL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADASGL_IRQHandler
B INTADASGL_IRQHandler
PUBWEAK INTADACNT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTADACNT_IRQHandler
B INTADACNT_IRQHandler
PUBWEAK INTT0RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT0RX_IRQHandler
B INTT0RX_IRQHandler
PUBWEAK INTT0TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT0TX_IRQHandler
B INTT0TX_IRQHandler
PUBWEAK INTT0ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT0ERR_IRQHandler
B INTT0ERR_IRQHandler
PUBWEAK INTT1RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT1RX_IRQHandler
B INTT1RX_IRQHandler
PUBWEAK INTT1TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT1TX_IRQHandler
B INTT1TX_IRQHandler
PUBWEAK INTT1ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT1ERR_IRQHandler
B INTT1ERR_IRQHandler
PUBWEAK INTI2CWUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2CWUP_IRQHandler
B INTI2CWUP_IRQHandler
PUBWEAK INTI2C0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C0_IRQHandler
B INTI2C0_IRQHandler
PUBWEAK INTI2C0AL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C0AL_IRQHandler
B INTI2C0AL_IRQHandler
PUBWEAK INTI2C0BF_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C0BF_IRQHandler
B INTI2C0BF_IRQHandler
PUBWEAK INTI2C0NA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C0NA_IRQHandler
B INTI2C0NA_IRQHandler
PUBWEAK INTI2C1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C1_IRQHandler
B INTI2C1_IRQHandler
PUBWEAK INTI2C1AL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C1AL_IRQHandler
B INTI2C1AL_IRQHandler
PUBWEAK INTI2C1BF_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C1BF_IRQHandler
B INTI2C1BF_IRQHandler
PUBWEAK INTI2C1NA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C1NA_IRQHandler
B INTI2C1NA_IRQHandler
PUBWEAK INTI2C2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C2_IRQHandler
B INTI2C2_IRQHandler
PUBWEAK INTI2C2AL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C2AL_IRQHandler
B INTI2C2AL_IRQHandler
PUBWEAK INTI2C2BF_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C2BF_IRQHandler
B INTI2C2BF_IRQHandler
PUBWEAK INTI2C2NA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTI2C2NA_IRQHandler
B INTI2C2NA_IRQHandler
PUBWEAK INTUART0RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART0RX_IRQHandler
B INTUART0RX_IRQHandler
PUBWEAK INTUART0TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART0TX_IRQHandler
B INTUART0TX_IRQHandler
PUBWEAK INTUART0ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART0ERR_IRQHandler
B INTUART0ERR_IRQHandler
PUBWEAK INTUART1RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART1RX_IRQHandler
B INTUART1RX_IRQHandler
PUBWEAK INTUART1TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART1TX_IRQHandler
B INTUART1TX_IRQHandler
PUBWEAK INTUART1ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART1ERR_IRQHandler
B INTUART1ERR_IRQHandler
PUBWEAK INTUART2RX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART2RX_IRQHandler
B INTUART2RX_IRQHandler
PUBWEAK INTUART2TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART2TX_IRQHandler
B INTUART2TX_IRQHandler
PUBWEAK INTUART2ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTUART2ERR_IRQHandler
B INTUART2ERR_IRQHandler
PUBWEAK INTT32A00A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00A_IRQHandler
B INTT32A00A_IRQHandler
PUBWEAK INTT32A00ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00ACAP0_IRQHandler
B INTT32A00ACAP0_IRQHandler
PUBWEAK INTT32A00ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00ACAP1_IRQHandler
B INTT32A00ACAP1_IRQHandler
PUBWEAK INTT32A00B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00B_IRQHandler
B INTT32A00B_IRQHandler
PUBWEAK INTT32A00BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00BCAP0_IRQHandler
B INTT32A00BCAP0_IRQHandler
PUBWEAK INTT32A00BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00BCAP1_IRQHandler
B INTT32A00BCAP1_IRQHandler
PUBWEAK INTT32A00C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00C_IRQHandler
B INTT32A00C_IRQHandler
PUBWEAK INTT32A00CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00CCAP0_IRQHandler
B INTT32A00CCAP0_IRQHandler
PUBWEAK INTT32A00CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A00CCAP1_IRQHandler
B INTT32A00CCAP1_IRQHandler
PUBWEAK INTT32A01A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01A_IRQHandler
B INTT32A01A_IRQHandler
PUBWEAK INTT32A01ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01ACAP0_IRQHandler
B INTT32A01ACAP0_IRQHandler
PUBWEAK INTT32A01ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01ACAP1_IRQHandler
B INTT32A01ACAP1_IRQHandler
PUBWEAK INTT32A01B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01B_IRQHandler
B INTT32A01B_IRQHandler
PUBWEAK INTT32A01BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01BCAP0_IRQHandler
B INTT32A01BCAP0_IRQHandler
PUBWEAK INTT32A01BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01BCAP1_IRQHandler
B INTT32A01BCAP1_IRQHandler
PUBWEAK INTT32A01C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01C_IRQHandler
B INTT32A01C_IRQHandler
PUBWEAK INTT32A01CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01CCAP0_IRQHandler
B INTT32A01CCAP0_IRQHandler
PUBWEAK INTT32A01CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A01CCAP1_IRQHandler
B INTT32A01CCAP1_IRQHandler
PUBWEAK INTT32A02A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02A_IRQHandler
B INTT32A02A_IRQHandler
PUBWEAK INTT32A02ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02ACAP0_IRQHandler
B INTT32A02ACAP0_IRQHandler
PUBWEAK INTT32A02ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02ACAP1_IRQHandler
B INTT32A02ACAP1_IRQHandler
PUBWEAK INTT32A02B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02B_IRQHandler
B INTT32A02B_IRQHandler
PUBWEAK INTT32A02BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02BCAP0_IRQHandler
B INTT32A02BCAP0_IRQHandler
PUBWEAK INTT32A02BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02BCAP1_IRQHandler
B INTT32A02BCAP1_IRQHandler
PUBWEAK INTT32A02C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02C_IRQHandler
B INTT32A02C_IRQHandler
PUBWEAK INTT32A02CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02CCAP0_IRQHandler
B INTT32A02CCAP0_IRQHandler
PUBWEAK INTT32A02CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A02CCAP1_IRQHandler
B INTT32A02CCAP1_IRQHandler
PUBWEAK INTT32A03A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03A_IRQHandler
B INTT32A03A_IRQHandler
PUBWEAK INTT32A03ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03ACAP0_IRQHandler
B INTT32A03ACAP0_IRQHandler
PUBWEAK INTT32A03ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03ACAP1_IRQHandler
B INTT32A03ACAP1_IRQHandler
PUBWEAK INTT32A03B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03B_IRQHandler
B INTT32A03B_IRQHandler
PUBWEAK INTT32A03BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03BCAP0_IRQHandler
B INTT32A03BCAP0_IRQHandler
PUBWEAK INTT32A03BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03BCAP1_IRQHandler
B INTT32A03BCAP1_IRQHandler
PUBWEAK INTT32A03C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03C_IRQHandler
B INTT32A03C_IRQHandler
PUBWEAK INTT32A03CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03CCAP0_IRQHandler
B INTT32A03CCAP0_IRQHandler
PUBWEAK INTT32A03CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A03CCAP1_IRQHandler
B INTT32A03CCAP1_IRQHandler
PUBWEAK INTT32A04A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04A_IRQHandler
B INTT32A04A_IRQHandler
PUBWEAK INTT32A04ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04ACAP0_IRQHandler
B INTT32A04ACAP0_IRQHandler
PUBWEAK INTT32A04ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04ACAP1_IRQHandler
B INTT32A04ACAP1_IRQHandler
PUBWEAK INTT32A04B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04B_IRQHandler
B INTT32A04B_IRQHandler
PUBWEAK INTT32A04BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04BCAP0_IRQHandler
B INTT32A04BCAP0_IRQHandler
PUBWEAK INTT32A04BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04BCAP1_IRQHandler
B INTT32A04BCAP1_IRQHandler
PUBWEAK INTT32A04C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04C_IRQHandler
B INTT32A04C_IRQHandler
PUBWEAK INTT32A04CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04CCAP0_IRQHandler
B INTT32A04CCAP0_IRQHandler
PUBWEAK INTT32A04CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A04CCAP1_IRQHandler
B INTT32A04CCAP1_IRQHandler
PUBWEAK INTT32A05A_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05A_IRQHandler
B INTT32A05A_IRQHandler
PUBWEAK INTT32A05ACAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05ACAP0_IRQHandler
B INTT32A05ACAP0_IRQHandler
PUBWEAK INTT32A05ACAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05ACAP1_IRQHandler
B INTT32A05ACAP1_IRQHandler
PUBWEAK INTT32A05B_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05B_IRQHandler
B INTT32A05B_IRQHandler
PUBWEAK INTT32A05BCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05BCAP0_IRQHandler
B INTT32A05BCAP0_IRQHandler
PUBWEAK INTT32A05BCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05BCAP1_IRQHandler
B INTT32A05BCAP1_IRQHandler
PUBWEAK INTT32A05C_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05C_IRQHandler
B INTT32A05C_IRQHandler
PUBWEAK INTT32A05CCAP0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05CCAP0_IRQHandler
B INTT32A05CCAP0_IRQHandler
PUBWEAK INTT32A05CCAP1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTT32A05CCAP1_IRQHandler
B INTT32A05CCAP1_IRQHandler
PUBWEAK INTDMAATC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTDMAATC_IRQHandler
B INTDMAATC_IRQHandler
PUBWEAK INTDMAAERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTDMAAERR_IRQHandler
B INTDMAAERR_IRQHandler
PUBWEAK INTRTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTRTC_IRQHandler
B INTRTC_IRQHandler
PUBWEAK INTRMC0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTRMC0_IRQHandler
B INTRMC0_IRQHandler
PUBWEAK INTFLCRDY_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTFLCRDY_IRQHandler
B INTFLCRDY_IRQHandler
PUBWEAK INTFLDRDY_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
INTFLDRDY_IRQHandler
B INTFLDRDY_IRQHandler
END

43
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf
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@ -1,43 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000218; /* 8_byte_aligned(117 + 16 vect * 4 bytes) */
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0xC00;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define symbol __BRAM_start__ = 0x20004000;
define symbol __BRAM_end__ = 0x200047FF;
define symbol __DFLASH_start__ = 0x30000000;
define symbol __DFLASH_end__ = 0x30007FFF;
define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ];
define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in BRAM_region { section .backup_ram };
place in DFLASH_region { section .data_flash };

13
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS for TMPM3H6
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in TMPM3Hx specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM3H6.h"
#include "cmsis_nvic.h"
#endif

15
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h
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@ -1,15 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic for TMPM3H6
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000
#define NVIC_USER_IRQ_NUMBER 117
#define NVIC_NUM_VECTORS (16 + 117) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

311
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c
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@ -1,311 +0,0 @@
/**
*******************************************************************************
* @file system_TMPM3Hx.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM3Hx' Device Series
* @version V1.0.7.0
* $Date:: 2017-11-06 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
#include "TMPM3H6.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
#define SYSCR_Val (0x00000000UL)
#define STBYCR_Val (0x00000000UL)
#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */
#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */
#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */
#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */
#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001)
#if (CLOCK_SETUP)
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
#define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL
#else
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000)
#define PLL0SEL_Ready CG_10M_MUL_4_FPLL
#endif
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
#define PLL0SEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define EOSC_6M (6000000UL)
#define EOSC_8M (8000000UL)
#define EOSC_10M (10000000UL)
#define EOSC_12M (12000000UL)
#define IOSC_10M (10000000UL)
#define EXTALH EOSC_12M /* External high-speed oscillator freq */
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
#define EOSC_6M_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
#define EOSC_8M_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
#define EOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
#define EOSC_12M_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
#define IOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
#if (CLOCK_SETUP)
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#else
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#endif
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (CLOCK_SETUP)
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (IXTALH)
#endif
#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL))
#define __CORE_CLK EOSC_6M_PLLON /* output clock is 39.98MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 6MHz */
#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL))
#define __CORE_CLK EOSC_8M_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK EOSC_10M_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL)
#define __CORE_CLK EOSC_12M_PLLON /* output clock is 39.94MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK IOSC_10M_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U )
#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{ /* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t CoreClockInput = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pll0sel = 0U;
uint32_t pll0on = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = IXTALH;
}
regval = TSB_CG->PLL0SEL;
pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
if (pll0sel && pll0on) { /* If PLL enabled */
if (CoreClock == EOSC_6M) { /* If input is 6MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) {
CoreClockInput = EOSC_6M_PLLON; /* output clock is 39.98MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) {
CoreClockInput = EOSC_8M_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = EOSC_10M_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) {
CoreClockInput = EOSC_12M_PLLON; /* output clock is 39.94MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = IOSC_10M_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else { /* If PLL not used */
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U: /* Gear -> fc */
SystemCoreClock = CoreClockInput;
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
if (CoreClockInput >= EOSC_8M) {
SystemCoreClock = CoreClockInput / 8U;
} else {
SystemCoreClock = 0U;
}
break;
case 4U: /* Gear -> fc/16 */
if (CoreClockInput > EOSC_12M) {
SystemCoreClock = CoreClockInput / 16U;
} else {
SystemCoreClock = 0U;
}
break;
case 5U:
case 6U:
case 7U:
SystemCoreClock = 0U;
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
#if (SIWD_SETUP) /* Watchdog Setup */
/* SIWD Disable */
TSB_SIWD0->EN = SIWDEN_Val;
TSB_SIWD0->CR = SIWDCR_Val;
#else
/* SIWD Enable (Setting after a Reset) */
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = SYSCR_Val;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
while (!TSB_CG_OSCCR_OSCF) {
;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
#else
/* Internal HOSC Enable (Setting after a Reset) */
#endif
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLL0SEL_Ready;
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Lockup */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
while (!TSB_CG_PLL0SEL_PLL0ST) {
;
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h
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/**
*****************************************************************************
* @file system_TMPM3Hx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM3Hx' Device Series
* @version V1.0.1.0
* $Date:: 2017-06-23 13:52:12 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*****************************************************************************
*/
#include <stdint.h>
#ifndef __SYSTEM_TMPM3H6_H
#define __SYSTEM_TMPM3H6_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_include.h"
extern const PinMap PinMap_GPIO_IRQ[];
void gpio_init(gpio_t *obj, PinName pin)
{
// Store above pin mask, pin name into GPIO object
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->mask = gpio_set(pin);
obj->port = (PortName)(pin >> 3);
TSB_CG->FSYSENA |= (1 << (obj->port));
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
uint32_t gpio_set(PinName pin)
{
// Check that pin is valid
MBED_ASSERT(pin != (PinName)NC);
// Set pin function as GPIO pin
pin_function(pin, GPIO_DATA);
// Return pin mask
return (1 << (pin & 0x07));
}
// Set gpio object pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
// Set direction
switch (direction) {
case PIN_INPUT:
pin_function(obj->pin, PIN_INPUT);
break;
case PIN_OUTPUT:
pin_function(obj->pin, PIN_OUTPUT);
break;
case PIN_INOUT:
pin_function(obj->pin, PIN_INOUT);
break;
default:
error("Invalid direction\n");
break;
}
}
// Write gpio object pin data
void gpio_write(gpio_t *obj, int value)
{
int port = 0;
uint8_t bit = 0;
uint32_t base = 0;
// Calculate port and pin position
port = PIN_PORT(obj->pin);
bit = PIN_POS(obj->pin);
base = BITBAND_PORT_BASE(port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
if (value == GPIO_PIN_SET) {
BITBAND_PORT_SET(base, bit);
} else if (value == GPIO_PIN_RESET) {
BITBAND_PORT_CLR(base, bit);
} else {
error("Invalid value\n");
}
}
// Read gpio object pin data
int gpio_read(gpio_t *obj)
{
int port = 0;
uint8_t bit = 0;
uint32_t base = 0;
uint32_t val = 0;
int BitValue = 0;
// Calculate port and pin position
port = PIN_PORT(obj->pin);
bit = PIN_POS(obj->pin);
base = BITBAND_PORT_BASE(port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
BITBAND_PORT_READ(val, base, bit);
if (val == GPIO_PIN_RESET) {
BitValue = GPIO_PIN_RESET;
} else {
BitValue = GPIO_PIN_SET;
}
return (BitValue);
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __GPIO_INCLUDE_H
#define __GPIO_INCLUDE_H
#include <stdint.h>
#include <stdbool.h>
#include "TMPM3H6.h"
#include "objects.h"
#include "serial_api.h"
#include "txz_driver_def.h"
enum BitMode {
GPIO_PIN_RESET = 0,
GPIO_PIN_SET,
};
enum PortFunction {
GPIO_Mode_DATA = 0x0, // 0x0: PxDATA
GPIO_Mode_CR = 0x04, // 0x4: PxCR
GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1
GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2
GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3
GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4
GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5
GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6
GPIO_Mode_OD = 0x28, // 0x28: PxOD
GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP
GPIO_Mode_PDN = 0x30, // 0x30: PxPDN
GPIO_Mode_IE = 0x38 // 0x38: PxIE
};
// GPIO
#define PORT_BASE (0x400C0000UL) // Port Register Base Adress
#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value
#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress
#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress
#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set
#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear
#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read
#define GPIO_DATA PIN_DATA(0, 2)
#define CHANNEL_NUM 16
#define PORT_PIN_NUM 8
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF)
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0))
#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16)
#define PIN_DIR(X) ((X) & 0xFFFF)
// SPI
#define TIMEOUT 1000
#define INITIAL_SPI_FREQ 1000000
// I2C
#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080)
#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002)
#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001)
#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8)
#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8)
#define I2CxCR2_INIT ((uint32_t)0x00000008)
#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010)
#define I2CxCR2_TRX ((uint32_t)0x00000040)
#define I2CxST_I2C ((uint32_t)0x00000001)
#define I2CxST_CLEAR ((uint32_t)0x0000000F)
#define I2CxCR1_ACK ((uint32_t)0x00000010)
#define I2CxSR_BB ((uint32_t)0x00000020)
#define I2CxSR_LRB ((uint32_t)0x00000001)
#define I2CxOP_RSTA ((uint32_t)0x00000008)
#define I2CxOP_SREN ((uint32_t)0x00000002)
#define I2CxOP_MFACK ((uint32_t)0x00000001)
#define I2CxOP_INIT ((uint32_t)0x00000084)
#define I2CxIE_CLEAR ((uint32_t)0x00000000)
#define I2CxPRS_PRCK ((uint32_t)0x0000000F)
#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF)
#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084)
#define I2CAR_SA_MASK ((uint32_t)0x000000FE)
#define I2CxSR_TRX ((uint32_t)0x00000040)
#define I2CxOP_SAST ((uint32_t)0x00000020)
#define I2CxIE_INTI2C ((uint32_t)0x00000001)
#define I2C_NO_DATA (0)
#define I2C_READ_ADDRESSED (1)
#define I2C_WRITE_ADDRESSED (3)
#define I2C_ACK (1)
#define I2C_TIMEOUT (100000)
// DAC
#define DAC_START ((uint32_t)0x00000001)
#define DAC_STOP ((uint32_t)0x00000000)
// ADC
#define ADC_12BIT_RANGE 0xFFF
#define ADC_SCLK_1 ((uint32_t)0x00000000)
#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000)
#define ADxMOD0_DACON_ON ((uint32_t)0x00000001)
#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000)
#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040)
#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080)
#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002)
#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000)
#define ADxST_SNGF_IDLE ((uint32_t)0x00000000)
#define ADxST_SNGF_RUN ((uint32_t)0x00000004)
#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001)
#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001)
#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0)
// Timer & PWM
#define T32A_INT_MASK ((uint32_t)0x0000000F)
#define T32A_MODE_32 ((uint32_t)0x00000001)
#define T32A_PRSCLx_32 ((uint32_t)0x30000000)
#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008)
#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004)
#define T32A_COUNT_STOP ((uint32_t)0x00000004)
#define T32A_COUNT_START ((uint32_t)0x00000002)
#define T32A_RUN_ENABLE ((uint32_t)0x00000001)
#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002)
#define T32A_COUNT_DONT_START ((uint32_t)0x00000000)
#define T32A_RUN_DISABLE ((uint32_t)0x00000000)
#define T32A_WBF_ENABLE ((uint32_t)0x00100000)
#define T32A_RELOAD_TREGx ((uint32_t)0x00000700)
#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001)
#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008)
#define T32A_OCR_DISABLE ((uint32_t)0x00000000)
#define DEFAULT_PERIOD 0.02f // 20ms
#define DEFAULT_CLOCK_DIVISION 32
#define MAX_COUNTER_16B 0xFFFF
// UART
#define UART_ENABLE_RX ((uint32_t)0x00000001)
#define UART_ENABLE_TX ((uint32_t)0x00000002)
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
#define UART_PLESCALER_1 ((uint32_t)0x00000000)
#define UART_DIVISION_ENABLE ((uint32_t)0x00800000)
#define UART_TX_INT_ENABLE ((uint32_t)0x00000040)
#define UART_RX_INT_ENABLE ((uint32_t)0x00000010)
#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
#define UART_RANGE_K_MIN ((uint32_t)0x00000000)
#define UART_RANGE_K_MAX ((uint32_t)0x0000003F)
#define UART_RANGE_N_MIN ((uint32_t)0x00000001)
#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF)
#define UART_NUM 3
typedef struct {
uint32_t ken; // Enable/Disable Division Definition
uint32_t brk; // Division Value K
uint32_t brn; // Division Value N
} uart_boudrate_t;
// Sleep
#define CG_STBY_MODE_IDLE 0x0
#define CG_STBY_MODE_STOP1 0x1
#define EXTERNEL_OSC_MASK 0xFFFFFFF9
#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
#define IHOSC_CFG_CLOCK ((uint64_t)(10000000))
#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000)
#endif // __GPIO_INCLUDE_H

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "gpio_include.h"
#include "mbed_critical.h"
const PinMap PinMap_GPIO_IRQ[] = {
{PC0, GPIO_IRQ_0, PIN_DATA(0, 0)},
{PC1, GPIO_IRQ_1, PIN_DATA(0, 0)},
{PC2, GPIO_IRQ_2, PIN_DATA(0, 0)},
{PB1, GPIO_IRQ_3, PIN_DATA(0, 0)},
{PJ4, GPIO_IRQ_4, PIN_DATA(0, 0)},
{PK1, GPIO_IRQ_5, PIN_DATA(0, 0)},
{PH3, GPIO_IRQ_6, PIN_DATA(0, 0)},
{PA6, GPIO_IRQ_7, PIN_DATA(0, 0)},
{PL3, GPIO_IRQ_8, PIN_DATA(0, 0)},
{PM2, GPIO_IRQ_9, PIN_DATA(0, 0)},
{PN3, GPIO_IRQ_A, PIN_DATA(0, 0)},
{PA7, GPIO_IRQ_B, PIN_DATA(0, 0)},
{PL4, GPIO_IRQ_C, PIN_DATA(0, 0)},
{PK7, GPIO_IRQ_D, PIN_DATA(0, 0)},
{PP3, GPIO_IRQ_E, PIN_DATA(0, 0)},
{PM6, GPIO_IRQ_F, PIN_DATA(0, 0)},
{NC, NC, 0}
};
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState);
static cg_intactivestate CurrentState;
static void INT_IRQHandler(PinName pin, uint32_t index);
// Initialize gpio IRQ pin
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint8_t bit = 0;
uint32_t port_base = 0;
// Get gpio interrupt ID
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
// Disable interrupt by CPU
core_util_critical_section_enter();
// Calculate port and pin position
obj->port = (PortName)PIN_PORT(pin);
obj->pin = pin;
bit = PIN_POS(pin);
port_base = BITBAND_PORT_BASE(obj->port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
BITBAND_PORT_CLR(port_base, bit);
// Enable gpio interrupt function
pinmap_pinout(pin, PinMap_GPIO_IRQ);
// Get GPIO irq source
switch (obj->irq_id) {
case GPIO_IRQ_0:
obj->irq_src = cg_int_src_0;
break;
case GPIO_IRQ_1:
obj->irq_src = cg_int_src_1;
break;
case GPIO_IRQ_2:
obj->irq_src = cg_int_src_2;
break;
case GPIO_IRQ_3:
obj->irq_src = cg_int_src_3;
break;
case GPIO_IRQ_4:
obj->irq_src = cg_int_src_4;
break;
case GPIO_IRQ_5:
obj->irq_src = cg_int_src_5;
break;
case GPIO_IRQ_6:
obj->irq_src = cg_int_src_6;
break;
case GPIO_IRQ_7:
obj->irq_src = cg_int_src_7;
break;
case GPIO_IRQ_8:
obj->irq_src = cg_int_src_8;
break;
case GPIO_IRQ_9:
obj->irq_src = cg_int_src_9;
break;
case GPIO_IRQ_A:
obj->irq_src = cg_int_src_a;
break;
case GPIO_IRQ_B:
obj->irq_src = cg_int_src_b;
break;
case GPIO_IRQ_C:
obj->irq_src = cg_int_src_c;
break;
case GPIO_IRQ_D:
obj->irq_src = cg_int_src_d;
break;
case GPIO_IRQ_E:
obj->irq_src = cg_int_src_e;
break;
case GPIO_IRQ_F:
obj->irq_src = cg_int_src_f;
break;
default:
break;
}
// Save irq handler
hal_irq_handler[obj->irq_src] = handler;
// Save irq id
channel_ids[obj->irq_src] = id;
// Initialize interrupt event as both edges detection
obj->event = cg_int_active_state_both_edges;
CurrentState = cg_int_active_state_both_edges;
// Set interrupt event and enable INTx clear
SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE);
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id);
core_util_critical_section_exit();
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
// Clear gpio_irq
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Reset interrupt handler
hal_irq_handler[obj->irq_src] = NULL;
// Reset interrupt id
channel_ids[obj->irq_src] = 0;
}
// Set interrupt event of gpio_irq object
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
uint8_t bit = 0;
uint32_t port_base = 0;
//Disable GPIO interrupt on obj
gpio_irq_disable(obj);
if (enable) {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_both_edges)) {
obj->event = cg_int_active_state_both_edges;
} else {
obj->event = cg_int_active_state_rising;
}
} else if (event == IRQ_FALL) {
if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_both_edges)) {
obj->event = cg_int_active_state_both_edges;
} else {
obj->event = cg_int_active_state_falling;
}
} else {
error("Not supported event\n");
}
} else {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_invalid)) {
obj->event = cg_int_active_state_invalid;
} else {
obj->event = cg_int_active_state_falling;
}
} else if (event == IRQ_FALL) {
if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_invalid)) {
obj->event = cg_int_active_state_invalid;
} else {
obj->event = cg_int_active_state_rising;
}
} else {
error("Not supported event\n");
}
}
CurrentState = obj->event;
// Calculate port and pin position
bit = PIN_POS(obj->pin);
port_base = BITBAND_PORT_BASE(obj->port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
if (obj->event != cg_int_active_state_invalid ) {
// Set interrupt event and enable INTx clear
SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE);
BITBAND_PORT_CLR(port_base, bit);
} else {
BITBAND_PORT_SET(port_base, bit);
}
//Enable GPIO interrupt on obj
gpio_irq_enable(obj);
}
// Enable gpio_irq object
void gpio_irq_enable(gpio_irq_t *obj)
{
// Clear and Enable gpio_irq object
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
}
// Disable gpio_irq object
void gpio_irq_disable(gpio_irq_t *obj)
{
// Disable gpio_irq object
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
}
static void INT_IRQHandler(PinName pin, uint32_t index)
{
int port = 0;
uint8_t bit = 0;
uint32_t data = 0;
uint32_t port_base = 0;
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Clear interrupt request
SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, DISABLE);
port_base = BITBAND_PORT_BASE(port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
BITBAND_PORT_READ(data, port_base, bit);
switch (data) {
// Falling edge detection
case 0:
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
break;
// Rising edge detection
case 1:
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
break;
default:
break;
}
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)(cg_int_src_0 + index));
// Enable interrupt request
SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, ENABLE);
}
void INT00_IRQHandler(void)
{
INT_IRQHandler(PC0, 0);
}
void INT01_IRQHandler(void)
{
INT_IRQHandler(PC1, 1);
}
void INT02_IRQHandler(void)
{
INT_IRQHandler(PC2, 2);
}
void INT03_IRQHandler(void)
{
INT_IRQHandler(PB1, 3);
}
void INT04_IRQHandler(void)
{
INT_IRQHandler(PJ4, 4);
}
void INT05_IRQHandler(void)
{
INT_IRQHandler(PK1, 5);
}
void INT06_IRQHandler(void)
{
INT_IRQHandler(PH3, 6);
}
void INT07_IRQHandler(void)
{
INT_IRQHandler(PA6, 7);
}
void INT08_IRQHandler(void)
{
INT_IRQHandler(PL3, 8);
}
void INT09_IRQHandler(void)
{
INT_IRQHandler(PM2, 9);
}
void INT10_IRQHandler(void)
{
INT_IRQHandler(PN3, 10);
}
void INT11_IRQHandler(void)
{
INT_IRQHandler(PA7, 11);
}
void INT12_IRQHandler(void)
{
INT_IRQHandler(PL4, 12);
}
void INT13_IRQHandler(void)
{
INT_IRQHandler(PK7, 13);
}
void INT14_IRQHandler(void)
{
INT_IRQHandler(PP3, 14);
}
void INT15_IRQHandler(void)
{
INT_IRQHandler(PM6, 15);
}
static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState)
{
__IO uint8_t *p_imc;
if (intsource < 3U) {
p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource));
*p_imc = (uint8_t)(0xC0 | ActiveState | NewState);
} else {
intsource -= 3;
p_imc = (__IO uint8_t *)(&TSB_IB->IMC033 + (intsource));
*p_imc = (uint8_t)(0xC0 | ActiveState | NewState);
}
// Dummy read is need
{
__IO uint8_t imc = *p_imc;
}
}

81
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h
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@ -1,81 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_BIT_VALUE_1 ((uint8_t)0x01)
#define GPIO_BIT_VALUE_0 ((uint8_t)0x00)
#define GPIO_BIT_ALL ((uint8_t)0xFF)
typedef enum {
cg_int_src_0 = 0U,
cg_int_src_1,
cg_int_src_2,
cg_int_src_3,
cg_int_src_4,
cg_int_src_5,
cg_int_src_6,
cg_int_src_7,
cg_int_src_8,
cg_int_src_9,
cg_int_src_a,
cg_int_src_b,
cg_int_src_c,
cg_int_src_d,
cg_int_src_e,
cg_int_src_f
} cg_intsrc;
typedef enum {
cg_int_active_state_l = 0x00U,
cg_int_active_state_h = 0x02U,
cg_int_active_state_falling = 0x04U,
cg_int_active_state_rising = 0x06U,
cg_int_active_state_both_edges = 0x08U,
cg_int_active_state_invalid = 0x0AU
} cg_intactivestate;
typedef struct {
PinName pin;
uint32_t mask;
PortName port;
} gpio_t;
struct gpio_irq_s {
uint32_t mask;
PortName port;
PinName pin;
uint32_t irq_id;
cg_intactivestate event;
cg_intsrc irq_src;
};
static inline int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin != (PinName)NC);
}
#ifdef __cplusplus
}
#endif
#endif

673
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c
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@ -1,673 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#if DEVICE_I2C
#include "mbed_error.h"
#include "pinmap.h"
#include "gpio_include.h"
#if DEVICE_I2C_ASYNCH
#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
#else
#define I2C_S(obj) (struct i2c_s *) (obj)
#endif
static const PinMap PinMap_I2C_SDA[] = {
{PC1, I2C_0, PIN_DATA(1, 2)},
{PA5, I2C_1, PIN_DATA(1, 2)},
{PL1, I2C_2, PIN_DATA(3, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PC0, I2C_0, PIN_DATA(1, 2)},
{PA4, I2C_1, PIN_DATA(1, 2)},
{PL0, I2C_2, PIN_DATA(3, 2)},
{NC, NC, 0}
};
// Clock setting structure definition
typedef struct {
uint32_t sck;
uint32_t prsck;
} I2C_clock_setting_t;
// SCK Divider value table
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {
20, 24, 32, 48, 80, 144, 272, 528
};
I2C_clock_setting_t clk;
static uint32_t start_flag = 0;
#if DEVICE_I2C_ASYNCH
enum {
I2C_TRANSFER_STATE_IDLE = 0U,
I2C_TRANSFER_STATE_START,
I2C_TRANSFER_STATE_WRITE,
I2C_TRANSFER_STATE_RESTART,
I2C_TRANSFER_STATE_READ,
I2C_TRANSFER_STATE_MAX
} TransferState;
typedef struct {
IRQn_Type i2c;
} i2c_irq_t;
static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = {
{INTI2C0_IRQn}
};
static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = {
{INTI2C1_IRQn}
};
static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = {
{INTI2C2_IRQn}
};
#endif
static int32_t wait_status(i2c_t *p_obj);
static void i2c_start_bit(i2c_t *obj);
#if DEVICE_I2C_ASYNCH
static void disable_irq(uint32_t irqn);
static void clear_irq(uint32_t irqn);
static void i2c_irq_handler(i2c_t *obj);
#endif
// Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
struct i2c_s *obj_s = I2C_S(obj);
MBED_ASSERT(obj_s != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)i2c_name != NC);
switch (i2c_name) {
case I2C_0:
TSB_CG_FSYSENA_IPENA20 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE;
obj_s->i2c = TSB_I2C0;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH0_IRQN_TBL;
#endif
break;
case I2C_1:
TSB_CG_FSYSENA_IPENA21 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE;
obj_s->i2c = TSB_I2C1;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH1_IRQN_TBL;
#endif
break;
case I2C_2:
TSB_CG_FSYSENA_IPENA22 = ENABLE;
TSB_CG_FSYSENA_IPENA10 = ENABLE;
obj_s->i2c = TSB_I2C2;
#if DEVICE_I2C_ASYNCH
obj_s->irqn = (uint32_t)&I2C_CH2_IRQN_TBL;
#endif
break;
default:
error("I2C is not available");
break;
}
#if DEVICE_I2C_ASYNCH
obj_s->state = I2C_TRANSFER_STATE_IDLE;
#endif
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(scl, OpenDrain);
pin_mode(scl, PullUp);
i2c_reset(obj);
i2c_frequency(obj, 100000);
obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT);
obj_s->i2c->OP = I2CxOP_INIT;
obj_s->i2c->IE = I2CxIE_CLEAR;
}
// Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz)
{
struct i2c_s *obj_s = I2C_S(obj);
uint64_t sck;
uint64_t tmp_sck;
uint64_t prsck;
uint64_t tmp_prsck;
uint64_t fscl;
uint64_t tmp_fscl;
uint64_t fx;
SystemCoreClockUpdate();
if (hz <= 1000000) {
sck = tmp_sck = 0;
prsck = tmp_prsck = 1;
fscl = tmp_fscl = 0;
for (prsck = 1; prsck <= 32; prsck++) {
fx = ((uint64_t)SystemCoreClock / prsck);
if ((fx < 20000000U) && (fx > 6666666U)) {
for (sck = 0; sck <= 7; sck++) {
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
tmp_sck = sck;
tmp_prsck = (prsck < 32) ? prsck : 0;
}
}
}
}
clk.sck = (uint32_t)tmp_sck;
clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0;
}
obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
}
int i2c_start(i2c_t *obj)
{
start_flag = 1; // Start Condition
return 0;
}
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
uint32_t timeout = I2C_TIMEOUT;
obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) {
if (timeout == 0) {
break;
}
timeout--;
}
return 0;
}
void i2c_reset(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->i2c->CR2 = I2CxCR2_SWRES_10;
obj_s->i2c->CR2 = I2CxCR2_SWRES_01;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int32_t result = 0;
int32_t count = 0;
int32_t pdata = 0;
if (length > 0) {
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) {
while (count < length) {
pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1));
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
}
return result;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int32_t result = 0;
int32_t count = 0;
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, address) == I2C_ACK) {
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
return result;
}
int i2c_byte_read(i2c_t *obj, int last)
{
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = 0;
obj_s->i2c->ST = I2CxST_CLEAR;
if (last) {
obj_s->i2c->OP |= I2CxOP_MFACK;
} else {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
}
obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK);
if (wait_status(obj) < 0) {
result = -1;
} else {
result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK);
}
return result;
}
int i2c_byte_write(i2c_t *obj, int data)
{
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = 0;
obj_s->i2c->ST = I2CxST_CLEAR;
if (start_flag == 1) {
obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK);
i2c_start_bit(obj);
start_flag = 0;
} else {
obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK);
}
if (wait_status(obj) < 0) {
return -1;
}
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
result = 1;
} else {
result = 0;
}
return result;
}
static void i2c_start_bit(i2c_t *obj) // Send START command
{
struct i2c_s *obj_s = I2C_S(obj);
uint32_t opreg = 0;
opreg = obj_s->i2c->OP;
opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
if ((obj_s->i2c->SR & I2CxSR_BB)) {
opreg |= I2CxOP_SREN;
}
obj_s->i2c->OP = opreg;
obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION;
}
static int32_t wait_status(i2c_t *p_obj)
{
struct i2c_s *obj_s = I2C_S(p_obj);
volatile int32_t timeout;
timeout = I2C_TIMEOUT;
while (!((obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) {
if ((timeout--) == 0) {
return (-1);
}
}
return 0;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
struct i2c_s *obj_s = I2C_S(obj);
if (enable_slave) {
i2c_reset(obj);
obj_s->i2c->OP = I2CxOP_SLAVE_INIT;
obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
obj_s->i2c->CR2 = I2CxCR2_INIT;
obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK);
obj_s->i2c->IE = I2CxIE_INTI2C;
} else {
i2c_reset(obj);
obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT);
obj_s->i2c->OP = I2CxOP_INIT;
obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj_s->i2c->ST = I2CxST_CLEAR;
}
}
int i2c_slave_receive(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
int32_t result = I2C_NO_DATA;
if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) {
// Detect and clear arbitration lost.
if(!(obj_s->i2c->SR & 0x08)) {
obj_s->i2c->DBR = 0x00;
}
if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) {
result = I2C_READ_ADDRESSED;
} else {
result = I2C_WRITE_ADDRESSED;
}
}
return (result);
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
struct i2c_s *obj_s = I2C_S(obj);
int32_t count = 0;
while (count < length) {
int32_t pdata = i2c_byte_read(obj, 0);
if ((obj_s->i2c->SR & I2CxSR_TRX)) {
return (count);
} else {
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
}
i2c_slave_mode(obj,1);
return (count);
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
int32_t count = 0;
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
i2c_slave_mode(obj,1);
return (count);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->address = address & I2CAR_SA_MASK;
i2c_slave_mode(obj,1);
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}
#if DEVICE_I2C_ASYNCH
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address,
uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_irq_t *p_irqn = (i2c_irq_t *)obj_s->irqn;
if(obj_s->state == I2C_TRANSFER_STATE_IDLE) {
// Disable and clear interrupt flag.
disable_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
obj_s->i2c->ST = I2CxST_CLEAR;
clear_irq(obj_s->irqn);
// Store given buffer data and lenght into I2C object and set state as I2C_TRANSFER_STATE_START.
obj_s->address = address;
obj_s->event = 0;
obj_s->stop = stop;
obj->tx_buff.buffer = (void *)tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
obj->rx_buff.buffer = rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
obj_s->state = I2C_TRANSFER_STATE_START;
// Enable I2C interrupt.
obj_s->i2c->IE = I2CxIE_INTI2C;
if ((tx_length == 0) && (rx_length != 0)) {
i2c_start_bit(obj);
obj_s->i2c->DBR = ((address | 1U) & I2CxDBR_DB_MASK);
} else {
i2c_start_bit(obj);
obj_s->i2c->DBR = (address & I2CxDBR_DB_MASK);
}
// Enable I2C interrupr in NVIC.
NVIC_EnableIRQ(p_irqn->i2c);
NVIC_SetVector(p_irqn->i2c, handler);
}
}
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
i2c_irq_handler(obj);
return (obj_s->event & I2C_EVENT_ALL);
}
uint8_t i2c_active(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
uint8_t ret_val = 0;
if ((obj_s->i2c->CR2 & 0x08)) {
ret_val = 1;
}
return ret_val;
}
void i2c_abort_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
// Generate Stop condition on I2C bus
i2c_stop(obj);
// Set state as idle and disable I2C interrupt.
obj_s->state = I2C_TRANSFER_STATE_IDLE;
disable_irq(obj_s->irqn);
clear_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
// Given I2C Software Reset
i2c_reset(obj);
// Re-Store the I2C configuration
obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | I2CxCR2_INIT);
obj_s->i2c->OP = I2CxOP_INIT;
obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj_s->i2c->ST = I2CxST_CLEAR;
}
static void disable_irq(uint32_t irqn)
{
i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
NVIC_DisableIRQ(p_irqn->i2c);
}
static void clear_irq(uint32_t irqn)
{
i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
NVIC_ClearPendingIRQ(p_irqn->i2c);
}
static void i2c_irq_handler(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->i2c->ST = I2CxST_CLEAR;
switch(obj_s->state) {
case I2C_TRANSFER_STATE_START:
// Check ACK for sent slave address.
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
if(obj->tx_buff.length != (unsigned long)0) { // Check Tx buff length.
obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK;
obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t);
obj->tx_buff.pos++;
obj_s->state = I2C_TRANSFER_STATE_WRITE;
} else if(obj->rx_buff.length != 0) { // Check Rx buff length.
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
obj_s->state = I2C_TRANSFER_STATE_READ;
} else { // Return transfer complete because of not given any Tx/Rx data.
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else { // Return "No Slave", Because of Did not get any ACK for sent slave address.
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_WRITE:
if(obj->tx_buff.pos < obj->tx_buff.length) {
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
obj_s->i2c->DBR = *((uint8_t *)obj->tx_buff.buffer)& I2CxDBR_DB_MASK;
obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + sizeof(uint8_t);
obj->tx_buff.pos++;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else if(obj->rx_buff.length != 0) {
if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
i2c_start_bit(obj);
obj_s->i2c->DBR = ((obj_s->address | 1U) & I2CxDBR_DB_MASK);
obj_s->state = I2C_TRANSFER_STATE_RESTART;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
} else {
if(obj_s->stop) {
obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
}
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_RESTART:
if(!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
// Set ACK/NACK
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
obj_s->state = I2C_TRANSFER_STATE_READ;
} else {
obj_s->event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
case I2C_TRANSFER_STATE_READ:
if(obj->rx_buff.pos < obj->rx_buff.length) {
*((uint8_t *)obj->rx_buff.buffer) = (uint8_t)obj_s->i2c->DBR & I2CxDBR_DB_MASK;
obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + sizeof(uint8_t);
obj->rx_buff.pos++;
}
if(obj->rx_buff.pos < obj->rx_buff.length) {
// Set ACK/NACK
if ((obj->rx_buff.pos < (obj->rx_buff.length - 1))) {
obj_s->i2c->OP &= ~I2CxOP_MFACK;
} else {
obj_s->i2c->OP |= I2CxOP_MFACK;
}
obj_s->i2c->DBR = 0x00;
} else {
if(obj_s->stop) {
obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION;
}
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
obj_s->state = I2C_TRANSFER_STATE_IDLE;
}
break;
default:
break;
}
if(obj_s->state == I2C_TRANSFER_STATE_IDLE) {
disable_irq(obj_s->irqn);
obj_s->i2c->IE = I2CxIE_CLEAR;
}
}
#endif // #if DEVICE_I2C_ASYNCH
#endif // #if DEVICE_I2C

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include <stddef.h>
#include "PortNames.h"
#include "PeripheralNames.h"
#include "txz_tspi.h"
#include "PinNames.h"
#include "TMPM3H6.h"
#include "gpio_include.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t BaudRate;
uint32_t DataBits;
uint32_t StopBits;
uint32_t Parity;
uint32_t Mode;
uint32_t FlowCtrl;
} uart_inittypedef_t;
struct port_s {
PortName port;
uint32_t mask;
};
typedef struct {
uint8_t PinDATA;
uint8_t PinCR;
uint8_t PinFR[6];
uint8_t PinOD;
uint8_t PinPUP;
uint8_t PinPDN;
uint8_t PinIE;
} gpio_regtypedef_t;
typedef struct {
__IO uint32_t DATA;
__IO uint32_t CR;
__IO uint32_t FR[6];
uint32_t RESERVED0[2];
__IO uint32_t OD;
__IO uint32_t PUP;
__IO uint32_t PDN;
uint32_t RESERVED1;
__IO uint32_t IE;
} TSB_Port_TypeDef;
struct serial_s {
PinName pin;
uint32_t index;
TSB_UART_TypeDef *UARTx;
uart_inittypedef_t uart_config;
};
struct analogin_s {
PinName pin;
ADCName adc;
TSB_AD_TypeDef *obj;
};
struct dac_s {
DACName dac;
TSB_DA_TypeDef *handler;
};
struct pwmout_s {
PinName pin;
TSB_T32A_TypeDef *channel;
uint16_t trailing_timing;
uint16_t leading_timing;
uint16_t divisor;
float period;
};
struct i2c_s {
uint32_t address;
TSB_I2C_TypeDef *i2c;
#if DEVICE_I2C_ASYNCH
uint32_t irqn;
uint32_t state;
uint32_t event;
uint32_t stop;
#endif
};
struct spi_s {
tspi_t p_obj;
SPIName module;
uint8_t bits;
PinName Slave_SCK;
#if DEVICE_SPI_ASYNCH
uint32_t irqn;
uint32_t event;
uint32_t max_size;
uint32_t state;
#endif
};
extern const gpio_regtypedef_t GPIO_SFRs[];
extern const uint32_t GPIO_Base[];
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

96
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h
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/**
*******************************************************************************
* @file txz_driver_def.h
* @brief All common macro and definition for TXZ peripheral drivers
* @version V1.0.0.0
* $Date:: 2018-01-22 15:26:40 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TXZ_DRIVER_DEF_H
#define __TXZ_DRIVER_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF
* @brief All common macro and definition for TXZ peripheral drivers
* @{
*/
/** @defgroup Device_Header_Included Device Header Included
* @brief Include the Device header file of a Target.
* @{
*/
#include "TMPM3H6.h" /*!< TMPM3H6 Group Header file. */
/**
* @}
*/ /* End of group Device_Header */
/** @defgroup TXZ_Exported_typedef TXZ Exported typedef
* @{
*/
typedef enum {
TXZ_SUCCESS = 0U,
TXZ_ERROR = 1U
} TXZ_Result;
typedef enum {
TXZ_BUSY = 0U,
TXZ_DONE = 1U
} TXZ_WorkState;
typedef enum {
TXZ_DISABLE = 0U,
TXZ_ENABLE = 1U
} TXZ_FunctionalState;
/**
* @}
*/ /* End of group TXZ_Exported_typedef */
/** @defgroup TXZ_Exported_macro TXZ Exported macro
* @{
*/
#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0)
/**
* @brief To report the name of the source file and source line number where the
* assert_param error has occurred, "DEBUG" must be defined. And detailed
* definition of assert_failed() is needed to be implemented, which can be
* done, for example, in the main.c file.
*/
#ifdef DEBUG
void assert_failed(char *file, int32_t line);
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
#else
#define assert_param(expr)
#endif /* DEBUG */
/**
* @}
*/ /* End of group TXZ_Exported_macro */
/**
* @}
*/ /* End of group Periph_Driver */
/**
* @}
*/ /* End of group TXZ_DRIVER_DEF */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TXZ_DRIVER_DEF_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c
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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h
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198
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "gpio_include.h"
void pin_function(PinName pin, int function)
{
int port = 0;
uint8_t bit = 0;
uint8_t func = 0;
uint8_t dir = 0;
uint32_t port_base = 0;
uint32_t mode_base = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Calculate pin function and pin direction
func = PIN_FUNC(function);
dir = PIN_DIR(function);
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
port_base = BITBAND_PORT_BASE(port);
// Initialization PxFR OFF
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
BITBAND_PORT_CLR(mode_base, bit);
// Initialize Input
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_SET(mode_base, bit);
switch (func) {
case 0:
break;
case 1:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
break;
case 2:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
break;
case 3:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
break;
case 4:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
break;
case 5:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
break;
case 6:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
break;
default:
break;
}
if (func != 0) {
BITBAND_PORT_SET(mode_base, bit);
}
if (dir == PIN_OUTPUT) {
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_SET(mode_base, bit);
} else if (dir == PIN_INOUT) {
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_SET(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_SET(mode_base, bit);
}
}
void pin_mode(PinName pin, PinMode mode)
{
int port = 0;
uint8_t bit = 0;
uint8_t val = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Check if function is in range
if (mode > OpenDrain) {
return;
}
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
val = (1 << bit);
switch (port) {
case PortA:
if (mode == OpenDrain) TSB_PA->OD |= val;
else if (mode == PullUp) TSB_PA->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val;
break;
case PortB:
if (mode == OpenDrain) TSB_PB->OD |= val;
else if (mode == PullUp) TSB_PB->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val;
break;
case PortC:
if (mode == OpenDrain) TSB_PC->OD |= val;
else if (mode == PullUp) TSB_PC->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val;
break;
case PortD:
if (mode == OpenDrain) TSB_PD->OD |= val;
else if (mode == PullUp) TSB_PD->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val;
break;
case PortE:
if (mode == OpenDrain) TSB_PE->OD |= val;
else if (mode == PullUp) TSB_PE->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val;
break;
case PortF:
if (mode == OpenDrain) TSB_PF->OD |= val;
else if (mode == PullUp) TSB_PF->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val;
break;
case PortG:
if (mode == OpenDrain) TSB_PG->OD |= val;
else if (mode == PullUp) TSB_PG->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val;
break;
case PortH:
if (mode == PullDown) TSB_PH->PDN |= val;
break;
case PortJ:
if (mode == OpenDrain) TSB_PJ->OD |= val;
else if (mode == PullUp) TSB_PJ->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val;
break;
case PortK:
if (mode == OpenDrain) TSB_PK->OD |= val;
else if (mode == PullUp) TSB_PK->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val;
break;
case PortL:
if (mode == OpenDrain) TSB_PL->OD |= val;
else if (mode == PullUp) TSB_PL->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val;
break;
case PortM:
if (mode == OpenDrain) TSB_PM->OD |= val;
else if (mode == PullUp) TSB_PM->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val;
break;
case PortN:
if (mode == OpenDrain) TSB_PN->OD |= val;
else if (mode == PullUp) TSB_PN->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val;
break;
case PortP:
if (mode == OpenDrain) TSB_PP->OD |= val;
else if (mode == PullUp) TSB_PP->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val;
break;
case PortR:
if (mode == OpenDrain) TSB_PR->OD |= val;
else if (mode == PullUp) TSB_PR->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val;
break;
default:
break;
}
}

159
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_include.h"
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(port <= PortR);
// Store port and port mask for future use
obj->port = port;
obj->mask = mask;
// Enabling Port Clock Supply
TSB_CG->FSYSENA |= (1 << (obj->port));
// Set port function and port direction
for (i = 0; i < PORT_PIN_NUM; i++) {
if (obj->mask & (1 << i)) { // If the pin is used
pin_function(port_pin(obj->port, i), dir);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortR);
// Set mode for masked pins
for (i = 0; i < PORT_PIN_NUM; i++) {
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
uint8_t bit = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortR);
// Set direction for masked pins
switch (dir) {
case PIN_INPUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_INPUT);
}
}
break;
case PIN_OUTPUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_OUTPUT);
}
}
break;
case PIN_INOUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_INOUT);
}
}
break;
default:
break;
}
}
void port_write(port_t *obj, int value)
{
uint8_t port_data = 0;
uint8_t data = 0;
int bit = 0;
uint8_t val = 0;
uint32_t base = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortR);
base = BITBAND_PORT_BASE(obj->port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
// Get current data of port
for (bit = 7; bit >= 0; bit--) {
BITBAND_PORT_READ(val, base, bit);
port_data <<= 1;
port_data |= val;
}
// Calculate data to write to masked pins
data = (port_data & ~obj->mask) | (value & obj->mask);
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
if (((data >> bit) & 0x01) == GPIO_PIN_SET) {
BITBAND_PORT_SET(base, bit);
} else {
BITBAND_PORT_CLR(base, bit);
}
}
}
}
int port_read(port_t *obj)
{
uint8_t port_data = 0;
uint8_t data = 0;
int bit = 0;
uint8_t val = 0;
uint32_t base = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortR);
base = BITBAND_PORT_BASE(obj->port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
// Get current data of port
for (bit = 7; bit >= 0; bit--) {
BITBAND_PORT_READ(val, base, bit);
port_data <<= 1;
port_data |= val;
}
// Calculate data of masked pins
data = port_data & obj->mask;
return data;
}
PinName port_pin(PortName port, int pin_n)
{
PinName pin = NC;
pin = (PinName)((port << 3 ) | pin_n);
return pin;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c
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@ -1,192 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "pinmap.h"
#include "gpio_include.h"
static const PinMap PinMap_PWM[] = {
{PP0, PWM_0, PIN_DATA(4, 1)},
{PC0, PWM_1, PIN_DATA(4, 1)},
{PJ0, PWM_2, PIN_DATA(4, 1)},
{PK2, PWM_3, PIN_DATA(4, 1)},
{PN0, PWM_4, PIN_DATA(4, 1)},
{NC, NC, 0}
};
static const uint32_t prescale_tbl[] = {
2, 8, 32, 128, 256, 512, 1024
};
void pwmout_init(pwmout_t* obj, PinName pin)
{
uint16_t counter = 0;
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel
MBED_ASSERT(pwm != (PWMName)NC);
switch (pwm) {
case PWM_0:
obj->channel = TSB_T32A1;
TSB_CG_FSYSENA_IPENA27 = ENABLE;
TSB_CG_FSYSENA_IPENA13 = ENABLE;
break;
case PWM_1:
obj->channel = TSB_T32A2;
TSB_CG_FSYSENA_IPENA28 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE;
break;
case PWM_2:
obj->channel = TSB_T32A3;
TSB_CG_FSYSENA_IPENA29 = ENABLE;
TSB_CG_FSYSENA_IPENA08 = ENABLE;
break;
case PWM_3:
obj->channel = TSB_T32A4;
TSB_CG_FSYSENA_IPENA30 = ENABLE;
TSB_CG_FSYSENA_IPENA09 = ENABLE;
break;
case PWM_4:
obj->channel = TSB_T32A5;
TSB_CG_FSYSENA_IPENA31 = ENABLE;
TSB_CG_FSYSENA_IPENA12 = ENABLE;
break;
default:
obj->channel = NULL;
break;
}
pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM
obj->pin = pin;
obj->period = DEFAULT_PERIOD;
obj->divisor = DEFAULT_CLOCK_DIVISION;
obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP);
obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE);
obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx);
obj->channel->OUTCRC0 = T32A_OCR_DISABLE;
obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR);
counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor);
obj->channel->RGC0 = counter;
obj->channel->RGC1 = counter;
obj->trailing_timing = counter;
obj->leading_timing = counter;
}
void pwmout_free(pwmout_t* obj)
{
// Stops and clear count operation
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
pwmout_write(obj, 0);
obj->pin = NC;
obj->channel = NULL;
obj->trailing_timing = 0;
obj->leading_timing = 0;
obj->divisor = 0;
}
void pwmout_write(pwmout_t* obj, float value)
{
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again
obj->leading_timing = (obj->trailing_timing -
(obj->trailing_timing * value)); // leading_timing value
obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register
obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation
}
float pwmout_read(pwmout_t* obj)
{
float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing)
/ obj->trailing_timing);
return duty_cycle;
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
void pwmout_period_us(pwmout_t* obj, int us)
{
float seconds = 0;
int cycles = 0;
uint32_t clkdiv = 0;
int i = 0;
float duty_cycle = 0;
seconds = (float)(us / 1000000.0f);
// Select highest timer resolution
for (i = 0; i < 7; ++i) {
cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds);
if (cycles <= MAX_COUNTER_16B) {
clkdiv = i + 1; // range 1:7
clkdiv <<= 28;
break;
} else {
cycles = MAX_COUNTER_16B;
clkdiv = 7;
clkdiv <<= 28;
}
}
// Stop timer for setting clock again
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
// Restore the duty-cycle
duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing)
/ obj->trailing_timing);
obj->trailing_timing = cycles;
obj->leading_timing = (cycles - (cycles * duty_cycle));
// Change the source clock division and period
obj->channel->MOD = T32A_MODE_32;
obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx);
obj->channel->OUTCRC0 = T32A_OCR_DISABLE;
obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR);
obj->channel->RGC0 = obj->leading_timing;
obj->channel->RGC1 = obj->trailing_timing;
obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
float seconds = 0;
float value = 0;
seconds = (float)(us / 1000000.0f);
value = (((seconds / obj->period) * 100.0f) / 100.0f);
pwmout_write(obj, value);
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM;
}

132
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/reset_reason_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "reset_reason_api.h"
#ifdef DEVICE_RESET_REASON
#include "TMPM3H6.h"
#include <stdbool.h>
static uint8_t set_bit_count(uint32_t reg);
static uint8_t bit_pos(uint32_t reg);
static bool bit_status(uint32_t reg, uint8_t bit_no);
static reset_reason_t reset_reason1[6] = {
RESET_REASON_POWER_ON,
RESET_REASON_UNKNOWN,
RESET_REASON_UNKNOWN,
RESET_REASON_PIN_RESET,
RESET_REASON_WAKE_LOW_POWER,
RESET_REASON_BROWN_OUT
};
static reset_reason_t reset_reason2[4] = {
RESET_REASON_SOFTWARE,
RESET_REASON_LOCKUP,
RESET_REASON_WATCHDOG,
RESET_REASON_PLATFORM
};
void hal_reset_reason_clear(void)
{
TSB_RLM->RSTFLG0 = 0;
TSB_RLM->RSTFLG1 = 0;
}
uint32_t hal_reset_reason_get_raw(void)
{
uint32_t ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF));
return ret;
}
reset_reason_t hal_reset_reason_get(void)
{
char multi_flag = 0;
reset_reason_t ret;
uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0);
uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1);
if (NoOfSetBitCountReg1 != 0x00) {
if (NoOfSetBitCountReg1 > 0x01) {
if (bit_status(TSB_RLM->RSTFLG0, 3)) {
ret = RESET_REASON_POWER_ON;
} else {
ret = RESET_REASON_MULTIPLE;
}
} else {
ret = reset_reason1[bit_pos(TSB_RLM->RSTFLG0)];
}
} else if (NoOfSetBitCountReg2 != 0x00) {
if (NoOfSetBitCountReg2 > 0x01) {
ret = RESET_REASON_MULTIPLE;
} else {
ret = reset_reason2[bit_pos(TSB_RLM->RSTFLG1)];
}
} else {
ret = RESET_REASON_UNKNOWN;
}
return ret;
}
void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
{
cap->reasons = 1 << RESET_REASON_UNKNOWN;
cap->reasons |= 1 << RESET_REASON_POWER_ON;
cap->reasons |= 1 << RESET_REASON_MULTIPLE;
}
static bool bit_status(uint32_t reg, uint8_t bit_no)
{
bool status = false;
if (reg & (1 << bit_no)) {
status = true;
}
return status;
}
static uint8_t set_bit_count(uint32_t reg)
{
uint8_t count = 0;
int8_t index = 0;
for (index = 0; index < (sizeof(uint32_t) * 8); index++) {
if (reg & (1 << index)) {
count++;
if (count > 0x01) {
break;
}
}
}
return count;
}
static uint8_t bit_pos(uint32_t reg)
{
uint8_t bit_no = 0;
for (bit_no = 0; bit_no < (sizeof(uint32_t) * 8); bit_no++) {
if (reg & (1 << bit_no)) {
return bit_no;
}
}
}
#endif // DEVICE_RESET_REASON

226
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/rtc_api.c
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@ -1,226 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#include "mbed_mktime.h"
#define RTC_24_HOUR_MODE ((uint8_t)0x01)
#define PAGER_PAGE_ONE ((uint8_t)0x01)
#define PAGER_PAGE_ZERO ((uint8_t)0xEE)
#define RTC_CLK_ENABLE ((uint8_t)0x08)
#define RTC_CLK_DISABLE ((uint8_t)0xE7)
#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20)
#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20)
#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000)
#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002)
#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000)
#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001)
#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001)
#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
#define ELOSC_CFG_CLOCK ((uint64_t)(32768))
#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro
#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro
static int rtc_inited = 0;
static int diff_year = 100; //our RTC register only support 2000~2099
static void external_losc_enable(void);
void rtc_init(void)
{
if (!rtc_inited) {
TSB_CG_FSYSENB_IPENB03 = 1; // Enable Sys Clock for RTC
external_losc_enable(); // Enable low-speed oscillator
TSB_RTC->PAGER = 0x00; // Disable clock and alarm
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->RESTR = 0xE7;
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter
}
TSB_RTC->PAGER |= PAGER_PAGE_ONE;
TSB_RTC->YEARR = 0x03; // Set leap year state
TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode
TSB_RTC->YEARR = 0x01; // Set year value
TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value
TSB_RTC->DATER = (uint8_t)0x01; // Set date value
TSB_RTC->DAYR = (uint8_t)0x0; // Set day value
TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value
TSB_RTC->MINR = (uint8_t)0x02; // Set minute value
TSB_RTC->SECR = (uint8_t)0x22; // Set second value
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
rtc_inited = 1; // Enable RTC initialzed status
}
}
void rtc_free(void)
{
rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE
}
int rtc_isenabled(void)
{
return rtc_inited; // Return status of RTC peripheral driver
}
time_t rtc_read(void)
{
if (!rtc_inited) {
// Return invalid time for now!
return 0;
}
struct tm timeinfo;
uint8_t read_1 = 0U;
uint8_t read_2 = 0U;
timeinfo.tm_isdst = 0;//no summer time
TSB_RTC->PAGER &= PAGER_PAGE_ZERO;
read_1 = TSB_RTC->SECR; // Get sec value
timeinfo.tm_sec = HEX2DEC(read_1);
do { // Get minute value
read_1 = TSB_RTC->MINR;
read_2 = TSB_RTC->MINR;
} while (read_1 != read_2);
timeinfo.tm_min = HEX2DEC(read_1);
do { // Get hour value
read_1 = TSB_RTC->HOURR;
read_2 = TSB_RTC->HOURR;
} while (read_1 != read_2);
timeinfo.tm_hour = HEX2DEC(read_1);
do { // Get Month date value
read_1 = TSB_RTC->DATER;
read_2 = TSB_RTC->DATER;
} while (read_1 != read_2);
timeinfo.tm_mday = HEX2DEC(read_1);
do { // Get Month value
read_1 = TSB_RTC->MONTHR;
read_2 = TSB_RTC->MONTHR;
} while (read_1 != read_2);
timeinfo.tm_mon = HEX2DEC(read_1)-1;
do { // Get weekday value
read_1 = TSB_RTC->DAYR;
read_2 = TSB_RTC->DAYR;
} while (read_1 != read_2);
timeinfo.tm_wday = HEX2DEC(read_1);
do { // Get year value
read_1 = TSB_RTC->YEARR;
read_2 = TSB_RTC->YEARR;
} while (read_1 != read_2);
timeinfo.tm_year = (HEX2DEC(read_1)+ diff_year);
time_t t;
if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return 0;
}
return t;
}
void rtc_write(time_t t)
{
if (!rtc_inited) {
// Initialize the RTC as not yet initialized
rtc_init();
}
struct tm timeinfo;
if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return;
}
diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100);
TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock
// Check current year is leap year or not
if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) ||
(timeinfo.tm_year % 400) == 0) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year
TSB_RTC->YEARR = 0x00;
} else if ((timeinfo.tm_year % 4) == 1) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year
TSB_RTC->YEARR = 0x01;
} else if ((timeinfo.tm_year % 4) == 2) {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year
TSB_RTC->YEARR = 0x02;
} else {
TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year
TSB_RTC->YEARR = 0x03;
}
TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0
TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value
// Set month value, tm_mon=0 means Jan while 1 is Jan
TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon+1));
TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value
TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value
TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value
TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value
TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value
TSB_RTC->RESTR |= RTCRESTR_RSTTMR_R_RUN;
while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) {
// Reset RTC sec counter, otherwise the 1st second will not be accurate
}
// Setting Wait
// When stop mode is selected, CaseA or CaseB is need.
// CaseA: Wait for RTC 1Hz interrupt.
// CaseB: Check the clock register setting.
{
uint8_t flag = 1;
time_t time_read = {0};
while(flag) {
time_read = rtc_read();
if( time_read == t) { // Wait for setting successfully
flag = 0;
}
}
}
TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock
}
static void external_losc_enable(void)
{
uint32_t work;
if( (TSB_RLM->LOSCCR & 0x01) == 0 ) { //external losc is not enabled.
uint64_t x = (uint64_t)(ELOSC_CFG_WARM_UP_TIME * ELOSC_CFG_CLOCK);
x = (uint64_t)(x / (uint64_t)(1000000));
work = (uint32_t)x;
work &= (uint32_t)(0xFFFFFFF0);
work <<= 8;
TSB_CG->WUPLCR = work;
TSB_RLM->LOSCCR = RLMLOSCCR_XTEN_RW_ENABLE;
work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK);
TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE);
while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) {
// No processing
}
}
}

436
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c
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@ -1,436 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "serial_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_include.h"
#include "objects.h"
static const PinMap PinMap_UART_TX[] = {
{PM1, SERIAL_0, PIN_DATA(1, 1)},
{PJ2, SERIAL_1, PIN_DATA(2, 1)},
{PB2, SERIAL_2, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PM2, SERIAL_0, PIN_DATA(1, 0)},
{PJ1, SERIAL_1, PIN_DATA(2, 0)},
{PB3, SERIAL_2, PIN_DATA(1, 0)},
{NC, NC, 0}
};
#if DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{PM3, SERIAL_0, PIN_DATA(1, 0)},
{PJ3, SERIAL_1, PIN_DATA(1, 0)},
{PB4, SERIAL_2, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RTS[] = {
{PM4, SERIAL_0, PIN_DATA(1, 1)},
{PJ4, SERIAL_1, PIN_DATA(1, 1)},
{PB5, SERIAL_2, PIN_DATA(1, 1)},
{NC, NC, 0}
};
#endif
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct);
static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate);
static void uart_swreset(TSB_UART_TypeDef *UARTx);
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart_name != NC);
obj->index = uart_name;
switch (uart_name) {
case SERIAL_0:
obj->UARTx = TSB_UART0;
TSB_CG_FSYSENA_IPENA23 = ENABLE;
TSB_CG_FSYSENA_IPENA11 = ENABLE;
break;
case SERIAL_1:
obj->UARTx = TSB_UART1;
TSB_CG_FSYSENA_IPENA24 = ENABLE;
TSB_CG_FSYSENA_IPENA08 = ENABLE;
TSB_CG_FSYSENA_IPENA09 = ENABLE;
break;
case SERIAL_2:
obj->UARTx = TSB_UART2;
TSB_CG_FSYSENA_IPENA25 = ENABLE;
TSB_CG_FSYSENA_IPENA01 = ENABLE;
break;
default:
error("UART is not available");
break;
}
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (tx != NC && rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
} else {
if (tx != NC) {
obj->uart_config.Mode = UART_ENABLE_TX;
} else {
if (rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX;
}
}
}
obj->uart_config.BaudRate = 9600;
obj->uart_config.DataBits = 8;
obj->uart_config.StopBits = 0;
obj->uart_config.Parity = ParityNone;
obj->uart_config.FlowCtrl = FlowControlNone;
uart_init(obj->UARTx, &obj->uart_config);
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
obj->UARTx->TRANS = 0;
obj->UARTx->CR0 = 0;
obj->UARTx->CR1 = 0;
uart_swreset(obj->UARTx);
obj->uart_config.BaudRate = 0;
obj->uart_config.DataBits = 0;
obj->uart_config.StopBits = 0;
obj->uart_config.Parity = 0;
obj->uart_config.Mode = 0;
obj->uart_config.FlowCtrl = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->uart_config.BaudRate = baudrate;
uart_init(obj->UARTx, &obj->uart_config);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
obj->uart_config.DataBits = data_bits;
obj->uart_config.StopBits = stop_bits;
obj->uart_config.Parity = parity;
uart_init(obj->UARTx, &obj->uart_config);
}
void INTUART0TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
}
void INTUART0RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
}
void INTUART1TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
}
void INTUART1RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
}
void INTUART2TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
}
void INTUART2RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
switch (obj->index) {
case SERIAL_0:
if (irq == RxIrq) {
irq_n = INTUART0RX_IRQn;
} else {
irq_n = INTUART0TX_IRQn;
}
break;
case SERIAL_1:
if (irq == RxIrq) {
irq_n = INTUART1RX_IRQn;
} else {
irq_n = INTUART1TX_IRQn;
}
break;
case SERIAL_2:
if (irq == RxIrq) {
irq_n = INTUART2RX_IRQn;
} else {
irq_n = INTUART2TX_IRQn;
}
break;
default:
break;
}
NVIC_ClearPendingIRQ(irq_n);
if (enable) {
NVIC_EnableIRQ(irq_n);
} else {
NVIC_DisableIRQ(irq_n);
}
}
int serial_getc(serial_t *obj)
{
int data = 0;
while (!serial_readable(obj)) { // Wait until Rx buffer is full
// Do nothing
}
if (obj->uart_config.Mode & UART_ENABLE_TX) {
obj->UARTx->TRANS &= 0x0D;
}
data = data | (obj->UARTx->DR & 0xFFU);
if (obj->uart_config.Mode & UART_ENABLE_TX) {
obj->UARTx->TRANS |= UART_ENABLE_TX;
}
return data;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
// Do nothing
}
if (obj->uart_config.Mode & UART_ENABLE_RX) {
obj->UARTx->TRANS &= 0x0E;
}
obj->UARTx->DR = c & 0xFFU;
if (obj->uart_config.Mode & UART_ENABLE_RX) {
obj->UARTx->TRANS |= UART_ENABLE_RX;
}
}
int serial_readable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x0000000F) != 0) {
ret = 1;
}
return ret;
}
int serial_writable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x8000) == 0) {
ret = 1;
}
return ret;
}
void serial_clear(serial_t *obj)
{
obj->UARTx->FIFOCLR = 0x03;
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
obj->UARTx->TRANS |= 0x08;
}
void serial_break_clear(serial_t *obj)
{
obj->UARTx->TRANS &= ~(0x08);
}
#if DEVICE_SERIAL_FC
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT((int)uart_name != NC);
pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS);
pin_mode(txflow, PullUp);
pin_mode(rxflow, PullUp);
obj->UARTx->CR0 |= (3U << 9);
}
#endif
static void uart_swreset(TSB_UART_TypeDef *UARTx)
{
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
UARTx->SWRST = UARTxSWRST_SWRST_10;
UARTx->SWRST = UARTxSWRST_SWRST_01;
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
}
static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate)
{
uint32_t clock = 0;
uint32_t k = 0;
uint64_t tx = 0;
uint64_t work = 1;
uint64_t p_range64 = 0;
uint64_t boud64 = 0;
uint64_t tx64 = 0;
uint64_t work64 = 1;
SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency
clock = SystemCoreClock;
tx = (uint64_t)((uint64_t)clock << 6);
tx /= work;
tx64 = (uint64_t)((uint64_t)clock << 8);
tx64 /= work64;
work = ((uint64_t)boudrate);
tx /= work;
tx >>= 4;
boud64 = (64U * boudrate);
p_range64 = ((boud64 / 100) * 3);
for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) {
work = tx + k;
if (work >= (uint64_t)((uint64_t)1 << 6)) {
work -= (uint64_t)((uint64_t)1 << 6);
work >>= 6;
if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) {
work64 = work <<6;
work64 = (uint64_t)(work64 + (64 - (uint64_t)k));
work64 = (tx64 / work64);
if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) {
brddiviser->brn = work;
brddiviser->brk = k;
break;
}
}
}
}
}
static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct)
{
uart_boudrate_t UTx_brd = {0};
uint32_t brk = 0;
uint32_t tmp = 0;
uint32_t parity_check = 0;
uint32_t data_length = 0;
UARTx->CLK = UART_PLESCALER_1; // Register Setting
uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate);
UTx_brd.ken = UART_DIVISION_ENABLE;
brk = (UTx_brd.brk << 16);
UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn);
parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0);
data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2);
tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length);
UARTx->CR0 = tmp;
UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE);
UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR);
UARTx->TRANS = InitStruct->Mode;
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}

89
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c
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@ -1,89 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "gpio_include.h"
static void warming_up_time(void);
void hal_sleep(void)
{
// Set low power consumption mode IDLE
TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
__DSB(); // Enter idle mode
__WFI();
}
void hal_deepsleep(void)
{
uint32_t tmp = 0;
TSB_CG_FSYSENB_IPENB31 = ENABLE;
TSB_SIWD0->EN = DISABLE;
TSB_SIWD0->CR = 0xB1;
while ((TSB_FC->SR0 & 0x01) != 0x01) {
// Flash wait
}
while (TSB_CG_WUPHCR_WUEF) {
// Wait for end of Warming-up for IHOSC1
}
TSB_CG_WUPHCR_WUCLK = DISABLE;
warming_up_time();
TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
TSB_CG_PLL0SEL_PLL0SEL = DISABLE;
while (TSB_CG_PLL0SEL_PLL0ST) {
// Wait for PLL status of fsys until off state(fosc=0)
}
TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys
TSB_CG_OSCCR_IHOSC1EN = ENABLE;
TSB_CG_OSCCR_OSCSEL = DISABLE;
while (TSB_CG_OSCCR_OSCF) {
// Wait for fosc status until IHOSC1 = 0
}
tmp = TSB_CG->OSCCR;
tmp &= EXTERNEL_OSC_MASK;
TSB_CG->OSCCR = tmp;
TSB_CG_OSCCR_IHOSC2EN = DISABLE;
while (TSB_CG_OSCCR_IHOSC2F) {
// Wait for status of OFD until off "0"
}
__DSB();
__WFI();
}
static void warming_up_time(void)
{
uint32_t work = 0;
uint64_t x = 0;
x = (uint64_t)(IHOSC_CFG_WARM_UP_TIME * IHOSC_CFG_CLOCK);
x = (uint64_t)(x / (uint64_t)(1000000));
work = (uint32_t)x;
work &= (uint32_t)(0xFFFFFFF0);
work <<= 16;
work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK);
TSB_CG->WUPHCR = work;
}

558
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c
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@ -1,558 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "spi_api.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "gpio_include.h"
#include "txz_tspi.h"
#define TIMEOUT 1000
#define INITIAL_SPI_FREQ 1000000
#if DEVICE_I2C_ASYNCH
#define SPI_S(obj) (struct spi_s *) (&((obj)->spi))
#else
#define SPI_S(obj) (struct spi_s *) (obj)
#endif
#if DEVICE_SPI_ASYNCH
static void spi_irq_handler(spi_t *obj);
static void disable_irq(uint32_t irqn);
static void clear_irq(uint32_t irqn);
enum {
SPI_TRANSFER_STATE_IDLE = 0U,
SPI_TRANSFER_STATE_BUSY
} SPI_TransferState;
typedef struct {
IRQn_Type Tx;
IRQn_Type Rx;
IRQn_Type Error;
} spi_irq_t;
static const spi_irq_t SPI_CH0_IRQN_TBL[1] = {
{INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn}
};
static const spi_irq_t SPI_CH1_IRQN_TBL[1] = {
{INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn}
};
#endif
static const PinMap PinMap_SPI_SCLK[] = {
{PM0, SPI_0, PIN_DATA(3, 1)},
{PP0, SPI_1, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PM1, SPI_0, PIN_DATA(3, 1)},
{PP1, SPI_1, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PM2, SPI_0, PIN_DATA(3, 0)},
{PP2, SPI_1, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PM3, SPI_0, PIN_DATA(3, 2)},
{PL6, SPI_1, PIN_DATA(1, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_SPISLAVE_SCLK[] = {
{PM0, SPI_0, PIN_DATA(3, 0)},
{PP0, SPI_1, PIN_DATA(1, 0)},
{NC, NC, 0}
};
void spi_init(spi_t *t_obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
struct spi_s *obj = SPI_S(t_obj);
// Check pin parameters
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->module!= NC);
// Identify SPI module to use
switch ((int)obj->module) {
case SPI_0:
obj->p_obj.p_instance = TSB_TSPI0;
TSB_CG_FSYSENA_IPENA18 = ENABLE;
TSB_CG_FSYSENA_IPENA11 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH0_IRQN_TBL;
#endif
break;
case SPI_1:
obj->p_obj.p_instance = TSB_TSPI1;
TSB_CG_FSYSENA_IPENA19 = ENABLE;
TSB_CG_FSYSENA_IPENA13 = ENABLE;
TSB_CG_FSYSENA_IPENA10 = ENABLE;
#if DEVICE_SPI_ASYNCH
obj->irqn = (uint32_t)&SPI_CH1_IRQN_TBL;
#endif
break;
default:
error("Cannot found SPI module corresponding with input pins.");
break;
}
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
obj->Slave_SCK = sclk;
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
//Control 1 configurations
obj->p_obj.init.id = (uint32_t)obj->module;
obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication
obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation
obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid
obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time continuously
//Control 2 configurations
obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low
obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_40MHz_OVER;
obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level
obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level
obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
//Control 3 configurations
obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear
obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear
//baudrate settings
spi_frequency(t_obj, (int)INITIAL_SPI_FREQ);
//Format Control 0 settings
obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
//Special control on polarity of signal and generation timing
obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
//Format Control 1 settings tspi_fmtr1_t
obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
obj->bits = (uint8_t)TSPI_DATA_LENGTH_8;
//initialize SPI
tspi_init(&obj->p_obj);
}
void spi_free(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
tspi_deinit(&obj->p_obj);
obj->module = (SPIName)NC;
}
void spi_format(spi_t *t_obj, int bits, int mode, int slave)
{
struct spi_s *obj = SPI_S(t_obj);
MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode
MBED_ASSERT((bits >= 8) && (bits <= 32));
obj->bits = bits;
obj->p_obj.init.fmr0.fl = (bits << 24);
if ((mode >> 1) & 0x1) {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
} else {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
}
if (mode & 0x1) {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
} else {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
}
if(slave) {
pinmap_pinout(obj->Slave_SCK, PinMap_SPISLAVE_SCLK);
obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation
}
tspi_init(&obj->p_obj);
}
void spi_frequency(spi_t *t_obj, int hz)
{
struct spi_s *obj = SPI_S(t_obj);
uint8_t brs = 0;
uint8_t brck = 0;
uint16_t prsck = 1;
uint64_t fscl = 0;
uint64_t tmp_fscl = 0;
uint64_t fx = 0;
uint64_t tmpvar = SystemCoreClock;
SystemCoreClockUpdate();
tmpvar = tmpvar / 2;
for (prsck = 1; prsck <= 512; prsck *= 2) {
fx = ((uint64_t)tmpvar / prsck);
for (brs = 1; brs <= 16; brs++) {
fscl = fx /brs;
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
obj->p_obj.init.brd.brck = (brck << 4);
if (brs == 16) {
obj->p_obj.init.brd.brs = 0;
} else {
obj->p_obj.init.brd.brs = brs;
}
}
}
brck ++;
}
tspi_init(&obj->p_obj);
}
int spi_master_write(spi_t *t_obj, int value)
{
struct spi_s *obj = SPI_S(t_obj);
uint8_t ret_value = 0;
tspi_transmit_t send_obj;
tspi_receive_t rec_obj;
// Transmit data
send_obj.tx8.p_data = (uint8_t *)&value;
send_obj.tx8.num = 1;
tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT);
// Read received data
rec_obj.rx8.p_data = &ret_value;
rec_obj.rx8.num = 1;
tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT);
return ret_value;
}
int spi_master_block_write(spi_t *t_obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(t_obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
int ret = 1;
uint32_t status;
tspi_get_status(&obj->p_obj, &status);
if((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) {
ret = 0;
}
return ret;
}
int spi_slave_read(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
uint8_t ret_value = 0;
ret_value = obj->p_obj.p_instance->DR & 0xFF;
// Receive Complete Flag is clear.
obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
return ret_value;
}
void spi_slave_write(spi_t *t_obj, int value)
{
struct spi_s *obj = SPI_S(t_obj);
// Enable TSPI Transmission Control.
obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
obj->p_obj.p_instance->DR = value & 0xFF;
}
int spi_busy(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
int ret = 1;
uint32_t status = 0;
tspi_get_status(&obj->p_obj, &status);
if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
ret = 0;
}
return ret;
}
uint8_t spi_get_module(spi_t *t_obj)
{
struct spi_s *obj = SPI_S(t_obj);
return (uint8_t)(obj->module);
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPISLAVE_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
#if DEVICE_SPI_ASYNCH
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width,
uint32_t handler, uint32_t event, DMAUsage hint)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn;
bool use_tx = (tx != NULL && tx_length > 0);
bool use_rx = (rx != NULL && rx_length > 0);
// don't do anything, if the buffers aren't valid
if (!use_tx && !use_rx) {
return;
}
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
obj->tx_buff.buffer = (void *)tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
obj->rx_buff.buffer = (void *)rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
spiobj->event = 0;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
NVIC_SetVector(p_irqn->Error, (uint32_t)handler);
NVIC_SetVector(p_irqn->Tx, (uint32_t)handler);
NVIC_SetVector(p_irqn->Rx, (uint32_t)handler);
// Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt
spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE);
if (use_tx && use_rx) {
spiobj->max_size = tx_length < rx_length ? rx_length:tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
} else if(use_tx) {
spiobj->max_size = tx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF;
} else if(use_rx) {
spiobj->max_size = rx_length;
spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
spiobj->p_obj.p_instance->DR = 0xFF;
}
spiobj->state = SPI_TRANSFER_STATE_BUSY;
NVIC_EnableIRQ(p_irqn->Error);
NVIC_EnableIRQ(p_irqn->Tx);
NVIC_EnableIRQ(p_irqn->Rx);
}
uint32_t spi_irq_handler_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
spi_irq_handler(obj);
return ((spiobj->event & SPI_EVENT_ALL)| SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ;
}
uint8_t spi_active(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
uint8_t ret_val = 0;
if (spiobj->state != SPI_TRANSFER_STATE_IDLE) {
ret_val = 1;
}
return ret_val;
}
void spi_abort_asynch(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
disable_irq(spiobj->irqn);
clear_irq(spiobj->irqn);
tspi_init(&spiobj->p_obj);
}
static void spi_irq_handler(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
// Check for revceive complete flag.
if((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) &&
(spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) {
// Check receiver FIFO level
uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF;
while((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) {
((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF;
rlvl--;
}
if(obj->rx_buff.pos == spiobj->max_size) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
// Clear rx buffer
spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE;
}
// Check for transmit completion flag
if(spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) {
obj->tx_buff.pos++;
spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR;
if(obj->tx_buff.pos == (spiobj->max_size)) {
spiobj->state = SPI_TRANSFER_STATE_IDLE;
}
if((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) {
spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF);
} else if (obj->tx_buff.pos < spiobj->max_size) {
spiobj->p_obj.p_instance->DR = 0xFF;
}
}
// Check for error flag
if(spiobj->p_obj.p_instance->ERR) {
spiobj->event = SPI_EVENT_ERROR;
spiobj->state = SPI_TRANSFER_STATE_IDLE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
return;
}
if(spiobj->state == SPI_TRANSFER_STATE_IDLE) {
spiobj->event = SPI_EVENT_COMPLETE;
disable_irq(spiobj->irqn);
spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
clear_irq(spiobj->irqn);
}
}
static void disable_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_DisableIRQ(p_irqn->Tx);
NVIC_DisableIRQ(p_irqn->Rx);
NVIC_DisableIRQ(p_irqn->Error);
}
static void clear_irq(uint32_t irqn)
{
spi_irq_t *p_irqn = (spi_irq_t *)irqn;
NVIC_ClearPendingIRQ(p_irqn->Tx);
NVIC_ClearPendingIRQ(p_irqn->Rx);
NVIC_ClearPendingIRQ(p_irqn->Error);
}
#endif

96
targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "us_ticker_api.h"
#include "gpio_include.h"
static bool us_ticker_inited = false; // Is ticker initialized yet?
const ticker_info_t* us_ticker_get_info(void)
{
static const ticker_info_t info = {
1248125, // (39.94 MHz / 32 )
32 // 32 bit counter
};
return &info;
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = true;
TSB_CG_FSYSENA_IPENA26 = TXZ_ENABLE;
TSB_T32A0->MOD = T32A_MODE_32;
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->CRC = T32A_PRSCLx_32;
TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(INTT32A00C_IRQn);
}
uint32_t us_ticker_read(void)
{
if (!us_ticker_inited) {
us_ticker_init();
}
return (TSB_T32A0->TMRC);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
NVIC_DisableIRQ(INTT32A00C_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->RGC1 = timestamp;
NVIC_EnableIRQ(INTT32A00C_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(INTT32A00C_IRQn);
NVIC_EnableIRQ(INTT32A00C_IRQn);
}
void us_ticker_disable_interrupt(void)
{
// Disable interrupts by NVIC
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
NVIC_DisableIRQ(INTT32A00C_IRQn);
}
void us_ticker_clear_interrupt(void)
{
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
}
void us_ticker_free(void)
{
TSB_CG_FSYSENA_IPENA26 = TXZ_DISABLE;
us_ticker_inited = false;
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
// Disable and clear interrupts in NVIC
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
NVIC_DisableIRQ(INTT32A00C_IRQn);
}

130
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PeripheralNames.h
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@ -1,130 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
SERIAL_2,
SERIAL_3,
SERIAL_4,
SERIAL_5,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
ADC_AINA00 = 0,
ADC_AINA01,
ADC_AINA02,
ADC_AINA03,
ADC_AINA04,
ADC_AINA05,
ADC_AINA06,
ADC_AINA07,
ADC_AINA08,
ADC_AINA09,
ADC_AINA10,
ADC_AINA11,
ADC_AINA12,
ADC_AINA13,
ADC_AINA14,
ADC_AINA15,
ADC_AINA16,
ADC_AINA17,
ADC_AINA18,
ADC_AINA19,
ADC_AINA20,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
DAC_A0 = 0,
DAC_A1,
INVALID_DAC = (int)NC
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1,
SPI_2,
SPI_3,
SPI_4,
INVALID_SPI = (int)NC
} SPIName;
typedef enum {
I2C_0 = 0,
I2C_1,
I2C_2,
I2C_3,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
GPIO_IRQ_00 = 0,
GPIO_IRQ_01,
GPIO_IRQ_02,
GPIO_IRQ_03,
GPIO_IRQ_04,
GPIO_IRQ_05,
GPIO_IRQ_06,
GPIO_IRQ_07,
GPIO_IRQ_08,
GPIO_IRQ_09,
GPIO_IRQ_10,
GPIO_IRQ_11,
GPIO_IRQ_12,
GPIO_IRQ_13,
GPIO_IRQ_14,
GPIO_IRQ_15,
GPIO_IRQ_16,
GPIO_IRQ_17_18,
GPIO_IRQ_19_22,
GPIO_IRQ_23_26,
GPIO_IRQ_27_28,
GPIO_IRQ_29,
GPIO_IRQ_30_31,
INVALID_GPIO_IRQ = (int)NC
} gpio_irqname;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART SERIAL_1
#ifdef __cplusplus
}
#endif
#endif

145
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PinNames.h
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@ -1,145 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM3HQ Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6,
PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6,
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5,
PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7,
PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7,
PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7,
PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5,
PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7,
PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7,
PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7,
PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5,
PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7,
// LED
LED1 = PK4,
LED2 = PK5,
LED3 = PK6,
LED4 = PK7,
// External data bus Pin Names
D0 = PV7,
D1 = PV6,
D2 = PC4,
D3 = PK2,
D4 = PC3,
D5 = PJ0,
D6 = PN0,
D7 = PM6,
D8 = PT0,
D9 = PG2,
D10 = PT1,
D11 = PT3,
D12 = PT4,
D13 = PT2,
D14 = PC1,
D15 = PC0,
// Analogue out pins
A0 = PF2,
A1 = PF3,
A2 = PF4,
A3 = PF5,
A4 = PF6,
A5 = PF7,
// DAC
DAC0 = PG0,
DAC1 = PG1,
// DAP_UART
USBTX = PJ1,
USBRX = PJ2,
MBEDIF_TXD = USBTX,
MBEDIF_RXD = USBRX,
// Push buttons
SW1 = PV0,
SW2 = PV1,
SW3 = PV2,
SW4 = PV3,
// Standardized button names
BUTTON1 = SW1,
BUTTON2 = SW2,
BUTTON3 = SW3,
BUTTON4 = SW4,
// TSPI2
MOSI = D11,
MISO = D12,
SCLK = D13,
CS = D10,
// SD Shield TSPI2
SD_SEL = CS, // Chip select
SD_CLK = SCLK, // SPI clock
SD_MISO = MISO, // Master in Salve out
SD_MOSI = MOSI, // Master out Salve in
// I2C pins
SDA = D14,
SCL = D15,
I2C_SDA = SDA,
I2C_SCL = SCL,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault
} PinMode;
typedef enum {
DISABLE = 0,
ENABLE
} FunctionalState;
#ifdef __cplusplus
}
#endif
#endif

50
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PortNames.h
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@ -1,50 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ,
PortK,
PortL,
PortM,
PortN,
PortP,
PortR,
PortT,
PortU,
PortV
} PortName;
#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number
#ifdef __cplusplus
}
#endif
#endif

103
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogin_api.c
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_ADC[] = {
{PD0, ADC_AINA00, PIN_DATA(0, 0)},
{PD1, ADC_AINA01, PIN_DATA(0, 0)},
{PD2, ADC_AINA02, PIN_DATA(0, 0)},
{PD3, ADC_AINA03, PIN_DATA(0, 0)},
{PE0, ADC_AINA04, PIN_DATA(0, 0)},
{PE1, ADC_AINA05, PIN_DATA(0, 0)},
{PE2, ADC_AINA06, PIN_DATA(0, 0)},
{PE3, ADC_AINA07, PIN_DATA(0, 0)},
{PE4, ADC_AINA08, PIN_DATA(0, 0)},
{PE5, ADC_AINA09, PIN_DATA(0, 0)},
{PE6, ADC_AINA10, PIN_DATA(0, 0)},
{PF0, ADC_AINA11, PIN_DATA(0, 0)},
{PF1, ADC_AINA12, PIN_DATA(0, 0)},
{PF2, ADC_AINA13, PIN_DATA(0, 0)},
{PF3, ADC_AINA14, PIN_DATA(0, 0)},
{PF4, ADC_AINA15, PIN_DATA(0, 0)},
{PF5, ADC_AINA16, PIN_DATA(0, 0)},
{PF6, ADC_AINA17, PIN_DATA(0, 0)},
{PF7, ADC_AINA18, PIN_DATA(0, 0)},
{PD4, ADC_AINA19, PIN_DATA(0, 0)},
{PD5, ADC_AINA20, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->obj = TSB_ADA;
TSB_CG_FSYSENB_IPENB15 = ENABLE; // ADC CG Fsys Enable
TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable
pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC
obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); // Set sample hold time and pre-scale clock
obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON);
obj->obj->MOD1 = ADC_MOD1_AVDD5_3V;
obj->obj->MOD2 = ADC_MOD2_TMPM3Hx;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t ADCResultValue = 0;
uint32_t ADCResultStored = 0;
wait_us(300); // Wait at least 300us to ensure the voltage is stable
obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion
obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion
obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE |
ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE);
while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) {
// Wait until AD conversion complete
}
wait_us(30); // Wait for register to update with convert value.
ADCResultStored = (obj->obj->REG0 | obj->adc); // Convert result
if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) {
ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4);
}
return ADCResultValue;
}
float analogin_read(analogin_t *obj)
{
float result = 0.0;
uint16_t value = 0;
value = analogin_read_u16(obj);
result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE));
return result;
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

105
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogout_api.c
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@ -1,105 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_DAC[] = {
{DAC0, DAC_A0, PIN_DATA(0, 3)},
{DAC1, DAC_A1, PIN_DATA(0, 3)},
{NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin)
{
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module
MBED_ASSERT(obj->dac != (DACName)NC);
pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC
TSB_CG_FSYSENA_IPENA06 = ENABLE;
if (obj->dac == DAC_A0) { // Compute handler
obj->handler = TSB_DA0;
TSB_CG_FSYSENB_IPENB17 = ENABLE;
} else {
if (obj->dac == DAC_A1) {
obj->handler = TSB_DA1;
TSB_CG_FSYSENB_IPENB18 = ENABLE;
} else {
obj->handler = NULL;
}
}
obj->handler->CTL = DAC_STOP;
}
void analogout_free(dac_t *obj)
{
obj->handler->CTL = DAC_STOP;
}
void analogout_write(dac_t *obj, float value)
{
uint8_t outputcode = 0;
// Enable DAC
obj->handler->CTL = DAC_START;
if (value < 0.0f) {
value = 0.0f;
} else {
if (value >= 1.0f) {
value = 1.0f;
}
}
outputcode = (uint8_t)(value * 255.0f);
obj->handler->REG = outputcode;
wait_ms(3);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
// Enable DAC
obj->handler->CTL = DAC_START;
obj->handler->REG = (uint8_t)(value & 0xFF);
wait_ms(3);
}
float analogout_read(dac_t *obj)
{
float result = 0.0;
uint32_t value = 0;
value = ((obj->handler->REG) & (0xFF));
result = ((float)value / 255.0f);
return result;
}
uint16_t analogout_read_u16(dac_t *obj)
{
uint16_t value = 0;
value = (uint16_t)((obj->handler->REG) & (0xFF));
return value;
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c
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@ -1,74 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "crc_api.h"
#include "device.h"
#ifdef DEVICE_CRC
static bool reflect_in;
static bool reflect_out;
static uint32_t final_xor;
void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
{
TSB_CG_FSYSENB_IPENB20 = 1;
// Intial Value as initial_xor
TSB_CRC->CLC = config->initial_xor;
reflect_in = config->reflect_in;
reflect_out = config->reflect_out;
final_xor = config->final_xor;
// Data width setting CRC data width is 8 bits (--01)
// Form setting CRC form is CRC16 (00--) or CRC32 (11--)
TSB_CRC->TYP = config->width == 16 ? 0x01 : 0x0D;
}
void hal_crc_compute_partial(const uint8_t *data, const size_t size)
{
if (data && size) {
uint32_t index = 0U;
bool reflect = reflect_in;
for(index = 0U; index < size; index++) {
unsigned int byte = data[index];
if (reflect) {
byte = __RBIT(byte) >> 24;
}
TSB_CRC->DIN = byte;
}
}
}
uint32_t hal_crc_get_result(void)
{
uint32_t result;
// Note: Please read [CRCCLC] twice and use the result of the 2nd time
result = TSB_CRC->CLC;
result = TSB_CRC->CLC;
if (reflect_out) {
result = __RBIT(result);
if ((TSB_CRC->TYP & 0x0C) == 0) {
result >>= 16;
}
}
result ^= final_xor;
return (result);
}
#endif // DEVICE_CRC

24
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h
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@ -1,24 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define TRANSACTION_QUEUE_SIZE_SPI 4
#include "objects.h"
#endif

4539
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TMPM3HQ.h
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613
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S
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@ -1,613 +0,0 @@
;/**
; *******************************************************************************
; * @file startup_TMPM3HQ.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for the
; * TOSHIBA 'TMPM3HQ' Device Series
; * @version V1.0.0.0
; * $Date:: 2017-12-08 #$
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
; *
; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt Pin 00
DCD INT01_IRQHandler ; 1: Interrupt Pin 01
DCD INT02_IRQHandler ; 2: Interrupt Pin 02
DCD INT03_IRQHandler ; 3: Interrupt Pin 03
DCD INT04_IRQHandler ; 4: Interrupt Pin 04
DCD INT05_IRQHandler ; 5: Interrupt Pin 05
DCD INT06_IRQHandler ; 6: Interrupt Pin 06
DCD INT07_IRQHandler ; 7: Interrupt Pin 07
DCD INT08_IRQHandler ; 8: Interrupt Pin 08
DCD INT09_IRQHandler ; 9: Interrupt Pin 09
DCD INT10_IRQHandler ; 10: Interrupt Pin 10
DCD INT11_IRQHandler ; 11: Interrupt Pin 11
DCD INT12_IRQHandler ; 12: Interrupt Pin 12
DCD INT13_IRQHandler ; 13: Interrupt Pin 13
DCD INT14_IRQHandler ; 14: Interrupt Pin 14
DCD INT15_IRQHandler ; 15: Interrupt Pin 15
DCD INT16_IRQHandler ; 16: Interrupt Pin 16
DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18
DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22
DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26
DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28
DCD INT29_IRQHandler ; 21: Interrupt Pin 29
DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31
DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt
DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt
DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt
DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0
DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1
DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A
DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B
DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0
DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1
DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished
DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished
DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished
DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0)
DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0)
DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0)
DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1)
DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1)
DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1)
DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2)
DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2)
DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2)
DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3)
DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3)
DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3)
DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4)
DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4)
DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4)
DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0)
DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt
DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt
DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt
DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt
DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt
DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt
DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt
DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt
DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt
DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt
DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt
DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt
DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt
DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt
DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt
DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt
DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0)
DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0)
DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0)
DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1)
DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1)
DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1)
DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2)
DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2)
DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2)
DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3)
DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3)
DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3)
DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4)
DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4)
DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4)
DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5)
DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5)
DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5)
DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow
DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0
DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1
DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow
DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0
DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1
DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow
DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0
DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1
DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow
DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0
DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1
DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow
DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0
DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1
DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow
DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0
DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1
DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow
DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0
DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1
DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow
DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0
DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1
DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow
DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0
DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1
DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow
DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0
DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1
DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow
DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0
DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1
DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow
DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0
DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1
DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow
DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0
DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1
DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow
DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0
DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1
DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow
DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0
DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1
DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow
DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0
DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1
DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow
DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0
DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1
DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow
DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0
DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1
DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow
DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0
DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1
DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow
DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0
DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1
DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow
DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0
DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1
DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow
DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0
DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1
DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow
DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0
DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1
DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow
DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0
DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1
DCD INTPARI_IRQHandler ; 157: RAM parity interrupt
DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer
DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error
DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer
DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error
DCD INTRTC_IRQHandler ; 162: Real time clock interrupt
DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt
DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt
DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT00_IRQHandler [WEAK]
EXPORT INT01_IRQHandler [WEAK]
EXPORT INT02_IRQHandler [WEAK]
EXPORT INT03_IRQHandler [WEAK]
EXPORT INT04_IRQHandler [WEAK]
EXPORT INT05_IRQHandler [WEAK]
EXPORT INT06_IRQHandler [WEAK]
EXPORT INT07_IRQHandler [WEAK]
EXPORT INT08_IRQHandler [WEAK]
EXPORT INT09_IRQHandler [WEAK]
EXPORT INT10_IRQHandler [WEAK]
EXPORT INT11_IRQHandler [WEAK]
EXPORT INT12_IRQHandler [WEAK]
EXPORT INT13_IRQHandler [WEAK]
EXPORT INT14_IRQHandler [WEAK]
EXPORT INT15_IRQHandler [WEAK]
EXPORT INT16_IRQHandler [WEAK]
EXPORT INT17_18_IRQHandler [WEAK]
EXPORT INT19_22_IRQHandler [WEAK]
EXPORT INT23_26_IRQHandler [WEAK]
EXPORT INT27_28_IRQHandler [WEAK]
EXPORT INT29_IRQHandler [WEAK]
EXPORT INT30_31_IRQHandler [WEAK]
EXPORT INTEMG0_IRQHandler [WEAK]
EXPORT INTOVV0_IRQHandler [WEAK]
EXPORT INTPMD0_IRQHandler [WEAK]
EXPORT INTENC00_IRQHandler [WEAK]
EXPORT INTENC01_IRQHandler [WEAK]
EXPORT INTADAPDA_IRQHandler [WEAK]
EXPORT INTADAPDB_IRQHandler [WEAK]
EXPORT INTADACP0_IRQHandler [WEAK]
EXPORT INTADACP1_IRQHandler [WEAK]
EXPORT INTADATRG_IRQHandler [WEAK]
EXPORT INTADASGL_IRQHandler [WEAK]
EXPORT INTADACNT_IRQHandler [WEAK]
EXPORT INTT0RX_IRQHandler [WEAK]
EXPORT INTT0TX_IRQHandler [WEAK]
EXPORT INTT0ERR_IRQHandler [WEAK]
EXPORT INTT1RX_IRQHandler [WEAK]
EXPORT INTT1TX_IRQHandler [WEAK]
EXPORT INTT1ERR_IRQHandler [WEAK]
EXPORT INTT2RX_IRQHandler [WEAK]
EXPORT INTT2TX_IRQHandler [WEAK]
EXPORT INTT2ERR_IRQHandler [WEAK]
EXPORT INTT3RX_IRQHandler [WEAK]
EXPORT INTT3TX_IRQHandler [WEAK]
EXPORT INTT3ERR_IRQHandler [WEAK]
EXPORT INTT4RX_IRQHandler [WEAK]
EXPORT INTT4TX_IRQHandler [WEAK]
EXPORT INTT4ERR_IRQHandler [WEAK]
EXPORT INTI2CWUP_IRQHandler [WEAK]
EXPORT INTI2C0_IRQHandler [WEAK]
EXPORT INTI2C0AL_IRQHandler [WEAK]
EXPORT INTI2C0BF_IRQHandler [WEAK]
EXPORT INTI2C0NA_IRQHandler [WEAK]
EXPORT INTI2C1_IRQHandler [WEAK]
EXPORT INTI2C1AL_IRQHandler [WEAK]
EXPORT INTI2C1BF_IRQHandler [WEAK]
EXPORT INTI2C1NA_IRQHandler [WEAK]
EXPORT INTI2C2_IRQHandler [WEAK]
EXPORT INTI2C2AL_IRQHandler [WEAK]
EXPORT INTI2C2BF_IRQHandler [WEAK]
EXPORT INTI2C2NA_IRQHandler [WEAK]
EXPORT INTI2C3_IRQHandler [WEAK]
EXPORT INTI2C3AL_IRQHandler [WEAK]
EXPORT INTI2C3BF_IRQHandler [WEAK]
EXPORT INTI2C3NA_IRQHandler [WEAK]
EXPORT INTUART0RX_IRQHandler [WEAK]
EXPORT INTUART0TX_IRQHandler [WEAK]
EXPORT INTUART0ERR_IRQHandler [WEAK]
EXPORT INTUART1RX_IRQHandler [WEAK]
EXPORT INTUART1TX_IRQHandler [WEAK]
EXPORT INTUART1ERR_IRQHandler [WEAK]
EXPORT INTUART2RX_IRQHandler [WEAK]
EXPORT INTUART2TX_IRQHandler [WEAK]
EXPORT INTUART2ERR_IRQHandler [WEAK]
EXPORT INTUART3RX_IRQHandler [WEAK]
EXPORT INTUART3TX_IRQHandler [WEAK]
EXPORT INTUART3ERR_IRQHandler [WEAK]
EXPORT INTUART4RX_IRQHandler [WEAK]
EXPORT INTUART4TX_IRQHandler [WEAK]
EXPORT INTUART4ERR_IRQHandler [WEAK]
EXPORT INTUART5RX_IRQHandler [WEAK]
EXPORT INTUART5TX_IRQHandler [WEAK]
EXPORT INTUART5ERR_IRQHandler [WEAK]
EXPORT INTT32A00A_IRQHandler [WEAK]
EXPORT INTT32A00ACAP0_IRQHandler [WEAK]
EXPORT INTT32A00ACAP1_IRQHandler [WEAK]
EXPORT INTT32A00B_IRQHandler [WEAK]
EXPORT INTT32A00BCAP0_IRQHandler [WEAK]
EXPORT INTT32A00BCAP1_IRQHandler [WEAK]
EXPORT INTT32A00C_IRQHandler [WEAK]
EXPORT INTT32A00CCAP0_IRQHandler [WEAK]
EXPORT INTT32A00CCAP1_IRQHandler [WEAK]
EXPORT INTT32A01A_IRQHandler [WEAK]
EXPORT INTT32A01ACAP0_IRQHandler [WEAK]
EXPORT INTT32A01ACAP1_IRQHandler [WEAK]
EXPORT INTT32A01B_IRQHandler [WEAK]
EXPORT INTT32A01BCAP0_IRQHandler [WEAK]
EXPORT INTT32A01BCAP1_IRQHandler [WEAK]
EXPORT INTT32A01C_IRQHandler [WEAK]
EXPORT INTT32A01CCAP0_IRQHandler [WEAK]
EXPORT INTT32A01CCAP1_IRQHandler [WEAK]
EXPORT INTT32A02A_IRQHandler [WEAK]
EXPORT INTT32A02ACAP0_IRQHandler [WEAK]
EXPORT INTT32A02ACAP1_IRQHandler [WEAK]
EXPORT INTT32A02B_IRQHandler [WEAK]
EXPORT INTT32A02BCAP0_IRQHandler [WEAK]
EXPORT INTT32A02BCAP1_IRQHandler [WEAK]
EXPORT INTT32A02C_IRQHandler [WEAK]
EXPORT INTT32A02CCAP0_IRQHandler [WEAK]
EXPORT INTT32A02CCAP1_IRQHandler [WEAK]
EXPORT INTT32A03A_IRQHandler [WEAK]
EXPORT INTT32A03ACAP0_IRQHandler [WEAK]
EXPORT INTT32A03ACAP1_IRQHandler [WEAK]
EXPORT INTT32A03B_IRQHandler [WEAK]
EXPORT INTT32A03BCAP0_IRQHandler [WEAK]
EXPORT INTT32A03BCAP1_IRQHandler [WEAK]
EXPORT INTT32A03C_IRQHandler [WEAK]
EXPORT INTT32A03CCAP0_IRQHandler [WEAK]
EXPORT INTT32A03CCAP1_IRQHandler [WEAK]
EXPORT INTT32A04A_IRQHandler [WEAK]
EXPORT INTT32A04ACAP0_IRQHandler [WEAK]
EXPORT INTT32A04ACAP1_IRQHandler [WEAK]
EXPORT INTT32A04B_IRQHandler [WEAK]
EXPORT INTT32A04BCAP0_IRQHandler [WEAK]
EXPORT INTT32A04BCAP1_IRQHandler [WEAK]
EXPORT INTT32A04C_IRQHandler [WEAK]
EXPORT INTT32A04CCAP0_IRQHandler [WEAK]
EXPORT INTT32A04CCAP1_IRQHandler [WEAK]
EXPORT INTT32A05A_IRQHandler [WEAK]
EXPORT INTT32A05ACAP0_IRQHandler [WEAK]
EXPORT INTT32A05ACAP1_IRQHandler [WEAK]
EXPORT INTT32A05B_IRQHandler [WEAK]
EXPORT INTT32A05BCAP0_IRQHandler [WEAK]
EXPORT INTT32A05BCAP1_IRQHandler [WEAK]
EXPORT INTT32A05C_IRQHandler [WEAK]
EXPORT INTT32A05CCAP0_IRQHandler [WEAK]
EXPORT INTT32A05CCAP1_IRQHandler [WEAK]
EXPORT INTT32A06A_IRQHandler [WEAK]
EXPORT INTT32A06ACAP0_IRQHandler [WEAK]
EXPORT INTT32A06ACAP1_IRQHandler [WEAK]
EXPORT INTT32A06B_IRQHandler [WEAK]
EXPORT INTT32A06BCAP0_IRQHandler [WEAK]
EXPORT INTT32A06BCAP1_IRQHandler [WEAK]
EXPORT INTT32A06C_IRQHandler [WEAK]
EXPORT INTT32A06CCAP0_IRQHandler [WEAK]
EXPORT INTT32A06CCAP1_IRQHandler [WEAK]
EXPORT INTT32A07A_IRQHandler [WEAK]
EXPORT INTT32A07ACAP0_IRQHandler [WEAK]
EXPORT INTT32A07ACAP1_IRQHandler [WEAK]
EXPORT INTT32A07B_IRQHandler [WEAK]
EXPORT INTT32A07BCAP0_IRQHandler [WEAK]
EXPORT INTT32A07BCAP1_IRQHandler [WEAK]
EXPORT INTT32A07C_IRQHandler [WEAK]
EXPORT INTT32A07CCAP0_IRQHandler [WEAK]
EXPORT INTT32A07CCAP1_IRQHandler [WEAK]
EXPORT INTPARI_IRQHandler [WEAK]
EXPORT INTDMAATC_IRQHandler [WEAK]
EXPORT INTDMAAERR_IRQHandler [WEAK]
EXPORT INTDMABTC_IRQHandler [WEAK]
EXPORT INTDMABERR_IRQHandler [WEAK]
EXPORT INTRTC_IRQHandler [WEAK]
EXPORT INTRMC0_IRQHandler [WEAK]
EXPORT INTFLCRDY_IRQHandler [WEAK]
EXPORT INTFLDRDY_IRQHandler [WEAK]
INT00_IRQHandler
INT01_IRQHandler
INT02_IRQHandler
INT03_IRQHandler
INT04_IRQHandler
INT05_IRQHandler
INT06_IRQHandler
INT07_IRQHandler
INT08_IRQHandler
INT09_IRQHandler
INT10_IRQHandler
INT11_IRQHandler
INT12_IRQHandler
INT13_IRQHandler
INT14_IRQHandler
INT15_IRQHandler
INT16_IRQHandler
INT17_18_IRQHandler
INT19_22_IRQHandler
INT23_26_IRQHandler
INT27_28_IRQHandler
INT29_IRQHandler
INT30_31_IRQHandler
INTEMG0_IRQHandler
INTOVV0_IRQHandler
INTPMD0_IRQHandler
INTENC00_IRQHandler
INTENC01_IRQHandler
INTADAPDA_IRQHandler
INTADAPDB_IRQHandler
INTADACP0_IRQHandler
INTADACP1_IRQHandler
INTADATRG_IRQHandler
INTADASGL_IRQHandler
INTADACNT_IRQHandler
INTT0RX_IRQHandler
INTT0TX_IRQHandler
INTT0ERR_IRQHandler
INTT1RX_IRQHandler
INTT1TX_IRQHandler
INTT1ERR_IRQHandler
INTT2RX_IRQHandler
INTT2TX_IRQHandler
INTT2ERR_IRQHandler
INTT3RX_IRQHandler
INTT3TX_IRQHandler
INTT3ERR_IRQHandler
INTT4RX_IRQHandler
INTT4TX_IRQHandler
INTT4ERR_IRQHandler
INTI2CWUP_IRQHandler
INTI2C0_IRQHandler
INTI2C0AL_IRQHandler
INTI2C0BF_IRQHandler
INTI2C0NA_IRQHandler
INTI2C1_IRQHandler
INTI2C1AL_IRQHandler
INTI2C1BF_IRQHandler
INTI2C1NA_IRQHandler
INTI2C2_IRQHandler
INTI2C2AL_IRQHandler
INTI2C2BF_IRQHandler
INTI2C2NA_IRQHandler
INTI2C3_IRQHandler
INTI2C3AL_IRQHandler
INTI2C3BF_IRQHandler
INTI2C3NA_IRQHandler
INTUART0RX_IRQHandler
INTUART0TX_IRQHandler
INTUART0ERR_IRQHandler
INTUART1RX_IRQHandler
INTUART1TX_IRQHandler
INTUART1ERR_IRQHandler
INTUART2RX_IRQHandler
INTUART2TX_IRQHandler
INTUART2ERR_IRQHandler
INTUART3RX_IRQHandler
INTUART3TX_IRQHandler
INTUART3ERR_IRQHandler
INTUART4RX_IRQHandler
INTUART4TX_IRQHandler
INTUART4ERR_IRQHandler
INTUART5RX_IRQHandler
INTUART5TX_IRQHandler
INTUART5ERR_IRQHandler
INTT32A00A_IRQHandler
INTT32A00ACAP0_IRQHandler
INTT32A00ACAP1_IRQHandler
INTT32A00B_IRQHandler
INTT32A00BCAP0_IRQHandler
INTT32A00BCAP1_IRQHandler
INTT32A00C_IRQHandler
INTT32A00CCAP0_IRQHandler
INTT32A00CCAP1_IRQHandler
INTT32A01A_IRQHandler
INTT32A01ACAP0_IRQHandler
INTT32A01ACAP1_IRQHandler
INTT32A01B_IRQHandler
INTT32A01BCAP0_IRQHandler
INTT32A01BCAP1_IRQHandler
INTT32A01C_IRQHandler
INTT32A01CCAP0_IRQHandler
INTT32A01CCAP1_IRQHandler
INTT32A02A_IRQHandler
INTT32A02ACAP0_IRQHandler
INTT32A02ACAP1_IRQHandler
INTT32A02B_IRQHandler
INTT32A02BCAP0_IRQHandler
INTT32A02BCAP1_IRQHandler
INTT32A02C_IRQHandler
INTT32A02CCAP0_IRQHandler
INTT32A02CCAP1_IRQHandler
INTT32A03A_IRQHandler
INTT32A03ACAP0_IRQHandler
INTT32A03ACAP1_IRQHandler
INTT32A03B_IRQHandler
INTT32A03BCAP0_IRQHandler
INTT32A03BCAP1_IRQHandler
INTT32A03C_IRQHandler
INTT32A03CCAP0_IRQHandler
INTT32A03CCAP1_IRQHandler
INTT32A04A_IRQHandler
INTT32A04ACAP0_IRQHandler
INTT32A04ACAP1_IRQHandler
INTT32A04B_IRQHandler
INTT32A04BCAP0_IRQHandler
INTT32A04BCAP1_IRQHandler
INTT32A04C_IRQHandler
INTT32A04CCAP0_IRQHandler
INTT32A04CCAP1_IRQHandler
INTT32A05A_IRQHandler
INTT32A05ACAP0_IRQHandler
INTT32A05ACAP1_IRQHandler
INTT32A05B_IRQHandler
INTT32A05BCAP0_IRQHandler
INTT32A05BCAP1_IRQHandler
INTT32A05C_IRQHandler
INTT32A05CCAP0_IRQHandler
INTT32A05CCAP1_IRQHandler
INTT32A06A_IRQHandler
INTT32A06ACAP0_IRQHandler
INTT32A06ACAP1_IRQHandler
INTT32A06B_IRQHandler
INTT32A06BCAP0_IRQHandler
INTT32A06BCAP1_IRQHandler
INTT32A06C_IRQHandler
INTT32A06CCAP0_IRQHandler
INTT32A06CCAP1_IRQHandler
INTT32A07A_IRQHandler
INTT32A07ACAP0_IRQHandler
INTT32A07ACAP1_IRQHandler
INTT32A07B_IRQHandler
INTT32A07BCAP0_IRQHandler
INTT32A07BCAP1_IRQHandler
INTT32A07C_IRQHandler
INTT32A07CCAP0_IRQHandler
INTT32A07CCAP1_IRQHandler
INTPARI_IRQHandler
INTDMAATC_IRQHandler
INTDMAAERR_IRQHandler
INTDMABTC_IRQHandler
INTDMABERR_IRQHandler
INTRTC_IRQHandler
INTRMC0_IRQHandler
INTFLCRDY_IRQHandler
INTFLDRDY_IRQHandler
B .
ENDP
END

49
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct
View File

@ -1,49 +0,0 @@
#! armcc -E
;; TMPM3HQFDFG scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 MBED_APP_START MBED_APP_SIZE
{
ER_IROM1 MBED_APP_START MBED_APP_SIZE
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200002D8 (0x10000 - 0x2D8 - Stack_Size)
{
tmpm3hq_fc.o (+RO)
.ANY (+RW, +ZI)
}
ARM_LIB_STACK (0x20000000+0x10000) EMPTY -Stack_Size { ; stack
}
}

582
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S
View File

@ -1,582 +0,0 @@
/**
*******************************************************************************
* @file startup_TMPM3HQ.s
* @brief CMSIS Cortex-M3 Core Device Startup File for the
* TOSHIBA 'TMPM3HQ' Device Series
* @version V5.00
* @date 2016/03/02
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop // Top of Stack
.long Reset_Handler // Reset Handler
.long NMI_Handler // NMI Handler
.long HardFault_Handler // Hard Fault Handler
.long MemManage_Handler // MPU Fault Handler
.long BusFault_Handler // Bus Fault Handler
.long UsageFault_Handler // Usage Fault Handler
.long 0 // Reserved
.long 0 // Reserved
.long 0 // Reserved
.long 0 // Reserved
.long SVC_Handler // SVCall Handler
.long DebugMon_Handler // Debug Monitor Handler
.long 0 // Reserved
.long PendSV_Handler // PendSV Handler
.long SysTick_Handler // SysTick Handler
// External interrupts
.long INT00_IRQHandler // 0: Interrupt Pin0
.long INT01_IRQHandler // 1: Interrupt Pin1
.long INT02_IRQHandler // 2: Interrupt Pin2
.long INT03_IRQHandler // 3: Interrupt Pin3
.long INT04_IRQHandler // 4: Interrupt Pin4
.long INT05_IRQHandler // 5: Interrupt Pin5
.long INT06_IRQHandler // 6: Interrupt Pin6
.long INT07_IRQHandler // 7: Interrupt Pin7
.long INT08_IRQHandler // 8: Interrupt Pin8
.long INT09_IRQHandler // 9: Interrupt Pin9
.long INT10_IRQHandler // 10: Interrupt Pin10
.long INT11_IRQHandler // 11: Interrupt Pin11
.long INT12_IRQHandler // 12: Interrupt Pin12
.long INT13_IRQHandler // 13: Interrupt Pin13
.long INT14_IRQHandler // 14: Interrupt Pin14
.long INT15_IRQHandler // 15: Interrupt Pin15
.long INT16_IRQHandler // 16: Interrupt Pin 16
.long INT17_18_IRQHandler // 17: Interrupt Pin 17_18
.long INT19_22_IRQHandler // 18: Interrupt Pin 19_22
.long INT23_26_IRQHandler // 19: Interrupt Pin 23_26
.long INT27_28_IRQHandler // 20: Interrupt Pin 27_28
.long INT29_IRQHandler // 21: Interrupt Pin 29
.long INT30_31_IRQHandler // 22: Interrupt Pin 30_31
.long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt
.long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt
.long INTPMD0_IRQHandler // 25: PMD0 interrupt
.long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0
.long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1
.long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A
.long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B
.long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0
.long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1
.long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished
.long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished
.long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished
.long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0)
.long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0)
.long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0)
.long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1)
.long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1)
.long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1)
.long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2)
.long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2)
.long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2)
.long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3)
.long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3)
.long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3)
.long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4)
.long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4)
.long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4)
.long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0)
.long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt
.long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt
.long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt
.long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt
.long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt
.long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt
.long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt
.long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt
.long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt
.long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt
.long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt
.long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt
.long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt
.long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt
.long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt
.long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt
.long INTUART0RX_IRQHandler // 67: UART reception (channel 0)
.long INTUART0TX_IRQHandler // 68: UART transmit (channel 0)
.long INTUART0ERR_IRQHandler // 69: UART error (channel 0)
.long INTUART1RX_IRQHandler // 70: UART reception (channel 1)
.long INTUART1TX_IRQHandler // 71: UART transmit (channel 1)
.long INTUART1ERR_IRQHandler // 72: UART error (channel 1)
.long INTUART2RX_IRQHandler // 73: UART reception (channel 2)
.long INTUART2TX_IRQHandler // 74: UART transmit (channel 2)
.long INTUART2ERR_IRQHandler // 75: UART error (channel 2)
.long INTUART3RX_IRQHandler // 76: UART reception (channel 3)
.long INTUART3TX_IRQHandler // 77: UART transmit (channel 3)
.long INTUART3ERR_IRQHandler // 78: UART error (channel 3)
.long INTUART4RX_IRQHandler // 79: UART reception (channel 4)
.long INTUART4TX_IRQHandler // 80: UART transmit (channel 4)
.long INTUART4ERR_IRQHandler // 81: UART error (channel 4)
.long INTUART5RX_IRQHandler // 82: UART reception (channel 5)
.long INTUART5TX_IRQHandler // 83: UART transmit (channel 5)
.long INTUART5ERR_IRQHandler // 84: UART error (channel 5)
.long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow
.long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0
.long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1
.long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow
.long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0
.long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1
.long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow
.long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0
.long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1
.long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow
.long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0
.long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1
.long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow
.long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0
.long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1
.long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow
.long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0
.long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1
.long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow
.long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0
.long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1
.long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow
.long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0
.long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1
.long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow
.long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0
.long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1
.long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow
.long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0
.long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1
.long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow
.long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0
.long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1
.long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow
.long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0
.long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1
.long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow
.long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0
.long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1
.long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow
.long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0
.long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1
.long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow
.long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0
.long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1
.long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow
.long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0
.long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1
.long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow
.long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0
.long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1
.long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow
.long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0
.long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1
.long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow
.long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0
.long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1
.long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow
.long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0
.long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1
.long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow
.long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0
.long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1
.long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow
.long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0
.long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1
.long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow
.long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0
.long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1
.long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow
.long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0
.long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1
.long INTPARI_IRQHandler // 157: RAM parity interrupt
.long INTDMAATC_IRQHandler // 158: DMAA end of transfer
.long INTDMAAERR_IRQHandler // 159: DMAA transfer error
.long INTDMABTC_IRQHandler // 160: DMAB end of transfer
.long INTDMABERR_IRQHandler // 161: DMAB transfer error
.long INTRTC_IRQHandler // 162: Real time clock interrupt
.long INTRMC0_IRQHandler // 163: Remote control reception interrupt
.long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt
.long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT00_IRQHandler
def_irq_handler INT01_IRQHandler
def_irq_handler INT02_IRQHandler
def_irq_handler INT03_IRQHandler
def_irq_handler INT04_IRQHandler
def_irq_handler INT05_IRQHandler
def_irq_handler INT06_IRQHandler
def_irq_handler INT07_IRQHandler
def_irq_handler INT08_IRQHandler
def_irq_handler INT09_IRQHandler
def_irq_handler INT10_IRQHandler
def_irq_handler INT11_IRQHandler
def_irq_handler INT12_IRQHandler
def_irq_handler INT13_IRQHandler
def_irq_handler INT14_IRQHandler
def_irq_handler INT15_IRQHandler
def_irq_handler INT16_IRQHandler
def_irq_handler INT17_18_IRQHandler
def_irq_handler INT19_22_IRQHandler
def_irq_handler INT23_26_IRQHandler
def_irq_handler INT27_28_IRQHandler
def_irq_handler INT29_IRQHandler
def_irq_handler INT30_31_IRQHandler
def_irq_handler INTEMG0_IRQHandler
def_irq_handler INTOVV0_IRQHandler
def_irq_handler INTPMD0_IRQHandler
def_irq_handler INTENC00_IRQHandler
def_irq_handler INTENC01_IRQHandler
def_irq_handler INTADAPDA_IRQHandler
def_irq_handler INTADAPDB_IRQHandler
def_irq_handler INTADACP0_IRQHandler
def_irq_handler INTADACP1_IRQHandler
def_irq_handler INTADATRG_IRQHandler
def_irq_handler INTADASGL_IRQHandler
def_irq_handler INTADACNT_IRQHandler
def_irq_handler INTT0RX_IRQHandler
def_irq_handler INTT0TX_IRQHandler
def_irq_handler INTT0ERR_IRQHandler
def_irq_handler INTT1RX_IRQHandler
def_irq_handler INTT1TX_IRQHandler
def_irq_handler INTT1ERR_IRQHandler
def_irq_handler INTT2RX_IRQHandler
def_irq_handler INTT2TX_IRQHandler
def_irq_handler INTT2ERR_IRQHandler
def_irq_handler INTT3RX_IRQHandler
def_irq_handler INTT3TX_IRQHandler
def_irq_handler INTT3ERR_IRQHandler
def_irq_handler INTT4RX_IRQHandler
def_irq_handler INTT4TX_IRQHandler
def_irq_handler INTT4ERR_IRQHandler
def_irq_handler INTI2CWUP_IRQHandler
def_irq_handler INTI2C0_IRQHandler
def_irq_handler INTI2C0AL_IRQHandler
def_irq_handler INTI2C0BF_IRQHandler
def_irq_handler INTI2C0NA_IRQHandler
def_irq_handler INTI2C1_IRQHandler
def_irq_handler INTI2C1AL_IRQHandler
def_irq_handler INTI2C1BF_IRQHandler
def_irq_handler INTI2C1NA_IRQHandler
def_irq_handler INTI2C2_IRQHandler
def_irq_handler INTI2C2AL_IRQHandler
def_irq_handler INTI2C2BF_IRQHandler
def_irq_handler INTI2C2NA_IRQHandler
def_irq_handler INTI2C3_IRQHandler
def_irq_handler INTI2C3AL_IRQHandler
def_irq_handler INTI2C3BF_IRQHandler
def_irq_handler INTI2C3NA_IRQHandler
def_irq_handler INTUART0RX_IRQHandler
def_irq_handler INTUART0TX_IRQHandler
def_irq_handler INTUART0ERR_IRQHandler
def_irq_handler INTUART1RX_IRQHandler
def_irq_handler INTUART1TX_IRQHandler
def_irq_handler INTUART1ERR_IRQHandler
def_irq_handler INTUART2RX_IRQHandler
def_irq_handler INTUART2TX_IRQHandler
def_irq_handler INTUART2ERR_IRQHandler
def_irq_handler INTUART3RX_IRQHandler
def_irq_handler INTUART3TX_IRQHandler
def_irq_handler INTUART3ERR_IRQHandler
def_irq_handler INTUART4RX_IRQHandler
def_irq_handler INTUART4TX_IRQHandler
def_irq_handler INTUART4ERR_IRQHandler
def_irq_handler INTUART5RX_IRQHandler
def_irq_handler INTUART5TX_IRQHandler
def_irq_handler INTUART5ERR_IRQHandler
def_irq_handler INTT32A00A_IRQHandler
def_irq_handler INTT32A00ACAP0_IRQHandler
def_irq_handler INTT32A00ACAP1_IRQHandler
def_irq_handler INTT32A00B_IRQHandler
def_irq_handler INTT32A00BCAP0_IRQHandler
def_irq_handler INTT32A00BCAP1_IRQHandler
def_irq_handler INTT32A00C_IRQHandler
def_irq_handler INTT32A00CCAP0_IRQHandler
def_irq_handler INTT32A00CCAP1_IRQHandler
def_irq_handler INTT32A01A_IRQHandler
def_irq_handler INTT32A01ACAP0_IRQHandler
def_irq_handler INTT32A01ACAP1_IRQHandler
def_irq_handler INTT32A01B_IRQHandler
def_irq_handler INTT32A01BCAP0_IRQHandler
def_irq_handler INTT32A01BCAP1_IRQHandler
def_irq_handler INTT32A01C_IRQHandler
def_irq_handler INTT32A01CCAP0_IRQHandler
def_irq_handler INTT32A01CCAP1_IRQHandler
def_irq_handler INTT32A02A_IRQHandler
def_irq_handler INTT32A02ACAP0_IRQHandler
def_irq_handler INTT32A02ACAP1_IRQHandler
def_irq_handler INTT32A02B_IRQHandler
def_irq_handler INTT32A02BCAP0_IRQHandler
def_irq_handler INTT32A02BCAP1_IRQHandler
def_irq_handler INTT32A02C_IRQHandler
def_irq_handler INTT32A02CCAP0_IRQHandler
def_irq_handler INTT32A02CCAP1_IRQHandler
def_irq_handler INTT32A03A_IRQHandler
def_irq_handler INTT32A03ACAP0_IRQHandler
def_irq_handler INTT32A03ACAP1_IRQHandler
def_irq_handler INTT32A03B_IRQHandler
def_irq_handler INTT32A03BCAP0_IRQHandler
def_irq_handler INTT32A03BCAP1_IRQHandler
def_irq_handler INTT32A03C_IRQHandler
def_irq_handler INTT32A03CCAP0_IRQHandler
def_irq_handler INTT32A03CCAP1_IRQHandler
def_irq_handler INTT32A04A_IRQHandler
def_irq_handler INTT32A04ACAP0_IRQHandler
def_irq_handler INTT32A04ACAP1_IRQHandler
def_irq_handler INTT32A04B_IRQHandler
def_irq_handler INTT32A04BCAP0_IRQHandler
def_irq_handler INTT32A04BCAP1_IRQHandler
def_irq_handler INTT32A04C_IRQHandler
def_irq_handler INTT32A04CCAP0_IRQHandler
def_irq_handler INTT32A04CCAP1_IRQHandler
def_irq_handler INTT32A05A_IRQHandler
def_irq_handler INTT32A05ACAP0_IRQHandler
def_irq_handler INTT32A05ACAP1_IRQHandler
def_irq_handler INTT32A05B_IRQHandler
def_irq_handler INTT32A05BCAP0_IRQHandler
def_irq_handler INTT32A05BCAP1_IRQHandler
def_irq_handler INTT32A05C_IRQHandler
def_irq_handler INTT32A05CCAP0_IRQHandler
def_irq_handler INTT32A05CCAP1_IRQHandler
def_irq_handler INTT32A06A_IRQHandler
def_irq_handler INTT32A06ACAP0_IRQHandler
def_irq_handler INTT32A06ACAP1_IRQHandler
def_irq_handler INTT32A06B_IRQHandler
def_irq_handler INTT32A06BCAP0_IRQHandler
def_irq_handler INTT32A06BCAP1_IRQHandler
def_irq_handler INTT32A06C_IRQHandler
def_irq_handler INTT32A06CCAP0_IRQHandler
def_irq_handler INTT32A06CCAP1_IRQHandler
def_irq_handler INTT32A07A_IRQHandler
def_irq_handler INTT32A07ACAP0_IRQHandler
def_irq_handler INTT32A07ACAP1_IRQHandler
def_irq_handler INTT32A07B_IRQHandler
def_irq_handler INTT32A07BCAP0_IRQHandler
def_irq_handler INTT32A07BCAP1_IRQHandler
def_irq_handler INTT32A07C_IRQHandler
def_irq_handler INTT32A07CCAP0_IRQHandler
def_irq_handler INTT32A07CCAP1_IRQHandler
def_irq_handler INTPARI_IRQHandler
def_irq_handler INTDMAATC_IRQHandler
def_irq_handler INTDMAAERR_IRQHandler
def_irq_handler INTDMABTC_IRQHandler
def_irq_handler INTDMABERR_IRQHandler
def_irq_handler INTRTC_IRQHandler
def_irq_handler INTRMC0_IRQHandler
def_irq_handler INTFLCRDY_IRQHandler
def_irq_handler INTFLDRDY_IRQHandler
.end

177
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld
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@ -1,177 +0,0 @@
/* Linker script for Toshiba TMPM3HQ */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 512K
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* 8_byte_aligned((166 + 16) vect * 4 bytes) = 8_byte_aligned(0x2D8) = 0x2D8 */
RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8)
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
*(.ram_func*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

1107
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S
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File diff suppressed because it is too large Load Diff

55
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf
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@ -1,55 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
/*Heap 1/4 of ram and stack 1/8*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define symbol __BRAM_start__ = 0x20010000;
define symbol __BRAM_end__ = 0x200107FF;
define symbol __DFLASH_start__ = 0x30000000;
define symbol __DFLASH_end__ = 0x30007FFF;
define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ];
define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
initialize by copy { section RAMCODE };
/* Place both in a block */
define block RamCode { section RAMCODE };
define block RamCodeInit { section RAMCODE_init };
/* Place them in ROM and RAM */
place in ROM_region { block RamCodeInit };
place in RAM_region { block RamCode };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in BRAM_region { section .backup_ram };
place in DFLASH_region { section .data_flash };

22
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis.h
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@ -1,22 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM3HQ.h"
#include "cmsis_nvic.h"
#endif

24
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/cmsis_nvic.h
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@ -1,24 +0,0 @@
/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000
#define NVIC_USER_IRQ_NUMBER 166
#define NVIC_NUM_VECTORS (16 + 166) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

340
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/system_TMPM3HQ.c
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@ -1,340 +0,0 @@
/**
*******************************************************************************
* @file system_TMPM3Hy.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM3Hy' Device Series
* @version 0.0.5.0
* $Date:: 2017-07-01 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
#include "TMPM3HQ.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
#define SYSCR_Val (0x00000000UL)
#define STBYCR_Val (0x00000000UL)
#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */
#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */
#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */
#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */
#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */
#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */
#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */
#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */
#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001)
#if (CLOCK_SETUP)
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
#define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL
#else
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000)
#define PLL0SEL_Ready CG_10M_MUL_8_FPLL
#endif
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
#define PLL0SEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define EOSC_6M (6000000UL)
#define EOSC_8M (8000000UL)
#define EOSC_10M (10000000UL)
#define EOSC_12M (12000000UL)
#define IOSC_10M (10000000UL)
#define EXTALH EOSC_12M /* External high-speed oscillator freq */
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */
#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */
#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */
#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
#if (CLOCK_SETUP)
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#else
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#endif
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (CLOCK_SETUP)
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (IXTALH)
#endif
#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL))
#define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL))
#define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 6MHz */
#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL))
#define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL))
#define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL)
#define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL)
#define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL)
#define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL)
#define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U )
#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{ /* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t CoreClockInput = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pll0sel = 0U;
uint32_t pll0on = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = IXTALH;
}
regval = TSB_CG->PLL0SEL;
pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
if (pll0sel && pll0on) { /* If PLL enabled */
if (CoreClock == EOSC_6M) { /* If input is 6MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) {
CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) {
CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) {
CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) {
CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) {
CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) {
CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) {
CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) {
CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else { /* If PLL not used */
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U: /* Gear -> fc */
SystemCoreClock = CoreClockInput;
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
if (CoreClockInput >= EOSC_8M) {
SystemCoreClock = CoreClockInput / 8U;
} else {
SystemCoreClock = 0U;
}
break;
case 4U: /* Gear -> fc/16 */
if (CoreClockInput > EOSC_12M) {
SystemCoreClock = CoreClockInput / 16U;
} else {
SystemCoreClock = 0U;
}
break;
case 5U:
case 6U:
case 7U:
SystemCoreClock = 0U;
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
#if (SIWD_SETUP) /* Watchdog Setup */
/* SIWD Disable */
TSB_SIWD0->EN = SIWDEN_Val;
TSB_SIWD0->CR = SIWDCR_Val;
#else
/* SIWD Enable (Setting after a Reset) */
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = SYSCR_Val;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
while (!TSB_CG_OSCCR_OSCF) {
;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
#else
/* Internal HOSC Enable (Setting after a Reset) */
#endif
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLL0SEL_Ready;
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Lockup */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
while (!TSB_CG_PLL0SEL_PLL0ST) {
;
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
}

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