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[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 2

pull/1076/head
ohagendorf 2015-04-26 01:47:43 +02:00
parent 2ad8ff1853
commit dbb04307e3
57 changed files with 21529 additions and 7565 deletions
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2307
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h Normal file
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271
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@ -17,37 +17,40 @@
control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
to interface with PCCARD devices. This driver is used for:
(+) PCCARD/compact flash memory configuration sequence using the function
HAL_PCCARD_Init() with control and timing parameters for both common and
attribute spaces.
(+) PCCARD/Compact Flash memory configuration sequence using the function
HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
both common and attribute spaces.
(+) Read PCCARD/compact flash memory maker and device IDs using the function
HAL_CF_Read_ID(). The read information is stored in the CompactFlash_ID
structure declared by the function caller.
(+) Read PCCARD/Compact Flash memory maker and device IDs using the function
HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
the CompactFlash_ID structure declared by the function caller.
(+) Access PCCARD/compact flash memory by read/write operations using the functions
(+) Access PCCARD/Compact Flash memory by read/write operations using the functions
HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
(+) Perform PCCARD/compact flash Reset chip operation using the function HAL_CF_Reset().
(+) Perform PCCARD/Compact Flash Reset chip operation using the function
HAL_PCCARD_Reset()/HAL_CF_Reset.
(+) Perform PCCARD/compact flash erase sector operation using the function
HAL_CF_Erase_Sector().
(+) Perform PCCARD/Compact Flash erase sector operation using the function
HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
(+) Read the PCCARD/compact flash status operation using the function HAL_CF_ReadStatus().
(+) Read the PCCARD/Compact Flash status operation using the function
HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
(+) You can monitor the PCCARD/compact flash device HAL state by calling the function
HAL_PCCARD_GetState()
(+) You can monitor the PCCARD/Compact Flash device HAL state by calling
the function HAL_PCCARD_GetState()/HAL_CF_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
operations. If a PCCARD/compact flash device contains different operations
operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -81,25 +84,39 @@
* @{
*/
/** @defgroup PCCARD
* @brief PCCARD driver modules
#ifdef HAL_PCCARD_MODULE_ENABLED
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @defgroup PCCARD PCCARD
* @brief PCCARD HAL module driver
* @{
*/
#ifdef HAL_PCCARD_MODULE_ENABLED
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
* @{
*/
#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFF
#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400
#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PCCARD_Private_Functions
/* Private function ----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
* @{
*/
/** @defgroup PCCARD_Group1 Initialization and de-initialization functions
/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -133,6 +150,8 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
if(hpccard->State == HAL_PCCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpccard->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
}
@ -215,7 +234,7 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
* @}
*/
/** @defgroup PCCARD_Group2 Input and Output functions
/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@ -238,10 +257,10 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
* @retval HAL status
*
*/
HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
uint32_t timeout = 0xFFFF, index;
uint8_t status;
uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -255,31 +274,31 @@ HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactF
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize the CF status */
*pStatus = CF_READY;
/* Initialize the PCCARD status */
*pStatus = PCCARD_READY;
/* Send the Identify Command */
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = 0xECEC;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
/* Read CF IDs and timeout treatment */
/* Read PCCARD IDs and timeout treatment */
do
{
/* Read the CF status */
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
/* Read the PCCARD status */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != 0x58) && timeout);
}while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
/* Read CF ID bytes */
/* Read PCCARD ID bytes */
for(index = 0; index < 16; index++)
{
CompactFlash_ID[index] = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_DATA);
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
}
@ -298,13 +317,13 @@ HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactF
* the configuration information for PCCARD module.
* @param pBuffer: pointer to destination read buffer
* @param SectorAddress: Sector address to read
* @param pStatus: pointer to CF status
* @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = 0xFFFF, index = 0;
uint8_t status;
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -318,44 +337,44 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pB
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize CF status */
*pStatus = CF_READY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0xE4A0;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status == 0x80) && timeout);
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
timeout = 0xFFFF;
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
/* wait till the Status = 0x58 */
status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
/* wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != 0x58) && timeout);
}while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Read bytes */
for(; index < CF_SECTOR_SIZE; index++)
for(; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)pBuffer++ = *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR);
*(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
}
/* Update the PCCARD controller state */
@ -374,13 +393,13 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pB
* the configuration information for PCCARD module.
* @param pBuffer: pointer to source write buffer
* @param SectorAddress: Sector address to write
* @param pStatus: pointer to CF status
* @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = 0xFFFF, index = 0;
uint8_t status;
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -394,42 +413,42 @@ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize CF status */
*pStatus = CF_READY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0x30A0;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
/* Wait till the Status = 0x58 */
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
/* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != 0x58) && timeout);
}while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
for(; index < CF_SECTOR_SIZE; index++)
for(; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
/* Wait till the Status = 0x50 */
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != 0x50) && timeout);
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
@ -447,13 +466,13 @@ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param SectorAddress: Sector address to erase
* @param pStatus: pointer to CF status
* @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = 0x400;
uint8_t status;
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -467,29 +486,29 @@ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t S
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize CF status */
*pStatus = CF_READY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_LOW) = 0x00;
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = 0x00;
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_NUMBER) = SectorAddress;
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = 0x01;
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CARD_HEAD) = 0xA0;
*(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = CF_ERASE_SECTOR_CMD;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
/* wait till the CF is ready */
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
/* wait till the PCCARD is ready */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while((status != 0x50) && timeout)
while((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
*pStatus = CF_TIMEOUT_ERROR;
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Check the PCCARD controller state */
@ -507,9 +526,8 @@ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t S
* the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
/* Process Locked */
__HAL_LOCK(hpccard);
@ -519,17 +537,17 @@ HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
return HAL_BUSY;
}
/* Provide an SW reset and Read and verify the:
- CF Configuration Option Register at address 0x98000200 --> 0x80
- Card Configuration and Status Register at address 0x98000202 --> 0x00
- Pin Replacement Register at address 0x98000204 --> 0x0C
/* Provide a SW reset and Read and verify the:
- PCCard Configuration Option Register at address 0x98000200 --> 0x80
- Card Configuration and Status Register at address 0x98000202 --> 0x00
- Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
*(__IO uint8_t *)(0x98000202) = 0x01;
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
@ -587,7 +605,6 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
}
}
/**
@ -607,7 +624,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
* @}
*/
/** @defgroup PCCARD_Group4 State functions
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
@verbatim
@ -637,37 +654,36 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
* @brief Get the compact flash memory status
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval New status of the CF operation. This parameter can be:
* @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - CompactFlash_READY: when memory is ready for the next operation
*
* - CompactFlash_READY: when memory is ready for the next operation
*/
CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
uint32_t timeout = 0x1000000, status_CF;
uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return CF_ONGOING;
return HAL_PCCARD_STATUS_ONGOING;
}
status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while((status_CF == CF_BUSY) && timeout)
while((status_pccard == PCCARD_BUSY) && timeout)
{
status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
status_CF = CF_TIMEOUT_ERROR;
status_pccard = PCCARD_TIMEOUT_ERROR;
}
/* Return the operation status */
return (CF_StatusTypedef) status_CF;
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
@ -677,31 +693,31 @@ CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
* - CompactFlash_ERROR: when the previous operation gererates error
* - CompactFlash_ERROR: when the previous operation generates error
*/
CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
uint8_t data = 0, status_CF = CF_BUSY;
uint8_t data = 0, status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return CF_ONGOING;
return HAL_PCCARD_STATUS_ONGOING;
}
/* Read status operation */
data = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
if((data & CF_TIMEOUT_ERROR) == CF_TIMEOUT_ERROR)
if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
{
status_CF = CF_TIMEOUT_ERROR;
status_pccard = PCCARD_TIMEOUT_ERROR;
}
else if((data & CF_READY) == CF_READY)
else if((data & PCCARD_READY) == PCCARD_READY)
{
status_CF = CF_READY;
status_pccard = PCCARD_READY;
}
return (CF_StatusTypedef) status_CF;
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
@ -711,8 +727,9 @@ CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* HAL_PCCARD_MODULE_ENABLED */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
* @}

236
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -44,11 +44,11 @@
#endif
/* Includes ------------------------------------------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#include "stm32f4xx_ll_fmc.h"
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
@ -56,16 +56,20 @@
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @addtogroup PCCARD
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
* @brief HAL PCCARD State structures definition
*/
typedef enum
{
@ -74,14 +78,14 @@ typedef enum
HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
}HAL_PCCARD_StateTypeDef;
typedef enum
{
CF_SUCCESS = 0,
CF_ONGOING,
CF_ERROR,
CF_TIMEOUT
}CF_StatusTypedef;
HAL_PCCARD_STATUS_SUCCESS = 0,
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
}HAL_PCCARD_StatusTypeDef;
/**
* @brief FMC_PCCARD handle Structure definition
@ -97,81 +101,159 @@ typedef struct
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
}PCCARD_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Constants
* @{
*/
#define CF_DEVICE_ADDRESS ((uint32_t)0x90000000)
#define CF_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
#define CF_COMMON_SPACE_ADDRESS CF_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
#define CF_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
#define CF_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
/* Compact Flash-ATA registers description */
#define CF_DATA ((uint8_t)0x00) /* Data register */
#define CF_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
#define CF_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
#define CF_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
#define CF_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
#define CF_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
#define CF_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
#define CF_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
#define CF_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
/* Compact Flash-ATA commands */
#define CF_READ_SECTOR_CMD ((uint8_t)0x20)
#define CF_WRITE_SECTOR_CMD ((uint8_t)0x30)
#define CF_ERASE_SECTOR_CMD ((uint8_t)0xC0)
#define CF_IDENTIFY_CMD ((uint8_t)0xEC)
/* Compact Flash status */
#define CF_TIMEOUT_ERROR ((uint8_t)0x60)
#define CF_BUSY ((uint8_t)0x80)
#define CF_PROGR ((uint8_t)0x01)
#define CF_READY ((uint8_t)0x40)
#define CF_SECTOR_SIZE ((uint32_t)255) /* In half words */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
* @{
*/
/** @brief Reset PCCARD handle state
* @param __HANDLE__: specifies the PCCARD handle.
* @retval None
*/
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
/* PCCARD State functions *******************************************************/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCCARD_Exported_Functions
* @{
*/
/** @addtogroup PCCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group3
* @{
*/
/* PCCARD State functions *******************************************************/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
* @{
*/
#define PCCARD_DEVICE_ADDRESS ((uint32_t)0x90000000)
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
/* Flash-ATA registers description */
#define ATA_DATA ((uint8_t)0x00) /* Data register */
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
/* Flash-ATA commands */
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
/* PC Card/Compact Flash status */
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
#define PCCARD_BUSY ((uint8_t)0x80)
#define PCCARD_PROGR ((uint8_t)0x01)
#define PCCARD_READY ((uint8_t)0x40)
#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
/**
* @}
*/
/* Compact Flash redefinition */
#define HAL_CF_Init HAL_PCCARD_Init
#define HAL_CF_DeInit HAL_PCCARD_DeInit
#define HAL_CF_MspInit HAL_PCCARD_MspInit
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
#define HAL_CF_Reset HAL_PCCARD_Reset
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
#define HAL_CF_GetState HAL_PCCARD_GetState
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
#define CF_BUSY PCCARD_BUSY
#define CF_PROGR PCCARD_PROGR
#define CF_READY PCCARD_READY
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
/* Private macros ------------------------------------------------------------*/
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/

174
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,31 +79,44 @@
* @{
*/
/** @defgroup PCD
/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/** @defgroup PCD_Private_Functions
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup PCD_Private_Functions PCD Private Functions
* @{
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/** @defgroup PCD_Group1 Initialization and de-initialization functions
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@ -153,7 +166,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[i].is_in = 1;
hpcd->IN_ep[i].num = i;
hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is actvated */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0;
hpcd->IN_ep[i].xfer_buff = 0;
@ -179,6 +192,14 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State= HAL_PCD_STATE_READY;
#ifdef USB_OTG_GLPMCFG_LPMEN
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1)
{
HAL_PCDEx_ActivateLPM(hpcd);
}
#endif /* USB_OTG_GLPMCFG_LPMEN */
USB_DevDisconnect (hpcd->Instance);
return HAL_OK;
}
@ -217,7 +238,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implenetd in the user file
the HAL_PCD_MspInit could be implemented in the user file
*/
}
@ -229,7 +250,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implenetd in the user file
the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@ -237,10 +258,10 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @}
*/
/** @defgroup PCD_Group2 IO operation functions
/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@ -276,7 +297,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
USB_DevDisconnect (hpcd->Instance);
USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -425,12 +446,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Resume Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
HAL_PCD_ResumeCallback(hpcd);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
#ifdef USB_OTG_GLPMCFG_LPMEN
if(hpcd->LPM_State == LPM_L1)
{
hpcd->LPM_State = LPM_L0;
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
}
else
#endif /* USB_OTG_GLPMCFG_LPMEN */
{
HAL_PCD_ResumeCallback(hpcd);
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
@ -444,8 +474,24 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
#ifdef USB_OTG_GLPMCFG_LPMEN
/* Handle LPM Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
if( hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
}
else
{
HAL_PCD_SuspendCallback(hpcd);
}
}
#endif /* USB_OTG_GLPMCFG_LPMEN */
/* Handle Reset Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
@ -504,8 +550,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle RxQLevel Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
@ -573,26 +618,28 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Data out stage callbacks
* @brief Data OUT stage callbacks
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callbacks
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
@ -603,7 +650,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
@ -615,7 +662,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
@ -627,7 +674,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
@ -640,7 +687,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
@ -652,31 +699,33 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callbacks
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO IN callbacks
* @brief Incomplete ISO IN callbacks
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
@ -688,7 +737,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
@ -700,18 +749,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implenetd in the user file
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PCD_Group3 Peripheral Control functions
* @brief management functions
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
@ -724,7 +773,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
* @brief Send an amount of data in blocking mode
* @brief Connect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -737,7 +786,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Send an amount of data in blocking mode
* @brief Disconnect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -766,7 +815,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
* @brief Open and configure an endpoint
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param ep_mps: endpoint max packert size
* @param ep_mps: endpoint max packet size
* @param ep_type: endpoint type
* @retval HAL status
*/
@ -845,7 +894,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
USB_OTG_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
@ -1019,43 +1067,43 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
* @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
* @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
/* active Remote wakeup signaling */
/* Activate Remote wake-up signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
* @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
/* active Remote wakeup signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
/* De-activate Remote wake-up signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup PCD_Group4 Peripheral State functions
* @brief Peripheral State functions
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
@ -1080,10 +1128,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup PCD_Private_Functions
* @{
*/
/**
* @brief DCD_WriteEmptyTxFifo
* check FIFO for the next packet to be loaded
* @param hpcd: PCD handle
* @param epnum : endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)

247
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,10 +55,13 @@
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief PCD State structures definition
*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
/**
* @brief PCD State structure definition
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
@ -68,6 +71,16 @@ typedef enum
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
#ifdef USB_OTG_GLPMCFG_LPMEN
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
}PCD_LPM_StateTypeDef;
#endif /* USB_OTG_GLPMCFG_LPMEN */
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
@ -78,23 +91,35 @@ typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
*/
typedef struct
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
void *pData; /*!< Pointer to upper stack Handler */
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
#ifdef USB_OTG_GLPMCFG_LPMEN
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */
#endif /* USB_OTG_GLPMCFG_LPMEN */
void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
/**
* @}
*/
/* Include PCD HAL Extension module */
#include "stm32f4xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup PCD_Speed
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0
@ -104,7 +129,7 @@ typedef struct
* @}
*/
/** @defgroup PCD_PHY_Module
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1
@ -112,28 +137,13 @@ typedef struct
/**
* @}
*/
/** @defgroup PCD_Instance_definition
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PCD_Interrupt_Clock
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
@ -146,85 +156,83 @@ typedef struct
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
~(USB_OTG_PCGCCTL_STOPCLK)
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define USB_FS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define USB_HS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define USB_HS_EXTI_LINE_WAKEUP ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_FS_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
#define __HAL_USB_HS_EXTI_ENABLE_IT() EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
#define __HAL_USB_HS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
#define __HAL_USB_HS_EXTI_GET_FLAG() EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
#define __HAL_USB_HS_EXTI_CLEAR_FLAG() EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
#define __HAL_USB_HS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP)
#define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
#define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
#define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
#define __HAL_USB_FS_EXTI_CLEAR_FLAG() EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_FS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* Include PCD HAL Extension module */
#include "stm32f4xx_hal_pcd_ex.h"
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/* I/O operation functions *****************************************************/
/* Non-Blocking mode: Interrupt */
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
* @{
*/
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
@ -240,8 +248,14 @@ void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/* Peripheral Control functions **********************************************/
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
@ -253,15 +267,42 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* Create an alias to keep compatibility with the old name */
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
/* Peripheral State functions **************************************************/
/* Peripheral State functions ************************************************/
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/**
* @}
*/
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}

81
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -46,29 +46,27 @@
* @{
*/
/** @defgroup PCDEx
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Private_Functions
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
@ -80,8 +78,10 @@
*/
/**
* @brief Update FIFO configuration
* @brief Set Tx FIFO
* @param hpcd: PCD handle
* @param fifo: The number of Tx fifo
* @param size: Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
@ -122,18 +122,63 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
}
/**
* @brief Update FIFO configuration
* @brief Set Rx FIFO
* @param hpcd: PCD handle
* @param size: Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
#if defined(STM32F446xx)
/**
* @brief HAL_PCDEx_ActivateLPM : active LPM Feature
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = ENABLE;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = DISABLE;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
}
#endif /* STM32F446xx */
/**
* @}
*/

37
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -53,12 +53,31 @@
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
#if defined(STM32F446xx)
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
#endif /* STM32F446xx */
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Peripheral Extended functions *********************************************/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#if defined(STM32F446xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
#endif /* STM32F446xx */
/**
* @}
@ -68,6 +87,14 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

224
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -47,7 +47,7 @@
* @{
*/
/** @defgroup PWR
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
@ -56,16 +56,34 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000)
#define PVD_MODE_EVT ((uint32_t)0x00020000)
#define PVD_RISING_EDGE ((uint32_t)0x00000001)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Private_Functions
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Group1 Initialization and de-initialization functions
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@ -78,7 +96,7 @@
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__PWR_CLK_ENABLE() macro.
__HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
@ -87,13 +105,12 @@
/**
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__PWR_FORCE_RESET();
__PWR_RELEASE_RESET();
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
@ -101,7 +118,6 @@ void HAL_PWR_DeInit(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @param None
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
@ -114,7 +130,6 @@ void HAL_PWR_EnableBkUpAccess(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @param None
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
@ -126,7 +141,7 @@ void HAL_PWR_DisableBkUpAccess(void)
* @}
*/
/** @defgroup PWR_Group2 Peripheral Control functions
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
@ -143,15 +158,16 @@ void HAL_PWR_DisableBkUpAccess(void)
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PVD_EXTI_ENABLE_IT() macro.
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** WakeUp pin configuration ***
*** Wake-up pin configuration ***
================================
[..]
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
(+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
(+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
Only for STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin 2 on PC.13
*** Low Power modes configuration ***
=====================================
@ -186,9 +202,9 @@ void HAL_PWR_DisableBkUpAccess(void)
are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption In Stop mode, FLASH can be powered off before
entering the Stop mode using the HAL_PWR_EnableFlashPowerDown() function.
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the Stop mode using
the HAL_PWR_DisableFlashPowerDown() function.
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
@ -214,18 +230,18 @@ void HAL_PWR_DisableBkUpAccess(void)
(++) Entry:
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(++) Exit:
(+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
(+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
*** Auto-wake-up (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wakeup mode).
Wake-up event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wake-up mode).
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
(+) RTC auto-wake-up (AWU) from the Stop and Standby modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
@ -234,8 +250,8 @@ void HAL_PWR_DisableBkUpAccess(void)
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
(++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
@ -250,52 +266,47 @@ void HAL_PWR_DisableBkUpAccess(void)
* detection level.
* @retval None
*/
void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= ~ (uint32_t)PWR_CR_PLS;
/* Set PLS[7:5] bits according to PVDLevel value */
tmpreg |= sConfigPVD->PVDLevel;
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
/* Store the new value */
PWR->CR = tmpreg;
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure the EXTI 16 interrupt */
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
(sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\
(sConfigPVD->Mode == PWR_MODE_IT_RISING))
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Clear the edge trigger for the EXTI Line 16 (PVD) */
EXTI->RTSR &= ~EXTI_RTSR_TR16;
EXTI->FTSR &= ~EXTI_FTSR_TR16;
/* Configure the rising edge */
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
(sConfigPVD->Mode == PWR_MODE_IT_RISING))
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
EXTI->RTSR |= PWR_EXTI_LINE_PVD;
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the falling edge */
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
(sConfigPVD->Mode == PWR_MODE_IT_FALLING))
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
EXTI->FTSR |= PWR_EXTI_LINE_PVD;
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enables the Power Voltage Detector(PVD).
* @param None
* @retval None
*/
void HAL_PWR_EnablePVD(void)
@ -305,7 +316,6 @@ void HAL_PWR_EnablePVD(void)
/**
* @brief Disables the Power Voltage Detector(PVD).
* @param None
* @retval None
*/
void HAL_PWR_DisablePVD(void)
@ -314,31 +324,37 @@ void HAL_PWR_DisablePVD(void)
}
/**
* @brief Enables the WakeUp PINx functionality.
* @brief Enables the Wake-up PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)ENABLE;
/* Enable the wake up pin */
SET_BIT(PWR->CSR, WakeUpPinx);
}
/**
* @brief Disables the WakeUp PINx functionality.
* @brief Disables the Wake-up PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)DISABLE;
/* Disable the wake up pin */
CLEAR_BIT(PWR->CSR, WakeUpPinx);
}
/**
@ -367,6 +383,9 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
@ -385,7 +404,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
/**
* @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* @note When exiting Stop mode by issuing an interrupt or a wake-up event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
@ -403,25 +422,15 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Select the regulator state in Stop mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
/* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
tmpreg |= Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
@ -432,10 +441,12 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
@ -446,16 +457,15 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
* Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pin 1 (PA0) if enabled.
* @param None
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
PWR->CR |= PWR_CR_PDDS;
SET_BIT(PWR->CR, PWR_CR_PDDS);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
@ -468,25 +478,23 @@ void HAL_PWR_EnterSTANDBYMode(void)
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
* @param None
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
/* Check PWR exti flag */
if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET)
/* Check PWR Exti flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR Exti pending bit */
__HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD);
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
/**
* @brief PWR PVD interrupt callback
* @param None
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
@ -496,6 +504,56 @@ __weak void HAL_PWR_PVDCallback(void)
*/
}
/**
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enables CORTEX M4 SEVONPEND bit.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disables CORTEX M4 SEVONPEND bit.
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/

349
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,6 +55,11 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
@ -67,45 +72,25 @@ typedef struct
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
/* Exported constants --------------------------------------------------------*/
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* Alias word address of PMODE bit */
#define PMODE_BitNumber 0x0E
#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PWR_WakeUp_Pins
* @{
*/
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
/**
* @}
*/
/** @defgroup PWR_PVD_detection_level
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
/**
* @}
*/
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
@ -115,74 +100,55 @@ typedef struct
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
(Compare internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
*/
/** @defgroup PWR_Regulator_state_in_STOP_mode
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
#define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/**
* @}
*/
/** @defgroup PWR_Flag
/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
@ -190,7 +156,6 @@ typedef struct
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
/**
* @}
*/
@ -200,7 +165,28 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
UNUSED(tmpreg); \
} while(0)
#else
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
@ -211,7 +197,14 @@ typedef struct
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
UNUSED(tmpreg); \
} while(0)
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
/** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check.
@ -244,65 +237,116 @@ typedef struct
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @brief Enable the PVD Exti Line.
* @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
* This parameter can be:
* @arg PWR_EXTI_LINE_PVD
* @brief Enable the PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
/**
* @brief Disable the PVD EXTI Line.
* @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
* This parameter can be:
* @arg PWR_EXTI_LINE_PVD
* @brief Disable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
/**
* @brief Enable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
/**
* @brief Disable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be:
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
* @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
* This parameter can be:
* @arg PWR_EXTI_LINE_PVD
* @retval EXTI PVD Line Status.
*/
#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/**
* @brief Clear the PVD Exti flag.
* @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
* This parameter can be:
* @arg PWR_EXTI_LINE_PVD
* @retval None.
*/
#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
* This parameter can be:
* @arg PWR_EXTI_LINE_PVD
* @brief Generates a Software interrupt on PVD EXTI line.
* @retval None
*/
#define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
/**
* @}
*/
/* Include PWR HAL Extension module */
#include "stm32f4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
/* PVD configuration */
void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
@ -315,9 +359,112 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
/* Power PVD IRQ Handler */
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
/* Cortex System Control functions *******************************************/
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWR_Private_Constants PWR Private Constants
* @{
*/
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/** @defgroup PWR_register_alias_address PWR Register alias address
* @{
*/
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define PWR_CR_OFFSET 0x00
#define PWR_CSR_OFFSET 0x04
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/**
* @}
*/
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
* @{
*/
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
/* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
/* Alias word address of PMODE bit */
#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
/**
* @}
*/
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
* @{
*/
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
/**
* @}
*/
/**
* @}

208
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -46,7 +46,7 @@
* @{
*/
/** @defgroup PWREx
/** @defgroup PWREx PWREx
* @brief PWR HAL module driver
* @{
*/
@ -55,19 +55,27 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWREx_Private_Constants
* @{
*/
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define PWR_BKPREG_TIMEOUT_VALUE 1000
#define PWR_VOSRDY_TIMEOUT_VALUE 1000
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWREx_Private_Functions
* @{
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @defgroup PWREx_Group1 Peripheral Extended features functions
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
* @brief Peripheral Extended features functions
*
@verbatim
@ -83,7 +91,7 @@
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
retained even in Standby or VBAT mode when the low power backup regulator
is enabled. It can be considered as an internal EEPROM when VBAT is
always present. You can use the HAL_PWR_EnableBkUpReg() function to
always present. You can use the HAL_PWREx_EnableBkUpReg() function to
enable the low power backup regulator.
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
@ -109,7 +117,7 @@
=======================================
[..]
(+) By setting the FPDS bit in the PWR_CR register by using the
HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power
HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
down mode when the device enters Stop mode. When the Flash memory
is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
@ -148,7 +156,6 @@
/**
* @brief Enables the Backup Regulator.
* @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
@ -173,7 +180,6 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
/**
* @brief Disables the Backup Regulator.
* @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
@ -198,7 +204,6 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
/**
* @brief Enables the Flash Power Down in Stop mode.
* @param None
* @retval None
*/
void HAL_PWREx_EnableFlashPowerDown(void)
@ -208,7 +213,6 @@ void HAL_PWREx_EnableFlashPowerDown(void)
/**
* @brief Disables the Flash Power Down in Stop mode.
* @param None
* @retval None
*/
void HAL_PWREx_DisableFlashPowerDown(void)
@ -216,11 +220,154 @@ void HAL_PWREx_DisableFlashPowerDown(void)
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
}
/**
* @brief Return Voltage Scaling Range.
* @retval The configured scale for the regulator voltage(VOS bit field).
* The returned value can be one of the following:
* - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
* - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
* - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
return (PWR->CR & PWR_CR_VOS);
}
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/**
* @brief Configures the main internal regulator output voltage.
* @param VoltageScaling: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
* the maximum value of fHCLK = 168 MHz.
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
* the maximum value of fHCLK = 144 MHz.
* @note When moving from Range 1 to Range 2, the system frequency must be decreased to
* a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
* When moving from Range 2 to Range 1, the system frequency can be increased to
* a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
uint32_t tickstart = 0;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Enable PWR RCC Clock Peripheral */
__HAL_RCC_PWR_CLK_ENABLE();
/* Set Range */
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
/* Get Start Tick*/
tickstart = HAL_GetTick();
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
{
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Configures the main internal regulator output voltage.
* @param VoltageScaling: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
* the maximum value of fHCLK is 168 MHz. It can be extended to
* 180 MHz by activating the over-drive mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
* the maximum value of fHCLK is 144 MHz. It can be extended to,
* 168 MHz by activating the over-drive mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
* the maximum value of fHCLK is 120 MHz.
* @note To update the system clock frequency(SYSCLK):
* - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
* - Call the HAL_RCC_OscConfig() to configure the PLL.
* - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
* - Set the new system clock frequency using the HAL_RCC_ClockConfig().
* @note The scale can be modified only when the HSI or HSE clock source is selected
* as system clock source, otherwise the API returns HAL_ERROR.
* @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
* value in the PWR_CR1 register are not taken in account.
* @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
* @note The new voltage scale is active only when the PLL is ON.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
uint32_t tickstart = 0;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Enable PWR RCC Clock Peripheral */
__HAL_RCC_PWR_CLK_ENABLE();
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
/* Disable the main PLL */
__HAL_RCC_PLL_DISABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set Range */
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
/* Enable the main PLL */
__HAL_RCC_PLL_ENABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
{
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
* @brief Enables Main Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
* @param None
* @retval None
*/
void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
@ -231,7 +378,6 @@ void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
/**
* @brief Disables Main Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
* @param None
* @retval None
*/
void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
@ -242,7 +388,6 @@ void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
/**
* @brief Enables Low Power Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
* @param None
* @retval None
*/
void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
@ -253,7 +398,6 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
/**
* @brief Disables Low Power Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
* @param None
* @retval None
*/
void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
@ -263,7 +407,7 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/**
* @brief Activates the Over-Drive mode.
* @note This function can be used only for STM32F42xx/STM32F43xx devices.
@ -273,14 +417,13 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
uint32_t tickstart = 0;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
__HAL_PWR_OVERDRIVE_ENABLE();
@ -321,14 +464,13 @@ HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
{
uint32_t tickstart = 0;
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* Disable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_DISABLE();
@ -380,7 +522,7 @@ HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
*
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* @note When exiting Stop mode by issuing an interrupt or a wake-up event,
* the HSI RC oscillator is selected as system clock.
*
* @note When the voltage regulator operates in low power mode, an additional
@ -402,7 +544,7 @@ HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
*/
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tmpreg = 0;
uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check the parameters */
@ -410,7 +552,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Enable Power ctrl clock */
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Under-drive Mode ---------------------------------------------*/
/* Clear Under-drive flag */
__HAL_PWR_CLEAR_ODRUDR_FLAG();
@ -431,15 +573,15 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
}
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
tmpreg1 = PWR->CR;
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
tmpreg |= Regulator;
tmpreg1 |= Regulator;
/* Store the new value */
PWR->CR = tmpreg;
PWR->CR = tmpreg1;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -461,7 +603,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
return HAL_OK;
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/

184
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -56,48 +56,22 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ------------- PWR registers bit address in the alias region ---------------*/
/* --- CR Register ---*/
/* Alias word address of FPDS bit */
#define FPDS_BitNumber 0x09
#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
/* Alias word address of ODEN bit */
#define ODEN_BitNumber 0x10
#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
/* Alias word address of ODSWEN bit */
#define ODSWEN_BitNumber 0x11
#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
/* Alias word address of MRLVDS bit */
#define MRLVDS_BitNumber 0x0B
#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
/* Alias word address of LPLVDS bit */
#define LPLVDS_BitNumber 0x0A
#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of BRE bit */
#define BRE_BitNumber 0x09
#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
* @{
*/
#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
/**
* @}
*/
/** @defgroup PWREx_Over_Under_Drive_Flag
/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
* @{
*/
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
@ -106,14 +80,34 @@
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
#else
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode. */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
168 MHz by activating the over-drive mode. */
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/** @brief Macros to enable or disable the Over drive mode.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
*/
@ -158,13 +152,25 @@
*/
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1
* @{
*/
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
@ -173,11 +179,99 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWREx_Private_Constants PWREx Private Constants
* @{
*/
/** @defgroup PWREx_register_alias_address PWREx Register alias address
* @{
*/
/* ------------- PWR registers bit address in the alias region ---------------*/
/* --- CR Register ---*/
/* Alias word address of FPDS bit */
#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
/* Alias word address of ODEN bit */
#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODEN_BIT_NUMBER * 4))
/* Alias word address of ODSWEN bit */
#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODSWEN_BIT_NUMBER * 4))
/* Alias word address of MRLVDS bit */
#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (MRLVDS_BIT_NUMBER * 4))
/* Alias word address of LPLVDS bit */
#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPLVDS_BIT_NUMBER * 4))
/**
* @}
*/
/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
* @{
*/
/* --- CSR Register ---*/
/* Alias word address of BRE bit */
#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWREx_Private_Macros PWREx Private Macros
* @{
*/
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#else
#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}

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@ -0,0 +1,788 @@
/**
******************************************************************************
* @file stm32f4xx_hal_qspi.h
* @author MCD Application Team
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_QSPI_H
#define __STM32F4xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
/**
* @brief HAL QSPI State structures definition
*/
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef;
/**
* @brief QSPI Handle Structure definition
*/
typedef struct
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
__IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
__IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */
}QSPI_HandleTypeDef;
/**
* @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
This parameter can be a value of @ref QSPI_AlternateBytesSize */
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
This parameter can be a number between 0 and 31 */
uint32_t InstructionMode; /* Specifies the Instruction Mode
This parameter can be a value of @ref QSPI_InstructionMode */
uint32_t AddressMode; /* Specifies the Address Mode
This parameter can be a value of @ref QSPI_AddressMode */
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer.
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
/**
* @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
This parameter can be a value of @ref QSPI_MatchMode */
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
/**
* @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
*/
/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
/**
* @}
*/
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
/**
* @}
*/
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DdrMode QSPI Ddr Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
/**
* @}
*/
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
*/
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
*/
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
*/
/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
*/
/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
/**
* @}
*/
/** @defgroup QSPI_Interrupts QSPI Interrupts
* @{
*/
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
* @{
*/
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
/** @brief Reset QSPI handle state
* @param __HANDLE__: QSPI handle.
* @retval None
*/
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
/** @brief Enable QSPI
* @param __HANDLE__: specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable QSPI
* @param __HANDLE__: specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enables the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Time out interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disables the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Checks whether the specified QSPI interrupt source is enabled.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Time out interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Get the selected QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Time out flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Time out flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
*/
/** @addtogroup QSPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
/* QSPI status flag polling mode */
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group3
* @{
*/
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI status flag polling mode */
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group4
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
/**
* @}
*/
/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
* @{
*/
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
/**
* @}
*/
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
/** @defgroup QSPI_FlashSize QSPI Flash Size
* @{
*/
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
/**
* @}
*/
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
((FLA) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE))
/** @defgroup QSPI_Instruction QSPI Instruction
* @{
*/
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
/**
* @}
*/
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
* @{
*/
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
/**
* @}
*/
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
((MODE) == QSPI_INSTRUCTION_4_LINES))
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
((MODE) == QSPI_ADDRESS_1_LINE) || \
((MODE) == QSPI_ADDRESS_2_LINES) || \
((MODE) == QSPI_ADDRESS_4_LINES))
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
((MODE) == QSPI_DATA_1_LINE) || \
((MODE) == QSPI_DATA_2_LINES) || \
((MODE) == QSPI_DATA_4_LINES))
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
/** @defgroup QSPI_Interval QSPI Interval
* @{
*/
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
/**
* @}
*/
/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
* @{
*/
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
/**
* @}
*/
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR))
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
* @{
*/
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
/**
* @}
*/
#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
((FLAG) == QSPI_FLAG_TO) || \
((FLAG) == QSPI_FLAG_SM) || \
((FLAG) == QSPI_FLAG_FT) || \
((FLAG) == QSPI_FLAG_TC) || \
((FLAG) == QSPI_FLAG_TE))
#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup QSPI_Private_Functions QSPI Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F446xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

175
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -35,11 +35,30 @@
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
##### RCC Limitations #####
==============================================================================
[..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
after the clock enable bit is set on the hardware register
(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
after the clock enable bit is set on the hardware register
[..]
Possible Workarounds:
(#) Enable the peripheral clock sometimes before the peripheral read/write
register is required.
(#) For AHB peripheral, insert two dummy read to the peripheral register.
(#) For APB peripheral, insert a dummy read to the peripheral register.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -73,7 +92,7 @@
* @{
*/
/** @defgroup RCC
/** @defgroup RCC RCC
* @brief RCC HAL module driver
* @{
*/
@ -82,32 +101,40 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
/** @addtogroup RCC_Private_Constants
* @{
*/
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
/* Private macro -------------------------------------------------------------*/
#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
#define MCO1_PIN GPIO_PIN_8
#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define MCO2_GPIO_PORT GPIOC
#define MCO2_PIN GPIO_PIN_9
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RCC_Private_Functions
* @{
/** @defgroup RCC_Exported_Functions RCC Exported Functions
* @{
*/
/** @defgroup RCC_Group1 Initialization and de-initialization functions
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -138,7 +165,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
and if a HSE clock failure occurs(HSE used directly or through PLL as System
clock source), the System clockis automatically switched to HSI and an interrupt
clock source), the System clocks automatically switched to HSI and an interrupt
is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
(Non-Maskable Interrupt) exception vector.
@ -202,7 +229,6 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @param None
* @retval None
*/
void HAL_RCC_DeInit(void)
@ -239,9 +265,9 @@ void HAL_RCC_DeInit(void)
* @note The PLL is not disabled when used as system clock.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@ -251,9 +277,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@ -279,7 +306,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@ -316,8 +343,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
@ -422,7 +450,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
__PWR_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
@ -432,7 +460,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -447,7 +475,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -456,7 +484,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@ -464,7 +492,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -478,7 +506,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -501,7 +529,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@ -518,11 +546,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
(RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@ -636,7 +664,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@ -653,14 +682,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -670,7 +699,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -680,7 +719,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -715,7 +754,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@ -732,14 +772,13 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -749,7 +788,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -759,7 +808,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@ -804,7 +853,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @}
*/
/** @defgroup RCC_Group2 Peripheral Control functions
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
@ -859,7 +908,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* MCO1 Clock Enable */
__MCO1_CLK_ENABLE();
/* Configue the MCO1 pin in alternate function mode */
/* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
@ -877,7 +926,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* MCO2 Clock Enable */
__MCO2_CLK_ENABLE();
/* Configue the MCO2 pin in alternate function mode */
/* Configure the MCO2 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO2_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
@ -897,22 +946,20 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
* software about the failure (Clock Security System Interrupt, CSSI),
* allowing the MCU to perform rescue operations. The CSSI is linked to
* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
* @param None
* @retval None
*/
void HAL_RCC_EnableCSS(void)
{
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Clock Security System.
* @param None
* @retval None
*/
void HAL_RCC_DisableCSS(void)
{
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
}
/**
@ -943,10 +990,9 @@ void HAL_RCC_DisableCSS(void)
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
*
* @param None
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t pllm = 0, pllvco = 0, pllp = 0;
uint32_t sysclockfreq = 0;
@ -969,7 +1015,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (__RCC_PLLSRC() != 0)
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
@ -1000,7 +1046,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @param None
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
@ -1013,7 +1058,6 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @param None
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
@ -1026,7 +1070,6 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
* @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @param None
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
@ -1042,7 +1085,7 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
* will be configured.
* @retval None
*/
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
@ -1116,7 +1159,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/**
* @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
* @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
* @param pFLatency: Pointer on the Flash Latency.
* @retval None
@ -1145,7 +1188,6 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
/**
* @brief This function handles the RCC CSS interrupt request.
* @note This API should be called under the NMI_Handler().
* @param None
* @retval None
*/
void HAL_RCC_NMI_IRQHandler(void)
@ -1154,7 +1196,7 @@ void HAL_RCC_NMI_IRQHandler(void)
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
HAL_RCC_CCSCallback();
HAL_RCC_CSSCallback();
/* Clear RCC CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
@ -1163,13 +1205,12 @@ void HAL_RCC_NMI_IRQHandler(void)
/**
* @brief RCC Clock Security System interrupt callback
* @param none
* @retval none
* @retval None
*/
__weak void HAL_RCC_CCSCallback(void)
__weak void HAL_RCC_CSSCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RCC_CCSCallback could be implemented in the user file
the HAL_RCC_CSSCallback could be implemented in the user file
*/
}

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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h
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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@ -15,20 +15,21 @@
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
[..]
The RNG HAL driver can be used as follows:
(#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro.
(#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro.
(#) Wait until the 32 bit Random Number Generator contains a valid
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function.
(#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
in HAL_RNG_MspInit().
(#) Activate the RNG peripheral using HAL_RNG_Init() function.
(#) Wait until the 32 bit Random Number Generator contains a valid
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -62,8 +63,7 @@
* @{
*/
/** @defgroup RNG
* @brief RNG HAL module driver.
/** @addtogroup RNG
* @{
*/
@ -72,22 +72,31 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define RNG_TIMEOUT_VALUE 1000
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNG_Private_Functions
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RNG_Private_Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
* @{
*/
/** @defgroup RNG_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
/** @addtogroup RNG_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@ -97,14 +106,13 @@
(+) DeInitialize the RNG peripheral
(+) Initialize the RNG MSP
(+) DeInitialize RNG MSP
@endverbatim
* @{
*/
/**
* @brief Initializes the RNG according to the specified
* parameters in the RNG_InitTypeDef and creates the associated handle.
* @brief Initializes the RNG peripheral and creates the associated handle.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
@ -116,12 +124,17 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
return HAL_ERROR;
}
__HAL_LOCK(hrng);
if(hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@ -130,7 +143,9 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
__HAL_UNLOCK(hrng);
/* Return function status */
return HAL_OK;
}
@ -143,22 +158,16 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
/* Check the RNG peripheral state */
if(hrng->State == HAL_RNG_STATE_BUSY)
/* Check the RNG handle allocation */
if(hrng == HAL_NULL)
{
return HAL_BUSY;
return HAL_ERROR;
}
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Disable the RNG Peripheral */
__HAL_RNG_DISABLE(hrng);
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Set the RNG registers to their reset values */
hrng->Instance->CR &= 0xFFFFFFF3;
hrng->Instance->SR &= 0xFFFFFF98;
hrng->Instance->DR &= 0x0;
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
@ -181,8 +190,8 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RNG_MspInit could be implemented in the user file
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
}
@ -194,8 +203,8 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RNG_MspDeInit could be implemented in the user file
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
}
@ -203,8 +212,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
* @}
*/
/** @defgroup RNG_Group2 Peripheral Control functions
* @brief management functions.
/** @addtogroup RNG_Exported_Functions_Group2
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
@ -215,51 +224,182 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
(+) Get the 32 bit Random number with interrupt enabled
(+) Handle RNG interrupt request
@endverbatim
* @{
*/
/**
* @brief Returns a 32-bit random number.
* @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
* @param random32bit: pointer to generated random number variable if successful.
* @retval HAL status
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
uint32_t random32bit = 0;
uint32_t tickstart = 0;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
/* Check RNG peripheral state */
if(hrng->State == HAL_RNG_STATE_READY)
{
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Get a 32bit Random number */
random32bit = hrng->Instance->DR;
/* Check if data register contains valid random data */
while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return HAL_TIMEOUT;
}
}
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
*random32bit = hrng->RandomNumber;
hrng->State = HAL_RNG_STATE_READY;
}
else
{
status = HAL_ERROR;
}
/* Process Unlocked */
__HAL_UNLOCK(hrng);
/* Return the 32 bit random number */
return random32bit;
return status;
}
/**
* @brief Returns a 32-bit random number with interrupt enabled.
* @brief Generates a 32-bit random number in interrupt mode.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
if(hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hrng);
status = HAL_ERROR;
}
return status;
}
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User has
* to check that the clock controller is correctly configured to provide
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
* The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
* @note In the case of a seed error, the generation of random numbers is
* interrupted as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
* or CEIS are set.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
/* RNG clock error interrupt occurred */
if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
HAL_RNG_ErrorCallback(hrng);
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
}
/* Check RNG data ready interrupt occurred */
if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
if(hrng->State != HAL_RNG_STATE_ERROR)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
/* Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
}
}
}
/**
* @brief Returns generated random number in polling mode (Obsolete)
* Use HAL_RNG_GenerateRandomNumber() API instead.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval Random value
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
{
if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
{
return hrng->RandomNumber;
}
else
{
return 0;
}
}
/**
* @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
* Use HAL_RNG_GenerateRandomNumber_IT() API instead.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
@ -268,7 +408,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
uint32_t random32bit = 0;
/* Process Locked */
/* Process locked */
__HAL_LOCK(hrng);
/* Change RNG peripheral state */
@ -285,84 +425,27 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
}
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User has
* to check that the clock controller is correctly configured to provide
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG().
* The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
* @note In the case of a seed error, the generation of random numbers is
* interrupted as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
* @brief Read latest generated random number.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
* @retval random value
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
/* RNG clock error interrupt occurred */
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
{
HAL_RNG_ErrorCallback(hrng);
/* Clear the clock error flag */
__HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI);
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
}
/* RNG seed error interrupt occurred */
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
{
HAL_RNG_ErrorCallback(hrng);
/* Clear the seed error flag */
__HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI);
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
}
/* Check RNG data ready flag */
if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET)
{
/* Data Ready callback */
HAL_RNG_ReadyCallback(hrng);
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
/* Clear the RNG Data Ready flag */
__HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY);
/* Process Unlocked */
__HAL_UNLOCK(hrng);
}
}
return(hrng->RandomNumber);
}
/**
* @brief Data Ready callback in non-blocking mode.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit: generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RNG_ReadyCallback could be implemented in the user file
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
@ -374,17 +457,17 @@ __weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RNG_ErrorCallback could be implemented in the user file
*/
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
}
/**
* @}
*/
*/
/** @defgroup RNG_Group3 Peripheral State functions
* @brief Peripheral State functions.
/** @addtogroup RNG_Exported_Functions_Group3
* @brief Peripheral State functions
*
@verbatim
===============================================================================
@ -397,7 +480,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
@endverbatim
* @{
*/
/**
* @brief Returns the RNG state.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
@ -412,7 +495,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
/**
* @}
*/
/**
* @}
*/
@ -420,6 +503,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
*/

262
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_RNG_H
@ -45,6 +45,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@ -52,15 +53,20 @@
* @{
*/
/** @addtogroup RNG
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief RNG HAL State Structure definition
*/
/** @defgroup RNG_Exported_Types RNG Exported Types
* @{
*/
/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
* @{
*/
typedef enum
{
HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
@ -72,47 +78,55 @@ typedef enum
}HAL_RNG_StateTypeDef;
/**
* @brief RNG Handle Structure definition
* @}
*/
/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
* @{
*/
typedef struct
{
RNG_TypeDef *Instance; /*!< Register base address */
RNG_TypeDef *Instance; /*!< Register base address */
HAL_LockTypeDef Lock; /*!< RNG locking object */
HAL_LockTypeDef Lock; /*!< RNG locking object */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
}RNG_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_Exported_Constants
/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
/** @defgroup RNG_Interrupt_definition
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
* @{
*/
#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */
#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
((IT) == RNG_IT_SEI))
*/
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
/**
* @}
*/
/** @defgroup RNG_Flag_definition
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
* @{
*/
#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */
#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */
#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */
*/
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
@ -121,7 +135,11 @@ typedef struct
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RNG_Exported_Macros RNG Exported Macros
* @{
*/
/** @brief Reset RNG handle state
* @param __HANDLE__: RNG Handle
@ -144,21 +162,29 @@ typedef struct
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
* @brief Gets the selected RNG's flag status.
* @brief Check the selected RNG flag status.
* @param __HANDLE__: RNG Handle
* @param __FLAG__: RNG flag
* @retval The new state of RNG_FLAG (SET or RESET).
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready
* @arg RNG_FLAG_CECS: Clock error current status
* @arg RNG_FLAG_SECS: Seed error current status
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the RNG's pending flags.
* @param __HANDLE__: RNG Handle
* @param __FLAG__: RNG flag
* @brief Clears the selected RNG flag status.
* @param __HANDLE__: RNG handle
* @param __FLAG__: RNG flag to clear
* @note WARNING: This is a dummy macro for HAL code alignment,
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
*/
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__: RNG Handle
@ -176,47 +202,163 @@ typedef struct
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param __HANDLE__: RNG Handle
* @param __INTERRUPT__: specifies the RNG interrupt source to check.
* @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready interrupt
* @arg RNG_FLAG_CECS: Clock error interrupt
* @arg RNG_FLAG_SECS: Seed error interrupt
* @retval The new state of RNG_FLAG (SET or RESET).
* @arg RNG_IT_DRDY: Data ready interrupt
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/* Exported functions --------------------------------------------------------*/
/**
* @brief Clear the RNG interrupt status flags.
* @param __HANDLE__: RNG Handle
* @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
* @retval None
*/
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
/* Initialization/de-initialization functions **********************************/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_Exported_Functions RNG Exported Functions
* @{
*/
/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
/* Peripheral Control functions ************************************************/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
/**
* @}
*/
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup RNG_Private_Types RNG Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RNG_Private_Defines RNG Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup RNG_Private_Variables RNG Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RNG_Private_Constants RNG Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RNG_Private_Macros RNG Private Macros
* @{
*/
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNG_Private_Functions RNG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

114
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@ -61,7 +61,7 @@
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__PWR_CLK_ENABLE() function.
__HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
@ -93,22 +93,22 @@
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
on an external interrupt (Auto-wakeup mode), by using the RTC alarm
or the RTC wakeup events.
on an external interrupt (Auto-wake-up mode), by using the RTC alarm
or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -142,7 +142,7 @@
* @{
*/
/** @defgroup RTC
/** @defgroup RTC RTC
* @brief RTC HAL module driver
* @{
*/
@ -156,11 +156,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTC_Private_Functions
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Group1 Initialization and de-initialization functions
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -183,7 +183,7 @@
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
initialization, calendar update or after wakeup from low power modes
initialization, calendar update or after wake-up from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
@ -218,6 +218,8 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
if(hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@ -376,7 +378,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implenetd in the user file
the HAL_RTC_MspInit could be implemented in the user file
*/
}
@ -389,7 +391,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implenetd in the user file
the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@ -397,7 +399,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
* @}
*/
/** @defgroup RTC_Group2 RTC Time and Date functions
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @brief RTC Time and Date functions
*
@verbatim
@ -418,8 +420,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@ -436,7 +438,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@ -543,10 +545,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers.
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@ -569,7 +572,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
/* Check the input parameters format */
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
@ -587,8 +590,8 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@ -603,14 +606,14 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
@ -696,8 +699,11 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@ -717,7 +723,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
@ -731,7 +737,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @}
*/
/** @defgroup RTC_Group3 RTC Alarm functions
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @brief RTC Alarm functions
*
@verbatim
@ -751,8 +757,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@ -762,8 +768,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_ALARM(sAlarm->Alarm));
assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@ -773,7 +779,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@ -937,8 +943,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@ -948,8 +954,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_ALARM(sAlarm->Alarm));
assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@ -959,7 +965,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@ -1106,7 +1112,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
@ -1122,7 +1128,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/**
* @brief Deactive the specified RTC Alarm
* @brief Deactivate the specified RTC Alarm
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
@ -1136,7 +1142,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_ALARM(Alarm));
assert_param(IS_RTC_ALARM(Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -1224,8 +1230,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
* @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@ -1234,7 +1240,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_ALARM(Alarm));
assert_param(IS_RTC_ALARM(Alarm));
if(Alarm == RTC_ALARM_A)
{
@ -1262,7 +1268,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
@ -1308,7 +1314,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
}
/* Clear the EXTI's line Flag for RTC Alarm */
__HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@ -1366,7 +1372,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @}
*/
/** @defgroup RTC_Group4 Peripheral Control functions
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@ -1387,7 +1393,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
* initialization, calendar update or after wakeup from low power modes
* initialization, calendar update or after wake-up from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
@ -1418,7 +1424,11 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
return HAL_OK;
}
/** @defgroup RTC_Group5 Peripheral State functions
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim

467
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -54,7 +54,11 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
@ -165,7 +169,7 @@ typedef struct
}RTC_AlarmTypeDef;
/**
* @brief Time Handle Structure definition
* @brief RTC Handle Structure definition
*/
typedef struct
{
@ -179,165 +183,93 @@ typedef struct
}RTC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
#define RTC_TIMEOUT_VALUE 1000
/** @defgroup RTC_Hour_Formats
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
/**
* @}
*/
/** @defgroup RTC_Output_selection_Definitions
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
((OUTPUT) == RTC_OUTPUT_WAKEUP))
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
/**
* @}
*/
/** @defgroup RTC_Asynchronous_Predivider
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
/**
* @}
*/
/** @defgroup RTC_Synchronous_Predivider
* @{
*/
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
/**
* @}
*/
/** @defgroup RTC_Time_Definitions
* @{
*/
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
/**
* @}
*/
/** @defgroup RTC_StoreOperation_Definitions
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define FORMAT_BIN ((uint32_t)0x000000000)
#define FORMAT_BCD ((uint32_t)0x000000001)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
/**
* @}
*/
/** @defgroup RTC_Year_Date_Definitions
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
@ -351,14 +283,11 @@ typedef struct
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
@ -368,48 +297,20 @@ typedef struct
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
/** @defgroup RTC_Alarm_Definitions
* @{
*/
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
@ -418,32 +319,20 @@ typedef struct
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Value
* @{
*/
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
@ -477,30 +366,13 @@ typedef struct
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
to activate alarm. */
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_None))
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)0x00008000)
@ -514,7 +386,7 @@ typedef struct
* @}
*/
/** @defgroup RTC_Flags_Definitions
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
@ -541,6 +413,9 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__: specifies the RTC handle.
@ -622,18 +497,18 @@ typedef struct
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
* @param __FLAG__: specifies the RTC Alarm Flag to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@ -655,81 +530,133 @@ typedef struct
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
/**
* @brief Enable the RTC Exti line.
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_EXTI_LINE_ALARM_EVENT
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
/* alias define maintained for legacy */
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Disable the RTC Exti line.
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_EXTI_LINE_ALARM_EVENT
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
* @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
/* alias define maintained for legacy */
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_EXTI_LINE_ALARM_EVENT
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
* @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Clear the RTC Exti flags.
* @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_EXTI_LINE_ALARM_EVENT
* @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
* @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
* @retval None
* @brief Enable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/* alias define maintained for legacy */
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
/**
* @brief Disable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Clear the RTC Alarm associated Exti line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extension module */
#include "stm32f4xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTC_Exported_Functions
* @{
*/
/** @addtogroup RTC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group2
* @{
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group3
* @{
*/
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
@ -738,16 +665,146 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group4
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
#define RTC_TIMEOUT_VALUE 1000
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
((OUTPUT) == RTC_OUTPUT_WAKEUP))
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
*/
/**
* @}

121
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@ -22,13 +22,13 @@
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
*** RTC Wakeup configuration ***
*** RTC Wake-up configuration ***
================================
[..]
(+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
function. You can also configure the RTC Wakeup timer in interrupt mode
(+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
function. You can also configure the RTC Wake-up timer in interrupt mode
using the HAL_RTC_SetWakeUpTimer_IT() function.
(+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
(+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
function.
*** TimeStamp configuration ***
@ -40,7 +40,7 @@
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
function.
(+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8) depending on the value of TSINSEL bit in
or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
or HAL_RTC_SetTimeStamp_IT() function.
@ -53,7 +53,7 @@
HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTC_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
or HAL_RTC_SetTamper_IT() function.
@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -103,7 +103,7 @@
* @{
*/
/** @defgroup RTCEx
/** @defgroup RTCEx RTCEx
* @brief RTC HAL module driver
* @{
*/
@ -117,12 +117,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTCEx_Private_Functions
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
*/
/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
* @brief RTC TimeStamp and Tamper functions
*
@verbatim
@ -151,7 +150,8 @@
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
* @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@ -210,7 +210,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
* @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@ -246,7 +247,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
/* RTC timestamp Interrupt Configuration: EXTI configuration */
__HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@ -307,8 +308,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* FORMAT_BIN: Binary data format
* FORMAT_BCD: BCD data format
* RTC_FORMAT_BIN: Binary data format
* RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@ -336,7 +337,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
if(Format == FORMAT_BIN)
if(Format == RTC_FORMAT_BIN)
{
/* Convert the TimeStamp structure parameters to Binary format */
sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
@ -368,14 +369,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -418,14 +419,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -452,7 +453,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@ -474,7 +475,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
{
assert_param(IS_TAMPER(Tamper));
assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -541,7 +542,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
}
}
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
__HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@ -604,7 +605,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
{
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
/* Clear the TIMESTAMP OverRun Flag */
/* Clear the TIMESTAMP Overrun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
/* Change TIMESTAMP state */
@ -705,7 +706,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
* @}
*/
/** @defgroup RTCEx_Group2 RTC Wake-up functions
/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
* @brief RTC Wake-up functions
*
@verbatim
@ -732,8 +733,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -765,16 +766,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
}
}
/* Clear the Wakeup Timer clock source bits in CR register */
/* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
/* Configure the Wakeup Timer counter */
/* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
/* Enable the Wakeup Timer */
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@ -801,8 +802,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@ -834,24 +835,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
}
}
/* Configure the Wakeup Timer counter */
/* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
/* Clear the Wakeup Timer clock source bits in CR register */
/* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
__HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
/* Enable the Wakeup Timer */
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@ -883,7 +884,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Disable the Wakeup Timer */
/* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
@ -954,8 +955,8 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
__HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@ -1014,7 +1015,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
*/
/** @defgroup RTCEx_Group3 Extension Peripheral Control functions
/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
* @brief Extension Peripheral Control functions
*
@verbatim
@ -1213,12 +1214,12 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
* the configuration information for RTC.
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
* @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
* @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
@ -1625,7 +1626,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
* @}
*/
/** @defgroup RTCEx_Group4 Extended features functions
/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
* @brief Extended features functions
*
@verbatim
@ -1633,7 +1634,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) RTC Alram B callback
(+) RTC Alarm B callback
(+) RTC Poll for Alarm B request
@endverbatim

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@ -0,0 +1,269 @@
/**
******************************************************************************
* @file stm32f4xx_hal_sai_ex.c
* @author MCD Application Team
* @version V1.3.0
* @date 09-March-2015
* @brief SAI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of SAI extension peripheral:
* + Extension features functions
*
@verbatim
==============================================================================
##### SAI peripheral extension features #####
==============================================================================
[..] Comparing to other previous devices, the SAI interface for STM32F446xx
devices contains the following additional features :
(+) Possibility to be clocked from PLLR
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to manage several sources to clock SAI
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup SAIEx SAIEx
* @brief SAI Extension HAL module driver
* @{
*/
#ifdef HAL_SAI_MODULE_ENABLED
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* SAI registers Masks */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SAI_Private_Functions SAI Private Functions
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
* @{
*/
/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
* @brief Extension features functions
*
@verbatim
===============================================================================
##### Extension features Functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the possible
SAI clock sources.
@endverbatim
* @{
*/
/**
* @brief Configure SAI Block synchronization mode
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval SAI Clock Input
*/
void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
{
uint32_t tmpregisterGCR = 0;
#if defined(STM32F446xx)
/* This setting must be done with both audio block (A & B) disabled */
switch(hsai->Init.SynchroExt)
{
case SAI_SYNCEXT_DISABLE :
tmpregisterGCR = 0;
break;
case SAI_SYNCEXT_IN_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCIN_0;
break;
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
break;
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
break;
}
if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
{
SAI1->GCR = tmpregisterGCR;
}
else
{
SAI2->GCR = tmpregisterGCR;
}
#endif /* STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* This setting must be done with both audio block (A & B) disabled */
switch(hsai->Init.SynchroExt)
{
case SAI_SYNCEXT_DISABLE :
tmpregisterGCR = 0;
break;
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
break;
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
break;
}
SAI1->GCR = tmpregisterGCR;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
}
/**
* @brief Get SAI Input Clock based on SAI source clock selection
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval SAI Clock Input
*/
uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
{
/* This variable used to store the SAI_CK_x (value in Hz) */
uint32_t saiclocksource = 0;
#if defined(STM32F446xx)
if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
{
saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
}
else /* SAI2_Block_A || SAI2_Block_B*/
{
saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
}
#endif /* STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
uint32_t vcoinput = 0, tmpreg = 0;
/* Check the SAI Block parameters */
assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
/* SAI Block clock source selection */
if(hsai->Instance == SAI1_Block_A)
{
__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
}
else
{
__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
}
/* VCO Input Clock value calculation */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
else
{
/* In Case the PLL Source is HSE (External Clock) */
vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
}
/* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
{
/* Configure the PLLI2S division factor */
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
saiclocksource = saiclocksource/(tmpreg);
}
else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
saiclocksource = saiclocksource/(tmpreg);
}
else /* sConfig->ClockSource == SAI_CLKSource_Ext */
{
/* Enable the External Clock selection */
__HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
saiclocksource = EXTERNAL_CLOCK_VALUE;
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/* the return result is the value of SAI clock */
return saiclocksource;
}
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SAI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

101
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h Normal file
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@ -0,0 +1,101 @@
/**
******************************************************************************
* @file stm32f4xx_hal_sai_ex.h
* @author MCD Application Team
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SAI Extension HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_SAI_EX_H
#define __STM32F4xx_HAL_SAI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup SAIEx
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAIEx_Exported_Functions
* @{
*/
/** @addtogroup SAIEx_Exported_Functions_Group1
* @{
*/
/* Extended features functions ************************************************/
void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_SAI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

202
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@ -30,14 +30,14 @@
It is used as follows:
(#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
(##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE();
(##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
(##) SDIO pins configuration for SD card
(+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE();
(+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE();
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDIO and DMA interrupt priorities using functions
@ -54,7 +54,7 @@
================================================
[..]
To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
the SD Card and put it into StandBy State (Ready for data transfer).
the SD Card and put it into Standby State (Ready for data transfer).
This function provide the following operations:
(#) Apply the SD Card initialization process at 400KHz and check the SD Card
@ -90,14 +90,14 @@
==============================
[..]
(+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
This function support only 512-byte block length (the block size should be
chosen as 512 byte).
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
This function support only 512-byte block length (the block size should be
chosen as 512 byte).
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
@ -107,13 +107,13 @@
===============================
[..]
(+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
This function support only 512-byte block length (the block size should be
chosen as 512 byte).
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
This function support only 512-byte block length (the block size should be
This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
@ -133,7 +133,7 @@
==================================
[..]
Below the list of most used macros in SD HAL driver.
(+) __HAL_SD_SDIO_ENABLE : Enable the SD device
(+) __HAL_SD_SDIO_DISABLE : Disable the SD device
(+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
@ -149,7 +149,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -179,25 +179,27 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
#ifdef HAL_SD_MODULE_ENABLED
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup SD
* @brief SD HAL module driver
/** @addtogroup SD
* @{
*/
#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SD_Private_Define
/** @addtogroup SD_Private_Defines
* @{
*/
/**
* @brief SDIO Static flags, TimeOut, FIFO Address
* @brief SDIO Data block size
*/
#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
/**
* @brief SDIO Static flags, Timeout, FIFO Address
*/
#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
@ -223,7 +225,7 @@
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)
#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
@ -271,6 +273,7 @@
* SDIO_APP_CMD should be sent before sending these commands.
*/
#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
/**
* @}
*/
@ -278,8 +281,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
/** @addtogroup SD_Private_Functions_Prototypes
* @{
*/
static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
@ -305,15 +307,15 @@ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @defgroup SD_Private_Functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SD_Exported_Functions
* @{
*/
/** @defgroup SD_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
/** @addtogroup SD_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@ -338,6 +340,8 @@ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *S
__IO HAL_SD_ErrorTypedef errorstate = SD_OK;
SD_InitTypeDef tmpinit;
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SD_MspInit(hsd);
@ -429,7 +433,7 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
* @}
*/
/** @defgroup SD_Group2 IO operation functions
/** @addtogroup SD_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
@ -451,7 +455,7 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
* @param pReadBuffer: pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
* This parameter should be 512
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to read
* @retval SD Card error state
*/
@ -490,7 +494,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
/* Configure the SD DPSM (Data Path State Machine) */
sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4);
sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
@ -522,7 +526,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
}
/* Poll on SDIO flags */
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@ -547,7 +555,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
}
/* In case of single block transfer, no need of stop transfer at all */
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@ -559,7 +571,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
tempbuff += 8;
}
}
}
}
/* Send stop transmission command in case of multiblock read */
@ -599,6 +611,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
return errorstate;
}
#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -607,6 +620,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
return errorstate;
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@ -635,7 +649,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be written
* @param BlockSize: SD card Data block size
* This parameter should be 512.
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to write
* @retval SD Card error state
*/
@ -717,7 +731,11 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
/* Write block(s) in polling mode */
if(NumberOfBlocks > 1)
{
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@ -749,8 +767,12 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
}
else
{
/* In case of single data block transfer no need of stop command at all */
/* In case of single data block transfer no need of stop command at all */
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@ -817,6 +839,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
return errorstate;
}
#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -825,6 +848,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
return errorstate;
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@ -853,7 +877,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
* @param pReadBuffer: Pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
* This paramater should be 512.
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to read.
* @retval SD Card error state
*/
@ -882,11 +906,18 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
}
/* Enable transfer interrupts */
#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_RXOVERR |\
SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_RXOVERR));
#endif /* SDIO_STA_STBITERR */
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@ -896,7 +927,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks));
HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
@ -941,7 +972,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
@ -970,7 +1001,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be read
* @param BlockSize: the SD card Data block size
* This parameter should be 512.
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to write
* @retval SD Card error state
*/
@ -999,18 +1030,25 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri
}
/* Enable transfer interrupts */
#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_TXUNDERR |\
SDIO_IT_STBITERR));
SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_TXUNDERR));
#endif /* SDIO_STA_STBITERR */
/* Configure DMA user callbacks */
hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks));
HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@ -1298,7 +1336,7 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint
{
}
/* Wait untill the card is in programming state */
/* Wait until the card is in programming state */
errorstate = SD_IsCardProgramming(hsd, &cardstate);
delay = SD_DATATIMEOUT;
@ -1365,6 +1403,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SD_XferErrorCallback(hsd);
}
#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -1373,15 +1412,22 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SD_XferErrorCallback(hsd);
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
}
}
/* Disable all SDIO peripheral interrupt sources */
#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
SDIO_IT_RXOVERR);
#endif /* SDIO_STA_STBITERR */
}
@ -1465,7 +1511,7 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
* @}
*/
/** @defgroup SD_Group3 Peripheral Control functions
/** @addtogroup SD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
@ -1578,7 +1624,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
/* Byte 10 */
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024);
pCardInfo->CardBlockSize = 512;
}
else
@ -1586,7 +1632,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
/* Not supported card type */
errorstate = SD_ERROR;
}
pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
@ -1848,8 +1894,11 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
{
return errorstate;
}
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@ -1886,6 +1935,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
return errorstate;
}
#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -1894,11 +1944,12 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
return errorstate;
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
}
count = SD_DATATIMEOUT;
while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
@ -1925,7 +1976,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
* @}
*/
/** @defgroup SD_Group4 Peripheral State functions
/** @addtogroup SD_Exported_Functions_Group4
* @brief Peripheral State functions
*
@verbatim
@ -2000,13 +2051,13 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
/* Send ACMD13 (SD_APP_STATUS) with argument as card's RCA */
sdio_cmdinitstructure.Argument = 0;
sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS;
sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;
SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS);
errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
if (errorstate != SD_OK)
{
@ -2014,7 +2065,11 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
}
/* Get status data */
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@ -2051,6 +2106,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
return errorstate;
}
#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -2059,6 +2115,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
return errorstate;
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@ -2195,7 +2252,8 @@ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatu
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
@ -2218,6 +2276,9 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
{
}
/* Disable the DMA channel */
HAL_DMA_Abort(hdma);
/* Transfer complete user callback */
HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
}
@ -2253,7 +2314,10 @@ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
while(hsd->SdTransferCplt == 0)
{
}
/* Disable the DMA channel */
HAL_DMA_Abort(hdma);
/* Transfer complete user callback */
HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
}
@ -2384,7 +2448,7 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
}
/**
* @brief Selects od Deselects the corresponding card.
* @brief Selects of Deselects the corresponding card.
* @param hsd: SD handle
* @param addr: Address of the card to be selected
* @retval SD Card error state
@ -2429,6 +2493,10 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
/* Set Power State to ON */
SDIO_PowerState_ON(hsd->Instance);
/* 1ms: required power up waiting time before starting the SD initialization
sequence */
HAL_Delay(1);
/* Enable SDIO Clock */
__HAL_SD_SDIO_ENABLE();
@ -2446,7 +2514,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
if(errorstate != SD_OK)
{
/* CMD Response TimeOut (wait for CMDSENT flag) */
/* CMD Response Timeout (wait for CMDSENT flag) */
return errorstate;
}
@ -2479,7 +2547,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
/* Check for error conditions */
errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
/* If errorstate is Command TimeOut, it is a MMC card */
/* If errorstate is Command Timeout, it is a MMC card */
/* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
or SD card 1.x */
if(errorstate == SD_OK)
@ -2799,7 +2867,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
return(SD_STREAM_WRITE_OVERRUN);
}
if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
@ -2887,7 +2955,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
else
{
/* No error flag set */
}
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@ -2931,7 +2999,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
else
{
/* No error flag set */
}
}
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
@ -3174,8 +3242,11 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
return errorstate;
}
#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
#endif /* SDIO_STA_STBITERR */
{
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
{
@ -3208,6 +3279,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
return errorstate;
}
#ifdef SDIO_STA_STBITERR
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@ -3216,6 +3288,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
return errorstate;
}
#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@ -3370,7 +3443,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
return(SD_STREAM_WRITE_OVERRUN);
}
if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
@ -3403,6 +3476,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
*/
#endif /* HAL_SD_MODULE_ENABLED */
/**
* @}
*/

188
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -50,20 +50,22 @@
* @{
*/
/** @addtogroup SD
/** @defgroup SD SD
* @brief SD HAL module driver
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SD_Exported_Types
/** @defgroup SD_Exported_Types SD Exported Types
* @{
*/
/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
* @{
*/
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
/**
* @brief SDIO Handle Structure definition
*/
typedef struct
{
SD_TypeDef *Instance; /*!< SDIO register base address */
@ -93,9 +95,12 @@ typedef struct
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
}SD_HandleTypeDef;
/**
* @brief Card Specific Data: CSD Register
* @}
*/
/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
@ -138,10 +143,13 @@ typedef struct
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CSDTypedef;
/**
* @brief Card Identification Data: CID Register
* @}
*/
/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
@ -156,10 +164,13 @@ typedef struct
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CIDTypedef;
/**
* @brief SD Card Status returned by ACMD13
* @}
*/
/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
* @{
*/
typedef struct
{
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
@ -174,10 +185,13 @@ typedef struct
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypedef;
/**
* @brief SD Card information structure
* @}
*/
/** @defgroup SD_Exported_Types_Group5 SD Card information structure
* @{
*/
typedef struct
{
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
@ -188,10 +202,13 @@ typedef struct
uint8_t CardType; /*!< SD card type */
}HAL_SD_CardInfoTypedef;
/**
* @brief SD Error status enumeration Structure definition
* @}
*/
/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
* @{
*/
typedef enum
{
/**
@ -245,10 +262,13 @@ typedef enum
SD_OK = (0)
}HAL_SD_ErrorTypedef;
/**
* @brief SD Transfer state enumeration structure
*/
* @}
*/
/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
* @{
*/
typedef enum
{
SD_TRANSFER_OK = 0, /*!< Transfer success */
@ -256,10 +276,13 @@ typedef enum
SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
}HAL_SD_TransferStateTypedef;
/**
* @brief SD Card State enumeration structure
*/
* @}
*/
/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
* @{
*/
typedef enum
{
SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
@ -273,10 +296,13 @@ typedef enum
SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
}HAL_SD_CardStateTypedef;
/**
* @brief SD Operation enumeration structure
*/
* @}
*/
/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
* @{
*/
typedef enum
{
SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
@ -285,10 +311,16 @@ typedef enum
SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
}HAL_SD_OperationTypedef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SD_Exported_Constants
/** @defgroup SD_Exported_Constants SD Exported Constants
* @{
*/
@ -354,7 +386,7 @@ typedef enum
*/
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
@ -396,11 +428,10 @@ typedef enum
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/** @defgroup SD_Exported_macros SD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SD device.
@ -609,12 +640,11 @@ typedef enum
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SD_Exported_Functions
/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup SD_Group1
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
@ -624,9 +654,8 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
*/
/* I/O operation functions ***************************************************/
/** @addtogroup SD_Group2
/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
* @{
*/
/* Blocking mode: Polling */
@ -653,9 +682,8 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup SD_Group3
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
@ -667,7 +695,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
*/
/* Peripheral State functions ************************************************/
/** @addtogroup SD_Group4
/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
@ -681,19 +709,81 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup SD_Private_Types SD Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup SD_Private_Defines SD Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup SD_Private_Variables SD Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SD_Private_Constants SD Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SD_Private_Macros SD Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_SD_H */
#endif /* __STM32F4xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

38
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -97,26 +97,24 @@
* @{
*/
/** @defgroup SDRAM
/** @defgroup SDRAM SDRAM
* @brief SDRAM driver modules
* @{
*/
#ifdef HAL_SDRAM_MODULE_ENABLED
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SDRAM_Private_Functions
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
/** @defgroup SDRAM_Group1 Initialization and de-initialization functions
/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -148,6 +146,8 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
if(hsdram->State == HAL_SDRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
}
@ -272,12 +272,11 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup SDRAM_Group2 Input and Output functions
/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@ -330,8 +329,7 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr
return HAL_OK;
}
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
@ -375,7 +373,6 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd
return HAL_OK;
}
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
@ -623,12 +620,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
return HAL_OK;
}
/**
* @}
*/
/** @defgroup SDRAM_Group3 Control functions
/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@ -717,7 +713,7 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
/* Update the SDRAM controller state state */
/* Update the SDRAM controller state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
@ -800,7 +796,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
* @}
*/
/** @defgroup SDRAM_Group4 State functions
/** @defgroup SDRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@ -833,7 +829,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SDRAM_MODULE_ENABLED */
/**
* @}

75
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_fmc.h"
@ -57,6 +57,9 @@
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
* @{
*/
/**
* @brief HAL SDRAM State structure definition
@ -88,19 +91,35 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
}SDRAM_HandleTypeDef;
/* Exported types ------------------------------------------------------------*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
* @{
*/
/** @brief Reset SDRAM handle state
* @param __HANDLE__: specifies the SDRAM handle.
* @retval None
*/
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
/** @addtogroup SDRAM_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
@ -110,8 +129,14 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* I/O operation functions *****************************************************/
/** @addtogroup SDRAM_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
@ -121,7 +146,13 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
/**
* @}
*/
/** @addtogroup SDRAM_Exported_Functions_Group3
* @{
*/
/* SDRAM Control functions *****************************************************/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
@ -129,14 +160,28 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
/* SDRAM State functions ********************************************************/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
*/
/** @addtogroup SDRAM_Exported_Functions_Group4
* @{
*/
/* SDRAM State functions ********************************************************/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}

413
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@ -34,7 +34,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
(+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
@ -42,11 +42,11 @@
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
(++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_SMARTCARD_MspInit() API.
by calling the customized HAL_SMARTCARD_MspInit() API.
[..]
(@) The specific SMARTCARD interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
__HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
[..]
Three operation modes are available within this driver :
@ -100,7 +100,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -134,63 +134,77 @@
* @{
*/
/** @defgroup SMARTCARD
/** @defgroup SMARTCARD SMARTCARD
* @brief HAL USART SMARTCARD module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Constants
* @{
*/
#define SMARTCARD_TIMEOUT_VALUE 22000
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/* Private functions ---------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Functions
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
/** @defgroup SMARTCARD_Group1 SmartCard Initialization and de-initialization functions
/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
in Smartcard mode.
[..]
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
[..]
The USART can provide a clock to the smartcard through the SCLK output.
In smartcard mode, SCLK is not associated to the communication but is simply derived
from the internal peripheral input clock through a 5-bit prescaler.
[..]
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
please refer to Reference manual for possible SMARTDARD frame formats.
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
(++) Prescaler
(++) GuardTime
(++) NACKState: The Smartcard NACK state
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
in Smartcard mode.
[..]
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
[..]
The USART can provide a clock to the smartcard through the SCLK output.
In smartcard mode, SCLK is not associated to the communication but is simply derived
from the internal peripheral input clock through a 5-bit prescaler.
[..]
(+) For the Smartcard mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length => Should be 9 bits (8 bits + parity)
(++) Stop Bit
(++) Parity: => Should be enabled
+-------------------------------------------------------------+
| M bit | PCE bit | SMARTCARD frame |
|---------------------|---------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | STB | |
+-------------------------------------------------------------+
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
(++) Prescaler
(++) GuardTime
(++) NACKState: The Smartcard NACK state
(+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
(++) Word Length = 9 Bits
@ -198,13 +212,13 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
(++) Even parity
(++) BaudRate = 12096 baud
(++) Tx and Rx enabled
[..]
Please refer to the ISO 7816-3 specification for more details.
[..]
Please refer to the ISO 7816-3 specification for more details.
-@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
to use 1.5 stop bits for both transmitting and receiving to avoid switching
between the two configurations.
[..]
-@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
to use 1.5 stop bits for both transmitting and receiving to avoid switching
between the two configurations.
[..]
The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
procedure (details for the procedure are available in reference manual (RM0329)).
@ -233,6 +247,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
if(hsc->State == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsc->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SMARTCARD_MspInit(hsc);
}
@ -255,13 +271,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
/* Enable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Framing Error Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Enable the Peripharal */
__SMARTCARD_ENABLE(hsc);
/* Enable the Peripheral */
__HAL_SMARTCARD_ENABLE(hsc);
/* Configure the Smartcard NACK state */
MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
@ -295,6 +311,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
hsc->State = HAL_SMARTCARD_STATE_BUSY;
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsc);
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsc);
@ -316,7 +335,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspInit could be implenetd in the user file
the HAL_SMARTCARD_MspInit could be implemented in the user file
*/
}
@ -329,7 +348,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspDeInit could be implenetd in the user file
the HAL_SMARTCARD_MspDeInit could be implemented in the user file
*/
}
@ -337,7 +356,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
* @}
*/
/** @defgroup SMARTCARD_Group2 IO operation functions
/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
@ -346,11 +365,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
===============================================================================
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard. The USART should be configured as:
(+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
@ -362,7 +381,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectivelly at the end of the Transmit or Receive process
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
@ -427,34 +446,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
{
hsc->TxXferCount--;
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
hsc->TxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
pData +=2;
}
else
{
pData +=1;
}
}
else
{
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hsc->Instance->DR = (*pData++ & (uint8_t)0xFF);
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
pData +=1;
}
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
@ -519,43 +520,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
/* Check the remain data to be received */
while(hsc->RxXferCount > 0)
{
hsc->RxXferCount--;
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
pData +=2;
}
else
{
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
pData +=1;
}
}
else
{
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
*pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
}
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
pData +=1;
}
/* Check if a non-blocking transmit process is ongoing or not */
@ -617,17 +593,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
/* Enable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Enable the SMARTCARD Transmit data register empty Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
return HAL_OK;
}
@ -674,18 +650,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
{
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
/* Enable the SMARTCARD Data Register not empty Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Enable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Data Register not empty Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Enable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
return HAL_OK;
}
@ -734,7 +709,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
/* Set the SMARTCARD DMA transfert complete callback */
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
/* Set the DMA error callback */
@ -744,6 +719,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the SMARTCARD CR3 register */
hsc->Instance->CR3 |= USART_CR3_DMAT;
@ -798,7 +776,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
/* Set the SMARTCARD DMA transfert complete callback */
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
/* Set the DMA error callback */
@ -836,7 +814,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
tmp1 = hsc->Instance->SR;
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
/* SMARTCARD parity error interrupt occured --------------------------------*/
/* SMARTCARD parity error interrupt occurred --------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
@ -844,7 +822,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD frame error interrupt occured ---------------------------------*/
/* SMARTCARD frame error interrupt occurred ---------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
@ -852,7 +830,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD noise error interrupt occured ---------------------------------*/
/* SMARTCARD noise error interrupt occurred ---------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
@ -860,7 +838,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD Over-Run interrupt occured ------------------------------------*/
/* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
@ -880,6 +858,13 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
SMARTCARD_Transmit_IT(hsc);
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
}
/* Call the Error call Back in case of Errors */
if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
@ -933,7 +918,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
* @}
*/
/** @defgroup SMARTCARD_Group3 Peripheral State and Errors functions
/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SMARTCARD State and Errors functions
*
@verbatim
@ -943,7 +928,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
[..]
This subsection provides a set of functions allowing to control the SmartCard.
(+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
(+) HAL_SMARTCARD_GetError() check in run-time errors that could be occured durung communication.
(+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
@ -990,27 +975,8 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
in the USART CR3 register */
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
/* Wait for SMARTCARD TC Flag */
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout Occured */
hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
HAL_SMARTCARD_ErrorCallback(hsc);
}
else
{
/* No Timeout */
/* Check if a non-blocking receive process is ongoing or not */
if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
else
{
hsc->State = HAL_SMARTCARD_STATE_READY;
}
HAL_SMARTCARD_TxCpltCallback(hsc);
}
/* Enable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
/**
@ -1086,8 +1052,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@ -1109,8 +1075,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@ -1139,63 +1105,56 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
{
tmp = (uint16_t*) hsc->pTxBuffPtr;
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
hsc->pTxBuffPtr += 2;
}
else
{
hsc->pTxBuffPtr += 1;
}
}
else
{
hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF);
}
tmp = (uint16_t*) hsc->pTxBuffPtr;
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
hsc->pTxBuffPtr += 1;
if(--hsc->TxXferCount == 0)
{
/* Disable the SMARTCARD Transmit data register empty Interrupt */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
/* Disable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Check if a non-blocking receive process is ongoing or not */
if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
else
{
hsc->State = HAL_SMARTCARD_STATE_READY;
}
HAL_SMARTCARD_TxCpltCallback(hsc);
return HAL_OK;
/* Enable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
return HAL_BUSY;
}
}
/**
* @brief Wraps up transmission in non blocking mode.
* @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
/* Check if a receive process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
else
{
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
HAL_SMARTCARD_TxCpltCallback(hsmartcard);
return HAL_OK;
}
/**
* @brief Receive an amount of data in non blocking mode
* @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
@ -1210,41 +1169,19 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
{
tmp = (uint16_t*) hsc->pRxBuffPtr;
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
hsc->pRxBuffPtr += 2;
}
else
{
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
hsc->pRxBuffPtr += 1;
}
}
else
{
if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
{
*hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
}
else
{
*hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
}
}
tmp = (uint16_t*) hsc->pRxBuffPtr;
*tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
hsc->pRxBuffPtr += 1;
if(--hsc->RxXferCount == 0)
{
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Disable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Check if a non-blocking transmit process is ongoing or not */
if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
@ -1342,11 +1279,11 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
/*-------------------------- USART BRR Configuration -----------------------*/
if((hsc->Instance == USART1) || (hsc->Instance == USART6))
{
hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
}
else
{
hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
}
}

317
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -54,7 +54,11 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
@ -78,7 +82,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@ -91,11 +95,13 @@ typedef struct
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock
This parameter can be a value of @ref SMARTCARD_Prescaler */
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
The value given in the register (5 significant bits) is multiplied by 2
to give the division factor of the source clock frequency */
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
This parameter can be a value of @ref SmartCard_NACK_State */
@ -116,19 +122,6 @@ typedef enum
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
/**
* @brief HAL SMARTCARD Error Code structure definition
*/
typedef enum
{
HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */
}HAL_SMARTCARD_ErrorTypeDef;
/**
* @brief SMARTCARD handle Structure definition
*/
@ -136,7 +129,7 @@ typedef struct
{
USART_TypeDef *Instance; /* USART registers base address */
SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
@ -154,127 +147,160 @@ typedef struct
DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /* Locking object */
HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
__IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
__IO uint32_t ErrorCode; /* SmartCard Error code */
__IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SMARTCARD Error code */
}SMARTCARD_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Constants
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
* @{
*/
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
* @brief SMARTCARD Error Code
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup SMARTCARD_Word_Length
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
((LENGTH) == SMARTCARD_WORDLENGTH_9B))
/**
* @}
*/
/** @defgroup SMARTCARD_Stop_Bits
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
((STOPBITS) == SMARTCARD_STOPBITS_2))
/**
* @}
*/
/** @defgroup SMARTCARD_Parity
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
((PARITY) == SMARTCARD_PARITY_EVEN) || \
((PARITY) == SMARTCARD_PARITY_ODD))
/**
* @}
*/
/** @defgroup SMARTCARD_Mode
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
* @{
*/
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Polarity
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Phase
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
/**
* @}
*/
/** @defgroup SMARTCARD_Last_Bit
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
/**
* @}
*/
/** @defgroup SmartCard_NACK_State
/** @defgroup SmartCard_NACK_State SMARTCARD NACK State
* @{
*/
#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK)
#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000)
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
((NACK) == SMARTCARD_NACK_DISABLED))
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup SmartCard_DMA_Requests
/** @defgroup SmartCard_DMA_Requests SMARTCARD DMA requests
* @{
*/
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
/**
* @}
*/
/** @defgroup SmartCard_Flags
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */
/**
* @}
*/
/** @defgroup SmartCard_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
@ -287,23 +313,20 @@ typedef struct
* @}
*/
/** @defgroup SmartCard_Interrupt_definition
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR3 register
*
* @{
*/
#define SMARTCARD_IT_PE ((uint32_t)0x10000100)
#define SMARTCARD_IT_TXE ((uint32_t)0x10000080)
#define SMARTCARD_IT_TC ((uint32_t)0x10000040)
#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020)
#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010)
#define SMARTCARD_IT_ERR ((uint32_t)0x20000001)
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@ -313,6 +336,9 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
/** @brief Reset SMARTCARD handle state
* @param __HANDLE__: specifies the SMARTCARD Handle.
@ -333,7 +359,7 @@ typedef struct
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
* @arg SMARTCARD_FLAG_ORE: OverRun Error flag
* @arg SMARTCARD_FLAG_ORE: Overrun Error flag
* @arg SMARTCARD_FLAG_NE: Noise Error flag
* @arg SMARTCARD_FLAG_FE: Framing Error flag
* @arg SMARTCARD_FLAG_PE: Parity Error flag
@ -348,7 +374,7 @@ typedef struct
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
* error) flags are cleared by software sequence: a read operation to
* USART_SR register followed by a read operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
@ -364,8 +390,14 @@ typedef struct
* UART peripheral.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
(__HANDLE__)->Instance->DR;}while(0)
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0)
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@ -410,11 +442,10 @@ typedef struct
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
*/
#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF)
#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__: specifies the SmartCard Handle.
@ -430,11 +461,31 @@ typedef struct
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
/** @brief Macros to enable or disable the SmartCard interface.
* @param __HANDLE__: specifies the SmartCard Handle.
/** @brief Macro to enable the SMARTCARD's one bit sample method
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the SMARTCARD's one bit sample method
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
#define __SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable or disable the SmartCard DMA request.
* @param __HANDLE__: specifies the SmartCard Handle.
@ -443,23 +494,34 @@ typedef struct
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
*/
#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define __SMARTCARD_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@ -471,10 +533,16 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
@ -483,7 +551,66 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
/** @brief SMARTCARD interruptions flag mask
*
*/
#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR3_EIE )
#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100)
#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define SMARTCARD_BRR(_PCLK_, _BAUD_) ((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
#define SMARTCARD_CR1_REG_INDEX 1
#define SMARTCARD_CR3_REG_INDEX 3
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
((PARITY) == SMARTCARD_PARITY_ODD))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
((NACK) == SMARTCARD_NACK_DISABLE))
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,559 @@
/**
******************************************************************************
* @file stm32f4xx_hal_spdifrx.h
* @author MCD Application Team
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SPDIFRX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_SPDIFRX_H
#define __STM32F4xx_HAL_SPDIFRX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup SPDIFRX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
* @{
*/
/**
* @brief SPDIFRX Init structure definition
*/
typedef struct
{
uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
This parameter can be a value of @ref SPDIFRX_Input_Selection */
uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
This parameter can be a value of @ref SPDIFRX_Max_Retries */
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
This parameter can be a value of @ref SPDIFRX_Data_Format */
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
}SPDIFRX_InitTypeDef;
/**
* @brief SPDIFRX SetDataFormat structure definition
*/
typedef struct
{
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
This parameter can be a value of @ref SPDIFRX_Data_Format */
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
}SPDIFRX_SetDataFormatTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */
HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */
HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */
HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */
HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */
HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */
}HAL_SPDIFRX_StateTypeDef;
/**
* @brief SPDIFRX handle Structure definition
*/
typedef struct
{
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
__IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
__IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
__IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
}SPDIFRX_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
*/
/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
* @{
*/
#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */
#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */
/**
* @}
*/
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
* @{
*/
#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)
#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)
#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)
#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)
/**
* @}
*/
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
* @{
*/
#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)
#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)
#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)
#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)
/**
* @}
*/
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
* @{
*/
#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)
#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
/**
* @}
*/
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
* @{
*/
#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)
#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
* @{
*/
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
* @{
*/
#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)
#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
* @{
*/
#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)
#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
* @{
*/
#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)
#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
/**
* @}
*/
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
* @{
*/
#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)
#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)
#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)
/**
* @}
*/
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
* @{
*/
#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)
#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
/**
* @}
*/
/** @defgroup SPDIFRX_State SPDIFRX State
* @{
*/
#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)
#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
/**
* @}
*/
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
* @{
*/
#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
/**
* @}
*/
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
* @{
*/
#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
* @{
*/
/** @brief Reset SPDIFRX handle state
* @param __HANDLE__: SPDIFRX handle.
* @retval None
*/
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
/** @brief Enable the specified SPDIFRX peripheral (RCV State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
/** @brief Enable or disable the specified SPDIFRX interrupts.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
* @arg SPDIFRX_IT_CSRNE
* @arg SPDIFRX_IT_PERRIE
* @arg SPDIFRX_IT_OVRIE
* @arg SPDIFRX_IT_SBLKIE
* @arg SPDIFRX_IT_SYNCDIE
* @arg SPDIFRX_IT_IFEIE
* @retval None
*/
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
* @arg SPDIFRX_IT_CSRNE
* @arg SPDIFRX_IT_PERRIE
* @arg SPDIFRX_IT_OVRIE
* @arg SPDIFRX_IT_SBLKIE
* @arg SPDIFRX_IT_SYNCDIE
* @arg SPDIFRX_IT_IFEIE
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPDIFRX flag is set or not.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_RXNE
* @arg SPDIFRX_FLAG_CSRNE
* @arg SPDIFRX_FLAG_PERR
* @arg SPDIFRX_FLAG_OVR
* @arg SPDIFRX_FLAG_SBD
* @arg SPDIFRX_FLAG_SYNCD
* @arg SPDIFRX_FLAG_FERR
* @arg SPDIFRX_FLAG_SERR
* @arg SPDIFRX_FLAG_TERR
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
* @param __HANDLE__: specifies the USART Handle.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_PERR
* @arg SPDIFRX_FLAG_OVR
* @arg SPDIFRX_SR_SBD
* @arg SPDIFRX_SR_SYNCD
* @retval None
*/
#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPDIFRX_Exported_Functions
* @{
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
/**
* @}
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
* @{
*/
#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
((INPUT) == SPDIFRX_INPUT_IN2) || \
((INPUT) == SPDIFRX_INPUT_IN3) || \
((INPUT) == SPDIFRX_INPUT_IN0))
#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
((RET) == SPDIFRX_MAXRETRIES_3) || \
((RET) == SPDIFRX_MAXRETRIES_15) || \
((RET) == SPDIFRX_MAXRETRIES_63))
#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
((VAL) == SPDIFRX_VALIDITYMASK_ON))
#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
((VAL) == SPDIFRX_PARITYERRORMASK_ON))
#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
((CHANNEL) == SPDIFRX_CHANNEL_B))
#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
((MODE) == SPDIFRX_STEREOMODE_ENABLE))
#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F446xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_SPDIFRX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

416
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@ -35,7 +35,7 @@
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
@ -43,7 +43,7 @@
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_SPI_MspInit() API.
by calling the customized HAL_SPI_MspInit() API.
[..]
Circular mode restriction:
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
@ -59,7 +59,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -93,7 +93,7 @@
* @{
*/
/** @defgroup SPI
/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
@ -106,11 +106,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SPI_Private_Functions
* @{
*/
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_TxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxISR(SPI_HandleTypeDef *hspi);
static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@ -119,14 +123,16 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPI_Private_Functions
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_Group1 Initialization and de-initialization functions
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -134,7 +140,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
de-initialiaze the SPIx peripheral:
de-initialize the SPIx peripheral:
(+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@ -153,7 +159,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
(++) CRC Polynomial if CRC enabled
(+) Call the function HAL_SPI_DeInit() to restore the default configuration
of the selected SPIx periperal.
of the selected SPIx peripheral.
@endverbatim
* @{
@ -189,13 +195,15 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
if(hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
hspi->State = HAL_SPI_STATE_BUSY;
/* Disble the selected SPI peripheral */
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
@ -259,7 +267,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_MspInit could be implenetd in the user file
the HAL_SPI_MspInit could be implemented in the user file
*/
}
@ -272,7 +280,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_MspDeInit could be implenetd in the user file
the HAL_SPI_MspDeInit could be implemented in the user file
*/
}
@ -280,7 +288,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
* @}
*/
/** @defgroup SPI_Group2 IO operation functions
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@ -302,30 +310,11 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
will be executed respectivelly at the end of the transmit or Receive process
will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceive() in full duplex mode
(#) Non Blocking mode API's with Interrupt are :
(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
(++) HAL_SPI_IRQHandler()
(#) Non Blocking mode functions with DMA are :
(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SPI_TxCpltCallback()
(++) HAL_SPI_RxCpltCallback()
(++) HAL_SPI_ErrorCallback()
(++) HAL_SPI_TxRxCpltCallback()
(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
@ -371,15 +360,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->RxXferCount = 0;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Configure communication direction : 1Line */
__HAL_SPI_1LINE_TX(hspi);
SPI_1LINE_TX(hspi);
}
/* Check if the SPI is already enabled */
@ -408,7 +397,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -434,7 +423,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -454,7 +443,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
return HAL_TIMEOUT;
}
/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@ -514,13 +503,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
__HAL_SPI_1LINE_RX(hspi);
SPI_1LINE_RX(hspi);
}
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@ -554,7 +543,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -575,7 +564,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -601,7 +590,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
/* Wait until RXNE flag is set: CRC Received */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
@ -611,6 +600,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Read CRC to Flush RXNE flag */
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg);
}
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
@ -623,12 +613,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@ -698,9 +688,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxISR = 0;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Check if the SPI is already enabled */
@ -722,7 +712,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -752,7 +742,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxXferCount--;
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -793,7 +783,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -821,7 +811,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxXferCount--;
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@ -850,7 +840,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Read CRC from DR to close CRC calculation process */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@ -860,6 +850,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg);
}
/* Wait until Busy flag is reset before disabling SPI */
@ -873,14 +864,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Process Unlocked */
@ -940,13 +931,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
__HAL_SPI_1LINE_TX(hspi);
SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
@ -1012,7 +1003,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
__HAL_SPI_1LINE_RX(hspi);
SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
@ -1024,9 +1015,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Enable TXE and ERR interrupt */
@ -1102,9 +1093,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
hspi->RxXferCount = Size;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Enable TXE, RXNE and ERR interrupt */
@ -1168,13 +1159,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
__HAL_SPI_1LINE_TX(hspi);
SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Set the SPI TxDMA Half transfer complete callback */
@ -1189,9 +1180,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Enable Tx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@ -1202,6 +1190,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
/* Enable Tx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
return HAL_OK;
}
else
@ -1213,7 +1204,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/**
* @brief Receive an amount of data in no-blocking mode with DMA
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* the configuration information for SPI module.
* @param pData: pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
@ -1248,7 +1239,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
__HAL_SPI_1LINE_RX(hspi);
SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
@ -1260,9 +1251,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Set the SPI RxDMA Half transfer complete callback */
@ -1277,9 +1268,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Enable the Rx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
/* Enable Rx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@ -1290,6 +1278,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
/* Enable Rx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
return HAL_OK;
}
else
@ -1348,9 +1339,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->TxISR = 0;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
@ -1378,16 +1369,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable Rx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
/* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferCpltCallback = HAL_NULL;
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
{
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
}
else
{
hspi->hdmatx->XferErrorCallback = HAL_NULL;
}
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
@ -1398,8 +1399,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable Tx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
else
@ -1408,7 +1407,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
}
}
/**
* @brief Pauses the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@ -1453,8 +1451,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
/**
* @brief Stops the DMA Transfer.
* @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
@ -1507,7 +1505,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
/* SPI in mode Tramitter ---------------------------------------------------*/
/* SPI in mode Transmitter ---------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
hspi->TxISR(hspi);
@ -1564,7 +1562,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback could be implenetd in the user file
the HAL_SPI_TxCpltCallback could be implemented in the user file
*/
}
@ -1577,7 +1575,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback() could be implenetd in the user file
the HAL_SPI_RxCpltCallback() could be implemented in the user file
*/
}
@ -1590,7 +1588,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
*/
}
@ -1603,7 +1601,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
*/
}
@ -1616,7 +1614,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
*/
}
@ -1629,7 +1627,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
*/
}
@ -1642,7 +1640,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : - This function Should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback() could be implenetd in the user file.
the HAL_SPI_ErrorCallback() could be implemented in the user file.
- The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred.
*/
@ -1652,7 +1650,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
* @}
*/
/** @defgroup SPI_Group3 Peripheral State and Errors functions
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SPI control functions
*
@verbatim
@ -1684,7 +1682,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI Error Code
*/
HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
return hspi->ErrorCode;
}
@ -1721,7 +1719,7 @@ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@ -1777,7 +1775,7 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi)
if(hspi->TxXferCount == 0)
{
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* calculate and transfer CRC on Tx line */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@ -1796,7 +1794,7 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
@ -1806,6 +1804,7 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
/* Read CRC to reset RXNE flag */
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg);
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
@ -1819,7 +1818,7 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
}
@ -1914,7 +1913,7 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi)
hspi->RxXferCount--;
/* Enable CRC Transmission */
if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set CRC Next to calculate CRC on Rx side */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@ -1958,7 +1957,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
hspi->State = HAL_SPI_STATE_READY;
}
/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@ -1989,47 +1988,54 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
SPI_DMAEndTransmitReceive(hspi);
}
/* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
else
{
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Disable Rx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
hspi->RxXferCount = 0;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg);
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
}
/* Disable Rx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
@ -2046,6 +2052,61 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief End DMA SPI transmit receive process
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Check if CRC is done on going (RXNE flag set) */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg);
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
/* Wait until TXE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Disable Tx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
/* Wait until Busy flag is reset before disabling SPI */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Disable Rx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
hspi->TxXferCount = 0;
hspi->RxXferCount = 0;
}
/**
* @brief DMA SPI transmit receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@ -2058,52 +2119,10 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
{
/* Check if CRC is done on going (RXNE flag set) */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
/* Wait until TXE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Disable Tx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
/* Wait until Busy flag is reset before disabling SPI */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
/* Disable Rx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
hspi->TxXferCount = 0;
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
{ /**/
SPI_DMAEndTransmitReceive(hspi);
hspi->State = HAL_SPI_STATE_READY;
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
@ -2180,6 +2199,9 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
* @brief This function handles SPI Communication Timeout.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param Flag: SPI flag to check
* @param Status: Flag status to check: RESET or set
* @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
@ -2209,9 +2231,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;
@ -2243,9 +2265,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
__HAL_SPI_RESET_CRC(hspi);
SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;

309
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Configuration Structure definition
*/
@ -115,21 +118,6 @@ typedef enum
}HAL_SPI_StateTypeDef;
/**
* @brief HAL SPI Error Code structure definition
*/
typedef enum
{
HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
}HAL_SPI_ErrorTypeDef;
/**
* @brief SPI handle Structure definition
*/
@ -163,99 +151,90 @@ typedef struct __SPI_HandleTypeDef
__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
__IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
__IO uint32_t ErrorCode; /* SPI Error code */
}SPI_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants
* @{
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
/**
* @}
*/
/** @defgroup SPI_Direction_mode
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_Error_Code SPI Error Code
* @brief SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000010) /*!< Flag: RXNE,TXE, BSY */
/**
* @}
*/
/** @defgroup SPI_mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
*/
/** @defgroup SPI_Direction_mode SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
/**
* @}
*/
/** @defgroup SPI_data_size
/** @defgroup SPI_data_size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
@ -266,56 +245,38 @@ typedef struct __SPI_HandleTypeDef
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))
/**
* @}
*/
/** @defgroup SPI_TI_mode
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
#define SPI_TIMODE_ENABLED SPI_CR2_FRF
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
((MODE) == SPI_TIMODE_ENABLED))
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
/** @defgroup SPI_Interrupt_configuration_definition
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@ -325,7 +286,7 @@ typedef struct __SPI_HandleTypeDef
* @}
*/
/** @defgroup SPI_Flag_definition
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE
@ -335,7 +296,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_FLAG_OVR SPI_SR_OVR
#define SPI_FLAG_BSY SPI_SR_BSY
#define SPI_FLAG_FRE SPI_SR_FRE
/**
* @}
*/
@ -345,7 +305,9 @@ typedef struct __SPI_HandleTypeDef
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
@ -406,44 +368,74 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
UNUSED(tmpreg); \
} while(0)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
(__HANDLE__)->Instance->SR;}while(0)
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
} while(0)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
}while(0)
/** @brief Enable SPI
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
/** @brief Disable SPI
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@ -466,10 +458,16 @@ void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Control functions **************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
@ -479,6 +477,95 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT))
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
((MODE) == SPI_TIMODE_ENABLE))
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

35
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sram.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -98,27 +98,27 @@
* @{
*/
/** @defgroup SRAM
/** @defgroup SRAM SRAM
* @brief SRAM driver modules
* @{
*/
#ifdef HAL_SRAM_MODULE_ENABLED
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SRAM_Private_Functions
/* Exported functions --------------------------------------------------------*/
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @defgroup SRAM_Group1 Initialization and de-initialization functions
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -150,6 +150,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
if(hsram->State == HAL_SRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
@ -219,7 +221,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
/**
* @brief DMA transfer complete callback.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@ -232,7 +234,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete error callback.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@ -247,7 +249,7 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
* @}
*/
/** @defgroup SRAM_Group2 Input and Output functions
/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@ -567,7 +569,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
* @}
*/
/** @defgroup SRAM_Group3 Control functions
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@ -635,7 +637,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
* @}
*/
/** @defgroup SRAM_Group4 State functions
/** @defgroup SRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@ -660,7 +662,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
/**
* @}
*/
@ -668,7 +669,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
* @}

94
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -48,23 +48,27 @@
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
#include "stm32f4xx_ll_fmc.h"
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx)
/** @addtogroup SRAM
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
@ -97,23 +101,49 @@ typedef struct
}SRAM_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__: SRAM handle
* @retval None
*/
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
@ -123,26 +153,46 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
/* SRAM Control functions ******************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/* SRAM State functions *********************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3
* @{
*/
/* SRAM Control functions ******************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4
* @{
*/
/* SRAM State functions *********************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
#ifdef __cplusplus
}
#endif

1995
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c
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959
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h
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307
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -103,7 +103,7 @@
* @{
*/
/** @defgroup TIMEx
/** @defgroup TIMEx TIMEx
* @brief TIM HAL module driver
* @{
*/
@ -114,15 +114,21 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions
* @{
*/
/* Private function prototypes -----------------------------------------------*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TIMEx_Group1 Timer Hall Sensor functions
/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
*
@verbatim
@ -398,9 +404,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callback */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream for Capture 1*/
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
@ -440,12 +446,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Group2 Timer Complementary Output Compare functions
/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
*
@verbatim
@ -472,10 +477,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -486,7 +491,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@ -503,10 +508,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -517,7 +522,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -534,10 +539,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -579,12 +584,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
break;
}
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
@ -599,10 +607,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -643,13 +651,19 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
default:
break;
}
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@ -664,10 +678,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -697,10 +711,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@ -713,10 +727,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@ -729,10 +743,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@ -745,10 +759,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@ -765,7 +779,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@ -782,10 +796,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -830,7 +844,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -842,12 +856,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Group3 Timer Complementary PWM functions
/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
*
@verbatim
@ -883,10 +896,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -897,7 +910,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@ -913,10 +926,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -927,7 +940,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -944,10 +957,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -995,7 +1008,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@ -1012,10 +1025,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1057,13 +1070,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
break;
}
/* Disable the TIM Break interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the TIM Break interrupt (only if no more channel is active) */
if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -1080,10 +1096,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -1113,10 +1129,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@ -1129,10 +1145,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@ -1145,10 +1161,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@ -1161,10 +1177,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@ -1181,7 +1197,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@ -1198,10 +1214,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1/
* TIM_CHANNEL_2/
* TIM_CHANNEL_3/
* TIM_CHANNEL_4
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1246,7 +1262,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -1263,7 +1279,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @}
*/
/** @defgroup TIMEx_Group4 Timer Complementary One Pulse functions
/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
*
@verbatim
@ -1282,14 +1298,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/**
* @brief Starts the TIM One Pulse signal generation on the complemetary
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1 /
* IM_CHANNEL_2
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@ -1300,7 +1316,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@ -1314,7 +1330,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1 / TIM_CHANNEL_2
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@ -1326,7 +1343,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -1343,7 +1360,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1 / IM_CHANNEL_2
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@ -1360,7 +1378,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
/* Enable the Main Ouput */
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@ -1374,7 +1392,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* TIM_CHANNEL_1 / IM_CHANNEL_2
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@ -1391,7 +1410,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Ouput */
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@ -1400,11 +1419,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Group5 Peripheral Control functions
/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@ -1435,11 +1454,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* TIM_TS_ITR0 /
* TIM_TS_ITR1 /
* TIM_TS_ITR2 /
* TIM_TS_ITR3 /
* TIM_TS_NONE
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@ -1485,11 +1504,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* TIM_TS_ITR0 /
* TIM_TS_ITR1 /
* TIM_TS_ITR2 /
* TIM_TS_ITR3 /
* TIM_TS_NONE
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@ -1539,11 +1558,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* TIM_TS_ITR0 /
* TIM_TS_ITR1 /
* TIM_TS_ITR2 /
* TIM_TS_ITR3 /
* TIM_TS_NONE
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@ -1574,9 +1593,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@ -1643,6 +1662,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
/* Process Locked */
__HAL_LOCK(htim);
@ -1670,11 +1690,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module..
* @param TIM_Remap: specifies the TIM input remapping source.
* the configuration information for TIM module.
* @param Remap: specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
* @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
* @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
* @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
* @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
* @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
@ -1703,12 +1723,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
return HAL_OK;
}
/**
* @}
*/
/** @defgroup TIMEx_Group6 Extension Callbacks functions
/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
* @brief Extension Callbacks functions
*
@verbatim
@ -1749,12 +1768,11 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup TIMEx_Group7 Extension Peripheral State functions
/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
* @brief Extension Peripheral State functions
*
@verbatim
@ -1790,7 +1808,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* the configuration information for the specified DMA module.
* @retval None
*/
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@ -1798,7 +1816,10 @@ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_CommutationCallback(htim);
}
/**
* @}
*/
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral

164
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -46,7 +46,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
@ -90,31 +93,33 @@ typedef struct {
*/
typedef struct
{
uint32_t OffStateRunMode; /*!< TIM off state in run mode.
uint32_t OffStateRunMode; /*!< TIM off state in run mode.
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level.
uint32_t LockLevel; /*!< TIM Lock level.
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time.
uint32_t DeadTime; /*!< TIM dead Time.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State.
uint32_t BreakState; /*!< TIM Break State.
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity.
uint32_t BreakPolarity; /*!< TIM Break input polarity.
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
}TIM_BreakDeadTimeConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants
/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap
/** @defgroup TIMEx_Remap TIM Remap
* @{
*/
#define TIM_TIM2_TIM8_TRGO (0x00000000)
#define TIM_TIM2_ETH_PTP (0x00000400)
#define TIM_TIM2_USBFS_SOF (0x00000800)
@ -126,29 +131,26 @@ typedef struct
#define TIM_TIM11_GPIO (0x00000000)
#define TIM_TIM11_HSE (0x00000002)
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
((TIM_REMAP) == TIM_TIM5_GPIO)||\
((TIM_REMAP) == TIM_TIM5_LSI)||\
((TIM_REMAP) == TIM_TIM5_LSE)||\
((TIM_REMAP) == TIM_TIM5_RTC)||\
((TIM_REMAP) == TIM_TIM11_GPIO)||\
((TIM_REMAP) == TIM_TIM11_HSE))
/**
* @}
*/
#if defined (STM32F446xx)
#define TIM_TIM11_SPDIFRX (0x00000001)
#endif /* STM32F446xx */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
@ -165,7 +167,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@ -178,7 +186,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channe
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@ -190,7 +204,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Chann
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
@ -199,23 +219,40 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t Out
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
/**
* @}
*/
/* Extnsion Control functions ************************************************/
/** @addtogroup TIMEx_Exported_Functions_Group5
* @{
*/
/* Extension Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6
* @{
*/
/* Extension Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7
* @{
*/
/* Extension Peripheral State functions **************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
/**
* @}
*/
@ -223,7 +260,62 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Private Macros
* @{
*/
#if defined (STM32F446xx)
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
((TIM_REMAP) == TIM_TIM5_GPIO)||\
((TIM_REMAP) == TIM_TIM5_LSI)||\
((TIM_REMAP) == TIM_TIM5_LSE)||\
((TIM_REMAP) == TIM_TIM5_RTC)||\
((TIM_REMAP) == TIM_TIM11_GPIO)||\
((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
((TIM_REMAP) == TIM_TIM11_HSE))
#else
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
((TIM_REMAP) == TIM_TIM5_GPIO)||\
((TIM_REMAP) == TIM_TIM5_LSI)||\
((TIM_REMAP) == TIM_TIM5_LSE)||\
((TIM_REMAP) == TIM_TIM5_RTC)||\
((TIM_REMAP) == TIM_TIM11_GPIO)||\
((TIM_REMAP) == TIM_TIM11_HSE))
#endif /* STM32F446xx */
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

223
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@ -63,7 +63,7 @@
[..]
(@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
HAL_UART_MspInit() API.
[..]
@ -79,13 +79,9 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
(+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
(+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
@ -121,6 +117,7 @@
(+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
(+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
(+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
(+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
[..]
(@) You can refer to the UART HAL driver header file for more useful macros
@ -129,7 +126,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -163,7 +160,7 @@
* @{
*/
/** @defgroup UART
/** @defgroup UART UART
* @brief HAL UART module driver
* @{
*/
@ -171,12 +168,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup UART_Private_Constants
* @{
*/
#define UART_TIMEOUT_VALUE 22000
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
static void UART_SetConfig (UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
@ -184,14 +191,16 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup UART_Private_Functions
/* Exported functions ---------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
/** @defgroup UART_Group1 Initialization and de-initialization functions
/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -211,7 +220,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Methode
(++) Over Sampling Method
[..]
The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
@ -235,20 +244,25 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
return HAL_ERROR;
}
/* Check the parameters */
if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
/* Check the parameters */
{
/* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
}
else
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@ -291,9 +305,16 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@ -343,11 +364,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
{
return HAL_ERROR;
}
/* Check the Break detection length parameter */
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@ -389,13 +416,13 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
* @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param Address: USART address
* @param WakeUpMethode: specifies the USART wakeup method.
* @param WakeUpMethod: specifies the USART wake-up method.
* This parameter can be one of the following values:
* @arg UART_WAKEUPMETHODE_IDLELINE: Wakeup by an idle line detection
* @arg UART_WAKEUPMETHODE_ADDRESSMARK: Wakeup by an address mark
* @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
* @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
if(huart == HAL_NULL)
@ -403,12 +430,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
return HAL_ERROR;
}
/* Check the Address & wake up method parameters */
assert_param(IS_UART_WAKEUPMETHODE(WakeUpMethode));
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
assert_param(IS_UART_ADDRESS(Address));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@ -432,9 +464,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Set the USART address node */
huart->Instance->CR2 |= Address;
/* Set the wake up methode by setting the WAKE bit in the CR1 register */
/* Set the wake up method by setting the WAKE bit in the CR1 register */
huart->Instance->CR1 &= ~(USART_CR1_WAKE);
huart->Instance->CR1 |= WakeUpMethode;
huart->Instance->CR1 |= WakeUpMethod;
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
@ -507,7 +539,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
* @}
*/
/** @defgroup UART_Group2 IO operation functions
/** @defgroup UART_Exported_Functions_Group2 IO operation functions
* @brief UART Transmit and Receive functions
*
@verbatim
@ -528,7 +560,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
will be executed respectivelly at the end of the transmit or receive process.
will be executed respectively at the end of the transmit or receive process.
The HAL_UART_ErrorCallback() user callback will be executed when
a communication error is detected.
@ -921,6 +953,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
huart->Instance->CR3 |= USART_CR3_DMAT;
@ -1055,14 +1090,14 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
}
else if(huart->State == HAL_UART_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resumming the Rx transfer*/
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Rx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
/* Clear the Overrun flag before resumming the Rx transfer*/
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Tx & Rx request */
huart->Instance->CR3 |= USART_CR3_DMAT;
@ -1175,6 +1210,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
UART_Transmit_IT(huart);
}
tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
/* UART in mode Transmitter end --------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
UART_EndTransmit_IT(huart);
}
if(huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* Set the UART state ready to be able to start again the process */
@ -1253,7 +1296,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
* @}
*/
/** @defgroup UART_Group3 Peripheral Control functions
/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
* @brief UART control functions
*
@verbatim
@ -1425,7 +1468,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
* @}
*/
/** @defgroup UART_Group4 Peripheral State and Errors functions
/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief UART State and Errors functions
*
@verbatim
@ -1486,27 +1529,8 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
in the UART CR3 register */
huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
/* Wait for UART TC Flag */
if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout occurred */
huart->State = HAL_UART_STATE_TIMEOUT;
HAL_UART_ErrorCallback(huart);
}
else
{
/* No Timeout */
/* Check if a receive process is ongoing or not */
if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
else
{
huart->State = HAL_UART_STATE_READY;
}
HAL_UART_TxCpltCallback(huart);
}
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
/* DMA Circular mode */
else
@ -1658,7 +1682,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/**
* @brief Sends an amount of data in non blocking mode.
* @param huart: pointer to a UART_HandleTypeDef structure that contains
* @param huart: Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@ -1693,31 +1717,8 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
/* Check if a receive process is ongoing or not */
if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
else
{
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
huart->State = HAL_UART_STATE_READY;
}
/* Wait on TC flag to be able to start a second transfer */
if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
HAL_UART_TxCpltCallback(huart);
return HAL_OK;
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
return HAL_OK;
}
@ -1727,6 +1728,39 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
}
}
/**
* @brief Wraps up transmission in non blocking mode.
* @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
/* Check if a receive process is ongoing or not */
if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
else
{
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
huart->State = HAL_UART_STATE_READY;
}
HAL_UART_TxCpltCallback(huart);
return HAL_OK;
}
/**
* @brief Receives an amount of data in non blocking mode
* @param huart: pointer to a UART_HandleTypeDef structure that contains
@ -1809,19 +1843,10 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
uint32_t tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
/* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
}
/*-------------------------- USART CR2 Configuration -----------------------*/
tmpreg = huart->Instance->CR2;
@ -1870,11 +1895,11 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
else
@ -1882,11 +1907,11 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
}

353
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,6 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init Structure definition
@ -80,14 +83,14 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling */
}UART_InitTypeDef;
@ -106,203 +109,186 @@ typedef enum
HAL_UART_STATE_ERROR = 0x04 /*!< Error */
}HAL_UART_StateTypeDef;
/**
* @brief HAL UART Error Code structure definition
*/
typedef enum
{
HAL_UART_ERROR_NONE = 0x00, /*!< No error */
HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
HAL_UART_ERROR_FE = 0x04, /*!< frame error */
HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
}HAL_UART_ErrorTypeDef;
/**
* @brief UART handle Structure definition
*/
typedef struct
{
USART_TypeDef *Instance; /* UART registers base address */
USART_TypeDef *Instance; /*!< UART registers base address */
UART_InitTypeDef Init; /* UART communication parameters */
UART_InitTypeDef Init; /*!< UART communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /* UART Tx Transfer size */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
uint16_t TxXferCount; /* UART Tx Transfer Counter */
uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /* UART Rx Transfer size */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
uint16_t RxXferCount; /* UART Rx Transfer Counter */
uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /* Locking object */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef State; /* UART communication state */
__IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
__IO HAL_UART_StateTypeDef State; /*!< UART communication state */
__IO uint32_t ErrorCode; /*!< UART Error code */
}UART_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants
/** @defgroup UART_Exported_Constants UART Exported constants
* @{
*/
/** @defgroup UART_Word_Length
/** @defgroup UART_Error_Code UART Error Code
* @brief UART Error Code
* @{
*/
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
/**
* @}
*/
/** @defgroup UART_Stop_Bits
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 ((uint32_t)0x00000000)
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
((STOPBITS) == UART_STOPBITS_2))
/**
* @}
*/
/** @defgroup UART_Parity
/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE ((uint32_t)0x00000000)
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
((PARITY) == UART_PARITY_EVEN) || \
((PARITY) == UART_PARITY_ODD))
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS) || \
((CONTROL) == UART_HWCONTROL_CTS) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
/**
* @}
*/
/** @defgroup UART_Mode
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
/** @defgroup UART_State
/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE ((uint32_t)0x00000000)
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
((STATE) == UART_STATE_ENABLE))
/**
* @}
*/
/** @defgroup UART_Over_Sampling
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
((SAMPLING) == UART_OVERSAMPLING_8))
/**
* @}
*/
/** @defgroup UART_LIN_Break_Detection_Length
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
/**
* @}
*/
/** @defgroup UART_WakeUp_functions
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
#define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
#define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800)
/**
* @}
*/
/** @defgroup UART_Flags
/** @defgroup UART_Flags UART FLags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define UART_FLAG_CTS ((uint32_t)0x00000200)
#define UART_FLAG_LBD ((uint32_t)0x00000100)
#define UART_FLAG_TXE ((uint32_t)0x00000080)
#define UART_FLAG_TC ((uint32_t)0x00000040)
#define UART_FLAG_RXNE ((uint32_t)0x00000020)
#define UART_FLAG_IDLE ((uint32_t)0x00000010)
#define UART_FLAG_ORE ((uint32_t)0x00000008)
#define UART_FLAG_NE ((uint32_t)0x00000004)
#define UART_FLAG_FE ((uint32_t)0x00000002)
#define UART_FLAG_PE ((uint32_t)0x00000001)
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup UART_Interrupt_definition
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - 0001: CR1 register
* - 0010: CR2 register
* - 0011: CR3 register
*
* @{
*/
#define UART_IT_PE ((uint32_t)0x10000100)
#define UART_IT_TXE ((uint32_t)0x10000080)
#define UART_IT_TC ((uint32_t)0x10000040)
#define UART_IT_RXNE ((uint32_t)0x10000020)
#define UART_IT_IDLE ((uint32_t)0x10000010)
*/
#define UART_IT_LBD ((uint32_t)0x20000040)
#define UART_IT_CTS ((uint32_t)0x30000400)
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
#define UART_IT_ERR ((uint32_t)0x30000001)
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@ -312,6 +298,9 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
/** @brief Reset UART handle state
* @param __HANDLE__: specifies the UART Handle.
@ -321,7 +310,7 @@ typedef struct
*/
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
/** @brief Flushs the UART DR register
/** @brief Flushes the UART DR register
* @param __HANDLE__: specifies the UART Handle.
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
@ -338,7 +327,7 @@ typedef struct
* @arg UART_FLAG_TC: Transmission Complete flag
* @arg UART_FLAG_RXNE: Receive data register not empty flag
* @arg UART_FLAG_IDLE: Idle Line detection flag
* @arg UART_FLAG_ORE: OverRun Error flag
* @arg UART_FLAG_ORE: Overrun Error flag
* @arg UART_FLAG_NE: Noise Error flag
* @arg UART_FLAG_FE: Framing Error flag
* @arg UART_FLAG_PE: Parity Error flag
@ -358,7 +347,7 @@ typedef struct
* @arg UART_FLAG_TC: Transmission Complete flag.
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@ -377,8 +366,14 @@ typedef struct
* UART peripheral.
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
(__HANDLE__)->Instance->DR;}while(0)
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0)
/** @brief Clear the UART FE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@ -411,11 +406,11 @@ typedef struct
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified UART interrupt.
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @param __INTERRUPT__: specifies the UART interrupt source to check.
* @param __INTERRUPT__: specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
@ -425,14 +420,28 @@ typedef struct
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @param NewState: new state of the specified UART interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define UART_IT_MASK ((uint32_t)0x0000FFFF)
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @param __INTERRUPT__: specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
@ -531,39 +540,56 @@ typedef struct
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0)
/** @brief macros to enables or disables the UART's one bit sampling method
/** @brief macros to enables the UART's one bit sample method
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief macros to disables the UART's one bit sample method
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable UART
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions
* @{
*/
/** @addtogroup UART_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@ -580,18 +606,29 @@ void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
@ -599,7 +636,83 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
/** @brief UART interruptions flag mask
*
*/
#define UART_CR1_REG_INDEX 1
#define UART_CR2_REG_INDEX 2
#define UART_CR3_REG_INDEX 3
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
((STOPBITS) == UART_STOPBITS_2))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
((PARITY) == UART_PARITY_EVEN) || \
((PARITY) == UART_PARITY_ODD))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS) || \
((CONTROL) == UART_HWCONTROL_CTS) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
((STATE) == UART_STATE_ENABLE))
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
((SAMPLING) == UART_OVERSAMPLING_8))
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup UART_Private_Functions UART Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

239
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@ -33,7 +33,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
(+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
@ -41,11 +41,11 @@
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
(++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_USART_MspInit(&husart) API.
by calling the customized HAL_USART_MspInit(&husart) API.
-@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process.
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
@ -59,15 +59,11 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
(+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxCpltCallback
add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
@ -109,7 +105,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -143,19 +139,30 @@
* @{
*/
/** @defgroup USART
/** @defgroup USART USART
* @brief HAL USART Synchronous module driver
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define DUMMY_DATA 0xFFFF
/** @addtogroup USART_Private_Constants
* @{
*/
#define DUMMY_DATA 0xFFFF
#define USART_TIMEOUT_VALUE 22000
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup USART_Private_Functions
* @{
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
static void USART_SetConfig (USART_HandleTypeDef *husart);
@ -165,14 +172,16 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/** @defgroup USART_Private_Functions
/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
/** @defgroup USART_Group1 USART Initialization and de-initialization functions
/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -223,6 +232,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_USART_MspInit(husart);
}
@ -239,7 +250,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
/* Enable the Peripheral */
__USART_ENABLE(husart);
__HAL_USART_ENABLE(husart);
/* Initialize the USART state */
husart->ErrorCode = HAL_USART_ERROR_NONE;
@ -267,6 +278,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
husart->State = HAL_USART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_USART_DISABLE(husart);
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
@ -288,7 +302,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_MspInit could be implenetd in the user file
the HAL_USART_MspInit could be implemented in the user file
*/
}
@ -301,7 +315,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_MspDeInit could be implenetd in the user file
the HAL_USART_MspDeInit could be implemented in the user file
*/
}
@ -309,7 +323,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
* @}
*/
/** @defgroup USART_Group2 IO operation functions
/** @defgroup USART_Exported_Functions_Group2 IO operation functions
* @brief USART Transmit and Receive functions
*
@verbatim
@ -335,7 +349,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
using DMA mode.
The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
user callbacks
will be executed respectivelly at the end of the transmit or Receive process
will be executed respectively at the end of the transmit or Receive process
The HAL_USART_ErrorCallback() user callback will be executed when a communication
error is detected
@ -354,13 +368,18 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceie_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_USART_TxHalfCpltCallback()
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxHalfCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
@endverbatim
* @{
*/
@ -687,14 +706,14 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
to benefit for the frame error and noise interrupts the USART mode should be
configured only for transmit "USART_MODE_TX"
The __USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
Noise error interrupt */
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Transmit Data Register Empty Interrupt */
__USART_ENABLE_IT(husart, USART_IT_TXE);
__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@ -730,18 +749,18 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Enable the USART Data Register not empty Interrupt */
__USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
__USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__USART_ENABLE_IT(husart, USART_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Data Register not empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
/* Send dummy byte in order to generate the clock for the slave to send data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
@ -783,20 +802,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
/* Enable the USART Data Register not empty Interrupt */
__USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
__USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__USART_ENABLE_IT(husart, USART_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Data Register not empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
/* Enable the USART Transmit Data Register Empty Interrupt */
__USART_ENABLE_IT(husart, USART_IT_TXE);
__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@ -847,6 +866,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
@ -992,6 +1014,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
/* Clear the Overrun flag: mandatory for the second transfer in circular mode */
__HAL_USART_CLEAR_OREFLAG(husart);
@ -1171,6 +1196,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
USART_TransmitReceive_IT(husart);
}
}
tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
/* USART in mode Transmitter (transmission end) ----------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
USART_EndTransmit_IT(husart);
}
}
/**
@ -1255,7 +1288,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
* @}
*/
/** @defgroup USART_Group3 Peripheral State and Errors functions
/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief USART State and Errors functions
*
@verbatim
@ -1315,22 +1348,12 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
husart->TxXferCount = 0;
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Wait for USART TC Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout occurred */
husart->State = HAL_USART_STATE_TIMEOUT;
HAL_USART_ErrorCallback(husart);
}
else
{
/* No Timeout */
/* Disable the DMA transfer for transmit request by setting the DMAT bit
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAT);
husart->State= HAL_USART_STATE_READY;
HAL_USART_TxCpltCallback(husart);
}
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
/* DMA Circular mode */
@ -1368,23 +1391,24 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
husart->RxXferCount = 0;
husart->State= HAL_USART_STATE_READY;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAR);
husart->State= HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
}
/* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAR);
husart->Instance->CR3 &= ~(USART_CR3_DMAT);
husart->State= HAL_USART_STATE_READY;
HAL_USART_TxRxCpltCallback(husart);
}
}
@ -1395,7 +1419,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
HAL_USART_RxCpltCallback(husart);
}
/* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
HAL_USART_TxRxCpltCallback(husart);
@ -1460,10 +1484,10 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__USART_DISABLE_IT(husart, USART_IT_TXE);
__USART_DISABLE_IT(husart, USART_IT_RXNE);
__USART_DISABLE_IT(husart, USART_IT_PE);
__USART_DISABLE_IT(husart, USART_IT_ERR);
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@ -1485,10 +1509,10 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__USART_DISABLE_IT(husart, USART_IT_TXE);
__USART_DISABLE_IT(husart, USART_IT_RXNE);
__USART_DISABLE_IT(husart, USART_IT_PE);
__USART_DISABLE_IT(husart, USART_IT_ERR);
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@ -1538,21 +1562,10 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
if(--husart->TxXferCount == 0)
{
/* Disable the USART Transmit data register empty Interrupt */
__USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__USART_DISABLE_IT(husart, USART_IT_ERR);
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxCpltCallback(husart);
return HAL_OK;
/* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
return HAL_OK;
}
@ -1562,6 +1575,27 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
}
}
/**
* @brief Wraps up transmission in non blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
{
/* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxCpltCallback(husart);
return HAL_OK;
}
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
@ -1613,13 +1647,13 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
if(husart->RxXferCount == 0)
{
/* Disable the USART RXNE Interrupt */
__USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
__USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__USART_DISABLE_IT(husart, USART_IT_ERR);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
@ -1672,7 +1706,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
/* Check the latest data transmitted */
if(husart->TxXferCount == 0)
{
__USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
}
}
}
@ -1713,13 +1747,13 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
/* Check the latest data received */
if(husart->RxXferCount == 0)
{
__USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
__USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__USART_DISABLE_IT(husart, USART_IT_ERR);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
@ -1770,7 +1804,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/* Set CPHA bit according to husart->Init.CLKPhase value */
/* Set LBCL bit according to husart->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg |= (uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity |
tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
/* Write to USART CR2 */
husart->Instance->CR2 = (uint32_t)tmpreg;
@ -1778,15 +1812,16 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/*-------------------------- USART CR1 Configuration -----------------------*/
tmpreg = husart->Instance->CR1;
/* Clear M, PCE, PS, TE and RE bits */
/* Clear M, PCE, PS, TE, RE and OVER8 bits */
tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
USART_CR1_RE));
USART_CR1_RE | USART_CR1_OVER8));
/* Configure the USART Word Length, Parity and mode:
Set the M bits according to husart->Init.WordLength value
Set PCE and PS bits according to husart->Init.Parity value
Set TE and RE bits according to husart->Init.Mode value */
tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
Set TE and RE bits according to husart->Init.Mode value
Force OVER8 bit to 1 in order to reach the max USART frequencies */
tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
/* Write to USART CR1 */
husart->Instance->CR1 = (uint32_t)tmpreg;
@ -1798,11 +1833,11 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/*-------------------------- USART BRR Configuration -----------------------*/
if((husart->Instance == USART1) || (husart->Instance == USART6))
{
husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
}
else
{
husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
}
}

302
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,6 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
@ -78,7 +82,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@ -107,19 +111,6 @@ typedef enum
HAL_USART_STATE_ERROR = 0x04 /*!< Error */
}HAL_USART_StateTypeDef;
/**
* @brief HAL USART Error Code structure definition
*/
typedef enum
{
HAL_USART_ERROR_NONE = 0x00, /*!< No error */
HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
HAL_USART_ERROR_FE = 0x04, /*!< frame error */
HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
}HAL_USART_ErrorTypeDef;
/**
* @brief USART handle Structure definition
*/
@ -149,125 +140,122 @@ typedef struct
__IO HAL_USART_StateTypeDef State; /* Usart communication state */
__IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */
__IO uint32_t ErrorCode; /* USART Error code */
}USART_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants
* @{
*/
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
((LENGTH) == USART_WORDLENGTH_9B))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_Error_Code USART Error Code
* @brief USART Error Code
* @{
*/
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x00000000)
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
((STOPBITS) == USART_STOPBITS_0_5) || \
((STOPBITS) == USART_STOPBITS_1_5) || \
((STOPBITS) == USART_STOPBITS_2))
/**
* @}
*/
/** @defgroup USART_Parity
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE ((uint32_t)0x00000000)
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
((PARITY) == USART_PARITY_EVEN) || \
((PARITY) == USART_PARITY_ODD))
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup USART_Mode
/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup USART_Clock
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLED ((uint32_t)0x00000000)
#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
((CLOCK) == USART_CLOCK_ENABLED))
#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW ((uint32_t)0x00000000)
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
/**
* @}
*/
/** @defgroup USART_Last_Bit
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
((LASTBIT) == USART_LASTBIT_ENABLE))
/**
* @}
*/
/** @defgroup USART_NACK_State
/** @defgroup USART_NACK_State USART NACK State
* @{
*/
#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
#define USARTNACK_DISABLED ((uint32_t)0x00000000)
#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
((NACK) == USARTNACK_DISABLED))
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define USART_NACK_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup USART_Flags
/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define USART_FLAG_TXE ((uint32_t)0x00000080)
#define USART_FLAG_TC ((uint32_t)0x00000040)
#define USART_FLAG_RXNE ((uint32_t)0x00000020)
@ -280,7 +268,7 @@ typedef struct
* @}
*/
/** @defgroup USART_Interrupt_definition
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
@ -290,18 +278,16 @@ typedef struct
*
* @{
*/
#define USART_IT_PE ((uint32_t)0x10000100)
#define USART_IT_TXE ((uint32_t)0x10000080)
#define USART_IT_TC ((uint32_t)0x10000040)
#define USART_IT_RXNE ((uint32_t)0x10000020)
#define USART_IT_IDLE ((uint32_t)0x10000010)
#define USART_IT_LBD ((uint32_t)0x20000040)
#define USART_IT_CTS ((uint32_t)0x30000400)
#define USART_IT_ERR ((uint32_t)0x30000001)
#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@ -309,8 +295,12 @@ typedef struct
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
/** @brief Reset USART handle state
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
@ -327,13 +317,12 @@ typedef struct
* @arg USART_FLAG_TC: Transmission Complete flag
* @arg USART_FLAG_RXNE: Receive data register not empty flag
* @arg USART_FLAG_IDLE: Idle Line detection flag
* @arg USART_FLAG_ORE: OverRun Error flag
* @arg USART_FLAG_ORE: Overrun Error flag
* @arg USART_FLAG_NE: Noise Error flag
* @arg USART_FLAG_FE: Framing Error flag
* @arg USART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified Smartcard pending flags.
@ -344,7 +333,7 @@ typedef struct
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@ -362,8 +351,14 @@ typedef struct
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
(__HANDLE__)->Instance->DR;}while(0)
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
@ -392,7 +387,7 @@ typedef struct
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified Usart interrupts.
/** @brief Enables or disables the specified USART interrupts.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __INTERRUPT__: specifies the USART interrupt source to check.
@ -403,20 +398,17 @@ typedef struct
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @param NewState: new state of the specified Usart interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define USART_IT_MASK ((uint32_t)0x0000FFFF)
#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
/** @brief Checks whether the specified Usart interrupt has occurred or not.
/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __IT__: specifies the USART interrupt source to check.
@ -432,22 +424,55 @@ typedef struct
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
#define __USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
#define __USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define __USART_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
/** @brief Macro to enable the USART's one bit sample method
* @param __HANDLE__: specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
/** @brief Macro to disable the USART's one bit sample method
* @param __HANDLE__: specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable USART
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_Exported_Functions
* @{
*/
/** @addtogroup USART_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@ -468,10 +493,83 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup USART_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
/** @brief USART interruptions flag mask
*
*/
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
#define USART_CR1_REG_INDEX 1
#define USART_CR2_REG_INDEX 2
#define USART_CR3_REG_INDEX 3
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
((NACK) == USART_NACK_DISABLE))
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
((LASTBIT) == USART_LASTBIT_ENABLE))
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
((CLOCK) == USART_CLOCK_ENABLE))
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
((LENGTH) == USART_WORDLENGTH_9B))
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
((STOPBITS) == USART_STOPBITS_0_5) || \
((STOPBITS) == USART_STOPBITS_1_5) || \
((STOPBITS) == USART_STOPBITS_2))
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
((PARITY) == USART_PARITY_EVEN) || \
((PARITY) == USART_PARITY_ODD))
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100)
#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup USART_Private_Functions USART Private Functions
* @{
*/
/**
* @}
*/
/**
* @}

57
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@ -40,7 +40,7 @@
##### How to use this driver #####
==============================================================================
[..]
(+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
@ -64,13 +64,13 @@
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
(+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
(+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wake-up interrupt
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -104,7 +104,7 @@
* @{
*/
/** @defgroup WWDG
/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
@ -116,13 +116,12 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_Group1 Initialization and de-initialization functions
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@ -164,6 +163,8 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hwwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
@ -255,7 +256,7 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
* @}
*/
/** @defgroup WWDG_Group2 IO operation functions
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@ -314,7 +315,7 @@ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Enable the Early Wakeup Interrupt */
__HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
__HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
/* Enable the peripheral */
__HAL_WWDG_ENABLE(hwwdg);
@ -369,20 +370,24 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* WWDG Early Wakeup Interrupt occurred */
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
/* Check if Early Wakeup Interrupt is enable */
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Early Wakeup callback */
HAL_WWDG_WakeupCallback(hwwdg);
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_READY;
/* Clear the WWDG Data Ready flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
/* Process Unlocked */
__HAL_UNLOCK(hwwdg);
/* Check if WWDG Early Wakeup Interrupt occurred */
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Early Wakeup callback */
HAL_WWDG_WakeupCallback(hwwdg);
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_READY;
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
/* Process Unlocked */
__HAL_UNLOCK(hwwdg);
}
}
}
@ -403,7 +408,7 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
* @}
*/
/** @defgroup WWDG_Group3 Peripheral State functions
/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim

231
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG HAL State Structure definition
*/
@ -98,89 +101,51 @@ typedef struct
__IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
}WWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_BitAddress_AliasRegion
* @brief WWDG registers bit address in the alias region
* @{
*/
/* --- CFR Register ---*/
/* Alias word address of EWI bit */
#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
/**
* @}
*/
/** @defgroup WWDG_Interrupt_definition
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
#define IS_WWDG_IT(__IT__) ((__IT__) == WWDG_IT_EWI)
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */
#define IS_WWDG_FLAG(__FLAG__) ((__FLAG__) == WWDG_FLAG_EWIF))
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/** @defgroup WWDG_Window
* @{
*/
#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
/**
* @}
*/
/** @defgroup WWDG_Counter
* @{
*/
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/** @brief Reset WWDG handle state
* @param __HANDLE__: WWDG handle
@ -195,6 +160,57 @@ typedef struct
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Disables the WWDG peripheral.
* @param __HANDLE__: WWDG handle
* @note WARNING: This is a dummy macro for HAL code alignment.
* Once enable, WWDG Peripheral cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
/**
* @brief Gets the selected WWDG's it status.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG's interrupt pending bits
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Enables the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Disables the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt to disable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note WARNING: This is a dummy macro for HAL code alignment.
* Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
/**
* @brief Gets the selected WWDG's flag status.
* @param __HANDLE__: WWDG handle
@ -215,41 +231,107 @@ typedef struct
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
* @param __HANDLE__: WWDG Handle.
* @param __INTERRUPT__: specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enables the WWDG early wakeup interrupt.
* @param __INTERRUPT__: specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
* @}
*/
#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
/** @brief Clear the WWDG's interrupt pending bits
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions **************************************************/
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Constants WWDG Private Constants
* @{
*/
/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
* @brief WWDG registers bit address in the alias region
* @{
*/
/* --- CFR Register ---*/
/* Alias word address of EWI bit */
#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions WWDG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
@ -257,8 +339,7 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif

762
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
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992
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h
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318
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -78,27 +78,24 @@
* @{
*/
/** @defgroup FSMC
/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
* @{
*/
#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FSMC_Private_Functions
/** @addtogroup FSMC_LL_Private_Functions
* @{
*/
/** @defgroup FSMC_NORSRAM Controller functions
/** @addtogroup FSMC_LL_NORSRAM
* @brief NORSRAM Controller functions
*
@verbatim
@ -122,7 +119,7 @@
* @{
*/
/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@ -165,20 +162,30 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
/* Get the BTCR register value */
tmpr = Device->BTCR[Init->NSBank];
/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
/* Set NORSRAM device control parameters */
tmpr = (uint32_t)(Init->DataAddressMux |\
Init->MemoryType |\
Init->MemoryDataWidth |\
Init->BurstAccessMode |\
Init->WaitSignalPolarity |\
Init->WrapMode |\
Init->WaitSignalActive |\
Init->WriteOperation |\
Init->WaitSignal |\
Init->ExtendedMode |\
Init->AsynchronousWait |\
Init->WriteBurst
);
tmpr |= (uint32_t)(Init->DataAddressMux |\
Init->MemoryType |\
Init->MemoryDataWidth |\
Init->BurstAccessMode |\
Init->WaitSignalPolarity |\
Init->WrapMode |\
Init->WaitSignalActive |\
Init->WriteOperation |\
Init->WaitSignal |\
Init->ExtendedMode |\
Init->AsynchronousWait |\
Init->WriteBurst
);
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
@ -190,7 +197,6 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
return HAL_OK;
}
/**
* @brief DeInitialize the FSMC_NORSRAM peripheral
* @param Device: Pointer to NORSRAM device instance
@ -247,15 +253,22 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
/* Get the BTCR register value */
tmpr = Device->BTCR[Bank + 1];
/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
FSMC_BTR1_ACCMOD));
/* Set FSMC_NORSRAM device timing parameters */
tmpr = (uint32_t)(Timing->AddressSetupTime |\
((Timing->AddressHoldTime) << 4) |\
((Timing->DataSetupTime) << 8) |\
((Timing->BusTurnAroundDuration) << 16) |\
(((Timing->CLKDivision)-1) << 20) |\
(((Timing->DataLatency)-2) << 24) |\
(Timing->AccessMode)
);
tmpr |= (uint32_t)(Timing->AddressSetupTime |\
((Timing->AddressHoldTime) << 4) |\
((Timing->DataSetupTime) << 8) |\
((Timing->BusTurnAroundDuration) << 16) |\
(((Timing->CLKDivision)-1) << 20) |\
(((Timing->DataLatency)-2) << 24) |\
(Timing->AccessMode));
Device->BTCR[Bank + 1] = tmpr;
@ -272,6 +285,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
uint32_t tmpr = 0;
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
{
@ -284,13 +299,23 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
((Timing->AddressHoldTime) << 4) |\
((Timing->DataSetupTime) << 8) |\
((Timing->BusTurnAroundDuration) << 16) |\
(((Timing->CLKDivision)-1) << 20) |\
(((Timing->DataLatency)-2) << 24) |\
(Timing->AccessMode));
/* Get the BWTR register value */
tmpr = Device->BWTR[Bank];
/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
FSMC_BWTR1_ACCMOD));
tmpr |= (uint32_t)(Timing->AddressSetupTime |\
((Timing->AddressHoldTime) << 4) |\
((Timing->DataSetupTime) << 8) |\
((Timing->BusTurnAroundDuration) << 16) |\
(((Timing->CLKDivision)-1) << 20) |\
(((Timing->DataLatency)-2) << 24) |\
(Timing->AccessMode));
Device->BWTR[Bank] = tmpr;
}
else
{
@ -299,16 +324,13 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions
* @brief management functions
*
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
* @brief management functions
*
@verbatim
==============================================================================
##### FSMC_NORSRAM Control functions #####
@ -348,7 +370,6 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
return HAL_OK;
}
/**
* @}
*/
@ -357,8 +378,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @}
*/
/** @defgroup FSMC_PCCARD Controller functions
* @brief PCCARD Controller functions
/** @addtogroup FSMC_LL_NAND
* @brief NAND Controller functions
*
@verbatim
==============================================================================
@ -382,9 +403,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @{
*/
/** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@ -408,7 +429,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
{
uint32_t tmppcr = 0;
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
@ -419,29 +440,43 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
if(Init->NandBank == FSMC_NAND_BANK2)
{
/* Get the NAND bank 2 register value */
tmpr = Device->PCR2;
}
else
{
/* Get the NAND bank 3 register value */
tmpr = Device->PCR3;
}
/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
/* Set NAND device control parameters */
tmppcr = (uint32_t)(Init->Waitfeature |\
FSMC_PCR_MEMORY_TYPE_NAND |\
Init->MemoryDataWidth |\
Init->EccComputation |\
Init->ECCPageSize |\
((Init->TCLRSetupTime) << 9) |\
((Init->TARSetupTime) << 13)
);
tmpr |= (uint32_t)(Init->Waitfeature |\
FSMC_PCR_MEMORY_TYPE_NAND |\
Init->MemoryDataWidth |\
Init->EccComputation |\
Init->ECCPageSize |\
((Init->TCLRSetupTime) << 9) |\
((Init->TARSetupTime) << 13));
if(Init->NandBank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PCR2 = tmppcr;
Device->PCR2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
Device->PCR3 = tmppcr;
Device->PCR3 = tmpr;
}
return HAL_OK;
}
/**
@ -454,7 +489,7 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmppmem = 0;
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@ -462,8 +497,23 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
if(Bank == FSMC_NAND_BANK2)
{
/* Get the NAND bank 2 register value */
tmpr = Device->PMEM2;
}
else
{
/* Get the NAND bank 3 register value */
tmpr = Device->PMEM3;
}
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
FSMC_PMEM2_MEMHIZ2));
/* Set FSMC_NAND device timing parameters */
tmppmem = (uint32_t)(Timing->SetupTime |\
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@ -472,12 +522,12 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PMEM2 = tmppmem;
Device->PMEM2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
Device->PMEM3 = tmppmem;
Device->PMEM3 = tmpr;
}
return HAL_OK;
@ -493,7 +543,7 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmppatt = 0;
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@ -501,8 +551,23 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
if(Bank == FSMC_NAND_BANK2)
{
/* Get the NAND bank 2 register value */
tmpr = Device->PATT2;
}
else
{
/* Get the NAND bank 3 register value */
tmpr = Device->PATT3;
}
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
FSMC_PATT2_ATTHIZ2));
/* Set FSMC_NAND device timing parameters */
tmppatt = (uint32_t)(Timing->SetupTime |\
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@ -511,18 +576,17 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PATT2 = tmppatt;
Device->PATT2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
Device->PATT3 = tmppatt;
Device->PATT3 = tmpr;
}
return HAL_OK;
}
/**
* @brief DeInitializes the FSMC_NAND device
* @param Device: Pointer to NAND device instance
@ -555,15 +619,13 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_FSMC_NAND_Group3 Control functions
* @brief management functions
*
/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
* @brief management functions
*
@verbatim
==============================================================================
##### FSMC_NAND Control functions #####
@ -575,7 +637,6 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
@endverbatim
* @{
*/
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
@ -598,7 +659,6 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank
return HAL_OK;
}
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@ -639,8 +699,8 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
/* Get tick */
tickstart = HAL_GetTick();
/* Wait untill FIFO is empty */
while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT))
/* Wait until FIFO is empty */
while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@ -674,7 +734,7 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @}
*/
/** @defgroup FSMC_PCCARD Controller functions
/** @addtogroup FSMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@verbatim
@ -698,9 +758,9 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @{
*/
/** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@ -724,19 +784,29 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
/* Get PCCARD control register value */
tmpr = Device->PCR4;
/* Clear TAR, TCLR, PWAITEN and PWID bits */
tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
FSMC_PCR4_PWID));
/* Set FSMC_PCCARD device control parameters */
Device->PCR4 = (uint32_t)(Init->Waitfeature |\
FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
(Init->TCLRSetupTime << 9) |\
(Init->TARSetupTime << 13));
tmpr |= (uint32_t)(Init->Waitfeature |\
FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
(Init->TCLRSetupTime << 9) |\
(Init->TARSetupTime << 13));
Device->PCR4 = tmpr;
return HAL_OK;
}
/**
@ -748,19 +818,28 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get PCCARD common space timing register value */
tmpr = Device->PMEM4;
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
FSMC_PMEM4_MEMHIZ4));
/* Set PCCARD timing parameters */
Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
(Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
tmpr |= (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
(Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24));
Device->PMEM4 = tmpr;
return HAL_OK;
}
@ -773,18 +852,27 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get PCCARD timing parameters */
tmpr = Device->PATT4;
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
FSMC_PATT4_ATTHIZ4));
/* Set PCCARD timing parameters */
Device->PATT4 = (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
(Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24));
Device->PATT4 = tmpr;
return HAL_OK;
}
@ -798,18 +886,28 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get FSMC_PCCARD device timing parameters */
tmpr = Device->PIO4;
/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
FSMC_PIO4_IOHIZ4));
/* Set FSMC_PCCARD device timing parameters */
Device->PIO4 = (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
(Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24));
Device->PIO4 = tmpr;
return HAL_OK;
}
@ -833,7 +931,6 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
return HAL_OK;
}
/**
* @}
*/
@ -842,9 +939,11 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
* @}
*/
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* HAL_FSMC_MODULE_ENABLED */
#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
/**
* @}
@ -853,5 +952,4 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

966
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h
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35
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@ -21,13 +21,6 @@
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
devices.
[..] The MultiMedia Card system specifications are available through the MultiMedia Card
Association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.
CE-ATA system specifications are available through the CE-ATA work group web site at
www.ce-ata.org.
[..] The SDIO features include the following:
(+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
@ -67,7 +60,7 @@
peripheral.
(+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
function and disable it using the function HAL_SDIO_PowerState_OFF(SDIOx).
function and disable it using the function SDIO_PowerState_OFF(SDIOx).
(+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
@ -107,7 +100,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
(++) Data TimeOut
(++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be from card (To SDIO)
@ -127,7 +120,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
(++) Data TimeOut
(++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be to card (To CARD)
@ -145,7 +138,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -179,8 +172,8 @@
* @{
*/
/** @defgroup SDMMC
* @brief SDMMC HAL module driver
/** @defgroup SDMMC_LL SDMMC Low Layer
* @brief Low layer module for SD and MMC driver
* @{
*/
@ -193,11 +186,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SDIO_Private_Functions
/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
* @{
*/
/** @defgroup HAL_SDIO_Group1 Initialization/de-initialization functions
/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@ -245,13 +238,11 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_SDIO_Group2 I/O operation functions
/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
* @brief Data transfers functions
*
@verbatim
@ -295,7 +286,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
* @}
*/
/** @defgroup HAL_SDIO_Group3 Peripheral Control functions
/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@ -436,7 +427,7 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDI
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
/* Set the SDIO Data TimeOut value */
/* Set the SDIO Data Timeout value */
SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
/* Set the SDIO DataLength value */

221
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -50,13 +50,12 @@
* @{
*/
/** @addtogroup SDMMC
/** @addtogroup SDMMC_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDIO_Exported_Types SDIO Exported Types
/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
* @{
*/
@ -143,12 +142,11 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Constants
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
/** @defgroup SDIO_Clock_Edge Clock Edge
* @{
*/
#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
@ -160,7 +158,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Clock_Bypass
/** @defgroup SDIO_Clock_Bypass Clock Bypass
* @{
*/
#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
@ -172,7 +170,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Clock_Power_Save
/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
@ -184,7 +182,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Bus_Wide
/** @defgroup SDIO_Bus_Wide Bus Width
* @{
*/
#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
@ -198,7 +196,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control
/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
@ -210,7 +208,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Clock_Division
/** @defgroup SDIO_Clock_Division Clock Division
* @{
*/
#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
@ -218,7 +216,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Command_Index
/** @defgroup SDIO_Command_Index Command Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
@ -226,7 +224,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Response_Type
/** @defgroup SDIO_Response_Type Response Type
* @{
*/
#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
@ -240,7 +238,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDIO_WAIT_NO ((uint32_t)0x00000000)
@ -254,7 +252,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_CPSM_State
/** @defgroup SDIO_CPSM_State CPSM State
* @{
*/
#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
@ -266,7 +264,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Response_Registers
/** @defgroup SDIO_Response_Registers Response Register
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
@ -282,7 +280,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Data_Length
/** @defgroup SDIO_Data_Length Data Lenght
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
@ -290,7 +288,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Data_Block_Size
/** @defgroup SDIO_Data_Block_Size Data Block Size
* @{
*/
#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
@ -328,7 +326,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Transfer_Direction
/** @defgroup SDIO_Transfer_Direction Transfer Direction
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
@ -340,7 +338,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Transfer_Type
/** @defgroup SDIO_Transfer_Type Transfer Type
* @{
*/
#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
@ -352,7 +350,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_DPSM_State
/** @defgroup SDIO_DPSM_State DPSM State
* @{
*/
#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
@ -364,11 +362,11 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
* @{
*/
#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
((MODE) == SDIO_READ_WAIT_MODE_DATA2))
@ -376,7 +374,7 @@ typedef struct
* @}
*/
/** @defgroup SDIO_Interrupt_sources
/** @defgroup SDIO_Interrupt_sources Interrupt Sources
* @{
*/
#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
@ -403,13 +401,11 @@ typedef struct
#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Flags
/** @defgroup SDIO_Flags Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
@ -436,124 +432,77 @@ typedef struct
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Instance_definition
* @{
*/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
* @{
*/
/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
* @{
*/
/* ------------ SDIO registers bit address in the alias region -------------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber 0x08
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
#define CLKEN_BITNUMBER 0x08
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define SDIOSUSPEND_BitNumber 0x0B
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
#define SDIOSUSPEND_BITNUMBER 0x0B
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BitNumber 0x0C
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
#define ENCMDCOMPL_BITNUMBER 0x0C
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
/* Alias word address of NIEN bit */
#define NIEN_BitNumber 0x0D
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
#define NIEN_BITNUMBER 0x0D
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
/* Alias word address of ATACMD bit */
#define ATACMD_BitNumber 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
#define ATACMD_BITNUMBER 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
#define DMAEN_BITNUMBER 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
/* Alias word address of RWSTART bit */
#define RWSTART_BitNumber 0x08
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
#define RWSTART_BITNUMBER 0x08
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
/* Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
#define RWSTOP_BITNUMBER 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
/* Alias word address of RWMOD bit */
#define RWMOD_BitNumber 0x0A
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
#define RWMOD_BITNUMBER 0x0A
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
/* Alias word address of SDIOEN bit */
#define SDIOEN_BitNumber 0x0B
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
#define SDIOEN_BITNUMBER 0x0B
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
/**
* @}
*/
/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
* @brief SDMMC_LL registers bit address in the alias region
* @{
*/
/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
@ -577,41 +526,40 @@ typedef struct
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
/* SDIO Intialization Frequency (400KHz max) */
/* SDIO Initialization Frequency (400KHz max) */
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
/* SDIO Data Transfer Frequency (25MHz max) */
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
/**
* @}
*/
/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/** @defgroup SDIO_Interrupt_Clock
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SDIO device.
* @param None
* @retval None
*/
#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
* @param None
* @retval None
*/
#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
* @param None
* @retval None
*/
#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
/**
* @brief Disable the SDIO DMA transfer.
* @param None
* @retval None
*/
#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
@ -798,102 +746,89 @@ typedef struct
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param None
* @retval None
*/
#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
* @param None
* @retval None
*/
#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
* @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
* @param None
* @retval None
*/
#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
* @param None
* @retval None
*/
#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
* @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
* @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
#if !defined(STM32F446xx)
/**
* @brief Enable the command completion signal.
* @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
/**
* @brief Disable the command completion signal.
* @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
/**
* @brief Enable the CE-ATA interrupt.
* @param None
* @retval None
*/
#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
/**
* @brief Disable the CE-ATA interrupt.
* @param None
* @retval None
*/
#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
/**
* @brief Enable send CE-ATA command (CMD61).
* @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
/**
* @brief Disable send CE-ATA command (CMD61).
* @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
#endif /* !defined(STM32F446xx) */
/**
* @}
*/
@ -903,12 +838,12 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDIO_Exported_Functions
/** @addtogroup SDMMC_LL_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
/** @addtogroup HAL_SDIO_Group1
/** @addtogroup HAL_SDMMC_LL_Group1
* @{
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
@ -917,7 +852,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
*/
/* I/O operation functions *****************************************************/
/** @addtogroup HAL_SDIO_Group2
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
/* Blocking mode: Polling */
@ -928,7 +863,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_SDIO_Group3
/** @addtogroup HAL_SDMMC_LL_Group3
* @{
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);

42
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@ -22,13 +22,13 @@
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
(#) The upper HAL HCD/PCD driver will call the righ routines for its internal processes.
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -167,7 +167,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @param USBx : Selected device
* @param mode : current core mode
* This parameter can be one of the these values:
* @arg USB_OTG_DEVICE_MODE: Peripheral mode mode
* @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
* @arg USB_OTG_DRD_MODE: Dual Role Device mode
* @retval HAL status
@ -202,13 +202,27 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
uint32_t i = 0;
/*Activate VBUS Sensing B */
#if defined(STM32F446xx)
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
if (cfg.vbus_sensing_enable == 0)
{
/*Desactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
/* B-peripheral session valid override enable*/
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
}
#else
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
if (cfg.vbus_sensing_enable == 0)
{
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
}
#endif /* STM32F446xx */
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
@ -779,12 +793,12 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
* @param USBx : Selected device
* @param src : source pointer
* @param ch_ep_num : endpoint or host channel number
* @param len : Noumber of bytes to read
* @param len : Number of bytes to read
* @param dma: USB dma enabled or disabled
* This parameter can be one of the these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval pointer to desctination buffer
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
@ -1121,11 +1135,15 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
/* no VBUS sensing*/
/* Activate VBUS Sensing B */
#if defined(STM32F446xx)
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
#endif /* STM32F446xx */
/* Disable the FS/LS support mode only */
if((cfg.speed == USB_OTG_SPEED_FULL)&&
(USBx != USB_OTG_FS))
@ -1310,7 +1328,7 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
* @param ep_type : Endpoint Type
* This parameter can be one of the these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochrounous type
* @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps : Max Packet Size
@ -1668,7 +1686,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
/* Clear any pending Host interrups */
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFF;
USBx->GINTSTS = 0xFFFFFFFF;
USB_EnableGlobalInt(USBx);

40
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
* @version V1.1.0
* @date 19-June-2014
* @version V1.3.0
* @date 09-March-2015
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -122,7 +122,9 @@ typedef struct
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
@ -224,11 +226,11 @@ typedef struct
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup USB_Core_Mode_
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0
@ -238,7 +240,7 @@ typedef struct
* @}
*/
/** @defgroup USB_Core_Speed_
/** @defgroup USB_Core_Speed_ USB Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0
@ -249,7 +251,7 @@ typedef struct
* @}
*/
/** @defgroup USB_Core_PHY_
/** @defgroup USB_Core_PHY_ USB Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1
@ -258,7 +260,7 @@ typedef struct
* @}
*/
/** @defgroup USB_Core_MPS_
/** @defgroup USB_Core_MPS_ USB Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512
@ -268,7 +270,7 @@ typedef struct
* @}
*/
/** @defgroup USB_Core_Phy_Frequency_
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
@ -279,7 +281,7 @@ typedef struct
* @}
*/
/** @defgroup USB_CORE_Frame_Interval_
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0
@ -290,7 +292,7 @@ typedef struct
* @}
*/
/** @defgroup USB_EP0_MPS_
/** @defgroup USB_EP0_MPS_ USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
@ -301,7 +303,7 @@ typedef struct
* @}
*/
/** @defgroup USB_EP_Speed_
/** @defgroup USB_EP_Speed_ USB EP Speed
* @{
*/
#define EP_SPEED_LOW 0
@ -311,7 +313,7 @@ typedef struct
* @}
*/
/** @defgroup USB_EP_Type_
/** @defgroup USB_EP_Type_ USB EP Type
* @{
*/
#define EP_TYPE_CTRL 0
@ -323,7 +325,7 @@ typedef struct
* @}
*/
/** @defgroup USB_STS_Defines_
/** @defgroup USB_STS_Defines_ USB STS Defines
* @{
*/
#define STS_GOUT_NAK 1
@ -335,7 +337,7 @@ typedef struct
* @}
*/
/** @defgroup HCFG_SPEED_Defines_
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
* @{
*/
#define HCFG_30_60_MHZ 0
@ -345,7 +347,7 @@ typedef struct
* @}
*/
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0
@ -380,7 +382,9 @@ typedef struct
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))